Biomed Eng Lett (2015) 5:271-280
DOI 10.1007/s13534-015-0196-9
ORIGINAL ARTICLE
A Knowledge-based Real Time Embedded Platform for Arrhythmia
Beat Classification
Sandeep Raj, Kshitij Maurya and Kailash Chandra Ray
Received: 17 March 2015 / Revised: 14 August 2015 / Accepted: 20 August 2015
The Korean Society of Medical & Biological Engineering and Springer 2015
Abstract
Purpose This paper aims for accurate classification of ECG
beats in real-time.
Methods The design, implementation and results of FPGA
oriented SOC based embedded platform in laboratory
experimental setup is presented. The platform is designed
using high-level systematic approach having the capability of
real-time classification of ECG beats at the place of patients
with high accuracy which will be helpful to enhance the
healthcare for cardiovascular diseases. The algorithm involves
the integration of the R-peak detection algorithm and Rule-
based approach to classify four generic heartbeat classes
namely Normal, PVC, Ventricular Fibrillation/Ventricular
Flutter, 2 heart block beat. The aforesaid algorithms are
performed in software on an integrated TSK3000A processor
core (IP cores used) and implemented in hardware targeting
FPGA (Xilinx Spartan 3AN). The developed platform is
validated by generating real-time ECG beats using MIT-BIH
arrhythmia database.
Results The performance of the proposed implementation is
evaluated in terms of sensitivity, specificity, positive predictivity
and accuracy which is 97.72%, 99.09%, 96.46% and 97.96%
respectively.
Conclusions The proposed hardware/software implementation
has yielded improved results in comparison to the existing
methodologies implemented on the FPGA platforms.
Keywords Electrocardiography, Arrhythmia beat, FPGA,
Real Time, QRS peak, RR-interval
Sandeep Raj ( ), Kshitij Maurya, Kailash Chandra Ray
Department of Electrical Engineering, Indian Institute of Technology
Patna, Patna 800013, India
Tel : +91-6122552085 / Fax : +123-45-678910
E-mail : srp@iitp.ac.in
INTRODUCTION
Cardiovascular disease (CVD) is the leading cause of deaths
in the developed and developing countries. An estimated
17.3 million people died from CVDs in 2008, representing
30% of all deaths globally and it is expected that the number
of mortalities will reach 23.3 million by 2030. Moreover, in
many cases patients suffering from heart attack die just
because they are unable to reach the hospital in time.
Since decades, ECG has been used as a non-invasive
clinical tool in the cardiology which shows the graphical
recordings of heart electrical activities. These recordings
determine the state of heart of a person whether the heart is
behaving normal or suffering from some abnormalities.
These electrical activities of heart are due to depolarization
and repolarization of the heart which results in the generation
of the three wave i.e P-wave, QRS wave and the T-wave.
The morphology, duration and height of these waves
provides sufficient information about the state of heart. The
graphical recordings i.e ECG is further analyzed by the
cardiologist from which the patient can be diagnosed.
These recordings vary greatly for different persons and
patient groups. Even for the same individual these recordings
vary with time under different physical conditions and
therefore are non-stationary in nature [1]. The abnormalities
are often termed as arrhythmias and they may occur regularly
or during a day or week. It may also be possible that the
same arrhythmia can also reveal different morphology at
different time. Moreover, these ECG signals are contaminated
with various kind of noise and artifacts during their acquisition
which makes the analysis more difficult. Thus, automatic
detection and classification of arrhythmias remains a challenge
as it may lead to sudden cardiac death also. In this context,
it is very critical to analyze these recordings more accurately
and precisely when performed in real time.
The standard resting ECG machines lacks the capability of
272
providing any real time feedback for thousands of heartbeats
they record. Hence, the arrhythmias may not be detected due
to the condition may not be present at that time while patient
visiting the hospitals. This makes a tedious job when analyzed
offline by a cardiologist. Various monitoring devices are
available for cardiac event recording and monitoring like
holter devices and event monitors to realize the underlying
heart condition and lacks real time classification rather
classification is performed offline. Some device facilitates
remote real-time monitoring system [2-4] where the recorded
ECG data is transferred to remote monitoring center where
the analysis and classification is performed, thus depriving
the user of real time feedback. A few of devices based on
Personal Digital Assistant (PDA) [5-8] has provided some
intermediate level of local real time classification but lacks
in giving a complete solution to CVD diagnosis. While
using these systems it is also important that they should be
flexible, upgradeable, have enough processing power and are
inexpensive. All these features can be integrated in Field
Programmable Gate Array (FPGA) based systems and can
be finally fabricated on single System-On-Programmable
chip (SoPC) for cardiac event monitoring.
In recent years, numerous research work have been carried
out for analysis, detection and classification of the ECG
signals. Various researcher have presented several algorithms,
which include ECG morphology [9-11], heartbeat interval
techniques [1, 9, 10], frequency-based analysis [12], Principal
Component Analysis methods [13], higher order cumulant
features [15], hermite polynomials [16] for feature extraction
and linear discriminants [9, 17], fuzzy hybrid neural network
[15], neuro-fuzzy approach [18], self organizing maps with
learning vector quantization [1], self organizing networks
[16] and support vector machines [13, 14] for classification
purposes. These algorithms are combined together to perform
real-time classification on a suitable hardware platforms like
microcontrollers and FPGA [19-22] and involves high
computational complexity. However, the performance of the
methodologies implemented on these hardware platforms are
not satisfactory either in terms of classification accuracy or
number of beats classified.
This work presents an efficient FPGA oriented System-
On-Chip (SOC) based embedded platform implementing the
proposed approach to perform real-time classification of
ECG beats. The proposed approach integrates two algorithms
i.e R-peak detection algorithm and the knowleged-based
Fig. 1. Block diagram representation.
Biomed Eng Lett (2015) 5:271-280
approach [23]. The first algorithm contributes for the detection
of the R-peak and the later presents the detection of
arrhythmic beats based on clinical procedures [23] provided
by medical experts. The only feature extracted is the RR-
interval between the consecutive ECG beats that are
classified using a set of rules with sliding window approach
which is computationally inexpensive in comparison to the
various existing methodologies. This kind of implementation
on FPGA platforms can provide real-time diagnosis to the
patients.
A FPGA-based embedded platform is developed and
customized by incorporating commercially available Intellectual
Property (IP) cores of Reduced Instruction Set Computing
(RISC) processor (TSK3000), Analog to Digital Converter
(ADC) controller and display controller (TFT). Further the
proposed algorithm is performed in software on an integrated
TSK3000A processor core and implemented in hardware
FPGA (Xilinx Spartan 3AN). A real time experiment is
performed by generating ECG signals on Arbitrary Function
Generator (AFG3252) using the available MIT-BIH database
[24]. The embedded platform aims for accurate detection and
classification of four classes of ECG beats (one normal beat
and three arrhythmia beats i.e PVC, V.Fib./Fl., 2o heart block
beat) in real time at the place of patients for monitoring
(displayed on TFT screen in our experimental setup) the state
of heart during their normal lifestyle. In this paper, we seek
to unite the portability of Holter monitors with real-time
processing capability of state-of-the-art resting ECG machines
to provide an assistive diagnosis solution using FPGA devices
embedded with soft-core microprocessors in systems.
The rest of this paper is organized as follows: The
algorithms for RR-interval computation and arrhythmia beat
classification are presented in section II. Section III describes
the system design of the developed platform for cardiac
beat monitoring whereas section IV describes experiments
performed. Section V presents the results and discussion and
finally section VI concludes the paper.
RR-INTERVAL COMPUTATION AND BEAT
CLASSIFICATION RULES
This section presents methods to compute the RR-interval of
the consecutive ECG signals and their classification. In the
beginning, R-peak detection algorithm is focussed to detect
Biomed Eng Lett (2015) 5:271-280 273

the R-peak in QRS complex signal of the ECG which is used
to compute RR-intervals of the ECG signals in our approach.
Further, a knowleged-based classifier algorithm is presented
to identify arrhythmia beats using these RR-intervals as
features. The major building blocks for the computation of
RR-interval with beat classifier algorithm is presented in
Fig. 1 and discussed in the following subsections.
RR-interval computation
A QRS complex detection algorithm i.e Pan-Tompkins [25]
is implemented due to its proven sensitivity of 99.69%
and positive prediction of 99.77% when evaluated with the
MIT-BIH arrhythmia database. This algorithm is based on
morphological properties of ECG signals on which the
preprocessing and decision stage is applied. The stages involved
in the RR-interval signal computation is summarized in
Table 1.
The recorded ECG signals taken from the MIT-BIH
database are contaminated with various kinds of noise during
their acquisition, so preprocessing is required in order to
remove them for analysis. The preprocessing stage performs
linear and non-linear filtering of the ECG signal and
produces a set of periodic vectors that describe the events. In
the linear filtering stage, a cascaded low-pass and high-pass
filters is employed to achieve a 3 dB passband from about
5-12 Hz. This digital bandpass filter improves the signal-to-
noise ratio and permits the use of lower thresholds than
would be possible on the unfiltered ECG. Secondly, the
filtered ECG is passed through a five-point derivative to
obtain the slope of R wave. The squaring stage identifies the
slope of the frequency response curve of the derivative and
restricts false positives caused by T waves with higher spectral
energy. Thenafter, a Moving Window Intergrator (MWI) is
applied to obtain waveform feature information in addition
to the slope of the R wave. The implemented equations of
the following stages are summarized in Table 1. The output
of MWI stage determines the size of QRS complex with the
varying nature of QRS complexes. This approach increases
the overall detection sensitivity and reduces the number of
false positives. Since the algorithm is performed in real time,
so no search-back is done and it is based on an amplitude
comparison to an adaptive threshold. QRS detection from the
filtered signal is subsequently performed by an adaptive
threshold detector which uses a set of thresholds.
The QRS detection algorithm in this study is based on
optimized filtering and on a simple decision algorithm as the
optimized filtering is considered to be the key to achieve
good timing accuracy.
The output of the decision stage determines the R-peak in
the ECG signal where the signal has maximum absolute value.
In Table 1, q(m) is the time-averaged signal, g(m) is the
band-passed ECG and h(m) is the differentiated ECG. N is
the number of samples in the width of the moving window.
After the peaks are detected, the main wave of the QRS
complex (R wave) is identified in the window length of
-280 ms to +120 ms. The RR-interval signal is constructed
by measuring the time interval between successive R peaks
of the ECG signals. These RR-intervals are used to classify
four ECG beats namely Normal beat, Preventricular Contraction
beat, Ventricular Fibrillation/ Flutter beats and 2o heart block
beat. The classification rules used to classify these generic
heartbeat classes is discussed in next subsection. Since, the
only feature extracted to classify the desired ECG signals is
the RR-interval signal offers less computation complexity for
further classification and implementation.
Beat classification rules
This work focusses to classify four ECG beats including normal
beat. A knowledge-based approach is adopted using a set of
rules, Arrhythmia beat-by-beat classification is performed on

Table 1. QRS peak detection and RR-interval computation algorithm.

Stages Process stage Implementation Remarks
Stage 1 Select the signal for Analysis ECG Raw Data from MIT-BIH database -
Stage 2 Cascaded low pass and high pass q(m) = 2g[m-1]-q[m-2]+h[m]-2h[m-6]+h[m-12] To attenuate Noise
filter q(m) = 32h[m-16]-g[m-1]+h[n]-h[m-32] Cutoff freq: 11 Hz(LP), 5 Hz(HP)
Stage 3 Apply a derivative operator q(m) = 1/8(-h[m-2]-2h[m-1]+2h[m+1]+h[m+2]) Provides Information about the
slope
Stage 4 Square and Integrate the signal g[m] = h[m]2 Makes data points positive
and amplifies the output
Stage 5 Moving Window Integrator q(m) = 1/N(h[m-(N-1)]+h[m-(N-2)]+.....+h[m]) To ensure the width of QRS
(MWI) complex
Stage 6 Placing a threshold; under this Adjusting two thresholds (THR_SIG and To Identify R peaks
value the signal will be zero THR_NOISE) to adapt continuously with
change in ECG Signal
Stage 7 Computation of RR-interval Computed as successive R-intervals For beat classification
274 Biomed Eng Lett (2015) 5:271-280

Table 2. Knowledge (rule) based beat classification [23].

Rule No. Rules Beat classification
Rule 1 Initialization: RR2i from window i is classified as NORMAL (Category 1) Normal Beat
Rule 2 a. If RR2i < 0.6 sec and 1.8 * RR1i then i. RR2i is classified in Category 3. V. Fl./Fib. Beat
ii. The RR2k of all the windows k = i+1, i+2,..., i+n with (RR1k < 0.7 and RR2k < 0.7 and
RR3k < 0.7) or (RR1k + RR2k + RR3k < 1.7) are classified in category 3.
b. If the number of intervals that are sequentially classified in category 3 is less than 4 then
they all are classified in Category 1 and the algorithm returns to window i.
Rule 3 If ((1.15 * RR2i < RR1i and (1.15 * RR2i < RR3i)) or ((|RR1i - RR2i | < 0.3 and ((RR1i < PVC Beat
0.8) and (RR2i < 0.8)) and (RR3i > 1.2 * mean(RR1i, RR2i)) ((|RR2i - RR3i | < 0.3) and
((RR2i < 0.8 and (RR3i < 0.8)) and (RR1i < 1.2 * mean(RR2i, RR3i)), then RR2i is
classified in Category 2.
Rule 4 If (2.2 < RR2i < 3.0) and (|RR1i - RR2i | < 0.2) or (|RR2i - RR3i | < 0.2) then RR2i is 2o Heart Block Beat
classified in Category 4.

the RR-interval signal. These rules [23] are provided by
medical experts and are used to detect arrhythmic events
from the RR-intervals based on clinical procedures. The
rules are used for the classification of the middle RR-interval
of a three RR-interval sliding window. The classification
concerns the second beat of the middle RR-interval. The
beats are classified in four categories: (1) normal sinus beats
(N) and three arrhythmic ones: (2) premature ventricular
contractions (PVC), (3) ventricular flutter/fibrillation (VF)
and (4) 2o heart block (BII).
It is therefore assumed that beat not belonging to one of
the above arrhythmic categories is classified as normal beat
i.e all other beats except PVC beat, V. Fib/Fl. beat and 2o
heart block (BII) beat will be classified as Normal irrespective
of their own identity.
The rules summarized in [23] in Table 2. This algorithm
starts with a window I, which consist of the three windows
i.e RR1i, RR2i and RR3i intervals. The middle of the RR-
interval i.e RR2i is considered as normal and classified in
Category 1. After the beats have passed through the rules for
the first window, the algorithm continues with the next window
i.e I = I + 1. The rules are applied sequentially and if beat is
classified to a category by one rule then this classification
cannot be changed by a following rule.
System design
A development system with FPGA (Xilinx Spartan 3AN) is
used for the system implementation. A TSK3000A soft
processor, a 32-bit MIPS-based RISC core is chosen for
suitable mixed hardware/software implementation. Hardware/
Software tradeoffs are easily analyzed. The system was built
using the Xilinx platform Embedded Development Kit
(EDK) which is a collection of tools for building embedded
systems on FPGAs. EDK also contains a large number of IP
cores that makes the design relatively easy. The C to hardware
compiler chc implements a complete co-design system and
thus enables quick hardware protyping. Using this approach,
the integrated algorithms are first implemented in software
on a standard processor and then incrementally optimized by
hardware coprocessors. Finally, system implementation
ranging from board-level systems to SOCs and configurable
SOCs (CSOCs) can also facilitated.
A prototype of the system is designed with the TSK3000
processor to which various peripherals are connected. The
TSK3000A is a Wishbone compatible and offers five stage
pipelining. Wishbone is mainly used as a master/slave memory
bus, but also supports multi-master systems and is useful for
process to process communication, regardless of whether the
processes are implemented as softwares or as hardware
processors. In addition to fast register access, the TSK3000A
features a user definable (from 1K Bytes up to 1M Bytes)
amount of zerowait state block Random-Access Memory
(RAM), with true dual port access. The memory bus excel
themselves in fast memory excess are novelty in design.
Because of their fast access, the XRAM connected to the bus
interfaces is used as stack and heap segment storage which
help them to decrease the data flow through the On chip
Peripheral (OPB) interface. Data and instruction caches of
the same size are also added to the TSK and used for caching
the OPB. All the above mentioned features make our system
best suited platform for the development of diagnosis system
for automatic detection and classification cardiac diseases in
real time.
Commercially available IP cores for the TSK-3000A
microprocessors and other controllers like Serial Peripheral
Interface (SPI) protocols for ADC and TFT controller are
customized to develop an embedded platform as explained in
the following steps.
Step 1: Building Open Bus System
The Embedded System is designed using the Altiums
Open Bus Flow. The building of the Open Bus System
(Embedded Hardware) mainly involves three steps.
1. The required IP core components has been placed on
the Open Bus System.
Biomed Eng Lett (2015) 5:271-280
Fig. 2. Connection with the physical devices.
Fig. 3. Software platform.
2. Interconnecting the Open Bus Components.
3. Configuring the Open Bus System.
The computation is performed in 32-bit RISC processor
(TSK 3000A). As, the computation of real time signal is
performed in digital domain and interfaced with the analog
domain using SPI controller for ADC and TFT.
Step 2: Building Top Level Schematic
After the Open Bus System designed and configured, the
microcontroller needs to be interfaced with the top-level
Schematic in the FPGA design which is done through a sheet
symbol placed on the schematic sheet. The last stage in
designing is to connect the Open Bus System into the FPGA
design to connect the microcontroller with the hardware (like
ADC, TFT and Memory) on the top-level schematic as
shown in Fig. 2.
Step 3: Creating the Software Platform
275
The physical ports which is implemented on the FPGA
board have to be configured and this step automatically
generates the software platform in Graphic User Interface
(GUI) to configure the ports which is presented in Fig. 3.
The devices like ADC and TFT controller based on SPI have
been selected for software platform modules and configured
in high level C++ language.
EXPERIMENTS PERFORMED
ECG signal database
The experiments are evaluated with MIT-BIH Arrhythmia
database [24]. The database contains 48 half hour excerpts of
two channel ambulatory ECG recordings of 47 different
patients. Each record of the database contains two leads with
276
V1 into 40 files, modified lead II in 45 files and II, V2, V4
and V5 distributed among 11 files [26]. The recordings are
digitized with a sampling frequency of 360 Hz and acquired
with 11-bit resolution over 10 mV range. Only 28 records
from the database are used for validation and analyzed using
modified lead-II signals for the classification of four classes
of heartbeats namely normal (N), premature ventricular
contraction (PVC), Ventricular Fibrillation/Flutter, 2o heart
block beat. This study uses the annotation to locate ECG
beats for their classification ans yielding the results.
A total of 10800 beats (i.e 6000 for Normal, 4000 for
PVC, 400 for V.Fib/Fl and 400 for 2o heart block beat) has
been selected and tested from the different files of MIT-BIH
Arrhythmia database [24] to evaluate the performance of the
developed classifier platform. It is worth to mention that only
the beats of desired class have been taken and tested while
the remaining class of beats from the database is ignored to
validate the performance of developed platform.
Implementation
The embedded platform (TSK-3000A and I/O Controllers) is
developed using Altium Designer environment and implemented
on hardware targeting a FPGA device i.e Xilinx Spartan
XC3S1400AN chip which is shown in laboratory experimental
setup in Fig. 4. Although, the TSK3000A software processor
core can operate at frequencies upto 200 MHz rather only the
processing speed of 100 MHz base frequency is presented.
The algorithms for computing RR-interval and beat classification
are developed in C++ language and implemented on aforesaid
FPGA-based embedded platform. This embedded platform
is interfaced with on board Analog to Digital Converter (4-
channel, 8-bit from National Semiconductor) to digitize the
real time ECG signals generated which is used for further
processing and a TFT Terminal is used to monitor the class
of outputs (classified beats) from this embedded computing
system.
As mentioned earlier, MIT-db data files contain ECG data
recorded at 360 Hz sampling frequency. It is observed that
the ECG data recorded are having maximum variation of
5 mV. This signal is converted in 0-5 V range so as to be
accepted by a typical ADC. At first, a series of arrhythmia
beats (Normal, PVC, V. Fib./Fl., 2o heart block beat) are
generated in text file and loaded in Arbitrary Function
Table 3. ECG beats taken from MIT-BIH database.
Beat type Beat annotations
N N 100, 101, 103, 105, 106, 121, 122, 123, 200, 201, 202, 208
PVC V 106, 119, 200, 203, 208, 210, 213, 214, 215, 217, 221, 223, 228, 233
V.Fib/V. Fl VFL
2o H.B BII
Biomed Eng Lett (2015) 5:271-280
Generator (AFG 3252) using Arb Express Application
Software and corresponding real time ECG signals (in this
case arrhythmia beats) are generated. In the AFG3252 the
ECG signal is amplified and sent to embedded computing
system for its direct processing by the ADC. The ADC
samples the input signals at a rate of 500 samples/s. The
laboratory experiments as in Fig. 4 are performed for ECG
signals (Arrhythmia Beats) taken from database and the
corresponding class of output beats are monitored on TFT of
the Altium Board as shown in Fig. 4. This figure shows the
classification of the PVC beat and similarly the other beats
are also being monitored.
In the beginning, R-peak is detected from the Pan-Tompkins
algorithm [25] while processing the ECG data. QRS peak
detection correctness is also cross-verified in a digital signal
oscilloscope (DSO). For this purpose, ECG sample values as
captured by ADC is converted to analog using digital-to-
analog converter (on-board DAC) and is fed as channel-1
input of DSO. QRS peak indicator signal is fed to a channel-2
input for display which is shown in Fig. 5. After the QRS
peaks are detected at maximum absolute value, the time
interval of the successive ECG beats are computed and
passed through a set of rules. The beat classified into a
particular class is determined by the beat falling in the
window of the three RR-interval sliding window followed by
set of rules discussed in the earlier section. The rules are
applied sequentially using for, if and else conditions in C++
programming language. After the detection of beat to a
Fig. 4. Laboratory setup for development of ECG beat monitoring
systems.
Record number Total samples
6000
4000
207 400
231 400
Total 10800
Biomed Eng Lett (2015) 5:271-280 277

determining these parameters True Positive (TP), True

Fig. 5. R-peak detection from MIT-BIH data.
particular class the window is updated consequently to
identify the next beat and the cycle continues. If any class of
beat other than the desired class is given as input to the
developed platform then it will be classified as normal.
The classification results of the proposed algorithm
implemented on the developed platform is presented in terms
of confusion matrix and discussed in the next section. This
matrix maps the classification of classified and misclassified
heartbeats into their subsequent classes which is further used
in their performance evaluation.
Performance evaluation
The testing of the hardware platform is evaluated using the
performance metrics parameters namely Sensitivity, Specificity
and Positive Predictivity. For the sake of validation and
Negative (TN), False Positive (FP), False Negative (FN) are
calculated from Table 4 where TP and TN represents the
correct classification of the normal and abnormal ECG
patterns. FN represents the misclassifications of normal as
abnormal beats while FP represents the misclassification of
the abnormal beats into normal beats. Sensitivity is the
correctly detected events among total no. of events. Specificity
refers to the rate of correctly classified non-events whereas
positive predictivity refers to the rate of correctly classified
events in all detected events. Using these definitions, sensitivity
and specificity can be defined as:
TP
- 100
Sensitivity (Se) = ------------------- (1a)
TP + FN
TN
Specificity (Sp) = -------------------- 100 (1b)
TN + FP
TP
Positive Predictivity (Pp) = -------------------- 100 (1c)
TP + FP
The accuracy of the classification system is given as:
Correctly classified beats
Classifier Accuracy = ------------------------------------------------------------- (2)
Total number of beats
The performance evaluation of each beat is summarized in
Table 5.
RESULTS AND DISCUSSION
In this study, real-time verification of beat classification
performance achieved, with the developed platform carried
out by the algorithms using MIT-BIH database is presented.

Table 4. Confusion matrix.

Correctly classified instances 10580 Accuracy : 97.98%
Incorrectly classified instances 220 Error rate : 2.02%
Predicted/Output Normal PVC VF 2 H.B Total
Normal 5921 61 13 5 6000
PVC 97 3878 17 8 4000
VF 1 9 389 1 400
2 H.B 7 0 1 392 400
Total 6026 3949 419 406 10800

Table 5. Performance evaluation for each class of ECG beat

Class of beats TP TN FP FN Se (%) Sp (%) Pp (%)
Normal 5921 4695 105 79 98.68 97.81 98.26
PVC 3878 6730 70 122 96.95 98.97 98.20
V.Fib./Fl 389 10369 31 11 97.25 99.70 92.84
2o H. B 392 10386 14 8 98 99.86 96.55
278
In particular, this platform allows to verify the detection of
arrhythmias which could be difficult using heart monitors.
Furthermore, the platform is investigated on a total of 10,800
ECG beats which includes the normal beats and three
arrhythmia beats taken from the database. The resource
utilization summary of implemented system achieved by
Xilinx tool is as follows: BUFGMUX's used is 1, I/O Pins
used are 99, Slice Flip Flops used are 1755 and the 4-Input
LUT's Logic used are 4224.
The snapshots of the classified beats displayed on TFT are
taken at the instant of time of their occurrence as shown in
right side of Fig. 6 for corresponding raw ECG beats as
shown in left side of the same figure.
The confusion matrix in Table 4 validates the performance
of developed hardware platform by classifying the beats into
their subsequent classes. Each row of the matrix in Table 4
represents the number of beats in the actual class taken from
MIT-BIH database i.e for example in case of total 6000
normal beats (first row) taken for testing, out of which 5921
are correctly classified into normal whereas 61, 13 and 5 are
misclassified into PVC, VF and 2o heart block beats
respectively. Similarly each column represents the number of
beats in the predicted class i.e for example, in case of normal
class in first column, 5921 are correctly classified into
normal whereas 97, 1, and 7 of PVC, VF, and 2o heart block
beats are misclassified into normal class. Thus total number
of 6026 beats out of 10800 beats are predicted in normal
class. Hence, it can be concluded from the matrix that the
developed hardware platform yields an overall accuracy of
97.96%.
On the basis of Table 4 and Eqs. (1) and (2), the performance
evaluation for each beat of a particular class is computed in
terms of sensitivity specificity and positive predictivity from
Fig. 6. Embedded hardware with inputs and outputs based on
experimental development in Fig. 4.
Biomed Eng Lett (2015) 5:271-280
the TP, TN, FP, FN which are presented in Table 5. The
results clearly shows that the overall accuracy of this aforesaid
platform is as high as 97.96% with overall sensitivity (Se),
specificity (Sp) and positive predicivity of 97.72%, 99.09%
and 96.46% respectively. It is worth to mention that the
proposed classifier system will work only for the beats of
desired class. The minimum classification accuracy reported
is more than 96% in case of PVC beat while 98.68%,
97.25%, and 98% in case of normal, VF and 2o heart block
beats.
The comparison between the various methodologies
depends on several factors like the database utilized, type
and number of records considered and several other factors.
Some of the researchers have also presented their study on
the data taken from the hospitals. In account of these factors,
a comparison between the proposed methodology with the
various methodologies implemented on the FPGA platform
evaluated on the benchmark of MIT-BIH arrhythmia database
is presented in Table 6 and discussed here.
In [19], only two classes of ECG beats (i.e Normal and
PVC) are classified on FPGA platform using the block
partitioning and Open Source ECG Analysis Software (OSEA)
methodology achieving a overall sensitivity and specificity
of 92.36% 95.54% respectively. In [20], three classes of
arrhythmias (i.e premature ventricular contraction (PVC),
fusion (F), and normal (N)) beats are classified using the
principal component analysis (PCA) and neural network
approach implemented on FPGA achieving an overall
accuracy of 97.66%. In [21], M. Cvikl et al. used the
geometrical and OSEA algorithms for classifying two classes
of ECG beats achieving an overall accuracy of 92.59%. In
[22], three classes of arrhythmia are classified on the FPGA
core using the wavelet-fuzzy approach achieving an average
accuracy of 85%. In [19-22], the results are presented only
for few specific recording taken from the MIT-BIH database
which is unfair due to the fact that variation in number of
records of different patients shall lead to degraded classification
performance. It is implicit from the table that implementation
of proposed methodology performs better by achieving an
overall accuracy of 97.98% and classifying four classes of
beats which is more in comparison with the various existing
methodologies provided in Table 6. While in the proposed
work, most of the records containing these three arrhythmia
(i.e PVC, V.Fib/V. Fl., 2o heart block) classes have been
considered which makes the proposed platform more adaptive
to the patients.
This work provides an efficient FPGA oriented SOC
based embedded platform for the accurate classification of
four class of heartbeats. Since the classification algorithm is
based on medical knowledge no training of the heartbeats is
required, rather only testing is performed for detection of
ECG beats in real time. While the methods presented in
Biomed Eng Lett (2015) 5:271-280
Table 6. Comparison of various methodologies implemented on FPGA.
Literature Method
Cvikl et al. [19] Block + OSEA
Ozdemir et al. [20] PCA + Neural Network
M. Cvikl et al. [21] Geometrical + OSEA
Nambakhsh et al. [22] Wavelet + Fuzzy
Proposed Thresholds + Rules
literature are supervised algorithms i.e they require training
and hence increases the computational complexity and time
required for classification. The platforms allow users to
perform assistive diagnosis solutions, such as establishing a
baseline level of abnormal beats. They can further utilize the
system to monitor their daily number of abnormal beats and
investigate on their own if lifestyle changes which can
enhance the health care for potentially dangerous arrhythmic
beats.
Since the platform is not specially designed for the
TSK3000A processor, it can be suggested that the processing
speed can be further increased. The greatest benefit from the
FPGA-based signal processing designs is the possibility of
multiplying the hardware cores. Namely, when the FPGA
device and the algorithm for a multi-channel ECG analysis
are carefully selected, the number of ECG channels for QRS
complex detection can be simply increased by multiplying
the hardware cores (detection logic) with no significant
degradation of the overall processing speed.
CONCLUSION
This study provides an enriched interface of hardware/
software implementation for real-time CVD monitoring. In
this paper, a FPGA oriented SOC based embedded platform
is developed and implemented for real time monitoring of
four ECG beats such as normal beat, PVC beat, V.Fib./Fl., 2o
heart block beat. The developed platform is evaluated in
terms of specificity, sensitivity and accuracy of 97.72%,
99.09% and 97.96% respectively. The future scope of this
work is to increase the number of detectable arrhythmias and
to fabricate a handheld and low cost diagnosis and monitoring
device which shall provide assistive diagnosis solution to
patients anywhere and at anytime.
CONFLICT OF INTEREST STATEMENTS
Raj S declares that s/he has no conflict of interest in relation
to the work in this article. Maurya K declares that s/he has
no conflict of interest in relation to the work in this article.
279
Number of classes Accuracy (%)
2 92.36 (SE)
3 97.66
2 92.59 (SE)
3 85 (Avg.)
4 97.96
Ray KC declares that s/he has no conflict of interest in
relation to the work in this article.
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