Scribd Logo
Upload

Welcome to Scribd!

  • Cadence Encounter Tutorial

    Uploaded by

    Gautam Navapara
    82 views10 pages
    This tutorial provides instructions for using Cadence Encounter to perform layout and routing of a synthesized Verilog netlist. The key steps include: 1. Importing the netlist and LEF files and setting supply nets 2. Specifying the floorplan and adding power rings 3. Placing standard cells and running clock tree synthesis 4. Routing the design and adding fillers 5. Verifying geometry and connectivity and generating timing reports 6. Saving the design for future use

    Original Description:

    Cadence

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    This tutorial provides instructions for using Cadence Encounter to perform layout and routing of a synthesized Verilog netlist. The key steps include: 1. Importing the netlist and LEF files and setting supply nets 2. Specifying the floorplan and adding power rings 3. Placing standard cells and running clock tree synthesis 4. Routing the design and adding fillers 5. Verifying geometry and connectivity and generating timing reports 6. Saving the design for future use

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    82 views10 pages

    Cadence Encounter Tutorial

    Uploaded by

    Gautam Navapara
    This tutorial provides instructions for using Cadence Encounter to perform layout and routing of a synthesized Verilog netlist. The key steps include: 1. Importing the netlist and LEF files and setting supply nets 2. Specifying the floorplan and adding power rings 3. Placing standard cells and running clock tree synthesis 4. Routing the design and adding fillers 5. Verifying geometry and connectivity and generating timing reports 6. Saving the design for future use

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 10

    Tutorial for Encounter

    1. Source the file from the folder where bash file is present: $ source .bashrc.cadence
    Note:
    Download .bashrc.cadence file from http://aimlab.seas.wustl.edu/courses/.bashrc.cadence :
    Create an empty file in your home directory.
    Copy the content from above link
    Paste it to the empty file you created
    Rename the empty file to .bashrc.cadence

    Note: Please follow the terminal to see the commands which encounter is executing on the terminal
    while we are modifying parameters in the GUI. Even look for errors on the terminal if any.

    2. Enter the following command: $encounter

    3. A window pops up which looks like the one as below


    4. Go to File -> Import Design and Add files to import your netlist file

    5. That is a synthesized Verilog (.syn.v) which is the netlist file of your design generated using
    Design compiler. Also you have to provide path for the LEF file from technology library.

    6. Set path to /project/linuxlab/cadence/vendors/VTVT/vtvt_tsmc180/vtvt_tsmc180_lef and


    select the vtvt_tsmc180.lef file from the folder.
    7. Also provide the supply nets as VDD and VSS in the appropriate boxes as below. Then click OK

    8. Load the Default.view for MMMC view definition file. Download it from the following link
    https://wustl.box.com/encounterview.

    9. You will be seeing a blank screen with horizontal lines on your main window (layout window) as
    above. Press f for full screen view of layout.
    10. Specify floorplan options in the Floorplan->Specify Floorplan and set the values as below.
    11. Set the global nets we defined as pins at Power->Connect Global Nets. Click Add to list, Apply
    and Close it.

    12. Go to Power->Add Ring and set Net pins to VDD VSS. Also you change width and spacing of
    power ring.
    13. We can also edit the pin placement in our design. Go to Edit->Pin Editor. Group some pins and
    you can place them on left or right side of the design. If you dont specify Encounter will be
    taking appropriate placement during optimization. Once done click OK

    14. Watch how your layout is changing while you are setting the parameters in the GUI
    15. Place the VDD and VSS in the design. Go to Route->Special Route

    16. Now we are all set to place the design. So we first go to Place->Place Standard Cell. Click OK.
    17. Clock tree synthesis: Run following commands in the terminal
    Download https://wustl.box.com/Clockctstch and place it in working directory.
    Download https://wustl.box.com/Clocktcl and place this in working directory.
    Run this tcl script line by line in the terminal.
    18. As part of routing go to Route->NanoRoute->Route. And click OK.

    19. You will see that your design got placed in the layout and also all the interconnections are done.
    20. Add Filler. Place -> Physical Cell -> Add Filler. Select filler cell name and click OK.
    21. Once Place and Route is done, verify the Geometry. Go to Verify->Verify Geometry. Click OK.

    22. Check the terminal for any violations and warnings.


    23. Verify the Connectivity. Go to Verify->Verify Connectivity. Click OK

    24. Check the terminal for any violations and warnings.

    25. Generating timing report


    26. Save your design for later use. File -> Save. Give an output file name for each floorplan, Place,
    Netlist and DEF file so that you can save all the optimization options and can load it later.

    You might also like