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Proceessors
Fifth generation digital signal processors from
Texas Instruments
16 bit floating point processors-using
p CMOS
technology
Have advanced Harvard architecture
Can execute 50 Million Instructions Per Second
(MIPS)
Features of TMS320C5xFam
mily of Digital Signal
Processors
16 bit CPU
20 to 50 ns single cycle instruction execuution time
Single cycle 16x16-bit MAC (Multiply and Accumulate) Unit
64k x 16-bit
16 bit external
t l program memory address
add space
64k x 16-bit external data memory addreess space
64k x 16-bit external IO address space
32kk x 16-bit
bi externall global
l b l memory adddddress space
2k to 32k x 16-bit single access On chip PROM
1k to 9k x 16-bit single access On chip program
p / data RAM
1k x 16-bit dual access On chip program m / data RAM
Synchronous , TDM and buffered serial ports
Programmable timer and PLL
IEEE standard JTAG ports
5V /3V operation with low power dissipaation and power down modes
DMA interfaces
100/128/132/144 pins in plastic QFP andd TQFP
Architecture of TMS320C5x
TMS320C5x has an advanced version of Harvard architecture (separate bus for data and program)
simultaneous access of data and program
On-chip memory (Internal) Program ROM ( 2k to 32k words) , Data/ Program Dual Access RAM
(DARAM) (1024+32 = 1056 words) , Data/ Program Single Access RAM (SARAM) (1k to 9k words)
On-chip peripheral (Internal) - clock generator , hardware timer , software programmable wait state
generators , parallel IO ports , Host Port Interface (HPI)
( , serial port , Buffered Serial port (BSP), Time
Division Multiplexed (TDM) serial port and user masskable interrupts
Architecture of TMS320C5x
TMS320C5x have a total meemory address space of 224k
(i l di
(including on-chip
hi memory)) with
ith addressability
dd bilit (memory
(
word size) of 16 bits.
03
0-3 03
0-3 nil
il RESERVED
S
6 6 IFR I
Interrupt Flag
Fl register
i
9 9 BRCR Bl k Repeat
Block R Counter
C registe
i er
12 C TREG0 T
Temporary reg 0(used
0( d for
f mu
ultiplicand)
l i li d)
15 F DBMR D
Dynamic
i bit manipulation
i l ti regg
Memory mapped registers
A 3 bit ARP
Contains logic ckts that decodees the instructions, manages the CPU
pipeline stores the stack of CPU
U operation and decodes the condition
operation due to parallelism in architecture,
a
The PC can perform 3 concurrrent or simultaneous memory opn in
any given machine cycle.
cycle
Fetch , read , write
16 bit program counter,16 bit status register STO and ST1,PMST-
Processor Mode Status Regisster, CBCR-Circular Buffer Control
Register
16x16 bit H/W stack
Address generation logic, instrruction register ,interrupt flag register
and mask register
STATUS register
2 -16
16 bit ST0,ST1-holds
ST0 ST1 holds the status of ALU
A result pointer for in direct addressing
result,
and various bit for interrupt ctrl ,hold mode
m and product shift mode
Status register can be stored in data mem
mory and leading for data mempory thereby
allowing processor status to be saved an
nd restored for subroutines
The LST writes to ST0 and ST1
SST- reads from ST0 and ST1
ST0 and ST1 each have an associateed 1-level deep
p shadow register
g stack for
automatic context saving when an interrrupt occurs
INTM and OVM bits in ST0
C,CNF,HM,SXM,TC and XF in ST
T1 can be individually set using SETC
instruction and can be cleared using CR
RLC instruction
On Chip Memoryy in TMS320C5x
On-Chip
Program ROM
The processors have internal-maskablee- program ROM (PROM) of size 2K to 3K
words.
The processor has an option for inccluding or excluding the on-chip PROM
addresses in the processor program mem
mory address space
The main purpose of PROM is to permanently
p Store the program code for a
specific
ifi application
li i during
d i manufacturi
f iing off the
h chip
hi itself.
i lf
The has an option of boot loading the content
c of PROM to internal/external RAM
during power-ON reset.
The content of the PROM can be proteccted so that any external device cannot have
access to the program code.
DATA /PROGRAM DUAL ACC
ACC
CESS RAM(DARAM)
The SARAM can be divided into blocck of 1k/2k words with continuous address.
address
The processor CPU can access one block for reading while writing in another
block.
block
On Chip peripherals of TMS320C5x
T Processors
Clock
Cl k generator
t
Consist of an internal Oscillator and a phase locked loop
Driven byy external crystal
y resonator circuit or
o supplied
pp byy an external clock source
The PLL generate an internal CPU by clocck by multiplying the clock source by a specified
factor
CPU-driven by high frequency clock & clock source -used as source for other peripherals
which run at low frequency clock
Hardware Timer
A 16 bit hardware timer with a 4 bit pre-scaller is available in TMS320C5x.
Programmable
g Timer ggenerates clock-rate between 1/2 & 1/32 of machine cycle
y rate
(CLKOUT1) depend on timer divide down ratio.
The timer can be stopped, restarted, reset or disabled by special status bit.
The processors has three registers to controol & operate the timer & they are Timer Control
Registers(TCR), Timer Counter Registers(TIIM), Timer Period Register(PRD)
Timer counter Register gives the current couunt of the timer
Timer Period Register defines the period off the Timer
The 16 bit Timer Control Registers controlss the operations of the timer
Software Programmable wait-State Geenerators
Generate/insert wait states in external bus cycles for interfacing with slow speed external
memory and IO devices.
The Processors consists of multiple wait
wait-st
sttate generating circuits , and each circuits is user
programmable to insert different number off wait states for external memory accesses.
Wait state generator can extend the externall bus cycles up to seven machine cycles.
Parallel IO parts
TMS3205Cx has 64k IO address space useed as 64 IO ports - 16 are memory mapped in
data memory space.
Each ports are addressed with IN and OUT
T instructions
Memoryy mapped
pp IO-accessed with anyy insttructions that reads from or writes to data
memory
TMS320C5x-generates a hardware signal IS
S during IO access to indicate a read or write -
through an IO port
TMS320C5x can easily interface with exterrnal IO devices through IO ports with minimal
external address decoding circuits.
Host Port Interface
Available on-TMS320C57S & TMS320LC557
HPI-8 bit parallel IO port-provides interface to a host processor for information exchange
b/w the Digital Signal Processors & the host processor
DSP-has 2k word-on chip memory that is accessible to both the host processor and DSP.
HPI is connected to this memory through a dedicated bus, so that
that-CPU
CPU works uninterrupted
while host processor accesses the memory from
f host port.
Serial Ports
Three kinds of serial ports-General purposee serial ports, Time Division Multiplexed (TDM)
serial port and Buffered Serial Port (BSP)
TMS320C5x contains atleast one-general
one general purpose,
purpose high sped,
sped full duplexed serial port-
port
used for direct communication with serial devices
d as codec, serial analog to digital & other
serial systems.
Continued.
With the
th help
h l off above
b regist
i ters
t ,att any one time,
ti t
two circular
i l
buffers can be defined. A Circullar Buffer Control Register (CBCR)
is used to enable / disable the ciircular buffers