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Abu Khari bin A'ain, Member, IEEE, *Chek T Lim, *Ng, Kok Hong, *Ng, Sheng Kwang, Liew Eng

Yew

Department of Electronics (INSEED)

Faculty of Electrical Engineering

Universiti Teknologi Malaysia

813 10 Skudai, Johor, MALAYSIA

Abstract This paper takes a look at the use of * Exhaustive

linear feedback shift registers (LFSR's) as test * Deterministic

pattern generators (TPG's) and signature * Pseudorandom

analyzers for built-in self-test (BIST). We also

propose a method to generate pseudorandom In exhaustive testing, all 2n input combinations

test patterns. The proposed method can for an n-input CUT are applied during the test

generate longer sequences of the same set of process. Exhaustive testing does not face the

test patterns. problem of random pattern resistant faults, and it

achieves 100% stuck-at fault coverage [2].

Keywords: LFSR, PRBS, BIST, ATPG However, test time becomes too long for CUTs

with large number of inputs. Test time can be

I. INTRODUCTION reduced by partitioning the CUT into subcircuits

and then testing each subcircuit exhaustively

THE process of testing a digital circuit will (pseudoexhaustive method). However, the fault

consist of applying successive sets of values to coverage for pseudoexhaustive testing is lower.

the primary inputs, and of observing the resulting Another category of testing techniques is

values appearing at the primary outputs. Each based on deterministic test set embedding. In

individual test, consisting of a set of input values deterministic test, the circuit under test (CUT) is

together with the corresponding set of correct, analyzed prior to testing to determine the

fault-free output values, is known as a test appropriate test set to be applied. After the test

pattern or test vector. A complete sequence of set has been obtained, the TPG is designed to

test patterns is called a test set. The central generate the predetennined test set. Various

problem of testing is the derivation of an techniques have been proposed to obtain the best

adequate test set for any particular circuit. This seeds and LFSR characteristic polynomials to

process is described as test pattern generation. cover a deterministic test set. However, these

Built-in self-test (BIST) denotes the approaches can only be applied to circuits with

ability of a circuit or system to test itself. It can small size or regular structures due to high

potentially eliminate the need for external test computational complexity of the search

equipment and introduces the capability for procedures [1].

testing devices after the circuit is integrated in a Pseudorandom testing is popular due to

system in the field (online testing). BIST is the simplicity of the linear feedback shift

gaining acceptance in the VLSI industry because registers (LFSRs) used as TPGs to generate a

of its many advantages [1]. For BIST in general, subset of the 2n test patterns. Fault coverage is

test patterns are generated on-chip by a test estimated by probabilistic methods. The number

pattern generator (TPG) and the responses of the of random patterns to be applied is decided by

circuit under test (CUT) is compressed and the detection probability of the faults [3].

analyzed by an on-chip signature analyzer. In terms of TPG hardware realization,

There are generally three strategies of two opposite architectures with respect to area

testing: overhead and testing time are the ROM based

architectures and the counter-based architectures.

The later architecture uses a ROM to store the

*Chek T Lim, Ng, Kok Hong, Ng, Sheng Kwang are Iwith vectors generated by an external automatic test

Intel Sdn. Bhd Penang.

ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

pattern generator (ATPG). High fault coverage able to generate a precomputed set of

and short testing times can be achieved. But the deterministic test vectors obtained with an ATPG

area overhead introduced by this method is in tool [6]. It provides a relatively simple way of

general prohibitive for practical applications. generating deterministic test vectors without

having to use complex procedures. It is also able

In counter-based architectures, the test

patterns are generated by a counter, which to produce the all-zero's test vector without the

introduces a small area penalty. The main need for additional circuitry (unlike conventional

disadvantage of this method is that long test LFSR). However, the use of LFSROM requires

sequences may be required to achieve an extra circuitry, especially for the MUX and its

related selector circuitry. Once implemented, the

acceptable fault coverage, which results in longer

testing time. set of test patterns produced is fixed and

unchangeable except by rewiring the OR gates

The most used BIST architectures are the

LFSR based architectures [4]. For these network. This means that once embedded in the

architectures, good fault coverage can be chip, the test patterns cannot be changed.

achieved in most cases and several techniques Shi and Zhang presents a reseeding

have been proposed to reduce the test time or to technique for LFSR-based test pattern

increase the fault coverage of LFSR based generation, which can generate pseudorandom

architectures. vectors in normal mode while also being able to

This paper is organized in the followingproduce the seed of a group of test vectors in

way. A brief review on previous architectures ofjumping mode [7].

LFSR based TPG is presented in part II. The Wang and Lee present an LFSR-based

proposed architecture of an LFSR-based TPG TPG that can accelerate the application of

that is used to generate pseodorandom patterns isdeterministic patterns from the LFSR to a scan

chain. The target scan chain is divided into

presented in part III. Initial experimental results

are explained in part IV. Future work is multiple sub-chains and an LFSR-based multiple

highlighted in part V and conclusion in part VI. sequence generator is used to generate all the

subsequences required by the sub-chains. A

II. PREVIOUS WORK generalized relationship between the bits in the

original scan chain and the state of the LFSR is

Wang and McCluskey discussed the derived such that the bits generated by an LFSR

theory of both standard and modular LFSRs. A in any future clock cycle can be pre-generated by

hybrid TPG design of standard and modular the proposed TPG [8].

LFSRs is also proposed. This design is used to

generate maximum length sequences and can be III. PROPOSED ARCHITECTURE

reconfigured to include the all zeros state for

exhaustive testing. Compared to the standard or

modular LFSR that uses m 2-input XOR gates,

the hybrid design uses only (m+l)/2 XOR gates

[5].

Chen and Gupta proposed a TPG design

called "input reduction". The proposed design

partitions the inputs of a CUT into groups,

similar to pseudo-exhaustive testing, where each

group corresponds to a test signal. However,

unlike pseudo-exhaustive testing, which only Rn-I Rn2 RIR1

combines unrelated inputs (inputs that are not in Fig. 1 Generic block diagram of proposed TPG

the same cone) into a test signal, the proposed structure.

technique analyzes the CUT to determine

compatible inputs to be combined into a test The proposed TPG structure is presented

signal, even if the inputs belong to the same cone in Figure 1. The structure is based on that of a

[1]. conventional LFSR signature analyzer. The TPG

Dufaza and Chevalier presents a TPG operates on two clock signals; one is the normal

design composed of a simplified LFSR clock for the LFSR registers and another clock

associated with an OR network and a set of signal, which is connected to the input D(X). The

multiplexers, called an LFSROM. The design is

ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

D(X) clock is set at a lower frequency from the The test patterns in Table I are generated

register clock. by a TPG using a standard LFSR with a

One characteristic of this TPG structure characteristic polynomial of X3+X2+1 and a

is that it can generate longer sequences of the seed value of Q2QlQo = 100. The frequency of

same set of pseudorandom test pattems. A TPG the D(X) clock is half of the register clock (f= 1/2

with an n stage LFSR can generate a maximum or t =2).

set of 2" _ 1 number of test vectors. In From the table, we see that the maximum

conventional LFSR TPGs, this set of test vectors length sequence of the conventional LFSR is 7

will then produces a maximum sequence length vectors. For the proposed TPG, the sequence

of 2" - 1 patteins, before the sequence repeats extends to a total of 14 vectors before the

itself. In the proposed TPG, this maximum sequence repeats itself.

length sequence can be extended to beyond 2" -1 Another thing to note is that the

patterns with the manipulation of the D(X) clock. proposed TPG is able to generate the all zeros

The total number of test vectors is still a state autonomously and is not stuck in the all

maximum of 2" -1, but there will be a duplicate zeros state.

of certain vectors within the same sequence.

Table I shows an example of the simulated IV. PRELIMINARY RESULTS

sequence generated by a conventional LFSR as

compared to the proposed TPG. Preliminary testing has revealed a

LFSR Conventional Proposed TPG

-[ S-

clockc LFSR sequence sequence, t-2 ratio and the maximum length of the sequence

Q2QxQo Q2QIQo generated by the proposed TPG.

Taking the frequency of the register

clock as f; and the frequency of the D(X) clock

2 asfDm, the ratio ofthe two clocks is r =fJIfDm.

-3 Table 2 shows some different values of r

and their corresponding sequence lengths, which

100 were obtained through simulation. In this

6 example, the LFSR used has the characteristic

7 1 00 polynomial of X3+X2+1 with a maximum length

-8 -- 1-10- 1 sequence of 7.

10 01 1 R Sequence length

11 I101 Conventional LFSR 7

2 14

123 -0 10 3 21

_14 ~ ~~100 10 0 I

4 28

15 1 10 010 5 35

16 1 1 1 011 6 - 42

17 011 101 7 14

18 101 1 10 8 56

19 010 I 11 10 70

20 00 1 1 1 1 14 14

21 1 00 011 21 21

22 1 10 001 28 28

23 I 1 1 100 Table 2: Different values of r and their respective

24 01 1 010 sequence lengths

25 101 00 1

26 010 000 Preliminary results suggest that for

27 001 000 values of r that is not multiples of 7 (the

Table 1 Maximum length sequences generated maximum length of a conventional sequence),

by TPG the corresponding sequence length is a multiple

of r and 7, which is the length of the

conventional sequence. For r - 7, the sequence

ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

sequence length is equals to r. Though the

number of test sequence is higher, it comes at the r=3

cost of testing speed which is now slower.

While the proposed TPG is capable of

cycling through the all zeros state, it does have

its own trivial sequences which will cause it to

be "stuck" in a similar manner that a

conventional LFSR is stuck at the all zero state.

The occurrence ofthese trivial sequences

is on condition of certain initial states at different

values of r. Figure 2 shows the state diagram of

an LFSR to illustrate how this can happen.

r=4

Fig 2 State diagram of LFSR with values of r

characteristic polynomial X3 + X2+ 1

V. FURTHER WORK

If the initial state of the LFSR is Q2QIQo

= 101, and at the first register clock, the input at Further work on this proposed TPG will

D(X) is 0, then the next LFSR state will be involve further testing using different lengths of

Q2QIQo = 010. If at the next register clock the LFSRs. LFSRs with non-primitive polynomials

input at D(X) is 1, then the LFSR will switch will also be tried out.

back to 101. Subsequently, an alternating stream At present, the D(X) uses symmetrical

of O's and l's will cause the LFSR to be stuck clock signals as input. In future, the input at

within these two states. D(X) will be tried out with asymmetrical input

For an r of 2 (D(X) frequency is half of signals to observe their effects on the LFSR

register clock frequency), the input at D(X) is output.

effectively an alternating stream of O's and l's, The occurrence of trivial sequences

as shown in Figure 3 below. should also be looked into. Seed values that will

cause trivial sequences should be identified so

that they will be avoided.

Towards the end, the performance of the

Register cik TPG will be evaluated by testing it on

DX a X0 0 0 benchmark circuits.

VI. CONCLUSION

Fig 3 Positive edge register clock with D(X)

clock at half frequency TPG methods, which can generate longer

sequences of test patterns, have been proposed.

The TPG operating at different values of This TPG architecture is derived from an LFSR

r will have different sets of trivial sequences, based signature analyzer, by manipulating the

some of which is shown in Figure 4. input of the analyzer. Preliminary results have

shown a relationship between frequencies of the

ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

LFSR register clock and the input signal to the Width Compression in BIST", Proceedings of

analyzer. the 1999 IEEE International Symposium on

Circuits and Systems, 1999. ISCAS '99, Volume:

ACKNOWLEDGEMENT 1, pp. 114 -118 vol.1 (1999)

[51 L.-T. Wang and E.J. McCluskey, "Hybrid

Thank you to Intel Penang for providing research designs generating maximum-length sequences",

fund and professional guidance. IEEE Transactions on Computer-Aided Design

of Integrated Circuits and Systems, Volume:

REFERENCES 7, Issue: 1 pp. 91 - 99 (1988)

[6] C. Dufaza and C. Chevalier, "LFSROM

[1] C.-A. Chen and S.K. Gupta, "A methodology Basic Principle and BIST Application", Design

to design efficient test pattern generators", Automation, 1993, with the European Event in

Proceedings of International Test Conference, ASIC Design. Proceedings. [4th] European

pp. 814- 823 (1995) Conference on; pp 211 -216 (1993)

[2] I. Hamzaoglu, J.H. Patel, "Reducing test [7] Y. Shi and Z.Zhang, "Multiple Test Set

application time for Built-in-Self-Test test Generation Method for LFSR-Based BIST",

pattern generators", VLSI Test Symposium, 2000. Proceedings of the ASP-DAC 2003. Asia and

Proceedings. 18th IEEE, pp. 369-375 (2000) South Pacific Design Automation Conference,

[3] B. Vasudevan, D.E. Ross, M. Gala and K.L. 2003, pp. 863 -868 (2003)

Watson, "LFSR based deterministic hardware for [8] W.L. Wang and K.J Lee, "Accelerated Test

at-speed BIST", Digest of Papers, Eleventh Pattern Generators for Mixed-Mode BIST

Annual 1993 IEEE VLSI Test Symposium, pp. Environments", Proceedings of the Ninth Asian

201 -207 (1993) Test Symposium 2000 (ATS 2000), pp. 368 - 373

[4] P. Flores, H. Neto, K. Chakrabarty and J. (2000)

Marques-Silva, "Test Pattern Generation For

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