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2016 Monolithic Power Systems, Inc. Patents Protected. All rights reserved.
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Linaro organisation, with ARM, aims for end-end open source cused on delivering an end to
end, cross-vendor solution for
Innovative use of MEMS for mid-range pressure sensing tem design benefits.
Available as a bare die, the
D istributor RS Components
is to be sole supplier of Sie-
mens' SIMATIC IOT2020 IoT gate-
says it is extending its portfolio of
industrial IoT (Internet of Things)
devices with the exclusive supply
ing the simplest way for engineers
to get started with the industrial
IoT and meet the challenges of an
as Java, C++ and JSON. This
openness enables various com-
munication possibilities to further
way targeting arrangement. increasingly connected world. The automation hardware or sensors
industrial engineers, education RS comments that a key global IOT2020 is an open and flexible via Modbus, PROFINET or other
and the maker community; RS trend in IoT technology open IoT gateway that is designed for protocols, or even the direct con-
source software, continuous industrial operation nection to cloud solutions via
including easy-to-use and comes with the appropriate MQTT or AMQP. In addition to the
IDEs, and ever-improv- certificates. It can be used to re- on-board interfaces the IOT2020
ing hardware. Siemens trieve, process, analyse and send is expandable with Arduino shields
and RS joined forces data to almost any kind of device and via an on-board PCIe port.
to offer an IoT plat- or network due to its various inter- The 89.00 device, which is an
form for the engineers faces including Ethernet, USB and industrial certified product with UL
of tomorrow, and the micro SD. The gateway is compat- and CE approval,
IOT2020 encapsulates ible with open source software is suited for edu- Complete
article, here
these trends, provid- such as the Arduino IDE and Yocto cational purposes.
SoCs and development kits for vehicle-to-everything comms ers can now develop systems that
support the corresponding V2X
Silicon Labs takes IoT RTOS in-house with Micrium purchase tools will continue to be available
to all silicon partners worldwide,
PM2.5
CO2 VOC
RH / T
Figure 1. Time allocated to embedded system design tasks. Source: UBM Electronics Embedded Markets
Study 2015
agement service that enables tency and determinism to events The article continues by explor-
timely task context switching. than a generic OS and this is ing the aspects ot real time that
Timeliness is expressed as la- why they can be found running are pertinent in the IoT context,
tency and determinism mea- on devices handling time critical, and notes the advantages of
sures of the speed of switching hardware specific event process- using an off-the-shelf solution.
between tasks and the time vari- ing and digital signal processing Click for pdf.
ance or jitter in the transition. An algorithms.
RTOS can respond with lower la-
A survey of MEMS
accelerometers reveals that
the lowest noise and lowest power
key uncertainty criteria, the time it
takes to fill that array has a direct
impact on the overall settling time.
six times lower than the energy
requirement for the low-power
component (ELP).
continuous operation. Second, for
measurement cycle times that are
greater than ~0.13 seconds, the
are not available in the same For example, the Allan Variance ADXL355 solution will consume
product at this time. curve in the ADXL355 datasheet less power. The bottom line is that
suggests that an averaging time with an open mind, sometimes
When comparing a low-noise of 0.01 seconds will reduce its we can achieve the lowest power
accelerometer, such as the uncertainty to less than 100 solution, by using the lowest-noise
ADXL355, with a popular low- g. Achieving a similar level of (highest performing) components.
power accelerometer, the uncertainty in the low-power
ADXL355 presents the following sensor will require an averaging Equation 3 captures the power
trade-offs: time that is 81 times longer dissipation that will come from
than the ADXL355, since noise these energy levels, with respect
- At 20 g/Hz, the noise density reduction in an averaging filter is to the time between each
is 9x lower. proportional to the square root of measurement (T).
- At 338 W, the power dissipation the averaging time.
is ~13x higher.
Equations 1 and 2 quantify this
For applications that will power trade-off in terms of the energy
cycle their sensors to save energy it takes for each sensor/filter
when they are not in use, the combination to support this
noise/power relationship can level of precision in a single The graphical view of this Figure 1. Power dissipation vs
actually be quite different. This data record. The results of this relationship (Figure 1) offers a measurement cycle time
difference comes from a source estimation are quite interesting, couple of interesting observations.
that may be surprising to some: because the much shorter First, at measurement cycle
settling time. In applications that averaging time (tLP = 81 x tADXL355) times (T) that are lower than
need to average a sequential causes the energy requirement 0.81 seconds, the low-power
array of sensor data to achieve for the ADXL355 (EADXL355) to be device will be supporting
quence through their cycle of one on, then the the processor via a lookup table based on the There are several components which contrib-
other, then both off, about thirty times per sec- BeerLambert law. The hardware and software ute to the absorption of light, listed below :
ond which allows the photodiode to respond to acquire SpO2 data will be included in the 1. Oxygenated haemoglobin in the blood
to the red and infrared light separately and also further extension of this application note. 2. De-oxygenated haemoglobin
adjust for the ambient light baseline. (Pulse 3. Absorption that is not from arterial blood
oximetry, n.d.) The amount of light that is trans- Signal processing 4. O
ptical attenuation due to scattering, geo-
mitted (in other words, that is not absorbed) is Some initial signal processing is required when metric factors etc.
measured, and separate normalized signals are trying to extract oxygen concentration from
produced for each wavelength. These signals the signal coming from a finger sensor. The Figure 4 shows the main block diagram of the
fluctuate in time because the amount of arte- calculations follow Beer-Lambert Law Pulse Oximeter application using the GreenPak
rial blood that is present increases (literally (Matviyenko, 2011) to assess the percentage device, SLG46140.
pulses) with each heartbeat. By subtracting the of the oxygenated blood. Mathematically given
minimum transmitted light from the peak trans- as:
mitted light in each wavelength, the effects
of other tissues is corrected for. The ratio of
the red light measurement to the infrared light Figure 3 shows how light is absorbed in the
measurement is then calculated by the proces- finger.
sor (which represents the ratio of oxygenated Figure 4. Block diagram
haemoglobin to deoxygenated haemoglobin), of the pulse oximeter
and this ratio is then converted to SpO2 by
and ASICs. Traditionally, the conversion from An isolated half-bridge with a cur-
48V down to PoL uses a two-stage approach. rent-doubler output topology is ex-
This entails a brick-type bus converter perform- tremely advantageous for this type of
ing an isolated conversion between 48V and an application, as shown in Figure 1. In
intermediate voltage such as 12V or 9V using a this topology, a GaN half-bridge (using
hard-switched half-bridge or full-bridge topol- the LMG5200) connects to the trans-
ogy, or a resonant topology such as inductor- former, which is referenced to a split
inductor-capacitor (LLC). Next, a multiphase capacitor network to provide voltage
buck converter converts down to PoL at up to balancing.
200A, while handling the transient response
requirements of a highly dynamic digital load. The secondary side connects in a
current-doubler synchronous rectifier,
The traditional solutions beginning-to-end ef- which enables better heat distribu-
ficiency is a product of the two individual stag- tion, a simpler transformer design and
es. With the first stage peak efficiency of 96% the advantage of foregoing high-side
and the multiphase buck stage peak efficiency switches, as both are ground refer-
Figure 2. This figure shows a half-bridge with current-
close to 92%, the total efficiency is only 88% enced. Since the charging current of doubler output.
(Figure 1) at frequency ranges between 100 the capacitor is the sum of the two
to 200 kHz. The two-stage solution also has a inductor currents, which are 180 out of phase, ferred choice is GaN FETs, as they present the
larger board-area footprint. the output voltage ripple is halved. advantage of zero recovery loss. Alternatively,
using silicon FETs requires very tight dead-time
A single-stage approach would improve Figure 2 shows synchronous rectifiers in- control.
efficiency and reduce board area. While this stead of diodes. The average current through
has been the desired target for a long time, these rectifiers can reach 25A, which a diode This article continues by demonstrating the
silicon-based designs have not demonstrated would not be capable of sustaining in an ap- waveforms in the conversion path, and looking
a compelling solution. GaN enables an elegant plication. Note that the rectifiers will be operat- at hardware design, converter efficiency and
new topology that offers PoL-level transient ing in continuous conduction mode and will be dynamic performance click for pdf.
response from a single, efficient 48-V to PoL subject to reverse recovery; therefore, the pre-
conversion stage, while running at higher fre-
quencies close to 600 kHz, further aiding size
Download PDF Find GaN FETs for POL applications
reduction.
of Article on EETsearch
Figure 1. Typical block diagram of an IEEE 802.3bt introduces four new high power PD
802.3bt PSE-PD link classes, bringing the total number of single-
signature classes to nine as shown in Table 1.
802.3bt introduces two new PD topologies: Classes 5 through 8 are new to PoE and trans-
single-signature and dual-signature. That is, late to PD power levels ranging from 40.0W to
a single-signature PD is an 802.3bt PD that 71.0W. PSEs still have their choice of using
shares the same detection signature, classi- the physical layer (i.e. 5-event classification for
fication signature and maintain power signa- 71W) or data link layer (i.e. link layer discovery
ture (MPS) between both pairsets, whereas a protocol, LLDP) to classify PDs, and PDs still Table 1. IEEE 802.3bt PD classes and power
dual-signature PD is an 802.3bt PD that has need to be able to support both classification levels
independent signatures between both pairsets. schemes in order to be compliant. 802.3bt
New 802.3bt designs will, no doubt, gravitate PDs may also implement an optional extension
towards the simpler and more cost-effective of the physical layer classification, known as This article continues by exploring low-power
single-signature topology, which only calls for a Autoclass, where an 802.3bt PSE measures the configurations, how the new standard may
single PD interface. Dual-signature PDs require actual maximum power draw of a connected maximise available power, and backward-com-
two parallel PD interfaces, one for each pairset, PD. This handy power management feature patibility issue, ansets out what is practical to
where the power from two PSEs are summed allows, for example, a PSE to allocate leftover market immediately. Click for pdf download.
together after each PD interface. Essentially, power to additional light bulbs if it knows that
the dual-signature topology uses, for example,
two 25.5W PDs to make a single 51W PD a
Download PDF Find POE 802.3BT 71W Standard
complex solution that can cost twice as much
as a single-signature 51W PD. of Article implementations on EETsearch
ent that ADAS applications require a lot more (Drive PX) provide adequate computational the risks outlined above. On the other hand,
processing power than traditional applications. power in the Teraflops range for the data-paral- portable and high-level design methods are
lel parts of ADAS applications. However, apart necessary to enable cost-effective application
Currently, it is very hard to predict which from lacking sufficient safety features, these development. These high level design require-
high-performance hardware architectures will devices are rather cost-intensive regarding their ments mandate modifications of the embed-
prevail for these kinds of applications. However, power consumption and purchasing price. Typi- ded compilers that were originally designed for
it is clear that compiler support will be required cal architectures for safety-critical applications traditional embedded applications.
for all architectures because ADAS applica- up to ASIL-D (incl. AURIX or RH850) have not
tions must be produced in a reusable and yet utilized some hardware based opportunities This brings us back to the initial question
cost-efficient manner. This mandates the use of to achieve higher data rates because these will concerning which new capabilities an embed-
abstract, portable design methodologies (e.g. be hard to certify according to ASIL-D. ded compiler must provide in order to meet the
C++11/14), model-based design and additional above-mentioned requirements. A necessary,
technologies including parallel programming OEMs or large suppliers of ADAS systems new compiler feature is the need to support the
(e.g. OpenCL, Pthreads). Furthermore, highly are therefore in danger of selecting an architec- typical code structures of ADAS applications
optimized, certified libraries will be required ture that may fail in the market because it is too in order to create highly-efficient code for this
to implement standard operations efficiently, large, too expensive or cannot meet the safety kind of application.
safely and with maximum hardware indepen- requirements. On the other hand, there is a
dence. risk to select an architecture that fully supports This article continues with a discussion of
safety-critical applications but is too small for the structure to be expected of the code in an
As ADAS applications intervene with the the more demanding computations. During the ADAS application, and looks at compiler op-
driving process, these applications and the development process, it might turn out that the timizations, especially as they relate to writing
hardware used to execute them must adhere envisioned application cannot be implemented effective and dependable parallel code. Click
to relevant safety standards (ASIL-B or higher; for efficiency reasons. for pdf
ISO 26262).
Thus, the requirements of ADAS projects are
Finding a suitable hardware quite complex. On the one hand, it is manda-
architecture tory to create very efficient, target specific
There is a risk for companies developing ADAS code, to meet all safety goals and to minimize
applications, associated with the fact that no
specific hardware architecture has prevailed
Download PDF Find Compilers for ADAS
until now. In general, major hardware accel-
erators including the NVIDIA GPU derivatives of Article on EETsearch
The U2 adder sums V(D) and the capacitor voltage V(C) with a gain of
two, defined by R7 & R8. Its output charges C1 through R9. With V(D) at
V(U1Out), the capacitor voltage will describe a linear-slope line, forming
The hysteresis band sets the amplitude of the triangular waveform across C1. a triangular waveform.
The adder input resistors R5 & R6 divide both voltages by two. The
Barkhausen stability criterion requires unity gain to perform oscillation, so
the adder gain must recover this loss:
The addition process can be described as two time functions: one from
T0 to T1, where V(C)T0 = -HsV and V(C)T1 = +HsV due to the positive va-
lue of V(D), and the other from T1 to T2, which reverses the process: V(C) At this maximum frequency, the adder output current through R9 & C1
T2 = -HsV, due to the negative value of V(D). Each integral must equal must be drivable by the op-amp. If necessary, calculate the RC impe-
zero because a DC offset is not expected. dance and C1 value in this example, to meet 2 k total: R9 = 1 k, XC
= 1 k.
Solving the general form of the equation, where V(C) initial value is zero
and V(D) toggles between positive and negative: The solution for V(C) is
a linear function of V(D) and time. V(D) toggles between positive and ne-
gative when it reaches HsV. If V(D) increases, the frequency will increase
too.
Duty-cycle adjustment is made by adding a DC component to V(D)
C1 Frequency through R4. The usable adjustment range is about 10%-90%.
10F 10-50 Hz
1F 100-500 Hz
0.1F 1-5 kHz
0.01F 10-50 kHz
The op-amps slew rate limits the frequency of this application. The com- Arturo Rivera is a professor at Universidad Nueva Esparta and owner of a
parator output must maintain a square shape, so the minimum period can company manufacturing DC-DC converters.
be defined using the total excursion and a factor of 10:
Maxim's 1-Wire interface meets Arduino and mbed Heterogeneous inside & out cores
meet many-core needs
M axim Integrated has posted details of its reference design,
MAXREFDES132#, which provides a platform for interfacing with
the company's 1-Wire devices, 1-Wire Evaluation Kits (EV kits), and iBut-
I magination Technologies has added the MIPS Warrior I-class I6500
CPU to its IP offering; a multi-threaded, multi-core, multi-cluster design
that promises increased levels of system efficiency and scalable comput-
ton devices using the DS2484 IC-to-1-Wire master, or a bit-bang master ing for many-core heterogeneous designs. The I6500 provides a highly
on D2 of the Arduino form-factor pinout. Use the design with 1-Wire net- scalable solution which can coherently implement optimized configura-
works, data logging, and for rapid pro- tions of CPU cores within a cluster this is
totyping. Maxim says that its 1-Wire bus what Imagination tags Heterogeneous Inside'
continues to flourish in the era of IoT. as well as a variety of configurations of CPU
This unique protocol provides communi- clusters and GPU or accelerator clusters on a
cation and power along chip depending on the require-
a single wire, at relative- article,
Complete
here
ments of the system (Hetero- Complete
article, here
ly long distances. geneous Outside).
Intel samples Stratix 10 FPGAs on 14nm node First 1000V silicon carbide MOSFET
24-pin MCUs with IOs to support up to 13 sensors QM series; TDKs revisit of modular PSU concept
AC/DC PSU outputs 40W from 4.5 sq in footprint RS-485 transmitters support 20 Mbps,
draw under 0.6 mW
X P Power's ECF40 series of single-output 40W ultra compact AC-DC
power supplies are open frame convection-cooled units capable of
delivering their full output power without the need for any external forced
E xar's high-speed RS-485/RS-422 transmitters, XR33193, XR33194
and XR33195, operate from a 3.3V supply and draw only 180 A
(375 A maximum) of supply current. All transmitters feature a shutdown
air flow up to +50C. XP claims the units as the smallest 40W open frame mode that consumes less than 2 A whenever the transmitters are dis-
power supply available, at 76.2 x 38.1 x 28.0 mm. XP intends the unit abled. The family is available in 3x3 mm 6-pin TSOT23 packages, ideal
for a range of applications in the healthcare, for high-speed point-to-point RS-485 applications
industrial and technology sectors, rating it where space is a concern. The XR33193/94/95
for an operating temperature range of -40 to offer 250 kbps, 2.5 Mbps and 20 Mbps data
+70C. The range comprises six models pro- rates; XR33193 and XR33194 have slew-limited
viding all the popular nominal outputs; XR33195 features 25
output voltages from +12 to Complete
article, here
nsec propagation delay and 5 Complete
article, here
+48 VDC. nsec driver-output skew.