Sheet

1 of 14

The MOS Transistor

These devices are known as FET’s (Field effect transistors), which consist of three regions
source, drain and gate. The resistance path between the drain and source is, controlled by
applying a voltage to the gate. This varies the depletion layer under the gate and thus
reduces or increases the conductance path. The FET input impedance (unlike the BJT which
is a few KΩ) is very high (~MΩ’s) and as a result the gate current can be considered as zero.

As per the BJT the FET is best described by it’s Output I-V DC characteristics (N-type
enhancement characteristics shown below), however things are complicated by the fact there
are two types of FET depletion and enhancement that are both available as N-type or P-type
devices. For low frequencies the enhancement devices is more commonly used (Depletion
mode types will be described when discussing microwave devices).

VDS = VGS − VT

Saturation region
ID

IDSS VGS3

VGS2
Increasing VGS
Triode
Region VGS1
Or
Linear
Region

VGS0 = 0V

VDS
Cut-off region

(1) Cut-Off Region – In this region the gate voltage is less than the pinch-off voltage Vp and
therefore very little current flows.

(2) Triode Region – In this mode the device is operating below pinch-off and is effectively a
variable resistor. ROUT is ~ linear but only over a small range of VDS.

(3) Saturation Region – This is the main operating region for the device. The drain voltage
has to be greater than the gate voltage less the pinch-off voltage – this sets the minimum
supply voltage. The curves in the saturation region can be extrapolated to a point 1/λ, where λ
is known as the ‘Channel length modulation parameter, (units V-1), - this is analogous to the
BJT Early voltage.
 Sheet
2 of 14

ID
Increasing VGS

1/λ VDS

Referring to the saturation region we can assume the response is approximately linear such
that the:-

1
= Device output resistance R O
slope of curve

slope of curve = Device output conductanc e G O

If we assume a straight line of the form y = - mx + c then

⎛ 1 ⎞ 1 ID
VDS = - ⎜⎜ ⎟⎟.ID + therefore G O = −
⎝ GO ⎠ λ ⎛ 1⎞
⎜ VDS − ⎟
⎝ λ⎠

λ is typically in the region 0.001 to 0.01

1 ID ID
then if >> VDS − = − G O ≈ λ.ID ie small conductanc e, high resistance
λ ⎛ 1⎞ 1
⎜ VDS − ⎟ −
⎝ λ⎠ λ

To complete the model for the FET we need to add the term for the linear region which, is
dependant on the device mobility and gate dimensions.
 Sheet
3 of 14

(1+ λ.VDS )
ID

Vgs-VT

ID = IDQ +∆ ∆
IDQ
IDQ + G O .VDS
Slope = gm

IDS + λ.IDS.VDS

= IDS.(1 + λ.VDS )
VDS

⎛W⎞⎡ V ⎤
µ O .C OX .⎜ ⎟.⎢(VGS - VT ) - DS ⎥.VDS
⎝ L ⎠⎣ 2 ⎦

⎛W⎞⎡ V ⎤
ID = µ O .C OX .⎜ ⎟.⎢(VGS - VT ) - DS ⎥.VDS (1 + λ.VDS ) non - saturation/linear region only
L
⎝ ⎠⎣ 2 ⎦

Where µ O = Surface mobility of device

ε OX
C OX = = capacitance per unit area of gate oxide
t OX

W = Effective channel width

L = Effective channel length
W/L = Known as the aspect ratio
VT = Device threshold voltage
λ = Channel length modulation parameter

For saturation region ie VDS > (VGS-VT)

 Sheet
4 of 14

ID = β[VGS - VT ] (1 + λ.VDS )
2

⎡W ⎤
µ O .C OX ⎢ ⎥
⎣L⎦
Where β = Known as the transconductance parameter
2

Sometimes re - written as

⎡W ⎤
K P .⎢ ⎥
⎣L⎦
ID = [VGS - VT ]2 (1 + λ.VDS )
2

Where K P = µ O .C OX Known as the Intrinsic transconductance parameter

Usually λ.VDS << 1 so

ID ≈ β[VGS - VT ]
2

The following page shows some typical values of the above parameters for use with a level 1
MOS model. The ADS version of this model is also shown
 Sheet
5 of 14

Typical MOS Spice Parameters

n-Well CMOS Level 1 SPICE Model parameters

Level 1 SPICE n-channel p-channel

Units
Parameter MOSFET MOSFET
Gate oxide thickness
150 150 Angstrom
TOX
Transconductance
50 x 10-6 25 x 10-6 Amp/V2
Parameter KP
Threshold Voltage VT0 1.0 -1.0 Volts
Channel-length
0.1/L 0.1/L
modulation parameter V-1
L in micron L in micron
LAMBDA
Bulk Threshold
0.6 0.6 V1/2
Parameter GAMMA
Surface Potential PHI 0.8 0.8 V
Gate-drain overlap
5 x 10-10 5 x 10-10 F/m
capacitance CGDO
Gate-source overlap
5 x 10-10 5 x 10-10 F/m
capacitance CGSO
Zero-bias planar bulk
depeletion 10-4 3 x 10-4 F/m2
capacitance CJ
Zero-bias sidewall bulk
-10
depletion capacitance 5 x 10 3.5 x 10-10 F/m
CJSW
Bulk junction potential
0.95 0.95 V
PB
Planar bulk junction
0.5 0.5 None
grading coefficient MJ
Sidewall bulk junction
grading coefficient 0.33 0.33 None
MJSW
 Sheet
6 of 14

Var
Eqn VAR
MOSFET_NMOS
VAR2
W=100 MOSFET1
Model=MOSFETM1
L=0.5
Length=L um
LAMBDA=0.1/L
Width=W um
LEVEL1_Model
Ad=
MOSFETM1
As=
NMOS=yes Cgbo= Kf=
Pd=
PMOS=no Rsh= Af=
Ps=
Vto=1 Cj=1e-4 Fc=
Nrd=
Kp=50e-6 Mj=0.5 Rg=
Nrs=
Gamma=0.6 Cjsw=5e-10 Rds=
Mult=
Phi=0.8 Mjsw=0.33 Tnom=
Region=
Lambda=LAMBDA Js= N=
Temp=
Rd= Tox=150e-10 Tt=
Mode=nonlinear
Rs= Nsub= Ffe=
Cbd= Nss= Imax=
Cbs= Tpg= AllParams=
Is= Ld=
Pb=0.95 Uo=
Cgso=5e-10 Nlev=
Cgdo=5e-10 Gdsnoi=1

As with the BJT it is possible to simulate a device under ADS to produce the device Output I-
V curve trace for a typical N-type MOS 3.3V 0.25um process enhancement device. The Spice
data for the MOSFET model is called up from the spice file ‘tsmc_typical2.net’.

I_Probe
IDS

V_DC
MOSFET_NMOS
SRC1 MOSFET1
Vdc=VDS Model=MODnch3_1
V_DC Length=.5 um
SRC3 Width=100 um
Vdc=VGS
spiceInclude
SPICE1
File="tsmc_typical2.net"
NetlistDebugMode=0

PARAMETER SWEEP Var VAR

DC Eqn
VAR1
ParamSweep DC VGS=0
Sweep1 DC1 VDS=0
SweepVar="VGS" SweepVar="VDS"
SimInstanceName[1]="DC1" Start=0
SimInstanceName[2]= Stop=3.3
SimInstanceName[3]= Step=.1
SimInstanceName[4]= Other=OutVar="MOSFET1.Gm"
SimInstanceName[5]=
SimInstanceName[6]=
Start=0
Stop=2
Step=0.2

The resulting plot

 Sheet
7 of 14

45

40

35

30

25
IDS.i, mA Vgs
20

15

10

-5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

VDS
The device will also have a transconductance Curve ie VGS vs IDS. The ADS simulation below
sweeps the gate voltage and measures the resulting drain current.

I_Probe
IDS

V_DC
MOSFET_NMOS
SRC1 MOSFET1
Vdc=VDS Model=MODnch3_1
V_DC Length=.5 um
SRC3 Width=100 um
Vdc=VGS
Var
Eqn
VAR
VAR1
VGS=0
VDS=3.3

DC
DC
DC1
SweepVar="VGS" spiceInclude
SPICE1
Start=0
File="tsmc_typical2.net"
Stop=3 NetlistDebugMode=0
Step=.1
Other=OutVar="MOSFET1.Gm"

Resulting transconductance curve, slope is the GM of the device.

 Sheet
8 of 14

0.085

0.080

0.075

0.070

0.065

0.060

0.055

IDS (A) 0.050

0.045
IDS.i

0.040
Slope of curve
0.035
= gm

0.030

0.025

0.020

0.015

0.010

0.005

0.000
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

VGS

Pinch-off voltage = 0.6V

 Sheet
9 of 14

And for the P-type device

Input transconductance trace

I_Probe
IDS

V_DC
SRC1
Vdc=VDS

V_DC
SRC3
Vdc=VGS
Var
Eqn VAR
VAR1
VGS=0
VDS=-3.3

DC MOSFET_PMOS
DC MOSFET1
DC1 Model=MODpch3_1
SweepVar="VGS" Length=0.5 um
Start=0 Width=100 um
Stop=-5 Ad=
Step=-.1 As=
Other=OutVar="MOSFET1.Gm" Pd=
Ps=
Nrd=
Nrs=
spiceInclude Mult=2
SPICE1 Region=
File="tsmc_typical2.net" Temp=
NetlistDebugMode=0 Mode=nonlinear

Resulting trace
 Sheet
10 of 14

0.00

-0.01

-0.02

-0.03
IDS.i

-0.04

-0.05

-0.06

-0.07
-5 -4 -3 -2 -1 0

VGS

I_Probe
IDS

V_DC MM9_NMOS
SRC3 MOSFET1
Vdc=VGS Model=MODnch3_1
V_DC Length=0.5 um
SRC1 Width=100 um
Vdc=VDS Ab=
Ls=
Lg=
Temp=
Var
Eqn
VAR Mult=2
VAR1 Mode=nonlinear
VGS=0
VDS=3.3

DC PARAMETER SWEEP
DC
DC1 ParamSweep
SweepVar="VDS" Sweep1
Start=0 SweepVar="VGS"
Stop=3 SimInstanceName[1]="DC1"
Step=.1 SimInstanceName[2]=
Other=OutVar="MOSFET1.Gm" SimInstanceName[3]=
SimInstanceName[4]=
SimInstanceName[5]=
SimInstanceName[6]=
Start=0
spiceInclude
SPICE1 Stop=5
File="tsmc_typical2.net" Step=1
NetlistDebugMode=0

Output characteristic trace

 Sheet
11 of 14

0.01

0.00

-0.01

-0.02

IDS.i
-0.03

-0.04

-0.05

-0.06

-0.07
-5 -4 -3 -2 -1 0

VDS
Body Effect

The FET body or ‘Bulk’ is known either as the substrate, back gate or more commonly the
Body. It is normally connected to the lowest voltage potential of the circuit (usually the
source). However if is left unconnected its effect on the DC characteristics of the device must
be taken into account. If we include the bulk effect the value of the threshold voltage VT will
increase with increasing bulk voltage.

(
VT = VTO + γ - VBS + 2.Φ.F − 2.Φ.F )
γ = Bulk threshold parameter(Volts)
Φ.F = Fermilevelpotential(Volts)
VBS = Bulksourcepotential(Volts)

Therefore, normally VTO = VT for VBS = 0 (ie bulk connectedto the source)

If the device was biased without the bulk node connected then a change in operating point
could take the device out of its saturation region and significantly change the circuit
performance. The bulk voltage is thus a very important parameter in circuit applications and
therefore it is best to connect the bulk to the device source connection.
 Sheet
12 of 14

The circuit is drawn as follows:-

Drain
Drain

Gate
Bulk Gate

Source
Source

The simulation below shows how varying the bulk voltage will vary the pinch-off voltage of the
device.

I_Probe
IDS MOSFET_NMOS
MOSFET1
Model=MODnch3_1
Length=.5 um
V_DC
Width=50 um
SRC1
Vdc=3.3
V_DC V_DC
SRC3 SRC4
Vdc=VGS Vdc=VBS
spiceInclude
SPICE1
File="tsmc_typical2.net"
NetlistDebugMode=0

PARAMETER SWEEP Var VAR

DC Eqn
VAR1
ParamSweep DC VGS=0
Sweep1 DC1 VBS=0
SweepVar="VGS" SweepVar="VBS"
SimInstanceName[1]="DC1" Start=0
SimInstanceName[2]= Stop=3
SimInstanceName[3]= Step=0.5
SimInstanceName[4]= Other=OutVar="MOSFET1.Gm"
SimInstanceName[5]=
SimInstanceName[6]=
Start=0
Stop=1
Step=0.1

Resulting plot showing that the pinch-off voltage increases with increasing bulk voltage
 Sheet
13 of 14

0.008

0.007

0.006

0.005

IDS.i
0.004

0.003

0.002

0.001

0.000
0.0 0.2 0.4 0.6 0.8 1.0

VGS

Increasing pinch-off voltage

From the last section we found that the drain current in the saturation region =

ID ≈ β[VGS - VT ]
2

Transconductance

∆ID
GM = ie slope of transfer curve
∆VGS

ID = β[VGS - VT ] ∆ID = 2β[VGS - VT ].∆VGS

2
thereforedifferentiate wrt VGS

GM = 2β[VGS - VT ] - (1)

ID
If we rearrange ID = β[VGS - VT ] then [VGS - VT ] =
2
sub into (1)
β

ID 0.5 0.5
GM = 2β = 2β1.ID β -0.5 = 2β 0.5 .ID = 2 β.ID
β
 Sheet
14 of 14

Output Conductance

∆ID
GO = ie slope of output characteristic
∆VDS

ID = β(VGS - VT ) (1 + λ.VDS ) Differentiate wrt VD S ∆ID = β(VGS - VT ) .λ.∆VDS

2 2
- (2)

From above ID = β(VGS - VT ) sub into (2)

2

∆ID
∆ID = ID .λ.∆VDS = = GO = ID .λ
∆VDS

Voltage Gain A

transconductance GM 2 β.ID 0.5 −1 -0.5

A= = = = 2.β 0.5 .ID .ID .λ −1 = 2.β 0.5 .ID .λ −1
Output Conductance GO λ.ID

2 β K .W 2 K .W 1 0.5 -0.5 1 2 K P .W
A= . and β = P = . P . = 21.λ -1.K P .W 0.5 .2-0.5.L-0.5 .ID = . .
λ ID 2L λ 2L ID λ ID L