NAME:

ST ID:
COE 341 FALL 2008 MAJOR 1
1) (35 pts) You are given the following revolutionary Karim processor with three pipelines. (U is
integer pipeline, V and W are arbitrary pipelines) In this processor, S1 can issue 3 instructions
simultaneously- one for each pipeline. Each stage of the pipeline takes 5 nsec of execution time
and all instructions should be finished in the same order they are issued. Show the execution of
the given program for the following processor and indicate how long it takes to execute the whole
program. (Use the table provide for your convenience.)

program

S1 S2 U pipeline S3 S4 S5 1I
2A
3A
S2 V pipeline S3 S4 S5 4A
5A
S2 W pipeline S3 S4 S5 6I
7I
8A
9I

T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T15

S1

S2 U

S3 U

S4 U
V

S5 U

V
W
2) You are given a synchronous bus with 40 nsec period. Specifications of the bus are given below.
Assuming that you have a memory with 75 nsec. latency and the memory starts working as soon
as MREQ signal is asserted; calculate the number of wait cycle(s) needed to read data from
memory in this system.
(Please show your work clearly!)

3) 4) (25 pts)You are given a PCI bus with 35 nsec period. Assuming that the memory used has 75
nsec latency and IRDY is given on the negative edge of T2, draw the read operation timing
diagram for PCI bus. Assume memory starts working after IRDY is given. Show only IRDY,
TRDY and DEVSEL signals and be accurate with your time scale.
4) An asynchronous bus system has the following delay parameters:
i) MREQ and RD is given 10 nsec after address appears on the address bus,
ii) MSYN appears 5 nsec after MREQ signal,
iii) Memory has a latency of 75 nsec,
iv) Memory asserts SSYN as soon as it puts the data on the data bus,
v) CPU can read the data in 10 nsec and assert MSYN at the end of the read operation,
vi) Memory responds to MSYN by generating SSYN after 5 nsec.

Calculate the duration of read cycle of this bus. Please show your work clearly.

5) We are trying to transfer 600 words (word is 32 bit) from main memory to cache memory using
block transfer. Assuming that we have a bus with 40 nsec clock period, how long it would take to
transfer this data. Assume your data bus is 32 bits. (Show your work!)