name: (FY sT#: COE 341 Major 1 Spring 2009 1) (20) The superscalar processor given in the figure has to execute the program below. Indicate how long it would take to execute the program, S1=5 ns, S2=5 ns, S3=10 ns , S5= 5 nsec. ALU operations take 35 nsec, LOAD takes 50 nsec, STORE takes 50 nsec and floating point operation takes 80 nsec. Calculate the total execution time for the following code fragment Program: LOAD LOAD STORE ALU Floating point STORE STORE 8. ALU NaUaYREoS qWwog “4 3401S avor zm inw Supeoiy al SHOLS wun Pr wun yun yoeq vor oie) u2e) au, pueiado onanisuy ss es 1s my mv2) (10) A CPU with 85 nsec clock period supposed to transfer 64 words to memory using block transfer. Figure out how long it would take to transfers all the data. is {oh 44> t© = Shic 3) (20)You are asked to use a synchronous bus with 205 nsec memory components. Assuming that the bus period can be set to 50, 60 or 70 nsec, find the arrangement with optimum performance which has the shortest read cycle. V\ se [yw * er =. 2 Ne book ist-2-(17 43) : = S27. ost 4 =e T-5 ut OO We yee For SD nse T - ‘ U ait 50-5 2 YF Los-4s= IGS We reed ieee tee 1G x50 = 339 ne Far bo asec T bo-5 255 LoS-SS = |F5O We read oe ye 1 eb ue = Fx G0= 39 Ager De-s2 65 Que tce (Wor ne cole Oe totd ayer = 45995 189 ngec ~ ded Lok wione anny ‘ UE wrteey v te tis optimum i's 22 nie 4) (15) We have a computer system with two levels of cache memory. L1 cache has speed of ‘Tnsec, L2 cache has speed of 20 nsec and main memory has speed of 35 nsec. After observing the performance of the system over a considerable time we have noticed that L1 cache has hit ratio of 50 %, L2 has hit ratio of 30% and main memory has hit ratio of 20%. Find the effective, mean access time of the system. Sov + 30x10 + Lex 45 Be 4 G0 44 ea v0 \os OS sen Jos5) (20) You are asked to design the data storage unit of RTA where all police stations and ‘mobile patrol units would like to access data online any time of the day. Study indicated that RTA has data bandwidth requirement of 600 MByte/sec at peak times and very serious about security of the data. RTA would like to have the ability to check integrity of the data as itis being written and read and should be able to recover quickly in case of catastrophic failure at any time, You are given highly reliable Western Digital Extreme capacity hard disks with 150 MByte /sec throughput. How would you design this system? Explain briefly. Rard lee DL , W bits encoded over % bits 1S he bef fa thu me ony sty > ne explana =F addchlew 6. (15) we have a PCI bus with 30 ns clock period. We have a memory with 75 nsec latency. Draw the write cycle for this system. Show all lines involved in the operation for one write cycle. - st TS se eee 18 1%