Digital Design

Chapter 4:
Datapath Components
Slides to accompany the textbook
Digital Design, with RTL Design, VHDL, and Verilog, 2nd Edition,
by Frank Vahid, John Wiley and Sons Publishers, 2010.
http://www.ddvahid.com

Copyright 2010 Frank Vahid

Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities,
subject to keeping this copyright notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf
Digital Design 2e
with animations) may not be posted to publicly-accessible websites, but may be posted for students on internal protected sites or distributed directly to students by other electronic means.
Copyright 2010 1
Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incurring royalties. Any other use requires explicit permission. Instructors
Frank Vahid
may obtain PowerPoint source or obtain special use permissions from Wiley see http://www.ddvahid.com for information.
 4.1

Introduction
Chpts 2 & 3: Introduced increasingly complex digital building
blocks
Gates, multiplexors, decoders, basic registers, and controllers
Controllers good for systems with control inputs/outputs
Control input: Single bit (or a few), representing environment
event or state
Ex: 1 bit representing button pressed
Data input: Multiple bits representing single entity
Ex: 7 bits representing temperature in binary
Need appropiate building blocks for data
Datapath components (register-transfer-level, or RTL)
components: store/transform data
Combine datapath components to form a datapath
Chpt 4 introduces some datapath components and simple Appropriate building
blocks:
datapaths Tires, seat, pedals
Next chapter will combine controllers and datapaths into Not:
processors Rubber, glue, metal
Digital Design 2e
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Frank Vahid Note: Slides with animation are denoted with a small red "a" near the animated items
 4.2

Registers
N-bit register: Stores N bits, N is the width
Common widths: 8, 16, 32 b x
Combinational n1
Storing data into register: Loading logic
Opposite of storing: Reading (does not alter contents) n0
Basic register of Ch 3: Loaded every cycle s1 s0

Useful for implementing FSMstores encoded state clk State register

a
I3 I2 I1 I0
load 4-bit register
I3 I2 I1 I0
D D D D
Q Q Q Q reg(4)

clk Q3 Q2 Q1 Q0

Q3 Q2 Q1 Q0

Basic register loads on every clock cycle

How extend to only load on certain cycles?

Digital Design 2e
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Frank Vahid
 Register with Parallel Load
Add 2x1 mux to front of each flip-flop
Registers load input selects mux input to pass
load=0: existing flip-flop value; load=1: new input value
I3 I2 I1 I0

1 0 1 0 1 0 1 0
load 2x1 I3 I2 I1 I0
load a
D D D D
Q3 Q2 Q1 Q0
Q Q Q Q
block symbol
Q3 Q2 Q1 Q0

I3 I2 I1 I0 I3 I2 I1 I0

load=1
load=0

10 10 10 10 10 10 10 10

D D D D D D D D

Q Q Q Q Q Q Q Q
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
Digital Design 2e
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Frank Vahid
 Register Example using the Load Input:
Weight Sampler
Scale has two displays
Present weight
Saved weight Scale Weight Sampler

Useful to compare 0 0 1 01
present item with
previous item Save
3 pounds
2
b 1 load
I3 I2 I1 I0 a

Use 4-bit parallel load clk

0011
Present weight Q3 Q2 Q1 Q0
register to store weight
Pressing button loads
present weight into 3 pounds
register Saved weight
Register contents
always displayed as
Saved weight, even
when new present
weight appears

Digital Design 2e
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Frank Vahid
 Buses
N-bit bus: N wires to carry Scale Weight Sampler

N-bit data item

Circuit drawings can become Save
b I3 I2 I1 I0
cluttered load
Present weight clk
Convention for drawing Q3 Q2 Q1 Q0

buses
Single bold line and/or small
angled line across Saved weight

ld

a
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Frank Vahid
 Register Example: Above-Mirror Display

0001010
C 8 Loaded on clock edge
d0 load reg0 T

2x4 i0
8
0 d1
1 load reg1
8-bit
Ch2 ex: Four simultaneous a0 0001010
A 41
values from cars computer i0
i1
1 8
To reduce wires: Computer a1
i1
d D
writes only 1 value at a time, d2 load reg2 I 8
loads into one of four i2
registers 8
Was: 8+8+8+8 = 32 wires e
d3 load reg3 M
Now: 8 +2+1 = 11 wires 1 i3 s1 s0
load
8
x y
Digital Design 2e
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Frank Vahid
 Register Example: Computerized Checkerboard
LED lit LED
Each register 1
holds values for
0
one column of
1
LEDs
1 lights LED 0

Microprocessor 0

loads one 0
register at a time 1
Occurs fast 0
enough that
R7 R6 R5 R4 R3 R2 R1 R0 Q
user sees I
R0
load
10100010
entire board
d7 d6 d5 d4 d3 d2 d1 d0
change at once 8 e i2 i1 i0 3x8 decoder from from
microprocessor decoder
D
microprocessor (a) (b)

Digital Design 2e
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Frank Vahid
Register Example: Computerized Checkerboard
LED

lit LED

a R7 R6 R5 R4 R3 R2 R1 R0
10100010 10100010 10100010 10100010
01000101 01000101 01000101 01000101

D 10100010 010000101 10100010 010000101 10100010 010000101 10100010 010000101

i2,i1,i0 000 (R0) 001 (R1) 010 (R2) 011 (R3) 100 (R4) 101 (R5) 110 (R6) 111 (R7)

e
clk

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Frank Vahid
 Shift Register
Register contents
1 1 0 1
Shift right 0
before shift right

Move each bit one position right

a

Register contents
0 1 1 0
Rightmost bit is dropped after shift right
Assume 0 shifted into leftmost bit

Q: Do four right shifts on 1001, showing value after each shift

a
A: 1001 (original)
0100
Implementation: Connect flip-flop
0010 output to next flip-flops input
0001 a
shr_in
0000

Digital Design 2e
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Frank Vahid
 Shift Register
To allow register to either shift or retain, use 2x1 muxes
shr: 0 means retain, 1 shift
shr_in: value to shift in
May be 0, or 1

shr_in

1 0

shr=1
shr 1 0 1 0 1 0 1 0 1 0 1 0 1 0
2x1 2x1
D D D D
D D D D
Q Q Q Q
Q Q Q Q
Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0 (b)
(a)
shr_in
shr
Left-shift register also easy to design
Q3 Q2 Q1 Q0
Digital Design 2e
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Frank Vahid
 Rotate Register

Register contents
1 1 0 1
before shift right
Rotate right: Like shift right,
Register contents
but leftmost bit comes from 1 1 1 0
after shift right

rightmost bit

Digital Design 2e
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Frank Vahid
 Shift Register Example: Above-Mirror Display

central computer
C 8

From the car's

Earlier example: d0 load reg0 T

mirror display
To the above
2 4 i0
8

8+2+1 = 11wires from a0

i0
d1 load reg1 A
8-bit
4 1
i1

cars computer to a1
i1
d2 load reg2 I
8
d
8
D

above-mirror displays d3 load reg3 M

8
i2

four registers load

8
i3 s1 s0

x y

Better than 32 wires,

Note: this line is 1 wire, rather than 8 like before
but 11 still a lot x y
c
want fewer for shr_in
d0 shr reg0 T
smaller wire bundles s1 s0
2x4 i0
Use shift registers shr_in
8
41
shr reg1
Wires: 1+2+1=4 a0 i0
d1 A
i1
Computer sends one a1 i1 8
shr_in d D
value at a time, one d2 shr reg2 I 8
bit per clock cycle i2
8
shr_in
shr reg3
e d3 M
Digital Design 2e shift i3
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Frank Vahid
 Multifunction Registers
Many registers have multiple functions
Functions:
Load, shift, clear (load all 0s)
s1 s0 Operation
And retain present value, of course 0 0 Maintain present value

Easily designed using muxes 0

1
1
0
Parallel load
Shift right
Just connect each mux input to achieve 1 1 (unused - let's load 0s)
desired function

shr_in I3 I2 I1 I0
0 0 0 0
s1 3 2 1 0 3210 3210 3210
s0 4x1 shr_in I3 I2 I1 I0
s1
D D D D s0
Q3 Q2 Q1 Q0
Q Q Q Q

(b)
Q3 Q2 Q1 Q0

Digital Design 2e
(a)
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Frank Vahid
 Multifunction Registers

s1 s0 Operation
0 0 Maintain present value
0 1 Parallel load
1 0 Shift right
1 1 Shift left

I3 I2 I1 I0

shr_in
shl_in

3210 3210 3210 3210

shl_in I3 I2 I1 I0
shr_in
D D D D s1
s0

Q Q Q Q Q3 Q2 Q1 Q0

Q3 Q2 Q1 Q0
(a) (b)
Digital Design 2e
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Frank Vahid
Multifunction Registers with Separate Control Inputs
s1 s0 Operation
ld shr shl Operation 0 0 Maintain present value
0 0 0 Maintain present value 0 1 Parallel load
0 0 1 Shift left 1 0 Shift right
0 1 0 Shift right 1 1 Shift left
0 1 1 Shift right shr has priority over shl
1 0 0 Parallel load
1 0 1 Parallel load ld has priority I3 I2 I1 I0
1 1 0 Parallel load ld has priority shr_in
1 1 1 Parallel load ld has priority I3 I2 I1 I0
ld shr_in
combi- s1 shl_in
shl_in

?
shr national s0
Truth table for combinational circuit circuit Q3 Q2 Q1 Q0
shl
Inputs Outputs Note
ld shr shl s1 s0 Operation Q3 Q2 Q1 Q0
0 0 0 0 0 Maintain value
0 0 1 1 1 Shift left a
0 1 0 1 0 Shift right
0 1 1 1 0 Shift right
1 0 0 0 1 Parallel load s1 = ld*shr*shl + ld*shr*shl + ld*shr*shl
1 0 1 0 1 Parallel load
1 1 0 0 1 Parallel load s0 = ld*shr*shl + ld a
1 1 1 0 1 Parallel load

a
Digital Design 2e
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Frank Vahid
 Register Operation Table
Register operations typically shown using compact version of table
X means same operation whether value is 0 or 1
One X expands to two rows
Two Xs expand to four rows
Put highest priority control input on left to make reduced table simple
Inputs Outputs Note
ld shr shl s1 s0 Operation ld shr shl Operation
0 0 0 0 0 Maintain value 0 0 0 Maintain value
0 0 1 1 1 Shift left 0 0 1 Shift left
0 1 0 1 0 Shift right 0 1 X Shift right
0 1 1 1 0 Shift right 1 X X Parallel load
1 0 0 0 1 Parallel load
1 0 1 0 1 Parallel load
1 1 0 0 1 Parallel load
1 1 1 0 1 Parallel load

Digital Design 2e
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Frank Vahid
 Register Design Process
Can design register with desired operations using simple
four-step process

Digital Design 2e
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Frank Vahid
 Register Design Example
s2 s1 s0 Operation
0 0 0 Maintain present value
Desired register operations 0 0 1 Parallel load
Load, shift left, synchronous clear, synchronous set 0 1 0 Shift left
Want unique control input for each operation 0 1 1 Synchronous clear
1 0 0 Synchronous set
1 0 1 Maintain present value
Step 1: Determine mux size 1 1 0 Maintain present value
1 1 1 Maintain present value
5 operations: above, plus maintain In
1 0 from
a present value (dont forget this one!) Qn-1
Use 8x1 mux s2
s1 7 6 5 4 3 2 1 0
s0
Step 2: Create mux operation table
D
Step 3: Connect mux inputs Q

Qn
Step 4: Map control lines Inputs Outputs
s2 = clr*set clr set ld shl s2 s1 s0 Operation
0 0 0 0 0 0 0 Maintain present value
s1 = clr*set*ld*shl + clr
0 0 0 1 0 1 0 Shift left
s0 = clr*set*ld + clr 0 0 1 X 0 0 1 Parallel load
0 1 X X 1 0 0 Set to all 1s
Digital Design 2e 1 X X X 0 1 1 Clear to all 0s
Copyright 2010
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Frank Vahid
 Register Design Example

I3 I2 I1 I0

shl I3 I2 I1 I0
s2
s1 shl_in
ld combi- s0 shl_in
national
set
circuit Q3 Q2 Q1 Q0
clr
Q3 Q2 Q1 Q0

Step 4: Map control lines Inputs Outputs

s2 = clr*set clr set ld shl s2 s1 s0 Operation
0 0 0 0 0 0 0 Maintain present value
s1 = clr*set*ld*shl + clr
0 0 0 1 0 1 0 Shift left
s0 = clr*set*ld + clr 0 0 1 X 0 0 1 Parallel load
0 1 X X 1 0 0 Set to all 1s
Digital Design 2e 1 X X X 0 1 1 Clear to all 0s
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Frank Vahid
 4.3

Adders
Adds two N-bit binary numbers Inputs Outputs
a1 a0 b1 b0 c s1 s0
2-bit adder: adds two 2-bit numbers, 0 0 0 0 0 0 0
0 0 0 1 0 0 1
outputs 3-bit result 0 0 1 0 0 1 0
e.g., 01 + 11 = 100 (1 + 3 = 4) 0
0
0
1
1
0
1
0
0
0
1
0
1
1
Can design using combinational 0
0
1
1
0
1
1
0
0
0
1
1
0
1
design process of Ch 2, but doesnt 0
1
1
0
1
0
1
0
1
0
0
1
0
0
work well for typical N 1 0 0 1 0 1 1
1 0 1 0 1 0 0
Why not? 1 0 1 1 1 0 1
1 1 0 0 0 1 1
1 1 0 1 1 0 0
1 1 1 0 1 0 1
1 1 1 1 1 1 0

Digital Design 2e
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Frank Vahid
 Why Adders Arent Built Using Standard 4.3

Combinational Design Process

Truth table too big Inputs Outputs
a1 a0 b1 b0 c s1 s0
2-bit adders truth table shown 0 0 0 0 0 0 0
(2+2) 0 0 0 1 0 0 1
Has 2 = 16 rows 0 0 1 0 0 1 0
0 0 1 1 0 1 1
8-bit adder: 2(8+8) = 65,536 rows 0
0
1
1
0
0
0
1
0
0
0
1
1
0
16-bit adder: 2(16+16) = ~4 billion rows 0
0
1
1
1
1
0
1
0
1
1
0
1
0
32-bit adder: ... 1
1
0
0
0
0
0
1
0
0
1
1
0
1

Big truth table with numerous 1s/0s yields 1

1
0
0
1
1
0
1
1
1
0
0
0
1
1 1 0 0 0 1 1
big logic 1 1 0 1 1 0 0
1 1 1 0 1 0 1
Plot shows number of transistors for N-bit 1 1 1 1 1 1 0

adders, using state-of-the-art automated 10000

combinational design tool
8000
Q: Predict number of transistors for 16-bit adder

Transistors
6000
A: 1000 transistors for N=5, doubles for each 4000
a increase of N. So transistors = 1000*2(N-5). Thus,
2000
for N=16, transistors = 1000*2(16-5) = 1000*2048 =
2,048,000. Way too many! 0
1 2 3 4 5 6 7 8
N
Digital Design 2e
Copyright 2010 a Size comes from implementing with two levels of gates. Following approach 22
Frank Vahid uses more levels to achieve smaller size.
 Alternative Method to Design an Adder: Imitate
Adding by Hand
Alternative adder
design: mimic 0 1 0 1 1 1

how people do A: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
a
B: + 0 1 1 0 + 0 1 1 0 + 0 1 1 0 + 0 1 1 0
addition by hand
One column at a
time 1 0 1 1 0 1 1 0 1 0 1

Compute sum,
add carry to next
column

Digital Design 2e
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Frank Vahid
 Alternative Method to Design an Adder: Imitate
Adding by Hand
Create 1 1 0
component for A: 1 1 1 1
B: + 0 1 1 0
each column
Adds that a
columns bits, 1 0 1 0 1
generates sum
1 1 0
and carry bits
A: 1 1 1 1

+ B: 0 1 1 0

b a ci b a ci b a ci b a
co s co s co s co s
1
0 1 0 1 SUM

Digital Design 2e
Full-adders Half-adder
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Frank Vahid
 Half-Adder
1 1 0
Half-adder: Adds 2 bits, generates
1 1 1
sum and carry A: 1

Design using combinational design + B: 0 1 1 0

process from Ch 2 b a ci b a ci b a ci b a
Inputs Outputs
co s co s co s co s
a b co s 1
0 0 0 0 0 1 0 1 SUM
Step 1: Capture the function 0 1 0 1
1 0 0 1
1 1 1 0

a b
Step 2A: Create equations
co = ab a b
s = ab + ab (same as s = a xor b)
Half-adder
(HA)
co s
a

Step 2B: Implement as co s

circuit (a) (b)

Digital Design 2e
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Frank Vahid
 Full-Adder
1 1 0
Full-adder: Adds 3 bits, generates
1 1 1
sum and carry A: 1

Design using combinational design + B: 0 1 1 0

process from Ch 2 b a ci b a ci b a ci b a
co s co s co s co s
1
0 1 0 1 SUM
Step 1: Capture the function
Step 2A: Create equations Step 2B: Implement as circuit
Inputs Outputs a b ci
a b ci co s co = abc + abc + abc + abc
0 0 0 0 0 co = abc +abc +abc +abc +abc +abc
0 0 1 0 1 co = (a+a)bc + (b+b)ac + (c+c)ab
0 1 0 0 1 co = bc + ac + ab
0 1 1 1 0
1 0 0 0 1 s = abc + abc + abc + abc
1 0 1 1 0 s = a(bc + bc) + a(bc + bc) Full
1 1 0 1 0 s = a(b xor c) + a(b xor c)
1 1 1 1 1
adder
s = a xor b xor c (FA)
co s
Digital Design 2e
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Frank Vahid
 Carry-Ripple Adder
Using half-adder and full-adders, we can build adder that adds like we
would by hand
Called a carry-ripple adder
4-bit adder shown: Adds two 4-bit numbers, generates 5-bit output
5-bit output can be considered 4-bit sum plus 1-bit carry out
Can easily build any size adder

a3 b3 a2 b2 a1 b1 a0 b0

a b ci a b ci a b ci a b
a3 a2 a1 a0 b3 b2 b1 b0
FA FA FA HA
4-bit adder
co s co s co s co s
co s3 s2 s1 s0

co s3 s2 s1 s0
(a)
(b)

Digital Design 2e
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Frank Vahid
 Carry-Ripple Adder
Using full-adder instead of half-adder for first bit, we can
include a carry in bit in the addition
Useful later when we connect smaller adders to form bigger adders

a3 b3 a2 b2 a1 b1 a0 b0 ci

a b ci a b ci a b ci a b ci a3 a2 a1 a0 b3 b2 b1 b0
FA FA FA FA 4-bit adder ci
co s co s co s co s co s3 s2 s1 s0

co s3 s2 s1 s0
(a) (b)

Digital Design 2e
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Frank Vahid
 Carry-Ripple Adders Behavior
000 00 0 000 0 0
0

a b ci a b ci a b ci a b ci
FA FA FA FA Assume all inputs initially 0
co s co s co s co s
0 0 0
0 0 0 0 0

000 10 0 100 1 1 0111+0001

0
(answer should be 01000)
a b ci a b ci a b ci a b ci
a
FA FA FA FA
co s co s co s co s
0 0 10
co2 co1 co0
0 0 1 1 0 Output after 2 ns (1FA delay)

Wrong answeris there a problem? Nojust need more time

Digital Design 2e
Copyright 2010 for carry to ripple through the chain of full adders. 29
Frank Vahid
 Carry-Ripple Adders Behavior
000 10 0 101 1 1
0 0111+0001
(answer should be 01000)
a b ci a b ci a b ci a b ci
FA FA FA FA
co s co s co s co s
0 1 1
co1 Outputs after 4ns (2 FA delays)
1 0 0
(b)
000 101
0 101 1 1
0

a b ci a b ci a b ci a b ci
FA FA FA FA
co s co s co s co s
1 1 1 a
co2 Outputs after 6ns (3 FA delays)
0 0 0
(c)
0 00
1 10 1 101 1 1
0

a b ci a b ci a b ci a b ci
FA FA FA FA
co s co s co s co s
1 1 1
0 1 0 0 0 Output after 8ns (4 FA delays)
Digital Design 2e
(d)
Copyright 2010 Correct answer appears after 4 FA delays 30
Frank Vahid
 Cascading Adders

a7 a6 a5 a4 b7 b6 b5 b4 a3 a2 a1 a0 b3 b2 b1 b0

a3 a2 a1 a0 b3 b2 b1 b0 a3 a2 a1 a0 b3 b2 b1 b0 a7.. a0 b7.. b0
4-bit adder ci 4-bit adder ci 8-bit adder ci +
co s3 s2 s1 s0 co s3 s2 s1 s0 co s7.. s0

C
co s7 s6 s5 s4 s3 s2 s1 s0
(a) (b) (c)

Block symbol Simplified

block symbol

Digital Design 2e
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Frank Vahid
 Adder Example: DIP-Switch-Based Adding Calculator
Goal: Create calculator that adds two 8-bit binary numbers, specified
using DIP switches
DIP switch: Dual-inline package switch, move each switch up or down
Solution: Use 8-bit adder
DIP switches

1
0

a7..a0 b7..b0
a
8-bit carry-ripple adder ci 0

co s7..s0

CALC

LEDs

Digital Design 2e
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Frank Vahid
 Adder Example: DIP-Switch-Based Adding Calculator
To prevent spurious values from appearing at output, can place register
at output
Actually, the light flickers from spurious values would be too fast for humans to
detectbut the principle of registering outputs to avoid spurious values being read by
external devices (which normally arent humans) applies here.
DIP switches

1
0

a7..a0 b7..b0

8-bit adder ci 0

co s7..s0

e
ld
8-bit register
clk
CALC

Digital Design 2e
Copyright 2010 LEDs 33
Frank Vahid
 Adder Example: Compensating Weight Scale
Weight scale with compensation amount of 0-7
To compensate for inaccurate sensor due to physical wear
Use 8-bit adder
0
weight 7 1 Dial, can
sensor 6 2 be set by
5 3 user
4
01000010 0 0 0 0 0 010
000

a7..a0 b7..b0
a
8-bit adder ci 0

co s7..s0

1 ld
clk
01000010
01000100
display register Weight
Adjuster

Digital Design 2e
Copyright 2010
to display 34
Frank Vahid
 Incrementer
Adds 1 to input A carries: 011
Inputs Outputs
0011
a3 a2 a1 a0 c0 s3 s2 s1 s0
unused
0 0 0 0 0 0 0 0 1 + 1
0 0 0 1 0 0 0 1 0
0 0 1 0 0 0 0 1 1 00100
a
0 0 1 1 0 0 1 0 0
0 1 0 0 0 0 1 0 1
0 1 0 1 0 0 1 1 0
0 1 1 0 0 0 1 1 1 a3 a2 a1 a0 1

Incrementer (+1)
0 1 1 1 0 1 0 0 0
a b a b a b a b a3 a2 a1 a0
1 0 0 0 0 1 0 0 1
1 0 0 1 0 1 0 1 0 HA HA HA HA +1
1 0 1 0 0 1 0 1 1 co s co s co s co s co s3 s2 s1 s0
1 0 1 1 0 1 1 0 0
1 1 0 0 0 1 1 0 1 co s3 s2 s1 s0
(b)
1 1 0 1 0 1 1 1 0
1 1 1 0 0 1 1 1 1 (a)
1 1 1 1 1 0 0 0 0

Could design using combinational design process, but smaller

design uses carry-ripple, only need half-adders
Digital Design 2e
Copyright 2010 35
Frank Vahid
 4.4

Comparators
N-bit equality comparator: Outputs 1 if two N-bit numbers are equal
4-bit equality comparator with inputs A and B
a3 must equal b3, a2 = b2, a1 = b1, a0 = b0
Two bits are equal if both 1, or both 0
eq = (a3b3 + a3b3) * (a2b2 + a2b2) * (a1b1 + a1b1) * (a0b0 + a0b0)
Note that function inside parentheses is XNOR
eq = (a3 xnor b3) * (a2 xnor b2) * (a1 xnor b1) * (a0 xnor b0)

a3 b3 a2 b2 a1 b1 a0 b0
0110 = 0111 ? 0 0 1 1 1 1 0 1

a3 a2 a1 a0 b3 b2 b1 b0
1 1 1 0
4-bit equality comparator =
eq

a
a
0 eq

Digital Design 2e
Copyright 2010 36
Frank Vahid
 Magnitude Comparator
N-bit magnitude comparator: A=1011 B=1001
Two N-bit inputs A and B,
outputs whether A>B, A=B, or 1011 1001 Equal
A<B, for 1011 1001 Equal a

How design? Consider 1011 1001 Not equal

comparing by hand.
First compare a3 and b3. If So A > B
equal, compare a2 and b2. And
so on.
Stop if comparison not equal (the
two bits are 0 and 1, or 1 and
0)whichever of A or B has the 1
is thus greater. If never see
unequal bit pair, then A=B.
Digital Design 2e
Copyright 2010 37
Frank Vahid
 Magnitude Comparator
By-hand example leads to idea for design
Start at left, compare each bit pair, pass results to the right
Each bit pair called a stage
Each stage has 3 inputs taking results of higher stage, outputs new results
to lower stage
a3 b3 a2 b2 a1 b1 a0 b0

a b a b a b a b
Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt AgtB
Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq AeqB
Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt AltB

Stage 3 Stage 2 Stage 1 Stage 0

a How design
each stage? 0 Igt a3a2a1a0 b3b2b1b0
AgtB
1 Ieq 4-bit magnitude comparator AeqB >=< a

0 Ilt AltB
Digital Design 2e
Copyright 2010 38
Frank Vahid
 Magnitude Comparator
a3 b3 a2 b2 a1 b1 a0 b0

a b a b a b a b
Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt AgtB
Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq AeqB
Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt AltB

Stage 3 Stage 2 Stage 1 Stage 0

Each stage:
out_gt = in_gt + (in_eq * a * b)
A>B if already determined in higher stage, or if higher stages equal but in this
stage a=1 and b=0
out_lt = in_lt + (in_eq * a * b)
a
A<B if already determined in higher stage, or if higher stages equal but in this
stage a=0 and b=1
out_eq = in_eq * (a XNOR b)
A=B (so far) if already determined in higher stage and in this stage a=b too
Simple circuit inside each stage, just a few gates (not shown)
Digital Design 2e
Copyright 2010 39
Frank Vahid
 Magnitude Comparator
How does it 1011 = 1001 ?
1 = 1 0 0 1 0 1 1
work? a3 b3 a2 b2 a1 b1 a0 b0

a b a b a b a b
0 0
Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt AgtB
Ieq=1 causes this 1 1
Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq AeqB
0 0
stage to compare Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt AltB

Stage3 Stage2 Stage1 Stage0

(a)
a

1 1 0 = 0 1 0 1 1
a3 b3 a2 b2 a1 b1 a0 b0

a b a b a b a b
0 0 0
Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt AgtB
1 1 1
Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq AeqB
0 0
Ilt in_lt out_lt 0 in_lt out_lt in_lt out_lt in_lt out_lt AltB

Stage3 Stage2 Stage1 Stage0

Digital Design 2e (b)
Copyright 2010 40
Frank Vahid
 Magnitude Comparator
1 1 0 0 1 > 0 1 1
1011 = 1001 ? a3 b3 a2 b2 a1 b1 a0 b0 Final answer
appears on the
a b a b a b a b right
Igt
0
in_gt out_gt in_gt out_gt 0 in_gt out_gt
1
in_gt out_gt AgtB Takes time for
1 0
Ieq in_eq out_eq 1
in_eq out_eq in_eq out_eq in_eq out_eq AeqB answer to
Ilt
0
in_lt out_lt in_lt out_lt 0 in_lt out_lt
0
in_lt out_lt AltB ripple from left
to right
Stage3 Stage2 Stage1 Stage0
Thus called
(c)
carry-ripple
a 1 1 0 0 1 0 1 1 style after the
a3 b3 a2 b2 a1 b1 a0 b0 carry-ripple
adder
a b a b a b a b Even though
Igt
0
in_gt out_gt in_gt out_gt in_gt out_gt 1 in_gt out_gt
1
AgtB theres no
Ieq
1
in_eq out_eq in_eq out_eq
0 0
in_eq out_eq in_eq out_eq AeqB carry
0 0 0
Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt AltB involved

Stage3 Stage2 Stage1 Stage0

(d)
Digital Design 2e
Copyright 2010 41
Frank Vahid
 Magnitude Comparator Example:
Minimum of Two Numbers
Design a combinational component that computes the
minimum of two 8-bit numbers
Solution: Use 8-bit magnitude comparator and 8-bit 2x1 mux
If A<B, pass A through mux. Else, pass B.

11000000 01111111
MIN A B 8 8

8 8 8 8
a A B
A B 1 I1 I0 Min
0 Igt AgtB s
C
1 Ieq 8-bit magnitude comparator AeqB 0 8-bit
0 Ilt AltB 2x1 mux 8
0
8 (b)
C
(a)
01111111

Digital Design 2e
Copyright 2010 42
Frank Vahid
 4.5

Multiplier Array Style

Can build multiplier that mimics multiplication by hand
Notice that multiplying multiplicand by 1 is same as ANDing with 1

Digital Design 2e
Copyright 2010 43
Frank Vahid
 Multiplier Array Style
Generalized representation of multiplication by hand

Digital Design 2e
Copyright 2010 44
Frank Vahid
 Multiplier Array Style
Multiplier design array of
AND gates
a3 a2 a1 a0

b0

pp1
b1

pp2
0 0

b2
+ (5-bit)

pp3
00
A B
b3
+ (6-bit) *
P

pp4
0 00

+ (7-bit) Block symbol

Digital Design 2e
Copyright 2010 p7..p0 45
Frank Vahid
 4.6

Subtractors and Signed Numbers

Can build subtractor as we built carry-ripple adder
Mimic subtraction by hand
Compute the borrows from columns on left
Use full-subtractor component:
wi is borrow by column on right, wo borrow from column on left
1st column 2nd column 3rd column 4th column
0 0 1 10 0 1 0
1 0 1 10 1 10 1 0 1 10 1 0 1 0 1 0
a
- 0 1 1 1 - 0 1 1 1 - 0 1 1 1 - 0 1 1 1
1 1 1 0 1 1 0 0 1 1

a3 b3 a2 b2 a1 b1 a0 b0 wi

a b wi a b wi a b wi a b wi a3 a2 a1 a0 b3 b2 b1 b0
FS FS FS FS 4-bit subtractor wi a

wo s wo s wo s wo s wo s3s2s1s0

wo s3 s2 s1 s0
(b) (c)
Digital Design 2e
Copyright 2010 46
Frank Vahid
 Subtractor Example: DIP-Switch Based
Adding/Subtracting Calculator
Extend earlier DIP switches
calculator example 1
Switch f indicates 0

whether want to
8 8 8 8
add (f=0) or 0 0
subtract (f=1) A B ci A B wi
8-bit adder 8-bit subtractor
Use subtractor and co S wo S
2x1 mux
1 f 8 8
0 2x1 1
0
8
e
ld
8-bit register
clk
CALC
8

LEDs
Digital Design 2e
Copyright 2010 47
Frank Vahid
 Subtractor Example:
Color Space Converter RGB to CMYK
Color
Often represented as weights
of three colors: red, green, and
blue (RGB)
Perhaps 8 bits each (0-255),
so specific color is 24 bits
White: R=11111111 (255),
G=11111111, B=11111111
Black: R=00000000,
G=00000000, B=00000000
Other colors: values in
between, e.g., R=00111111,
G=00000000, B=00001111 Printers use opposite color scheme
would be a reddish purple Because inks absorb light
Good for computer monitors, Use complementary colors of RGB:
which mix red, green, and blue Cyan (absorbs red), reflects green
lights to form colors and blue, Magenta (absorbs green),
and Yellow (absorbs blue)
Digital Design 2e
Copyright 2010 48
Frank Vahid
 Subtractor Example:
Color Space Converter RGB to CMYK

Printers must quickly convert 255

R
8 255
G
8 255
B
8
RGB to CMY 8 8 8

C=255-R, M=255-G, Y=255-B

Use subtractors as shown
8 8 8
C M Y

Digital Design 2e
Copyright 2010 49
Frank Vahid
 Subtractor Example:
Color Space Converter RGB to CMYK

Try to save colored inks

Expensive
Imperfect mixing C, M, Y doesnt
yield good-looking black
Solution: Factor out the black or
gray from the color, print that part
using black ink
e.g., CMY of (250,200,200)=
(200,200,200) + (50,0,0).
(200,200,200) is a dark gray use
black ink

Digital Design 2e
Copyright 2010 50
Frank Vahid
 Subtractor Example:
Color Space Converter RGB to CMYK
Call black part K R G B
8 8 8
(200,200,200): K=200
(Letter B already used for blue)
R G B
Compute minimum of C, RGB to CMY
C M Y
M, Y values
Use MIN component
8 8 8 8
designed earlier, using C M Y
comparator and mux, to
MIN
compute K
8
Output resulting K value,
and subtract K value from MIN
C, M, and Y values 8
K
Ex: Input of (250,200,200)
yields output of
(50,0,0,200)

8 8 8 8
C2 M2 Y2 K
Digital Design 2e
Copyright 2010 51
Frank Vahid
 Representing Negative Numbers: Twos
Complement
Negative numbers common
How represent in binary?
Signed-magnitude
Use leftmost bit for sign bit
So -5 would be:
1101 using four bits
10000101 using eight bits

Better way: Twos complement

Big advantage: Allows us to perform subtraction using addition
Thus, only need adder component, no need for separate
subtractor component

Digital Design 2e
Copyright 2010 52
Frank Vahid
 Tens Complement
1 9

2 8
Before introducing twos complement, 3 7
lets consider tens complement
4 6
But, be aware that computers DO NOT
5 5
USE TENS COMPLEMENT. Introduced
for intuition only. 6 4

Complements for each base ten number 7 3

shown to right. Complement is the number 8 2
that when added results in 10 9 1

Digital Design 2e
Copyright 2010 53
Frank Vahid
 Tens Complement
Nice feature of tens complement
Instead of subtracting a number, adding its complement results in answer
exactly 10 too much
So just drop the 1 results in subtracting using addition only
complements
1 9 10
2 8 4 6

3 7 7
4 6
0 10 20
5 5 4 +6
3 13 a
6 4
13
7 3
3
8 2
74=3 7+6=13 3
9 1 Adding the complement results in an answer that is
exactly 10 too much dropping the tens column gives
0 10 the right answer.
Digital Design 2e
Copyright 2010 54
Frank Vahid
 Twos Complement is Easy to Compute:
Just Invert Bits and Add 1
Hold on!
Sure, adding the tens complement achieves subtraction using addition only
But dont we have to perform subtraction to have determined the
complement in the first place? E.g., we only know that the complement of 4
is 6 by subtracting 10-4=6 in the first place.
True. But in binary, it turns out that the twos complement can be
computed easily
Twos complement of 011 is 101, because 011 + 101 is 1000
Could compute complement of 011 as 1000 011 = 101
Easier method: Just invert all the bits, and add 1
The complement of 011 is 100+1 = 101. It works!
Q: What is the twos complement of 0101? A: 1010+1=1011 a

(check: 0101+1011=10000)
Q: What is the twos complement of 0011? A: 1100+1=1101
Digital Design 2e
Copyright 2010 55
Frank Vahid
 Twos Complement
Twos complement can represent
negative numbers
Suppose have 4 bits
Positive numbers 0 to 7: 0000 to 0111
Negative numbers
-1: Take twos complement of 1: Quick method to determine
0001 1110+1 = 1111 magnitude of negative number
-2: 0010 1101+1 = 1110 4-bit: subtract right 3 bits from 8.
Ex. 1110: -(8 6) = -2
-8: 1000 0111+1 = 1000
So -1 to -8: 1111 to 1000 Or just take twos complement again:
Leftmost bit indicates sign of number, 1110 -(0001+1) = -0010 = -2
known as sign bit. 1 means negative.
Signed vs. unsigned N-bit number
Unsigned: 0 to 2N-1
Ex. Unsigned 8-bit: 0 to 255
Signed (twos complement): -2N-1 to 2N-1-1
Ex. Signed 8-bit: -128 to 127
Digital Design 2e
Copyright 2010 56
Frank Vahid
Twos Complement Subtractor Built with an Adder
Using twos complement
A B
A B = A + (-B)
= A + (twos complement of B) N-bit
= A + invert_bits(B) + 1
So build subtractor using A B 1
Adder cin
adder by inverting Bs bits,
and setting carry in to 1
S

Digital Design 2e
Copyright 2010 57
Frank Vahid
 Adder/Subtractor

Adder/subtractor: control
input determines whether B

add or subtract A N-bit b7 b6

sub
Can use 2x1 mux sub input
0 1
sub
passes either B or inverted B N-bit 2x1

Alternatively, can use XOR

A B
gates if sub input is 0, Bs Adder cin adders B inputs
bits pass through; if sub input S
is 1, XOR inverts Bs bits

Digital Design 2e
Copyright 2010 58
Frank Vahid
 Adder/Subtractor Example: Calculator
DIP switches
Previous calculator 1
used separate 0

adder and 8 8

subtractor 1 f A B
sub 8-bit adder/subtractor
0
Improve by using S
8
adder/subtractor, e
ld
8-bit register
and twos clk
CALC
8
complement
numbers 1
DIP switches
LEDs
0

8 8 8 8
A B ci 0 A B wi 0
8-bit adder 8-bit subtractor
co S wo S

1 f 8 8
0 2x1 1
0
8
e ld 8-bit register
clk CALC
8
Digital Design 2e
Copyright 2010 LEDs 59
Frank Vahid
 Overflow
Sometimes result cant be represented with given
number of bits
Either too large magnitude of positive or negative
Ex. 4-bit twos complement addition of 0111+0001 (7+1=8). But
4-bit twos complement cant represent number >7
0111+0001 = 1000 WRONG answer, 1000 in twos complement is
-8, not +8
Adder/subtractor should indicate when overflow has occurred,
so result can be discarded

Digital Design 2e
Copyright 2010 60
Frank Vahid
 Detecting Overflow: Method 1
For twos complement numbers, overflow occurs when the two
numbers sign bits are the same but differ from the results sign bit
If the two numbers sign bits are initially different, overflow is impossible
Adding positive and negative cant exceed largest magnitude positive or negative
Simple overflow detection circuit for 4-bit adder
overflow = a3b3s3 + a3b3s3
Include overflow output bit on adder/subtractor

sign bits

0 1 1 1 1 1 1 1 1 0 0 0

+0 0 0 1 +1 0 0 0 +0 1 1 1

1 0 0 0 0 1 1 1 1 1 1 1
overflow overflow no overflow
(a) (b) (c)
If the numbers sign bits have the same value, which
Digital Design 2e differs from the results sign bit, overflow has occurred.
Copyright 2010 61
Frank Vahid
 Detecting Overflow: Method 2
Even simpler method: Detect difference between carry-in to sign bit and
carry-out from sign bit
Yields simpler circuit: overflow = c3 xor c4

1 1 1 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 0 0 0

+0 0 0 1 +1 0 0 0 +0 1 1 1

0 1 0 0 0 10 1 1 1 01 1 1 1
overflow overflow no overflow
(a) (b) (c)

If the carry into the sign bit column differs from the
carry out of that column, overflow has occurred.

Digital Design 2e
Copyright 2010 62
Frank Vahid
 4.7

Arithmetic-Logic Unit: ALU

ALU: Component that
can perform various
arithmetic (add,
subtract, increment,
etc.) and logic (AND,
OR, etc.) operations,
based on control inputs

Digital Design 2e
Copyright 2010 63
Frank Vahid
 Multifunction Calculator without an ALU
Can build using separate
components for each
DIP switches
operation, and muxes 1
Too many wires, also 0
8 8
wastes power computing
operations when only use A B

one result at given time + +1 AND OR XOR NOT

Wasted
power
8 8
8
8
8 8 8
8
1 0 A lot of wires
0 1 2 3 4 5 6 7
x
s2
y 8-bit 8x1
s1
z s0
8
e
Id
8-bit register
clk
CALC
8

Digital Design 2e LEDs

Copyright 2010 64
Frank Vahid
 ALU
More efficient design uses ALU
ALU design not just separate components multiplexed (same problem as previous
slide)
Instead, ALU design uses single adder, plus logic in front of adders A and B inputs
Logic in front is called an arithmetic-logic extender
Extender modifies A and B inputs so desired operation appears at output of the adder

A B a7 b7 a6 b6 a0 b0
AL-extender
x
y AL-extender x
z y
z

IA IB abext abext abext cinext

Adder cin
a
IS ia7 ib7 ia6 ib6 ia0 ib0 cin
ALU (b)
S
(a)
Digital Design 2e
Copyright 2010 65
Frank Vahid
 Arithmetic-Logic Extender in Front of ALU
A B a7 b7 a6 b6 a0 b0
AL-extender
x
y AL-extender x
z y
z

IA IB abext abext abext cinext

Adder cin
IS ia7 ib7 ia6 ib6 ia0 ib0 cin
ALU (b)
S
(a)

xyz=000 Want S=A+B : just pass a to ia, b to ib, and set cin=0
xyz=001 Want S=A-B : pass a to ia, b to ib and set cin=1 (twos complement)
xyz=010 Want S=A+1 : pass a to ia, set ib=0, and set cin=1
xyz=011 Want S=A : pass a to ia, set ib=0, and set cin=0
xyz=100 Want S=A AND B : set ia=a*b, b=0, and cin=0
Others: likewise
Based on above, create logic for ia(x,y,z,a,b) and ib(x,y,z,a,b) for each abext, and
create logic for cin(x,y,z), to complete design of the AL-extender component
Digital Design 2e
Copyright 2010 66
Frank Vahid
 ALU Example: Multifunction Calculator
DIP swi tches
1
0
8 8

A B

+ +1 Wast ed
AND OR XOR NOT p o w er
8 8
8
8
8 8 8
DIP switches
8
1 0 0 1 2 3 4 5 6 7 A lot of wi res.
x s2
y
z
s1
s0
8-bit 8 1
1 1
8

clk
e
Id
8-bit reg ist er 0 0
CALC
8

LEDs
8 8
A B
A B
Design using ALU is x
y
x
ALU
y
elegant and efficient z z S
8
No mass of wires e
ld
No big waste of power clk
8-bit register

8 CALC

LEDs

Digital Design 2e
Copyright 2010 67
Frank Vahid
 4.8

Shifters
Shifting (e.g., left shifting 0011 yields 0110) useful for:
Manipulating bits
Converting serial data to parallel (remember earlier above-mirror display
example with shift registers)
Multiply/divide by 2 (unsigned numbers only)
Shift left once is same as multiplying by 2. Ex: 0011 (3) becomes 0110 (6)
Why? Essentially appending a 0 -- Note that multiplying decimal number by 10
accomplished just be appending 0, i.e., by shifting left (55 becomes 550)
Shift right once same as dividing by 2 i3 i2 i1 i0

i3 i2 i1 i0 inR
i3 i2 i1 i0 inL

in 2 01 201 2 01 2 01
shL s0
01 01 01 01 shR s1
in
sh
a
<<1
q3 q2 q1 q0 q3 q2 q1 q0
Symbol Shifter with left
Left shifter q3 q2 q1 q0
shift, right shift,
Digital Design 2e Shifter with left and no shift
Copyright 2010 68
Frank Vahid shift or no shift
 Shifter Example: Temperature Averager
Four registers storing a
0000111 (7) 001000 (8) 001100 (12) 001111 (15)
history of temperatures T
Ra Rb Rc Rd
Want to output the average clk
of those temperatures ld
ld

Add + +
a
Use three adders +
Then divide by four shift in 0 0101010 (42) divide by 4

Same as shift right by 2 0 >>2

0001010 (10) Note rounding
Ravg
ld

Tavg

Digital Design 2e
Copyright 2010 69
Frank Vahid
 Strength Reduction
Many multiplications not by power of 2 constants (2, 4, 8, )
E.g., by 5, or 10
Could use multiplier component, but shifters are small and fast
Replace multiplication by shifts and adds
Operator strength reduction (multiply is stronger than shift/add)
E.g., 5*C 4*C + C (4*C same as C<<2)
Replacing division by shifts and adds slightly harder
Approximate fraction using fraction having power of 2 denominator
E.g., C/5 = 0.20*C, approx. equals (102/512)*C = 0.199*C
(102/512)*C = C*(64+32+4+2)/512 = (C*64 + C*32 + C*4+C*2)/512
= ((C<<6) + (C<<5) + (C<<2) + (C<<1)) >> 9

Digital Design 2e
Copyright 2010 70
Frank Vahid
 Celsius to Fahrenheit Converter
C
F = C*9/5 + 32 16
F = C + C*4/5 + 32
F = C + 4*(C*64+C*32+C*4+C*2)/512 +32 <<6 <<5 <<2 <<1

(1/5 from prev. slide)

F = C + (C*64+C*32+C*4+C*2)/128+32 + +

+
a

Note: Uses wider buses, padded on the left, to >>7

avoid losing bits during shifts

Determine biggest possible internal values, +
0000000000100000
set width accordingly
Do divisions as late as possible to reduce +

rounding errors 16

F = C +(C*64+C*32+C*4+C*2)/128 + 32

Digital Design 2e
Copyright 2010 71
Frank Vahid
 Barrel Shifter i3 i2 i1 i0
in
A shifter that can shift by any amount 01 01 01 01
sh
4-bit barrel left shift can shift left by 0,
1, 2, or 3 positions
q3 q2 q1 q0
8-bit barrel left shifter can shift left by Shift by 1 shifter uses 2x1 muxes. 8x1
0, 1, 2, 3, 4, 5, 6, or 7 positions mux solution for 8-bit barrel shifter: too
(Shifting an 8-bit number by 8 positions many wires.
is pointless -- you just lose all the bits) Q: xyz=??? to
I
Could design using 8x1 muxes shift by 5? 8 00000110
1
Too many wires x sh <<4 in 0
More elegant design 8 01100000
Chain three shifters: 4, 2, and 1 0 a

Can achieve any shift of 0..7 by y sh <<2 in 0

enabling the correct combination of 8 01100000
those three shifters, i.e., shifts should 1
sum to desired amount z sh <<1 in 0

Digital Design 2e
Net result: shift by 5:8 11000000
Copyright 2010 Q 72
Frank Vahid
 4.9

Counters and Timers

N-bit up-counter: N-bit register 0 clr
01 cnt 4-bit up-counter
that can increment (add 1) to its tc C
a

own value on each clock cycle 4

0000, 0001, 0010, 0011, ...., 1110, 01 0001

0000
0101
0100
0011
0010
1110
...
1111
1111, 0000
Count rolls over from 1111 to 0000
Terminal (last) count, tc, equals1 4-bit up-counter

during value just before rollover clr

clr
Internal design cnt Id 4-bit register

Register, incrementer, and N-input

4 4 a
AND gate to detect terminal count +1
4
4
tc C

Digital Design 2e
Copyright 2010 73
Frank Vahid
 Counter Example: Turnstile with Display
Count people passing
through a turnstile
Assume turnstile
generates 1-clock pulse
on P
Connect count to display
reset
Button can reset count
clr
Simple solution using up- from
turnstile P cnt 32-bit up-counter
counter clk tc
32
unused

Display 8,406

Digital Design 2e
Copyright 2010 74
Frank Vahid
 Up/Down-Counter
Can count either up 4-bit up/down counter
or down
Includes both dir
1 4-bit 2 x 1 0
incrementer and 4
decrementer
clr
Use dir input to cnt
clr
ld 4-bit register
select, via 2x1 mux:
dir=0 means up
Likewise, dir selects 4 4 4 4
appropriate terminal 1 +1
4
count value (all 1s
4 4
or all 0s)
1 2x 1 0
tc C

Digital Design 2e
Copyright 2010 75
Frank Vahid
 Counter with Load
Up-counter that can be
L 4
loaded with external
ld
value 1 4-bit 2x1 0
4
Designed using 2x1 mux.
ld input selects cnt Id
clr 4-bit register
incremented value or clr

external value
4 4
Load the internal register 4 +1
when loading external
value or when counting tc C

Note that ld has priority

over cnt

Digital Design 2e
Copyright 2010 76
Frank Vahid
 Counter with Parallel Load
Useful to create pulses at 1000
specific multiples of clock 4

Not just at N-bit counters natural

wrap-around of 2N ld L
Example: Pulse every 9 clock 1
cnt 4-bit down-counter
cycles
Use 4-bit down-counter with clk
tc C
parallel load 4
Set parallel load input to 8 (1000)
Use terminal count to reload
When count reaches 0, next cycle
loads 8.
Why load 8 and not 9? Because 0
is included in count sequence:
8, 7, 6, 5, 4, 3, 2, 1, 0 9 counts
Digital Design 2e
Copyright 2010 77
Frank Vahid
 Counter Example:
New Years Eve Countdown Display
Chapter 2 example previously used microprocessor to count from 59 down
to 0 in binary
Can use 8-bit (or 7- or 6-bit) down-counter instead, initially loaded with 59
Happy
0 New
8 d0 Year!
59 L c0 i0
d1
c1 i1 1
d2
c2 i2 2
ld c3 i3 d3 3
c4 i4 Note: Use 8-
0 clr c5 i5 bit counter,
d58
c6 not 60-bit
cnt d59 counter
c7
d60
d61 58
clk 8-bit d62 59
fireworks
1 Hz down- 6x64
tc
counter dcd d63
Digital Design 2e
Copyright 2010 78
Frank Vahid
 Common Counter Use: Clock Divider
Suppose have 512 Hz
oscillator, but want 2 Hz
pulse
Thus, want divide fast clock 1
cnt 8-bit up-counter
by 256 osc
tc C
Design using 8-bit up- 512 MHz 8
p (unused)
counter, use tc output as 2 MHz
pulse
Counts from 0 to 255 (256
counts), so pulses tc every
256 cycles

Digital Design 2e
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Frank Vahid
 Clock Division by Amount not Power of 2
Example: 1 Hz Pulse Generator from 60 Hz Clock
Example: U.S. electricity standard uses 60 Hz signal
Device may convert that to 1 Hz signal to count seconds
Use 6-bit up-counter
Up counter: Detected count of 59 clears counter to 0; tc thus pulses every 60
cycles
Note: Detect 59, not 60 (because the first number, 0, is included)
Down counter approach also possible: When count reaches 0, load 59
1 11 0 11
clr
1 cnt 6-bit up-counter ld
osc tc C cnt
1 6-bit down-counter
60 Hz
osc tc C
p
60 Hz
p
unused
1 Hz

1 Hz
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Frank Vahid
 Measuring Time Between Events using an Up-Counter
Initially clear to 0. 1st event: Set cnt=1. 2nd event: Set cnt=0.
Then, multiply counted clock cycles by clock period to determine time
Ex: Highway speed measurement system
Two sensors a and b in road
Use FSM to detect a becoming 1, set cnt=1. Set cnt=0 when b 1
If clock is 1 kHz (period is 1 ms), then time is C * 0.001s
If a and b separated by 0.01 miles, then vehicle speed in mph is:
0.01 miles / (time * (1 hour / 3600 seconds))
E.g., if C is 500, then speed is 0.01 / ((500*0.001) / 3600) = 72 mph
Speed
a b Measurer
clr
a b
vehicle S0 S1 S2 cnt
C
clr=1 cnt=1 cnt=0
b (compute time 16
Speed s
Measurer and output
a speed)
Digital Design 2e
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Frank Vahid
 M

Timers -1
32
load
Pulses output at user- ld
32-bit register

specified timer interval when

enabled 1 4-bit 2x1 0

Ticks like a clock ld

Interval specified as multiple of enable cnt

32-bit
down-counter
base time unit 1 microsec tc C
oscillator
If base is 1 microsec and user unused
Q
wants pulse every 300 ms,
(a)
loads 300,000 into timer
32
Can design using oscillator,
M
register, and down-counter Q
load
enable 32-bit
1-microsec
(b)
Q timer

(c)
Digital Design 2e
Copyright 2010 82
Frank Vahid
 b

Timer Example: Laser Surgery

Laser
Surgery laser
x
System

System
clk

patient
(a)
Recall Chpt 3 laser surgery 300,000 (in binary)

example b ld M
load
Clock was 10 ns, wanted 30 ns, Controller
en
enable 32-bit
Q 1 microsec
used 3 states. clk Q
timer

What if wanted 300 ms? Adding 30 x

million states is not reasonable. (b)

Use timer
10 ns
clk
...
Controller FSM loads timer, Inputs:
enables, then waits for Q=1 b ...
300 ms
Q ...
Inputs: b, Q Outputs: ld, en, x
State Off Off Off Off Strt On ... On Off
x=0 ...
ld=1 Off b' Outputs:
en=0 x
b Q Q'
ld ...
x=0 x=1
ld=0 Strt On ld=0 en ...
Digital Design 2e en=1 en=1
Copyright 2010 (d) 83
Frank Vahid (c)
 4.10

Register Files

Accessing one of C
32
9
C 8 a
several registers is: d0d0 load reg0
load reg0 T huge mux
OK if just a few registers 4x162 4
32
i0 i0
Problematic when many too much 9 8
32-bit
8-bit
d1 fanout
load reg1 A
4 a0 9 41
16x1
Ex: Earlier above-mirror i0
i1
display, with 16 registers i3-i0i1 9 8
a1 9 dd DD
d2 load reg2 I
Much fanout (branching 9
328
of wire): Weakens signal i2
8 congestion
Many wires: Congestion d15
d3 load reg3
load reg15 M
e 16*32 =
e
load i15i3 512
s1 s0wires
load 32 8
s3-s0
4 32-bit registers tolerable x y
16 32-bit registers
begins to have fanout and wire
Digital Design 2e problems
Copyright 2010 84
Frank Vahid
 Register File
MxN register file: Efficient design for one-at-a-time write/read of many
registers
Consider 16 32-bit registers
Called write port

32 32 32-bit data that is read

read port
32-bit data to write W_data R_data
4-bit address specifies 4 4 4-bit address to specifies
W_addr R_addr
which register to write which register to read
W_en R_en
Enable (load) line: Reg 1632
Enable read
written on next clock register file
a

Digital Design 2e
Copyright 2010 85
Frank Vahid
 Register File 9
W_data
32
bus 9 32 9
R_data
d0 load reg0 driver d0
Internal design uses 2x4
32 9 2x4
drivers and bus 9
d1 load reg1 d1 a
1 1
driver W_addr
i0
i1
9
32 i0
i1
R_addr
1 load reg2 9 1
d2 d2
d q
write 32 read
q=d decoder 1 decoder
d3 load reg3
9 1 d3
Boosts signal e e
32 9 9
W_en R_en
three-state driver 1 4x32 register file 1
a c
d q Internal design of 4x32 RF; 16x32 RF follows similarly

c=1: q=d d q
d
c=0: q= Z q
like no connection

Note: Each driver in figure

actually represents 32 1-bit drivers
Digital Design 2e
Copyright 2010 86
Frank Vahid
 Register File Timing Diagram
Can write one cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6
clk
register and read 1 2 3 4 5 6
one register each W_data 9 22 X X 177 555
clock cycle W_addr 3 1 X X 2 3
May be same
W_en
register
R_data Z Z Z 9 Z 22 9 555

R_addr X X 3 X 1 3

R_en

0: ? 0: ? 0: ? 0: ? 0: ? 0: ? 0: ?
32 32
1: ? 1: ? 1: 22 1: 22 1: 22 1: 22 1: 22
W_data R_data
2: ? 2: ? 2: ? 2: ? 2: ? 2: 177 2: 177
2 2
W_addr R_addr
3: ? 3: 9 3: 9 3: 9 3: 9 3: 9 3: 555

W_en R_en
4x32
register file

Digital Design 2e
Copyright 2010 87
Frank Vahid
 Register-File Example: Above-Mirror Display
16 32-bit registers that
can be written by cars 32
OLD design
C
computer, and d0 load reg0
a

huge mux
displayed 32
i0
4 16
Use 16x32 register file C too much
32 32
32-bit D
W_data
fanout R_data
Simple, elegant design 4 WA 4
16x 1
4
W_addr R_addr
Register file hides i3-i0 load
W_en R_en d D
complexity internally 16x32
register file
1 32
RA
And because only one congestion
register needs to be e
d15 load reg15

written and/or read at a load

i15
32 s3-s0
time, internal design is
simple

Digital Design 2e
Copyright 2010 88
Frank Vahid
 Chapter Summary
Need datapath components to store and operate on multi-bit data
Also known as register-transfer-level (RTL) components
Components introduced
Registers
Adders
Comparators
Multipliers
Subtractors
Arithmetic-Logic Units
Shifters
Counters and Timers
Register Files
Next chapter combines knowledge of combinational logic design,
sequential logic design, and datapath components, to build digital
circuits that can perform general and powerful computations

Digital Design 2e
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Frank Vahid