422 IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION, VOL. 55, NO.
2, FEBRUARY 2007
A Layered Finite Element Method for Electromagnetic
Analysis of Large-Scale High-Frequency
Integrated Circuits
Dan Jiao, Senior Member, IEEE, Sourav Chakravarty, and Changhong Dai
AbstractA high-capacity electromagnetic solution, layered fi-
nite element method, is proposed for high-frequency modeling of
large-scale three-dimensional on-chip circuits. In this method, first,
the matrix system of the original 3-D problem is reduced to that of
2-D layers. Second, the matrix system of 2-D layers is further re-
duced to that of a single layer. Third, an algorithm of logarithmic
complexity is proposed to further speed up the analysis. In addi-
tion, an excitation and extraction technique is developed to limit
the field unknowns needed for the final circuit extraction to a single
layer only, as well as keep the right-hand side intact during the
matrix reduction process. The entire procedure is numerically rig-
orous without making any theoretical approximation. The compu-
tational complexity only involves solving a single layer irrespec-
tive of the original problem size. Hence, the proposed method is
equipped with a high capacity to solve large-scale IC problems. The
proposed method was used to simulate a set of large-scale inter-
connect structures that were fabricated on a test chip using con-
ventional Si processing techniques. Excellent agreement with the
measured data has been observed from dc to 50 GHz.
Index TermsElectromagnetics, finite element method, high ca-
pacity, high frequency, on-chip circuits, three dimension.
I. INTRODUCTION
S ON-CHIP designers move to faster clock frequencies
A enabled by process technology scaling with reduced
feature sizes, electromagnetic analysis has drawn the attention
of the on-chip design community. In 2001, a research team at
Intel started to validate RLC-based parasitic extraction at tens
of gigahertz. Significant mismatch between measurements and
RLC models was observed at multigigahertz frequencies on
3-D interconnect bus structures [1]. In contrast, full-wave elec-
tromagnetic-based modeling accurately captured the measured
behavior over the entire frequency band [1], [2]. The mismatch
between RLC models and measurements was attributed to
the decoupled E and H model employed in static modeling
by extracting the capacitance and inductance independent of
each other [1]. This finding demonstrated the importance of
full-wave electromagnetic-based solutions in high-frequency
Manuscript received May 21, 2006; revised August 31, 2006. This work was
supported in part by a grant from the Office of Naval Research under Award
N00014-06-1-0716 and in part by a grant from Intel Corporation.
D. Jiao is with the School of Electrical and Computer Engineering, Purdue
University, West Lafayette, IN 47906 USA (e-mail: djiao@purdue.edu).
S. Chakravarty and C. Dai are with the Design and Technology Solutions,
Intel Corporation, Santa Clara, CA 95052-8119 USA.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TAP.2006.889847
0018-926X/$25.00 2007 IEEE
IC design [3]. The importance has been further realized in
todays low power design. In power efficient mobile chips, low
power states and clock gating are gaining momentum as the
main power saving mechanisms. In these architectures, entire
blocks of circuits are switched on and off to achieve an optimal
power-performance operating point. These power reduction
techniques result in large processor current variations and fast
transient droops and noises in the power supply network, which
cannot be accurately captured by a static-based IR drop or
transient droop analysis.
In addition to high-frequency digital IC design, electromag-
netic analysis is also of paramount importance to analog, RF,
and mixed-signal IC design. Integrated computing and commu-
nication calls for increasing levels of integration of RF, ana-
logue, and digital systems. Integrating as many circuits as pos-
sible on the same die leads often to undesired coupling and
sometimes to system failure. For instance, switching currents
induced by logic circuits cause ringing in the power-supply rails
and in the output driver circuitry. This, in turn, couples through
the common substrate to corrupt sensitive analog signals on the
same chip. Prevailing circuit-based signal integrity paradigms
are reaching their limits of predictive accuracy when applied to
high-frequency mixed-signal settings. An electromagnetic so-
lution is indispensable to sustain the continual scaling and inte-
gration of digital, analog, mixed-signal, and RF circuitry.
However, high-frequency IC design imposes many modeling
challenges to electromagnetic analysis. These challenges in-
clude conductor loss, large numbers of dielectric stacks, strong
non-uniformity, the presence of substrate, large numbers of
conductors, large aspect ratio, broadband, and 3-D complexity
[3]. Almost every challenge increases the number of unknowns,
and hence the problem size one needs to solve when tackling
an IC problem. For instance, due to conductor loss, one has to
discretize into conductors with very fine elements to capture
rapid field variation within skin depth. This generates a large
number of unknowns even for small on-chip structures. In
addition to on-chip intricacy that increases the problem size,
the need for full-chip analysis also stresses problem size. A
full-chip analysis is often needed to capture the global electrical
interactions between integrated circuits on the die, and between
the die and the package. However, to date, the fastest integral
equation solver needs operations and
storage in dealing with -unknown electrodynamic problems;
the fastest partial-differential-equation based solvers scale
as in both memory requirement and CPU cost. This
performance is generally regarded as the limit that one can
JIAO et al.: A LAYERED FINITE ELEMENT METHOD FOR ELECTROMAGNETIC ANALYSIS 423

achieve in computational electromagnetics. Since is a big

number in IC analysis even for a circuitry of a modest size, the
current performance of computational electromagnetic tech-
niques is still insufficient when tackling a realistic IC design
problem that can involve billions of unknowns. Therefore, it is
of paramount importance to study and develop a high-capacity
electromagnetic solution.
Having realized the importance of full-wave electromagnetic
analysis in high frequency chip design, and the unique mod-
eling challenges of IC problems, researchers in both circuit and
fields have been working on developing innovative electromag-
netic solutions [2][13]. However, most of the research efforts
have been placed on enriching existing electromagnetic mod-
eling techniques with new capabilities to address on-chip intri-
cacy. Little work has been reported in open literature on high-ca-
pacity electromagnetic solutions, which can potentially tackle
full-chip problems. In [2], we presented a novel, rigorous, and
fast method for the full-wave modeling of large-scale high speed Fig. 1. 3-D circuit problems. (a) RF CMOS. (b) Global on-chip interconnects.
interconnect structures. In this method, a general interconnect (c) RF IC.
structure is decomposed into a few structure seeds. In each struc-
ture seed, the original wave propagation problem is represented
To solve (1), we formulate a numerical algorithm to obtain
into a generalized eigenvalue problem. A novel mode-matching
the fields or fields inside the computational domain at each
technique is developed to solve large-scale 3-D problems by
discretized point, from which the design parameters of interest
using 2-D-like CPU time and memory. This method has shown
are obtained. Due to the computational complexity of on-chip
great capability in modeling Manhattan-type large-scale inter-
circuit problems as stated in Section I, the resultant numerical
connect structures. In this paper, we propose a layered finite el-
system is generally extremely big even for a small circuitry. This
ement method to tackle both Manhattan- and non-Manhattan-
prevents the direct use of existing computational electromag-
type large-scale multilayered structures. Layout periodicity can
netic techniques in guiding chip-level high-frequency IC design.
be employed to further speed up the proposed method, but it is
We propose to tackle this problem by developing a layered fi-
not a must to achieve the high capacity of the proposed method.
nite-element method.
We will elaborate this method in the following six sections:
Section II problem statement, Section III layered finite-element III. LAYERED FINITE ELEMENT SCHEME
scheme, Section IV reduction of the 3-D layered system matrix
to a 2-D layered one, Section V reduction of the 2-D layered In accordance with variational principle [14], the solution to
system matrix to a single-layer one, Section VI an algorithm of the boundary value problem defined by (1) and its boundary
logarithmic complexity for further speed-up, Section VII excita- conditions can be obtained by seeking the stationary point of
tion and extraction, and Section VIII performance analysis. Fi- the functional
nally, we will demonstrate the accuracy and high capacity of the
proposed method by a number of numerical and experimental
results.

II. PROBLEM STATEMENT

Consider 3-D circuit problems shown in Fig. 1.
The circuit can be a RF CMOS device metallic system,
a global on-chip interconnect structure, an RF IC circuit, or
others. Inside these circuits, the electric field satisfies the
second-order vector wave equation
(1)
(2)
In (2), denotes the truncation boundary, which is the outer-
most region in the computational domain. is an operator as-
sociated with the absorbing boundary condition placed on the
truncation boundary. If the first-order absorbing boundary con-
dition is used, (2) can be written as

subject to certain boundary conditions. In (1), the bar over

denotes a complex permittivity that comprises both permittivity
and conductivity; is the relative permeability; and are
free-space wave number and impedance, respectively; is the
current source; V is the computational domain that encloses
the circuit. The stack-growth direction is defined as and used
(3)
throughout this paper.
424 IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION, VOL. 55, NO. 2, FEBRUARY 2007

Fig. 3. Unknown ordering scheme.

Fig. 2. Illustration of prism vector basis functions.

In (5), , and are area coordinates (also known as node
basis functions ([14, pp. 80]), is 0 at the bottom plane, and
For the boundaries that are shorted to ground, tangential is ex- 1 at the upper plane. Clearly, as shown in Fig. 2, basis func-
plicitly enforced to be zero therein. Next, we perform discretiza- tions , and reside on the surfaces of
tion. The discretization is conducted for both dielectric regions each layer, and hence their associated unknowns are called as
and conducting regions. Disretizing into conductors allows for surface unknowns throughout this paper, while the unknowns
an accurate modeling of conductor loss. The triangular prism el- associated with basis functions , and are named
ements are used to discretize the computational domain. These as volume unknowns. From (5), one can also see clearly that
elements are very suitable for the discretization of on-chip struc- the surface basis functions , and are
tures, which are multilayered structures. They extrude along the formed by multiplying or with edge basis functions
layer-growth direction while capturing the irregular geometry ([14, pp. 234237]).
in the transverse cross section. This allows for the modeling of Substituting (4) into (3), and taking the partial derivative of
irregular on-chip circuits such as trapezoidal- and spiral-type (3) with respect to unknown coefficients yield the following
interconnects. In this method, the layer-growth direction can be matrix equation:
chosen the same as the natural layer-growth direction, which is
the stack-growth direction. It can also be chosen from other di-
rections to minimize the number of unknowns in the transverse (6)
cross section that is perpendicular to the layer-growth direction. in which and are assembled from their elemental
For example, a Manhattan-type integrated circuit structure is counterparts
layered by looking from any of , and directions. There-
fore, the layer-growth direction can be chosen from any of the
, and directions to render a transverse cross section that
has the minimal problem size. (7)
In each prism element, the electric field is expanded into
prism vector basis functions [15] In (7), the inner product is defined as

(4)
(8)

The superscript denotes element. In each prism element,
there are nine vector bases as shown in Fig. 2.
These functions can be written as
By ordering the unknowns layer by layer as shown in Fig. 3, we
generate a banded matrix . Though a banded matrix, its solu-
tion can be highly computationally expensive when the number
of unknowns is large. A direct solution generally requires a large
amount of memory; an iterative solution can converge slowly,
and is inefficient in the presence of multiple right-hand sides.
To solve this problem, we first reduce the system matrix to
one that only involves 2-D surface unknowns in each layer, the
detail of which is illustrated in the next section.

IV. REDUCTION OF THE 3-D LAYERED SYSTEM MATRIX

TO A 2-D LAYERED ONE
To form a matrix system that only involves 2-D surface un-
knowns in each layer, we need to eliminate volume unknowns.
(5) This can be achieved by using the procedure we proposed in
JIAO et al.: A LAYERED FINITE ELEMENT METHOD FOR ELECTROMAGNETIC ANALYSIS 425

As a result, the need of evaluating and

is eliminated and only needs to be evaluated.
c) Matrix is equal to matrix in each layer

(12)
Fig. 4. Procedure of eliminating volume unknowns.
in which is the layer thickness. Therefore, based on b)
and c), the following equality holds true:
[16]. For instance, the volumetric unknowns in Layer 1, which
is , can be eliminated by using the procedure illustrated in
Fig. 4. and are the surface unknowns on the top and (13)
bottom surfaces of Layer 1.
d) Matrix is linearly proportional to the layer thickness.
In Fig. 4, matrix is formed between unknowns and
In fact, matrix is assembled from the following ele-
is formed between unknowns and is
mental matrix:
formed between unknowns and is formed between
unknowns and is formed between unknowns
and and is formed between unknowns and . (14)
The relationship between the transformed matrices and the
original matrices can be written as Therefore, matrix only needs to be formed and inverted
for a layer of unit thickness. Others can be obtained by
scaling accordingly.
e) For interconnect structures, matrix only needs to be
formed for each unique structure seed.
The concept of structure seeds in 3-D interconnect structures
(9) was first introduced in [2]. A structure seed has a unique cross
Essentially, the volume unknowns are eliminated by using the section. For a 3-D bus structure of orthogonal layers, the
relationship between the surface and volume unknowns. This number of structure seeds is . This number is small. For in-
relationship can be also used to recover volume unknowns from stance, for an interconnect involving seven metal layers, this
the surface unknowns. number is only 8 irrespective of the number of wires. If we
From (9), apparently, in order to eliminate volume unknowns, choose the layer-growth direction to be either or [please
one needs to fill in matrices , and for each refer to Fig. 1(b)], then each layer features the same dielectric
layer. In addition, one has to evaluate , and configuration. Then, from (14), one can see clearly that matrix
for each layer. The resultant computational cost can of unit thickness is different only when the conductor config-
be very high when the number of layers is large as well as the uration is different. Hence, matrix only needs to be formed
number of unknowns in each layer. In this paper, a fast tech- and inverted for each structure seed of unit thickness. The in-
nique is proposed to eliminate the volume unknowns efficiently. verse of matrix in each layer can then be readily obtained by
This fast technique is achieved by deriving the following matrix linearly scaling the structure-seed-based inverse matrix with the
properties. layer thickness .
a) Matrix is the same for all the layers. As an immediate result of the aforementioned factors, the
This is because matrix is assembled from the following computational cost of reducing the 3-D system matrix to a 2-D
elemental matrix: layered one only involves solving for each structure
seed. Since and are extremely sparse matrices, and gener-
ally there are only a few structure seeds for on-chip interconnect
(10) structures, the reduction can be performed very efficiently.

In (10), denotes the region forming a triangular element,
is the edge basis function ([14, pp. 234237]), and
is the node basis function ([14, pp. 80]). Since the perme-
ability does not change in the realistic on-chip struc-
tures, remains the same for all the layers. Therefore,
matrix only needs to be filled for one layer.
b) Matrices and are correlated
(11)
V. REDUCTION OF THE 2-D LAYERED SYSTEM MATRIX
TO A SINGLE-LAYER ONE
With all the volume unknowns eliminated, we obtain a system
matrix that only involves 2-D surface unknowns in each layer. If
the number of layers is only a few, we can stop there and solve
the reduced system matrix as a whole without further reduc-
tion. However, in reality, we often encounter a large number of
layers. For example, in a realistic on-chip interconnect structure,
one can encounter a large number of layers by either segmenting
along the or direction. Therefore, further reduction is often
426 IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION, VOL. 55, NO. 2, FEBRUARY 2007
Fig. 5. Matrix cascading.
needed. Hence, we continue to reduce the dimension of the
system matrix to the size that one can handle with available com-
putational resources. For instance, if one is only able to handle
ten layers, we reduce the system to involve only ten layers; if one
can only handle one layer, we reduce the system matrix all the
way down to the one that only involves single-layer unknowns.
The reduction process is conducted by matrix cascading.
Fig. 5 illustrates a matrix cascading process, in which
, and denote the top surface unknowns of layer 1,
layer 2, and layer 3, respectively. Cascading layer 1 with layer
2 is equivalent to eliminating unknowns. The relationship
between the submatrices in the reduced matrix and the original
ones can be written as
(15)
The reduction in (15) can be achieved efficiently by using sym-
metric backward Gaussian elimination [17]. To be specific, the
unknowns to be eliminated are first reordered to the bottom.
They are then eliminated one by one by symmetric backward
Gaussian elimination. Since the cascading is performed on the
field-based matrix in each layer, the tangential field continuity
is guaranteed at each interface. Therefore, different from cir-
cuit-port based cascading, the cascading procedure proposed
here is rigorous.
Now, assuming one is interested in layer , the matrix in each
layer before the th layer can be cascaded together to form ma-
trix . Similarly, those matrices after the th layer can be cas-
caded together to form matrix . If one is equipped with suf-
ficient resources to solve three layers, he can stop here: solving
the reduced matrix system shown in Fig. 6 to obtain the solu-
tion. If not, he can continue to cascade the three layers together
to form one that only involves single-layer unknowns. The mul-
tiple-layer matrix cascading can be implemented either serially
or in parallel.
Serial Implementation: First we cascade layer 1 with layer
2 using the procedure shown in Fig. 5, we obtain matrix
which is a square matrix relating unknowns to . The
interface unknowns is eliminated in this process. We then
cascade the with the submatrix in layer 3 to form matrix
, which is a square matrix relating unknowns to
In this process is eliminated. We continue this procedure
until we reach the th layer, the resultant matrix is
which relates to , where are the top surface un-
knowns of layer . Similarly, we cascade from layer to
layer to obtain matrix . Clearly the computational cost is
Fig. 6. Reduction of the 2-D layered system to a single-layer one.
the number of cascading multiplied by the time cost in each cas-
cading. The former is equal to the number of layers minus one,
while the latter is the cost of a single-layer unknown elimina-
tion. Therefore if one is capable of solving one-layer matrix, he
is capable of solving all the layers. However, due to the large
number of layers, this implementation could be slow despite the
high capacity it can achieve. A fast version can be obtained by
parallel implementation.
Parallel Implementation: Assuming there are L layers, we di-
vide them into L/2 groups. Each group consists of adjacent two
layers. Each group has no overlapping layers. We then assign
these L/2 groups to L/2 machines, each of which cascades two
matrices. Thus we obtain L/2 matrices simultaneously. We then
subdivide these matrices into L/4 groups, each of them again
contains a pair of matrices without overlapping. We then assign
them to L/4 machines, which return L/4 cascaded matrices si-
multaneously. We repeat this procedure until we have only two
matrices left. Clearly, with the above parallel implementation,
the computational cost is only multiplied by a single-
layer unknown elimination cost. This performance can be fur-
ther improved by exploring more advanced parallel algorithms.
VI. AN ALGORITHM OF LOGARITHMIC COMPLEXITY
FOR FURTHER SPEED-UP
If the on-chip structure is periodic with layers, com-
, plexity can be achieved even with a single machine. First, we use
the approaches in Sections IV and V to form the matrix for one
period. We then cascade two of this matrix to form the matrix
for two periods. We then cascade two of the two-period ma-
. trix to form the matrix for four periods. We continue this pro-
cedure until we reach the length of the structure. Clearly, for a
, structure which has layers, by using the aforementioned ap-
proach, one only needs to cascade times to reach the re-
quired length. This algorithm of logarithmic complexity drasti-
cally speeds up the analysis of periodic on-chip structures. This
JIAO et al.: A LAYERED FINITE ELEMENT METHOD FOR ELECTROMAGNETIC ANALYSIS
Fig. 7. Excitation and Extraction.
algorithm is also used to handle multiple layers resulted from the
discretization of thick silicon and conductors. For instance, the
thick silicon substrate often constitutes a numerical challenge to
a partial-differential-equation based solver because of the large
number of volume unknowns resulted from its discretization.
With this technique, it does not constitute a challenge any more
because one can account for its contribution to the rest of the
system in operations and single-layer storage. This algo-
rithm of logarithmic complexity, to certain extent, resembles the
one used for treating deep cavities with a constant cross section
[18].
VII. EXCITATION AND EXTRACTION
Here, we give a simple example to illustrate the excitation
and extraction scheme. Consider a wire sitting above a ground
plane as shown in Fig. 7. If the layer-growth direction is chosen
to be , we use a current source orientated in either or
direction; If the layer-growth direction is chosen to be , we
use a current source orientated in either or direction; if the
layer-growth direction is chosen to be , we use a current source
located in - plane. The purpose is to associate field unknowns
involved in the excitation and extraction to those remaining in
the final matrix system. For all the other unknowns, their cor-
responding right-hand sides are zero. Therefore, the matrix re-
duction process illustrated in Sections IV and V does not involve
the modification of the right-hand side at all, which is efficient.
Multiple columns of current filaments can be used from the wire
to the ground. Multiple rows can also be used. But they are all
placed in the layers or layer of interest. The right-hand sides
corresponding to the field unknowns associated with the current
filaments become
(16)
in which is the current and is the length of the current fil-
ament. When we inject current into one port, we leave other
ports open. We then sample the voltage generated at each port.
The voltage can be evaluated by performing a line integral of
the electric field from the port to the ground. Thus, we obtain
one column of the impedance matrix . We then inject current
into another port. We can obtain another column of matrix.
We continue this procedure by injecting current into each port
in turn. Finally, we obtain the entire matrix. From the ma-
trix, one can easily obtain both - and -parameter matrices.
It should be noted that, different from the general RLC-based
interconnect modeling process in which the extraction stage is
separated from the simulation stage, here one can obtain both
427
extraction and simulation results within one run. One can either
obtain the S-parameter model of the interconnects as aforemen-
tioned, or load the interconnect with current sources, and obtain
voltages directly from the proposed method. When the ground
plane is placed far away from the structure of interest, instead
of using a probe that goes all the way from the ground to the
structure, a short probe that does not start from the ground is
used. In doing so, the port current becomes unknown. It is ex-
tracted from the port voltages sampled at multiple points. With
port currents and voltages known, the Z-, Y-, and S-parameters
can be extracted.
VIII. PERFORMANCE ANALYSIS
The memory usage of the proposed method is modest com-
pared to the conventional finite element method. Maximally, it
only requires the storage of a single-layer matrix formed by sur-
face unknowns irrespective of the original problem size. There-
fore the proposed method possesses a high capacity to deal with
very large scale electromagnetic problems.
The CPU run time can be analyzed for step I and step
II in the content of both serial implementation and parallel
implementation.
Step I (Reduction of the 3-D Layered System Matrix to
a 2-D Layered One): Assuming the number of layers is
and the number of volume unknowns per layer is ,
the lower bound of the CPU cost for eliminating all the
volume unknowns is apparently . However, the
proposed method can achieve it in operations,
in which is the number of structure seed, which is gen-
erally much less than . If implemented in parallel, since
the elimination of the volume unknowns in different layers
is completely decoupled, each of them can be assigned to a
single processor, and no communication is needed between
the processors. Therefore, the CPU cost is just , the
cost of a single-layer sparse matrix inversion.
Step II (Reduction of the 2-D layered System Matrix to
a Single-layer One): Assuming the number of layers is ,
the total number of surface unknowns is the CPU cost
of the serial implementation can be estimated as
(17)
in which is the cost of a single-layer surface-un-
known elimination. The function depends on the compu-
tational complexity of the matrix solver used to solve the
single layer matrix. For instance, if an advanced sparse ma-
trix solver is used, can be a linear function
If an iterative solver such as the conjugate gradient method
is used
428 IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION, VOL. 55, NO. 2, FEBRUARY 2007

If a direct solver such as the LU decomposition is used

In contrast, the CPU cost of a conventional method is

(18)

assuming it uses the same matrix solver as used in the pro-

posed method for a fair comparison. Therefore, it can be
seen clearly from (17) and (18) that the speed up of step
II is determined by the speed of the conventional method.
The slower the conventional method is, the faster the pro-
posed method is. For instance, if the conventional method
uses LU decomposition to solve a matrix, the speed-up of
step II is . If the conventional method uses an advanced
sparse matrix solver that scales linearly with the number
of unknowns, then the serial implementation of step II
wouldnt save any CPU time. However, sparse solvers gen-
erally cannot scale linearly especially when the number
of unknowns is large. Therefore, one can still gain better
efficiency by implementing step II serially. Furthermore,
when multiple right-hand sides exist, due to the reduced
size of the final system matrix, the forward and backward
substitution time is much less compared to a conventional
direct solver. In addition, one benefits from the modest
memory usage of the proposed method. The CPU cost of
the parallel implementation of step II is log multiplied
by a single-layer elimination cost

(19)

This performance can be further improved by exploring more

advanced parallel algorithms. Therefore, compared to serial im-
plementation, the parallel implementation drastically speeds up
the analysis. It should be noted that the numerical procedure
of the proposed method facilitates the parallel implementation
because of the decoupled nature of subproblems, and hence
zeroing the communication between processors.

IX. EXAMPLES
To validate the proposed method, we simulated a set of inter-
connect structures that were fabricated on a test chip using con-
ventional Si processing techniques [1]. High resolution cross-
sectional scanning electron microscopy and optical microscopy
were used to measure the relevant dimensions of the fabricated
structures. Parasitics signals were removed from the measured
S-parameters using a de-embedding approach [1].
The first test structure is of 300 mu width. It involves a 10-mu Fig. 8. S-parameters of an on-chip interconnect structure of length 2000 mu.
wide strip in metal 2(M2) layer, one ground plane in metal 1 (a). S11 magnitude. (b) S11 phase. (c). S12 magnitude. (d) S12 phase.
(M1) layer, and one ground plane in metal 3 (M3) layer. The
distance of this strip to the M2 returns at the left- and right-hand
sides are 50 mu, respectively. The strip is of a length of 2000 mu. direction. The 2000 mu length is subdivided into 40 layers. The
The discretization is done in - plane, and extruded along the 2-D surface matrix is only formed for one layer. The algorithm
JIAO et al.: A LAYERED FINITE ELEMENT METHOD FOR ELECTROMAGNETIC ANALYSIS 429

of logarithmic complexity stated in Section VI is then used to

cascade all the layers to form one matrix that only involves the
surface unknowns on the near end and the far end planes. The
vertical current filament is placed between the ground and the
strip at the near end and the far end to excite the structure and
extract the circuit parameters. The back plane in M1 layer and
the top plane in M3 layer are both discretized to model the con-
ductor loss accurately. The simulated S-parameters are shown in
Fig. 8 in comparison with the measured data. Excellent agree-
ment is observed from dc to 50 GHz.
The second structure is a crosstalk structure. Two wires are
placed in the center of M2 layer. One is of 1.1 mu width, and the
other is of 2.07 mu width. The spacing between these two wires
is 2.0 mu. The distance to M2 returns at the left- and right-hand
sides is 10.1 mu. The solid planes in M1 and M3 layers in the
first test structure are replaced by 146 parallel returns, respec-
tively. These returns are 1.05-mu wide, and 1-mu apart. They
are shorted to the ground at the near and the far end. The struc-
ture is 2000 mu long. Like the first structure, only one structure
seed is involved. Hence, the 2-D surface matrix is formed for
one layer and cascaded by using the algorithm of logarithmic
complexity to form the final system matrix that only involves
surface unknowns at the near end and far end. In Fig. 9(b), we
compare measured and simulated crosstalk. Clearly the agree-
ment is good in both magnitude and phase. The current distri-
bution at 2 GHz at the near end of the structure is depicted in
Fig. 9(a).
The third structure again is a crosstalk structure. However,
the M1 and M3 metal layers are populated by orthogonal re-
turns. These returns are 1-mu wide each and 1-mu wide apart.
The length of the structure is 2000 mu. The crosstalk is mea-
sured between two wires embedded in the M2 layer. One is of
2.1 mu width; the other is of 1.1 mu width. The spacing between
these two wires is 1.95 mu. The distance to the M2 returns of
both wires is 10.3 mu. The 2-D surface matrices are formed for
two layers. One has the orthogonal returns present, while the
other does not. These two matrices are then cascaded to form
the matrix of a period. The one-period matrix is then cascaded
to form the matrix that covers 2000-mu length, and only involves
near-end and far-end surface unknowns. The current filaments Fig. 9. Simulation of an on-chip interconnect structure with parallel returns.
are placed between the ground and the M2 wires at the near and (a) Current distribution at 2 GHz. (b) Cross talk.
far end to extract circuit parameters. Fig. 10 shows the com-
parison of the simulated crosstalk in comparison with the mea-
sured data, which reveals an excellent agreement. If one uses a The backplane is 15-mu thick. Fig. 11(b) shows the Y parameter
standard finite element method to solve the problem, due to the and Q value simulated by the proposed method in comparison
densely populated orthogonal returns in M1 and M3 layers, one with those simulated by commercial electromagnetic simulator
has to solve over 3.043 million unknowns. In contrast, the pro- HFSS. Excellent agreement can be observed. Q value becomes
posed method solves the same problem rigorously using only negative because the inductor in fact becomes a capacitor at high
2270 unknowns. frequencies.
In the aforementioned examples, the layer-growth direction is Finally, we simulated a large-scale on-chip pentium4
chosen to be . In other words, the structure is segmented along M2-M8 power grid structure as shown in Fig. 12(a). The grid
. The layer-growth direction can also be chosen the same as the is 10 000 mu long and 200 mu wide. Before simulating this
stack-growth direction. This is useful to accommodate irregular example, we tested the accuracy of this method in power
geometries in the - plane. We simulated a spiral inductor to grid analysis by comparing its IR drop results at dc against a
demonstrate this capability. The geometry of the spiral inductor resistance (R)-based IR drop analysis. Since R-based analysis
is shown in Fig. 11(a). Its diameter (OD) is 1000 mu. The wire is generates a large number of resistances that are beyond the
50 mu wide ( mu) and 15 mu thick. The port separation, capability of a conventional SPICE-type circuit simulator, a
PS, is 50 mu. The inductor is backed by two package planes. 200 mu 400 mu block was sampled from the large-scale
430
Fig. 10. Crosstalk of a 3-D interconnect structure with orthogonal returns.
Fig. 11. Simulation of a RF spiral inductor. (a) Geometry. (b) Y-parameters
and Q value.
power grid for the purpose of validation. Eight C4 bumps
are landing at M8 wide metals, and 6-pair current sources
are attached at the bottom metal layer M4. Fig. 12(b) shows
IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION, VOL. 55, NO. 2, FEBRUARY 2007
Fig. 12. Simulation of an on-die power grid. (a) Geometry. (b) VSS voltage
droop at dc. (c) S-parameters.
the VSS voltage droop simulated by the proposed method in
comparison with those obtained by R-based analysis. Excellent
agreement can be observed. We then performed the dynamic
analysis of the entire structure. Eight ports were sampled on
the grid as shown in Fig. 12(a). Fig. 12(c) shows the calculated
S parameters. Despite the large number of unknowns, the peak
memory usage is only 738-Mbytes for this example.
X. CONCLUSION
In this paper, we proposed a layered finite element method
for high-frequency modeling of large-scale three-dimensional
on-chip circuit structures. This method is capable of solving
an orders-of-magnitude smaller system to rigorously obtain the
solution of the original big problem. The system matrix of the
original 3-D problem is first reduced to that of 2-D layers. For
on-chip interconnect structures, the computational cost of this
reduction is modest, only involving the solution of a few 2-D
structure seeds. The matrix system of 2-D layers is then further
JIAO et al.: A LAYERED FINITE ELEMENT METHOD FOR ELECTROMAGNETIC ANALYSIS
reduced to that of a single layer. This reduction only involves
single-layer unknowns irrespective of the original problem size.
As a result, the proposed method possesses a high capacity to
solve large-scale interconnect problems. Equally important, the
entire procedure is numerically rigorous without making any
theoretical approximation. In addition, it solves Maxwells cou-
pled E-H equations, and hence features uncompromised electro-
magnetic accuracy. Its accuracy and capacity are demonstrated
by numerical and experimental results.
ACKNOWLEDGMENT
The authors would like to thank M. J. Kobrinsky at Intel
Corporation for providing measured data, J. He (Intel) and
R. Chao (then Intel, now Taiwan National Chiao Tung Univer-
sity) for providing HFSS data.
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Dan Jiao (S00M02SM06) received the Ph.D.
degree in electrical engineering from the University
of Illinois at Urbana-Champaign, in October 2001.
From 2001 to September 2005, she was a Senior
CAD Engineer, Staff Engineer, and Senior Staff
Engineer in the Technology CAD Division at Intel
Corporation, Santa Clara, CA. In September 2005,
she joined Purdue University, West Lafayette, IN, as
an Assistant Professor in the School of Electrical and
Computer Engineering. She has authored two book
chapters and over 60 papers in refereed journals and
international conferences. Her current research interests include high frequency
digital, analogue, mixed-signal, and RF IC design and analysis, high-perfor-
mance VLSI CAD, modeling of micro- and nano-scale circuits, computational
electromagnetics, applied electromagnetics, fast and high-capacity numer-
ical methods, fast time domain analysis, scattering and antenna analysis,
RF, microwave, and millimeter wave circuits, wireless communication, and
bio-electromagnetics.
Dr. Jiao received the 2006 Jack and Cathie Kozik Faculty Start-up Award,
which recognizes an outstanding new faculty member in Purdue ECE. In
2004, she received the Best Paper Award from Intels annual corporate-wide
technology conference (Design and Test Technology Conference) for her work
on generic broadband model of high-speed circuits. In 2003, she won the
Intel Logic Technology Development (LTD) Divisional Achievement Award
in recognition of her work on the industry-leading BroadSpice modeling/sim-
ulation capability for designing high-speed microprocessors, packages, and
circuit boards. She was also awarded the Intel Technology CAD Divisional
Achievement Award for the development of innovative full-wave solvers for
high frequency IC design. In 2002, she was awarded by Intel Components
Research the Intel Hero Award (Intel-wide she was the tenth recipient) for the
timely and accurate two- and three- dimensional full-wave simulations. She
also won the Intel LTD Team Quality Award for her outstanding contribution
to the development of the measurement capability and simulation tools for
high frequency on-chip cross-talk. She was the winner of the 2000 Raj Mittra
Outstanding Research Award given her by the University of Illinois at Ur-
bana-Champaign. She has served as a reviewer for many IEEE journals and
conferences.
Sourav Chakravarty received the B.Tech. degree
in electronics and telecommunication from the
Regional Engineering College, Kurukshetra, India,
in 1992, the M.E. degree in telecommunications
from Jadavpur University, Calcutta, India, in 1997,
and the Ph.D. degree in electrical engineering from
the Pennsylvania State University, University Park,
in 2001.
From 1992 to 1995, he was a Senior Antenna
Design Engineer at Superline Microwave Pvt. Ltd.,
in Bangalore, India. He worked as a Research
Assistant in the Electromagnetic Communication Laboratory, Pennsylvania
State University, from 1997 to 2001. He is currently a Staff CAD Engineer at
Intel Corporation, Hillsboro, OR. His research interests include computational
electromagnetics with emphasis on probabilistic optimization techniques and
the applications of MoM and FDTD techniques to predict delay and crosstalk
in interconnects.
432 IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION, VOL. 55, NO. 2, FEBRUARY 2007
Changhong Dai received the B.S. degree in physics
from Beijing University, Beijing, China, in 1985, and
the M.S. and Ph.D. degrees in materials sciences and
engineering from Stanford University, Stanford, CA,
in 1992 and 1995, respectively.
He joined the Technology CAD Division of Intel
Corporation, Santa Clara, CA, in 1995, as a Senior
CAD Engineer. Since 1995, he has been an R&D En-
gineer or Manager for model and CAD tool develop-
ment for circuit analysis and physical design, in the
areas of circuit reliability, transistor modeling for cir-
cuit simulation, interconnect modeling for parasitic extraction, static and full
wave simulation of interconnects and RF devices, and power and power de-
livery modeling for IC product design. He is currently a Director with the Tech-
nology and Manufacturing Group of Intel Corporation, with the responsibility
of directing the development of Core CAD Technologies that enables Intel pro-
cessing technology and product design. His current responsibility covers the full
spectrum of CAD tool and infrastructure development with a focus of bridging
the processing technology and chip design.