MID-SEMESTER REPORT

ON

REDUCTION OF LEAKAGE POWER DISSIPATION IN CMOS

CIRCUITS

BY

SOMANSHU MISHRA 2015A8PS0427G

AT

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BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI
K.K. BIRLA GOA CAMPUS

IN REQUIREMENT OF COURSE INSTR F266

SUBMITTED ON 3 OCTOBER, 2017

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 ACKNOWLEDGEMENTS

I would like to thank Dr. C.K. Ramesha of BITS Pilani, K.K. Birla Goa Campus,
who is my guide and supervisor for the project for giving me the opportunity to
take this project under his supervision.

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 Title of the Project: REDUCTION OF LEAKAGE POWER DISSIPATION
IN CMOS CIRCUITS

ID Electronics and
No./Name(s)/ Somanshu Mishra 2015A8PS427G Instrumentation
Discipline(s)/o
f
the student(s)

Supervisor: Dr.C.K Ramesha BITS Pilani, K.K. Birla Goa Campus

Key Words: MTCMOS , VTCMOS , SOC ,CLOCK GATING ,SCALING

Project Areas Low power Vlsi Design

Abstract: This project aims to study the urgent need for reduction of
leakage power , short channel effects ,its consequences different
power minimization techniques and trying to propose an efficient
design

Signature(s) of Student(s) Signature of SOP Faculty

Plan for Coursework

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S.No. Description of Work Estimated duration and
element Time for completion

1 Study of different types of (8-15) August,2017

Power dissipation and need for reducing
leakage power

2 Study of switching power dissipation, (15-22) August,2017

Switching activity, glitching power
dissipation

3 Study of various short-channel (22-30) August,2017

effects

4 Study of leakage minimization techniques (1-14) September,2017

MTCMOS, VTCMOS

5 Clock gating and reduction of dynamic (15-25) September,2017

power
consumption

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 TABLE OF CONTENTS

Sr. no. Content Page no.

1 Introduction to leakage power dissipation 7

And subsequent need to reduce it

2 Types of power dissipation 10-11

3 Switching & glitching power dissipation 11-13

4 Various short-channel effects 15-17

5 Leakage power minimisation techniques 17-21

6 Reduction of dynamic power consumption using clock 22-25

gating

7 References 27

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 Problem Statement : Why worry about Leakage Power Dissipation? Why
low-power VLSI Design?
According to Moores law the number of transistors that can be placed
inexpensively on an integrated circuit will double approximately after two
years. This statement has often been subject to criticism : while it boldly states
the blessing of aggressive scaling but it fails to expose its bane. A direct
consequence of Moores low is that power density of an integrated circuit
increases exponentially with every technology generation. Since the 1970s,
most popular electronics manufacturing technologies used bipolar and nMOS
transistors. However, bipolar and nMOS transistors consume energy even in
their stable combinatorial state, and consequently, by 1980s, the power density
of bipolar designs was considered too high to be sustainable. IBM and Cray
started developing liquid, and nitrogen cooling solutions for higher-performance
computing systems. The 1990s saw an inevitable switch to a slower, but lower-
power CMOS technology.

So, subsequent need for low-power design came into picture when the leakage
power dissipation started to increase exponentially in every generation. With
aggressive scaling the leakage power started becoming comparable to the active
power. This was the point when actually researchers started worrying about it.

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Trend for Intel microprocessors

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 Power Dissipation

Power dissipation is measured commonly expressed in terms of two types of

metrics:

1. Peak power: Peak power consumed is the maximum amount of power that a
device can consume at any point of time. The high value of peak power is
generally associated with device failures or ruptures , for eg. melting of some
interconnections or power-line glitches.

2. Average power: Average power consumed by a device is the mean of the

amount of power a device consumes over a period of time. High values of
average power lead to problems in packaging and cooling of VLSI chips.

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Dynamic power : Dynamic power is the power consumed when the device is
active, that is, when the signals of the device are changing values. It is
generally categorized into three types (as shown above): switching power,
short-circuit power, and glitching power.

1) Switching power Dissipation - The first component of dynamic power

consumption is the switching power , that is the power required to charge
and discharge the output capacitance on a gate.

Energy per transition is expressed as

where CL is the load capacitance and Vdd is the supply voltage. Switching
power is therefore expressed as:

where f is the frequency of transitions, P(trans) is the probability of an output

transition ,and fclock is the frequency of the system clock.

Switching power is :
1) It is proportional to switching frequency and square of voltage,
independent of device parameters.
2) Because of square dependence voltage scaling is the most dominant
approach to reduce switching power.

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Apart from charging/discharging output load capacitance, switching power
dissipation occurs for charging and discharging internal node capacitances (that
might occur in some complex circuits). Secondly at different internal nodes the
swing might not be from GND to VDD.

So, in that case power consumption would be

Where (Vdd-Vt) is the reduced voltage swing. There wont be transition at any
node always when there is a transition at the input .So, here comes the role of
Switching Activity.

Switching Activity : It is defined as probability of transition and it depends

strongly on the function it realizes.

Let n( N) be the number of 0-to-Vdd output transitions in the time interval [0,N].
Total energy E[N] drawn from the power supply for this interval is given by

The average power dissipation during interval is

Where f is the clock frequency

Where gives us the expected (average) value of the

number of transitions per clock cycle, which is essentially the switching
activity.

Where alpha is the switching activity.

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In total dynamic power consumption is

where alpha0 is the switching activity at the output node, alphai is the switching
activity on the ith internal node, and f is the clock frequency and k is the
number of internal nodes.

CALCULATING SWITCHING FACTOR

Let P0 = probability of occurrence of 0

P1 = probability of occurrence of 1
Then probability of transition is P(0->1) = P0 * P1

As the sum of probabilities is one. P(0->1) is essentially the switching factor.

For example consider two input nand gate which has the following truth table

P0 = , P1 =
Switching factor(alpha) = P0 *P1 = 3/16

For an n-input gate, the total number of input combinations is 2^n. Out of 2^n
combinations in the truth table, let n0 be the total number of combinations for
which the output is 0 and n1 is the total number of combinations for which the
output is 1,

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Glitching Power Dissipation:

Actually in practice gates dont have zero delay. In practice, the gates will
have finite delay and this delay will lead to undesirable transitions at the
output. These undesirable signals are known as glitches .In the case of a
static CMOS circuit, the output node or internal nodes can make undesirable
transitions before attaining a stable value. It usually occurs in cascaded
circuits. It can be reduced by using balanced realization , but in worst cases
balancing is not possible if we try to use buffers to equalize delays.

Leakage Power Dissipation

While not in active mode of operation , the circuits consume a considerable

amount of static power especially in the sub-micron range. This is due to the
inherent construction of device , the way they are operated and realized there
are parasitic diodes present. It is basically due to the short channel effects
which get more pronounced in aggressively scaled devices. For understanding
these leakage mechanisms it is necessary to understand short channel effects.

p-n junction reverse biased current :

Sourcedrain diffusions and n-well diffusions form parasitic diodes in the bulk
of silicon substrate. As parasitic diodes are reverse-biased, their leakage
currents contribute to static power dissipation. The current for one diode is
given by

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Even for small reverse biased voltage this current tends to be Is and It increases
significantly with temperature.

Subthreshold Leakage Current

This current is primarily due to diffusion between source and drain region in the
weak inversion region (that is when Vgs<Vth). The subthreshold current
exhibits exponential relation with the gate voltage.There are various factors that
influence subthreshold current
1) Drain Induced Barrier Lowering (DIBL)
1) Body Effect
2) Narrow width effect
3) Effect Of Temperature

DRAIN INDUCED BARRIER LOWERING (DIBL)- In case of long channel

mosfet gate has total control over the channel but in case of short channel
devices this is not the case. For a conducting channel first the channel region
needs to get depleted but now in case of short-channel devices the depletion
region of the source and the drain intrude into the channel . So, effectively the
gate needs to support less charge required for inversion. As, a result less
potential is required for inversion and the gate loses its total control over the
channel . This phenomenon is called lowering of barrier potential.Now there

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arises a possibility that there might be conduction before gate voltage reaches
threshold voltage.

BODY EFFECT -If the substrate is negatively biased with respect to the source
the bulk depletion region gets widened as a result the threshold voltage
increases. This essetially happens because the depletion width increases and to
bring electrons to the surface it requires more amount of positive voltage.

Vth Roll-Off - The smaller the length greater is this roll off . Before inversion
the channel needs to be depleted but as the source and drain diffusion layers
protrude this task becomes easier and V (threshold) drops.

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Punch-Through -If the depletion regions of source and drain touch together ,
this condition is called as punch -through , it might lead to sudden increase in
current and permanent device failure. It occurs at high drain bias and is really
undesirable condition. The gate voltage loses the control on the current flow.
Hot-Carrier Effect- Aggressive device scaling and increased doping the electric
field can energize the electrons which might hit the thin oxide layer and knock
off and atom and become impurity, causing changes in threshold voltage.
So, we can see that all short channel effects cause variation in threshold voltage
and this variation in threshold voltage leads to change in leakage current. Hence
it was necessary to study the short channel effects.

LEAKAGE POWER MINIMIZATION TECHNIQUES

Our intention of using short channel mosfets is to make our circuits compact
and faster .Aggressive scaling has resulted in movement from millimetre era to
nanometre era. Performance has improved mainly because of reduction of gate
capacitance. Subsequently supply voltage must also scale at the same pace to
maintain constant field. This in turn demands threshold voltage to be scaled .
The reduction in threshold voltage leads to an exponential increase in sub-
threshold leakage current .As a result leakage power dissipation has become
comparable to total active power and this is a big concern. For example in case
of 90nm technology leakage power is 42% of total power and in case of 65nm
technology leakage power is 52% of total power.
Leakage Power Reduction techniques can be classified in to two broad types-
1) Standby leakage techniques - When a circuit is not in operation
2) Runtime leakage techniques When a circuit is in actual operation
Another classification possible is based upon when the technique is applied-
1) At the time of fabrication (static approach)
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 2) At runtime (dynamic approach)
FABRICATION OF MULTIPLE THRESHOLD VOLTAGES
Present day technology allows us to fabricate mosfets of different threshold
voltages on a single chip. In this the lower threshold voltage mosfet is for
improving speed and performance and the higher threshold voltage mosfet is for
reducing the leakage current.
There are various techniques to achieve this-
1) Multiple channel doping
2) Multiple oxide CMOS
3) Multiple body bias
Multiple channel doping The idea is to use different channel doping for the
two transistors. It is quite a tough job and that that makes this process costlier
than conventional fabrication in which all the transistors have the same
threshold voltage. We need to ensure doping is done properly as the mosfets are
very close to each other.
Multiple oxide cmos Another way of doing this is depositing oxide thickness
of two different thickness on the mosfets. Lower gate capacitance due to
increased gate oxide thickness increases threshold voltage. It also reduces gate
oxide tunnelling which occurs because of reduced gate oxide thickness.
Manufacturing of thicker gate oxide is easier , in thin gate oxides probability of
pin holes is also higher.
Multiple body bias - Applying body-bias, leads to increase in threshold voltage
as it widens the bulk depletion region. If we use this for transistors having
different threshold voltages and different gate oxide , we would use different
bias for each mosfet so they cant share the same well. So, for this process is
very costly to perform on.

TRANSISTOR STACKING
An inherent technique that is present in cmos circuits because of the way it is
realized. In this case the leakage current has a strong dependence on the number
of turned off transistors .

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The small voltages are due to small amount of leakage current flowing. Due to
negative Vgs the sub-threshold current decreases. Also because of body effect ,
Vth increases and sub-threshold current decreases.

APPLYING MTCMOS(MULTIPLE THRESHOLD VOLTAGE

TECHNIQUE)
Firstly we should know the critical path of the circuit. This is the most
important part of this approach. The critical path can be realised by using low
Vth mosfets as they switch faster and these would help in minimizing clock
periods. On the non-critical path high Vth mosfets can be used inorder to reduce
leakage currents. Typical high Vth devices reduce leakage current about ten
times as compared to low Vth devices.

Some variants of MTCMOS Technique

1) Dual Vth approach
2) VTCMOS (Variable Threshold CMOS) approach
3) Using Sleep transistors

Dual Vth approach In this technique we discretely partition the critical path
from the remaining paths and restrict usage of high Vth transistors on that path.

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This technique cant be implemented effectively when there are large number of
stages in the circuit. Also it might not always be possible to discretely partition
the circuit. Another disadvantage associated with it is that no effective cad tool
is present for realization.

VTCMOS (Variable threshold CMOS) - In VTCMOS approach instead of

employing multiple threshold voltage approach , circuit inherently uses low Vth
transistors and the substrate bias voltages of nmos and pmos are generated by
variable substrate bias control circuit. For example consider this inverter circuit
which has been employed with VTCMOS technique -

When the inverter is working in the active mode, it works as conventional

CMOS inverter circuit and does not experience any body effect. (High
switching speed because of low Vth) . But in the standby mode, substrate bias
control circuit generates bias voltages for pmos and nmos network .Thus
because of body bias the leakage power dissipation in the standby mode can be
significantly reduced. Unfortunately it has been proved that effectiveness of
this technique reduces as channel lengths become smaller or Vth values are

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lowered. Also VTCMOS is intrinsically more problematic for reliability since
high voltage across the oxide decreases as the lifetime of the device.
SLEEP TRANSISTORS - This method employs low Vth transistors to design
the logic gate for which switching speed is essential and employing high Vth
transistors(sleeping transistor) to isolate the logic gates in standby mode to
reduce leakage consumption. Sleep transistors in standby mode isolate the
actual logic from power supply.

But as a result of these sleep transistors the performance of the circuit in active
mode degrades as it reduces the available voltage swing. On the other side sleep
transistor is critical to the performance in terms of leakage power consumption
and noise immunity of MTCMOS circuits. Theoretically it has been proven that
for a pure combinational circuit we can use only nmos sleep transistor alone.

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Sleep transistors are controlled by a sleep signal is used for active/standby
mode. During active mode (sleep=0), the sleep transistor can be approximated
as a linear resistor as a result there is a finite voltage drop .In active mode this
causes the threshold voltage to increase due to body effect .Therefore resistance
should be smaller. Consequently the size of the transistor should be large.
However there is now trade off as the leakage current in sleep mode depends
upon the width of sleep transistor. As, a result optimal sizing of the sleep
transistor is tough to match a specific performance characteristic .A number
design methods of this sleep transistor have been proposed. The use of a single
sleep transistor has been proposed but this comes with its own disadvantage that
interconnect resistance for distant block increases so to compensate for that we
need to make size of transistor large. Making size large again increases the
leakage power !!!

REDUCING DYNAMIC POWER CONSUMPTION

All the methods proposed earlier were able to reduce static power dissipation
that is when the device is idle. This was also a good attempt as in the modern
era static power matches dynamic power. But still there is a need for using some
better approaches that are able to optimize power even in the active mode. One
such method is clock gating.

CLOCK GATING
It is a popular technique that is used in synchronous circuits for reducing
dynamic power consumption. This method involves pruning of clock tree.
Pruning the clock disables the portions of the circuitry so that the flip-flops in
them are unable to switch states. This ideally makes switching power
consumption tend to zero. Only concern then remains is the leakage current.
This method works by using the enable condition attached to registers and uses
them to gate the clocks. The best part is that combinational clock-gating is the
part of RTL compilers. It also reduces the excess area consumed by mux.

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 CLOCK SKEW
It is defined as the difference in arrival times of clock signals at any two flip-flops
that are interacting with each other. It makes sense only when the two flip-flops
are interacting with each other. Clock skew can be due to various reasons like
wire interconnect length, temperature, intermediate devices, capacitive coupling,
variations in input capacitances on the clock input devices using the clock.
Majority is all because of RC time constant delay.
Violations caused because of Clock skew:
1) Hold time violation
2) Setup time violation

Hold time violation It occurs when clock travels slower than the path from one
register to the another. This allows data to penetrate two registers on the same
clock tick destroying the integrity of latched data. (POSITIVE SKEW)

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Setup time violation In this case destination flip-flop receives clock edge before
the source flip-flop.(NEGATIVE SKEW)

In practice the sequential synchronous circuits need buffers in path of clock

to ensure slew rate.

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Maintaining this clock skew is actually quite costly affair .Power consumption
in the clock paths alone contribute to 50% of the total dynamic power consumed
within modern Socs (System on Chip). Soc is an integrated circuit that
integrates all components of a computer or electronic systems and may have
many functionalities.
Modern devices have some low-power modes in which only a small part of the
Soc is working and else are not functional . There might be some configuration
registers which need to be programmed seldom or very once .Assume that this
flip-flop is not switching for a considerable amount of time.

The flip-flop is not switching states but the clock tree buffers are switching
states and hence consuming power. Placing an and gate would ensure that the
clock tree buffers are not switching states. Hence we have eliminated dynamic
power dissipation.

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A disadvantage associated with this approach is that there might be output
glitches at the output of the and gate.

To ensure that there are no glitches what we can do is that enable signal is only
generated when the clock is low.

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References : -

1) Ajit Pal , Low power VLSI Circuits and Systems , Springer

2) International Journal of Computer and Electrical Engineering, Recent
Trends in Low Power VLSI Design (volume 6 , number 6 , December
2014)
3) Fundamentals of Microelectronics , Behzad Razavi
4) Solid state microelectronic and optoelectronic devices , Sarkar and Sarkar
5) http://www.eeherald.com/section/design-guide/Low-Power-VLSI-
Design.html
6) http://nptel.ac.in/courses/106105034/

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