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use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity main_encoder is
port
(
clk : in std_logic;
rst_n: in std_logic;
ain : in std_logic_vector(7 downto 0);
aout : out std_logic_vector(9 downto 0);
rd : out std_logic
);
end main_encoder;
begin
constant LUT_RDMINUS: mem_2d_type :=
(
begin
aout <= LUT_RDMINUS(to_integer(unsigned(ain)))(9 downto 0);
begin
aout <= LUT_RDPLUS(to_integer(unsigned(ain)))(9 downto 0);
port map
(
ain => ain,
rd => rd_reg,
aout => aout_next
);
begin
a9 <= to_unsigned(1, 3) when ain(9) = '1' else
to_unsigned(0, 3);
a8 <= to_unsigned(1, 3) when ain(8) = '1' else
to_unsigned(0, 3);
a7 <= to_unsigned(1, 3) when ain(7) = '1' else
to_unsigned(0, 3);
a6 <= to_unsigned(1, 3) when ain(6) = '1' else
to_unsigned(0, 3);
a5 <= to_unsigned(1, 3) when ain(5) = '1' else
to_unsigned(0, 3);
a4 <= to_unsigned(1, 3) when ain(4) = '1' else
to_unsigned(0, 3);
a3 <= to_unsigned(1, 3) when ain(3) = '1' else
to_unsigned(0, 3);
a2 <= to_unsigned(1, 3) when ain(2) = '1' else
to_unsigned(0, 3);
a1 <= to_unsigned(1, 3) when ain(1) = '1' else
to_unsigned(0, 3);
a0 <= to_unsigned(1, 3) when ain(0) = '1' else
to_unsigned(0, 3);
process(clk, rst_n)
begin
if (rst_n = '0') then
rd_reg <= '0';
aout_reg <= (others => '0');
elsif (clk'event and clk = '1') then
rd_reg <= rd_next;
aout_reg <= aout_next;
end if;
end process;