Faculty of Electrical Engineering, UTM

SKEE 1223 Digital Electronics / Session 2015/2016-2

Date: 23th May 2016 Time: 8.30 9.30pm
TEST 3

Marks
Name:

Matric No.: Section:

Lecturers Name: / 30
*The use of calculator is not allowed.

Question 1 (10 marks)

a) Answer the statements below with either TRUE or FALSE.

LE
i Latch has clock as one of the input pin. F
ii Counter can be used as frequency divider. T
iii To count 0 till 6, two unit of flip flops are required. F
iv It is easier to design an asynchronous counter than synchronous counter. T
SA (4 marks)

b) What improvement does a JK latch have over an SR latch?

R
(2 marks)
FO

When J and K are both high (JK=11), the output toggles (in SR latch is forbidden).

c) With the given input waveforms, sketch the output waveform Q of the JK flip flop in
Figure Q1. (4 marks)
T
O
N

Deduct 1 mark for each mistake on Q (each clock cycle). Max 4 mark if no mistake.
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 Faculty of Electrical Engineering, UTM
SKEE 1223 Digital Electronics / Session 2015/2016-2
Date: 23th May 2016 Time: 8.30 9.30pm
TEST 3

Question 2 (10 marks)

a) Figure 2a shows a counter circuit using T flip flops.

Figure Q2a
i. Sketch the output waveform for 8 clock cycles. The initial state is Q2Q1Q0 = 000.
(3 marks)

LE
SA
R
FO

1 mark for each correct waveform of Q2, Q1 and Q0. Total 3 marks.

ii. If Q2 and Q0 are the most and least significant bits. Determine the sequence of the
T

counter in decimal.
(1 marks)
O

0 1 2 3 4 5 6 7 0
1 mark for correct sequence.
N

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 Faculty of Electrical Engineering, UTM
SKEE 1223 Digital Electronics / Session 2015/2016-2
Date: 23th May 2016 Time: 8.30 9.30pm
TEST 3

b) Sketch the output waveform F for 8 clock cycles. The initial state is Q2Q1Q0 = 000.
(6 marks)

LE
SA
R
FO

1 mark for each correct waveform of Q2, Q1 and Q0. Total 3 marks.
T

1 mark for correct waveform of F: 1st and 2nd clocks.

1 mark for correct waveform of F: 3rd and 4th clocks.
O

1 mark for correct waveform for F: 5th and above clocks as repeating waveform.
N

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 Faculty of Electrical Engineering, UTM
SKEE 1223 Digital Electronics / Session 2015/2016-2
Date: 23th May 2016 Time: 8.30 9.30pm
TEST 3

Question 3 (10 marks)

a) From the given truth table in Table Q3, design a comparator circuit. Clearly show all
the steps in your design.
(6 marks)

LE
1 mark for each correct K-map with logic equation.
SA
R
FO
T

1 mark for each correct K-map with logic equation.

O
N

1 mark for each correct K-map with logic equation.

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 Faculty of Electrical Engineering, UTM
SKEE 1223 Digital Electronics / Session 2015/2016-2
Date: 23th May 2016 Time: 8.30 9.30pm
TEST 3

1 mark for each correct circuit implementation. Total 3 marks.

LE
b) Figure Q3 shows two unit of half adders and two unit of NOR gates. From the given
circuit, design a full adder.
SA (3 marks)
R
FO
T
O

1 mark for correct wiring of A, B and Cin.

1 mark for correct wiring of Sum and Cout.
N

1 mark for correct wiring of both NOR gates.

c) Briefly explain the limitation of half adder as compared to full adder.

(1 mark)

Full adder can be easily extended to ripple carry adder for adding multiple bit binary
numbers.

OR

Half adder is limited to adding two single bit numbers and cannot be directly used for
ripple carry adder.

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