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VIN VIN
CIN VOUT1 VOUT1
1uF COUT1
RT9011 1uF
EN1
Chip Enable
VOUT2 VOUT2
COUT2
EN2
1uF
GND
EN1 Shutdown
0.2uA VIN
and
Logic Control
VREF
-
MOS Driver
+
Error
Amplifier VOUT1
Current-Limit
and
Thermal
Protection
GND
EN2 Shutdown
0.2uA
and
Logic Control
VREF
-
MOS Driver
+
Error
Amplifier VOUT2
Current-Limit
and
Thermal
Protection
GND
Electrical Characteristics
(VIN = VOUT + 1V, VEN = VIN, CIN = COUT = 1F, TA = 40C to 85C, unless otherwise specified.)
Parameter Symbol Test Conditions Min Typ Max Unit
Input Voltage VIN = 2.5V to 5.5V 2.5 -- 5.5 V
Dropout Voltage (Note 5) VDROP IOUT = 300mA -- 240 330 mV
Output voltage range VOUT 1.2 -- 3.6 V
V OUT Accuracy V IOUT = 1mA to 300mA 3 -- +3 %
1.85 3.35
1.8 3.3
1.75 3.25
1.7 3.2
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (C) Temperature (C)
65
250
TJ = 25C
200
60
150
TJ = -40C
100
55
50
50 0
-50 -25 0 25 50 75 100 125 0 50 100 150 200 250 300
Temperature (C) Load Current (mA)
VIN 4.8
VEN (V)
(5V/Div) 3.8
VOUT2
VOUT1 (10mV/Div)
(1V/Div)
VOUT2 VOUT1
(2V/Div) (10mV/Div)
POR
(5V/Div)
VOUT1 VOUT1
(10mV/Div) (10mV/Div)
VIN 4.8
(V) IOUT
3.8 (50mA/Div)
VOUT2
(10mV/Div)
VOUT1
(20mV/Div)
VOUT1
(10mV/Div)
VOUT2
(20mV/Div)
IOUT V EN
(100mA/Div) (5V/Div)
V OUT2
VOUT1
(20mV/Div)
V OUT1
VOUT2
(20mV/Div) (1V/Div)
V EN
(5V/Div)
PSRR(dB)
-20
V OUT2 -40
V OUT1
-60
(1V/Div)
-80
Time (50s/Div) 10 100 1k
1000 10k
10000 100k
100000 1M
1000000
Frequency(Hz)
Noise Noise
RT9011-GS, No LOAD RT9011-GS, ILOAD = 50mA
VIN = VEN = 4.5V(By battery) VIN = VEN = 4.5V(By battery)
150 300
CIN = COUT1 = COUT2 = 1uF/X7R CIN = COUT1 = COUT2 = 1uF/X7R
100 200
Noise (V/Div)
Noise (V/Div)
50 100
0 0
-50 -100
-100 -200
-150 -300
VEN2 VEN1
VEN1 VEN1
(2V/Div) VEN1 (2V/Div)
VEN2 VEN2 VEN2
(2V/Div) V OUT2 (2V/Div)
V OUT1
V OUT1
(1V/Div) (1V/Div)
V OUT2
1
PD = (VIN-VOUT) x IOUT + VIN x IQ
RegionofofStable
Stable Range
0.1 The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
Region
1
Single Layer PCB
0.9
WDFN-8L 3x3
0.8
Power Dissipation (W)
WDFN-10L 3x3
0.7
WDFN-8L 2x2
0.6
0.5
0.4 TSOT-23-6
0.3
0.2 WDFN-6L 1.6x1.6
0.1
0
0 25 50 75 100 125
Ambient Temperature (C)
H
D
L
C B
A
A1
e
D2
D
E E2
SEE DETAIL A
1
2 1 2 1
e
b
A DETAIL A
A3
A1 Pin #1 ID and Tie Bar Mark Options
D2
D
E E2
SEE DETAIL A
1
2 1 2 1
e
b
A DETAIL A
A3
A1 Pin #1 ID and Tie Bar Mark Options
D2
D
E E2
SEE DETAIL A
1 2 1 2 1
e
b
DETAIL A
A
Pin #1 ID and Tie Bar Mark Options
A3
A1
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
D D2
E E2
SEE DETAIL A
1
2 1 2 1
e
b
A DETAIL A
A3 Pin #1 ID and Tie Bar Mark Options
A1
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.