3

The macros be placed such that the distance between the macros and the pins is minimum

Some space for the power grid should be reserved during the Macro placement this should be
considered to avoid congestion

The fixed cells should be taken into consideration while macro placement

The macros should be placed around the chip Periphery this is done to avoid any congestion. It also
helps in reducing the IR drop and a proper power distribution

The fly lines give the information about the connectivity between the blocks within the design. With this
the distance between the blocks can be minimised. It can also help to estimate the proper orientation of
the blocks.

Nldm

Nldm is the timing model. It gives the information about the input to output delay. It also gives
information about the output transition with respect to input transition time and output load.

The clock for which the reference port is not defined are known as the virtual clock. It can be said that if
the origin of the clock signal is not defined for a clock then that clock is called as virtual clock.

The virtual clock is defined to test the design.

Create_clock-20-waveform{0,10}

The difference between hollow and blockages are as follows

1. The hollow is the area around the macros so it can be said that the hollow is related to
macros.Where as the blockages are the area where the standard cells cannot be placed so they
are not specifically related to macros.
2. If the Macro is moved from its position the respective hello also moves with it. This is not the
case with the blockages, if the blockages are defined for a reason they does not move when the
macros are moved.

9
The setup and hold time can be defined with reference to the active clock edge

The duration for which the data should be stable before the active clock edge is known as the setup
time.

The duration for which the data should be stable after the active clock edge is known as hold time

10

The timing exceptions in the physical design are

1.false path

2. Muticycle path

3. Max min path

4. Disable timing arc

The timing exceptions are the part of the physical design which are not considered in Timing Analysis
because if we consider the timing exceptions in the Timing Analysis it can lead to wrong analysis or
timing violation. So the timing exceptions are added as a constraint to the physical design.

12

In a normal physical design process the width between the nets is generally of 1 unit and width is also of
of 1 unit. In critical conditions when the spacing between the net is one unit it can lead to cross talk
noise violation and timing violation. Also if the weight of the net is of 1 unit it can lead to improper
distribution of power. To deal with this problems non default rules are used it makes the spacing
between the net more than one unit and the width of the net more than one unit to avoid cross talk
timing violation and such problems. And therefore the non default rules are applied before placement.

13.

Before CTS the clocks are ideal that means that the clock sleeve rates and other parameters are
approximated at this point . After the CTS the accurate input and output rise time and fall time can be
known. Generally the hold violation is harder to fix when compared to the setup violation as the setup
violation can be fixed by just reducing the clock frequency so it can be said that the hold violation are
more critical for the design and it has to be solved therefore we solve hold violation in CTS

14

Antenna effect is the thing which occurs during fabrication. During fabrication due to ionization and
processes the charge may get deposited on the gate and other parts of the chip which may lead to
damage of the chip.
To avoid antenna effect how to reduce the intern effect the following methods can be adopted

1. Use of jumper insertion.

2. Dummy transistors
3. Placing reversed Biased diode

15.

1. Electromigration in some tracks there is accommodation of access charges resulting to Haier

heating effect in that area because of this overheating the tracks are open this phenomenon is
known as electromigration. Electromigration can be avoided bye increasing the width of the
wire buffer insertion and using higher metal layers
2. Congestion- in some areas the the density of the routing tracks is more this results in non
availability of the space for placement of cell. So the scarcity of the space for the placement of
the cell is known as congestion the condition is generally resulted from improper routing and
placement of macros and standard cells the congestion can be reduced by using the blockage
areas and modify the floor planning and placement.
3. Cross talk- if the data send at one track interfaces with the data in another track it is known as
cross talk in physical design process if a one signal interfaces or influences another signal this is
known as cross talk across stock is an undesirable thing which should be avoided because 8 may
result in glitches and noise cross talk can be avoided by increasing the width between the net.
4. CMOS latch up the letter is the high gotten flu between the power and the ground rail of an IC
. This high current flow leads to heating effect and damages the IC. The latch up can be avoided
by using the latch up protection Technology circuit and surrounding the p and and n mos with
insulating oxide layer called Trench.