Assign 09-28 ECE 320 Fall 2017 Due 10-12 (1:00 pm)

Lab 5 BCD counter on 7-Seg display and Frequency Dividers

INTRODUCTION
The purpose of this lab is for introducing you to Xilinx IP cores, which are targeted to different
applications from Digital Signal Processing (DSP), communication and networking, embedded
processors, audio and video processors, math co-processors, to memory interfaces and storage.
These cores address your general needs while designing specific embedded system targeting
specific field. These cores are easy to configure and implement on FPGA using the wizard and
IP catalog.

PRE/IN-LAB:

1) Inspect the pushbutton circuitry (for BTNU pushbutton) and draw two different circuits;
one indicates when the pushbutton is not pressed, and the other circuit should indicate
when it is pressed. For both circuits, find out the voltage at BTNU pin. (Use attached
schematic diagram of Nexys 4 (Nexys 4_sch.pdf) to draw the circuits). This step should
guide you to use the reset in your code

2) For each section (1-1, 1-2, and 2-1) draw (only) block diagrams for the top level module,
any instantiated module/IP core, and any always construct you will implement. Show
input/output ports for each block diagram.

Hint: If you think you can do section 2-1 by modifying section 1-1, then you can skip
section 1-2 which is an intermediate step to section 2-1.

PROCEDURE:

PART I:
Follow the same steps you went through in making a project. Read carefully Architectural
Wizard and IP Catalog.pdf file and follow the instructions throughout the lab steps. First, do
part 1-section 1 (you need it for part 2-section 1), and make sure it is working according to the
given specs. For part 1, section 1-2 you need to modify Lab2 which displayed the 4-bit binary
inputs as BCD value on 7-segment display. Therefore, section 1-2 would allow you to display
decimal numbers on two 7-segment displays (e.g.; 00, 11, 22, 33, 44, 55, 66, 77, 99) once at a
time. Then Part 2-section 2-1, would allow you to display the sequence 00, 11, 22, 33, ,99,
one count value per second.

PART II 2-digit BCD counter:

Modify part 2, section 2-1 so that the 7-segement display would show the count sequence
(count per second) : 00, 01, 02,., 09, 10, 11, 12,.,99, 00 and it repeats.

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Assign 09-28 ECE 320 Fall 2017 Due 10-12 (1:00 pm)
Lab 5 BCD counter on 7-Seg display and Frequency Dividers

Simulation is not necessary in this lab unless you need to troubleshoot your design for erroneous
behavioral code.

Implementation:
Take care when you modify Nexys4_Master.xdc file, probably it is better to consider the
modified xdc file that you used in Lab 2. When you do the pin assignment (in xdc file) make sure
to set the port name and pin number, and port name and IO standard.

Check off

PART I
Section 1-1:__________________Date____________________

Section 1-2:__________________Date____________________

Section 2-1:__________________Date____________________

PART II: ____________________Date____________________

Approved: Lab TA _______________________________ Date ________________

Things to turn in as your Lab1 Report:

A. This assignment sheet, with your name at the top, signed by the TA where shown.

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