Code: 9A04504 1

B.Tech III Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14
DIGITAL IC APPLICATIONS
(Electronics & Communication Engineering)
Time: 3 hours Max. Marks: 70

Answer any FIVE questions

All questions carry equal marks
*****

1 (a) Explain how to estimate sinking current for low output and sourcing current for high
output of CMOS gate.
(b) Explain the behavioral difference between simple transistor logic inverter and schottkey
logic inverter.

2 (a) Design a transistor circuit of 2-input ECL NOR gate. Explain the operation with the help
of function table.
(b) Draw the circuit diagram of basic TTL NAND gate and explain the three parts with the
help of functional operation.

3 (a) Explain the behavioral design model of VHDL.

(b) Write a process based VHDL program for the prime-number detector of 4-bit input and
explain the flow using logic circuit.

4 Design a 10 to 4 encoder with inputs 1- out of 10 code and outputs in BCD? Provide the
data flow style VHDL program.

5 Draw the logic symbol of 74 x 85, 4-bit comparator and write a VHDL code for it.

6 Write a VHDL code for fixed point to floating point conversion.

7 Explain the timing specifications of PLD with an appropriate diagram. Give the VHDL
code for PLD.

8 Design a 4X4 unsigned multiplier using 256X8 ROM.

*****
Code: 9A04504 2
B.Tech III Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14
DIGITAL IC APPLICATIONS
(Electronics & Communication Engineering)
Time: 3 hours Max. Marks: 70

Answer any FIVE questions

All questions carry equal marks
*****

1 (a) Explain how a CMOS device is destroyed.

(b) Design a 4-input CMOS OR-AND-INVERT gate. Explain the circuit with the help of logic
diagram and function table.

2 (a) Design a TTL three-state NAND gate and explain the operation with the help of function
table.
(b) Design a transistor circuit of 2-input ECL NOR gate. Explain the operation with the help
of function table.

3 (a) Write a VHDL Entity and architecture for a 3-bit Synchronous counter using flip-flops.
(b) Explain the use of packages. Give the syntax and structure of a package in VHDL.

4 (a) Using two 74138 decoders design a 4 to 16 decoder.

(b) Design a 16-bit comparator using 7485s.

5 Design a 16-bit ALU using a 74x381and 75x182.

6 Explain the details about simple floating point encoder with a suitable diagram and write
a VHDL code for it.

7 Explain the operation of a 4 bit synchronous binary counter with the required diagram
and wave forms.

8 Design a 8X8 diode ROM using 74X138 for the following data starting from the location
11, 22, 33, FF, DD, CC, 01, 7E.

*****
Code: 9A04504 3
B.Tech III Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14
DIGITAL IC APPLICATIONS
(Electronics & Communication Engineering)
Time: 3 hours Max. Marks: 70

Answer any FIVE questions

All questions carry equal marks
*****

1 (a) Design a three input NAND gate using diode logic and a transistor inverter. Analyze the
circuit with the help of transfer characteristics.
(b) Explain how a CMOS device is destroyed.

2 (a) Draw the circuit diagram of basic CMS gate and explain the operation.
(b) Mention the DC noise margin levels of ECL 10K family.

3 (a) Design the logic circuit and write a data-flow style VHDL program for the following
function.
F (P) = A,B,C,D (1, 7, 9, 13, 15)
(b) Explain the difference in program structure of VHDL and any other procedural language.
Give an example.

4 (a) Write a VHDL program for 74245.

(b) Design a 16-bit comparator using 7485 Ics.

5 Write a behavioral VHDL code for a74X280 (9 input parity checker).

6 What is a comparator? Explain the operation of a 2-bit comparator with a relevant

diagram. Draw its logic symbol and write a VHDL code for it.

7 Draw the logic diagram for the 74X 163 synchronous 4 bit binary counters and explain its
operation in free running mode with suitable wave forms.

8 Determine the ROM size needed to realize the combinational logic function performed by
each of the following MSI parts 74X49, 74X139, 74X153, 74X257, 74X381, 74X682.

*****
Code: 9A04504 4
B.Tech III Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14
DIGITAL IC APPLICATIONS
(Electronics & Communication Engineering)
Time: 3 hours Max. Marks: 70

Answer any FIVE questions

All questions carry equal marks
*****

1 (a) Explain the effect of floating inputs on CMOS gate. Explain how a CMOS device is
destroyed.
(b) Design a 4-input CMOS OR-AND-INVERT gate. Explain the circuit with the help of logic
diagram and function table.

2 (a) Explain the difference in program structure of VHDL and any other procedural language.
Give an example.
(b) Draw the circuit diagram of basic CMS gate and explain the operation.

3 (a) Design a logic circuit to detect prime number of a 4-bit input. Write the VHDL program for
the above design.
(b) Explain with example the syntax and the function of the following VHDL statements.
(i) If, else and else if statements.
(ii) Case statement.

4 (a) With the help of logic diagram explain 74157 multiplexer.

(b) Write the data flow style VHDL program for this IC.

5 Draw the logic diagram, logic symbol of 74 x 245 octal 3-state trans-receivers and
explain its operation.

6 Write a VHDL code for 8 bit comparator circuit. Using this entity write a VHDL code for
24 bit comparator. Use the structural model for it.

7 Find the feedback equation for a 4 bit linear feedback shift register that produces
maximum length sequence. Draw the logic diagram of LFSR and explain its operation
with the starting state four.

8 (a) Explain the detail view of internal structure of ROM with a good example.
(b) Realize the logic function performed by74X138 with ROM.

*****