Full-selective protection strategy for MTDC grids based on R-type
superconducting FCLs and mechanical DC circuit breakers
W R Leon Garcia*, A Bertinato*, P Tixador *, B Raison *, B Luscan*
*
SuperGrid Institute, France, william.leongarcia@supergrid-institute.com
Grenoble Laboratory of Electrical Engineering (G2Elab), France.
Keywords: HVDC, SFCL, Protection, DCCB, EMTP-RV.
Abstract
A novel protection strategy for multi-terminal high voltage
direct current (HVDC) grids based on the implementation of
breaking modules (BM) with both limiting and breaking
capabilities will be presented. It incorporates a resistive-type
superconducting fault current limiter (SFCL) in series with a
mechanical DC circuit breaker (DCCB). The proposed
arrangement of BMs allows an intrinsic selective fault
identification criteria based on the quenching of the SFCL.
The fault current limitation reduces the breaking capability,
speed and energy requirements for the DCCB. Furthermore, a
continuous grid operation can be assured by adding DC
inductors and capacitors, assuring a constant power flow
during and after the fault event. In this paper, a primary
protection scheme is conceptually described and off-line
simulation studies performed in EMTP-RV are discussed.
1 Introduction
The implementation of multi-terminal HVDC (MTDC) grids
is seen as the main solution for the increasing electricity
demand and integration of large-scale renewable energies
[1] [2]. However, DC technologies are not mature enough to
allow a faster development of MTDC grids [3] [4]. A core
problem concerns the system protection. Different protection
strategies are being developed based on the performances of a
DCCB with high speed current breaking capabilities [5] [6].
However, these approaches have not been achieved due to
high investment costs and unfeasible technical specifications.
Protection strategies for MTDC grids are starting to be
classified according to the inner requirements and constraints
of DC systems [7]. Open grid protection strategies [8] are
interesting in terms of feasibility, however, they may impact
the grid stability. Selective strategies involve line dedicated
protection [9] [10] [11] and may allow large MTDC grids to
operate with minor disturbances during the fault events.
Nevertheless, complex protection algorithms are required to
rapidly identify the faulted line, which are not yet validated in
a real-time basis. In addition, they rely on fast and costly
DCCB technology including large limiting reactors [12].
A full selective protection strategy is presented here and can
be integrated to the existing classification. It uses the
resistive-type SFCL to tackle the main constraints of DC
1
protection like the fault clearing time and fault current
amplitude. Furthermore, it allows the implementation of a
straightforward fault identification method. SFCLs are
becoming a mature and reliable technology in AC grids
[13] [14] where they are mainly used to reduce the increasing
short circuit power of the system, produced by, e.g.,
distributed generators. SFCL operating losses, function of the
current frequency, are an issue in AC but not in DC [15]
where the current ripple is very low. Some studies introduce
the SFCL for 2-level voltage-sourced converter (VSC) based
HVDC point-to-point systems [16] or MTDC grids [17].
However, the use of SFCLs into the protection strategy
remains confusing and a different insight is required for
modular multi-level converter (MMC) based HVDC grids.
This paper present the results obtained from ongoing studies
regarding the implementation of SFCLs for MMC-based
MTDC protection strategies. It introduces a primary
protection scheme that uses the electro-thermal properties of
the SFCL to identify the fault. First, a brief description of the
MTDC test grid used to validate the primary protection
scheme is given. This shows the location of the so-called
breaking module (BM) that integrates the SFCL in series with
a mechanical DCCB. Secondly, the operating principles of the
SFCL and the mechanical DCCB are explained along with
their main sizing parameters. Afterwards, an overview of the
protection strategy will be given, focusing on the main stages
of the primary protection scheme. Finally, the results obtained
from off-line simulation studies performed with the test grid
in EMTP-RV will be shown and analysed.
Table 1: Acronyms and definitions.
IGBT: Insulated-gate bipolar transistor
REBCO: Rare Earth Barium Copper Oxide
2G-HTS: 2nd generation high temperature superconductor.
SA: Surge arrester.
Protection A collection of protection devices (relays, fuses,
equipment: SFCL, etc.).
Protection An arrangement of protection equipment
system: required to achieve a specified function.
Protection The coordinated arrangements for the protection
scheme: of one or more elements of a power system. May
comprise several protection systems.
Protection A program or logic based on a protection
algorithm: principle and required to perform the protection
scheme. Usually performed by a protective relay.
2 MTDC Test Grid This fault location is the worst fault case scenario for
station MMC3: it will allow validating the performance of the
N1
i 13
BM: vSFCL vCB proposed protection system regarding the continuous
Breaking operation of an MMC station during the fault.
MMC 1 LDC1 i1 BM 13 Module
vMMC 1 v1 C 13 SFCL CB
BM 1 i 12 Following the same philosophy as in [22], passive elements
N3 are added at the DC side in order to guarantee a continuous
C DC1 i 31
BM 12
F LDC 3 MMC 3
grid operation through the fault: series DC reactors (LDC) are
BM 31 i3
C 12 located at the output of each MMC to limit the fault current
v3 vMMC 3
N2
i 32 BM 3 rate of rise and prevent them from blocking the IGBTs. The
i 21
BM 32 C DC3 maximum short circuit current for IGBTs is given in Table 2.
MMC2 LDC2 i2 BM 21 Moreover, capacitors are located at each DC busbar in order
C 23 to reduce the voltage drop seen by the MMC stations during
vMMC 2 v2
BM 2 i 23
the fault. In this way, a continuous control of power and
C DC2 BM 23 voltage is kept. Due to the topology of MMC converters [19],
the current will flow through the antiparallel diodes if the DC
Fig 1: Single pole diagram of the 3-terminal MTDC test grid. voltage is lower than 0.8 pu, thus, MMC control will not be
effective.
The studies carried out in this paper are based on the test grid
shown in Fig 1, which represents a single pole of a 3 Protection system
three-terminal MTDC meshed grid using underground cables
and half-bridge MMC converters in bipolar configuration. A protection system consisting of a breaking module (BM)
The AC grid is represented by an ideal voltage source with a placed at each DC busbar feeder branch is proposed, as seen
short circuit impedance. Table 2 shows the main values for in Fig 1. This BM encloses an SFCL in series with a CB. In
the grid parameters. The grid was simulated in EMTP-RV. this configuration, the electro-thermal properties of the SFCL
For better understanding of the results, grid voltages can be used to obtain an intrinsic fault identification method
and currents are measured following the convention given as it will be later explained. A CB is required to interrupt the
in Fig 1. A single pole to ground fault has been chosen as fault current, already limited by the SFCL.
fault scenario. A comprehensive fault analysis for MMC-
based MTDC grids can be found in [18]. The fault is located 3.1 Superconducting fault current limiter (SFCL)
at one end of cable C13 near the busbar N3. The operating principle of the resistive type SFCL is based on
the electro-thermal behaviour of REBCO-based 2G HTS
Table 2: Table of specifications for the MTDC test grid. tapes, shown in Fig 2. Below a critical temperature (T < Tc),
Symbol Description Value Units the maximum current that can flow through the SFCL without
VAC Rated voltage 400 kV losses (zero resistance) is called the critical current, Ic0. It
f Frequency 50 Hz decreases with the increasing temperature, being 0 at Tc
AC Side

k AC grid X/R ratio 10 / (Ic0(Tc) = 0). Thus, an operating temperature (T o) lower than
SSC Short-circuit power 30 GVA Tc must be maintained during normal operation of the SFCL
SAC Transformer rated power 500 MVA and the rated current IDC must be lower than Ic0(To). When the
XT Transformer reactance 0.18 pu current oversteps Ic0(To) the SFCL resistance increases
VDC Rated voltage 320 kV following a power law (1), where EO (electric field at Ic0(To))
IDC Rated current 1500 A and n are fitting parameters. Energy is dissipated through
MMC converter

SMMC Rated power (per pole) 500 MVA heating produced by power losses (2).
LARM Arm inductance 16 mH
Switching As the temperature increases, the SFCL resistance also
/ Model [19] / increases accelerating the heating. This ends up by producing
function arm
/ Number of sub-modules 400 / the thermal runaway of the SFCL, also known as quench.
Short-circuit current limit When T reaches Tc, RSFCL no longer follows a power law but
ISC-IGBT 4 kA it behaves as a regular temperature dependent resistance (1).
of a single IGBT [20]
l13 Length of cable 13 300 km A typical trajectory of the resistance value during the first
l12 Length of cable 12 150 km transient of a DC short-circuit is shown in blue in Fig 2.
DC grid side

l23 Length of cable 23 250 km

Following the analytical modelling for resistive-type SFCLs
LDCi LDC1, LDC2, LDC3 10 mH
presented in [23], the EMTP-RV electrical model shown in
CDCi CDC1, CDC2, CDC3 50 F
Fig 3 was implemented. It comprises an inductor (L SFCL) and
/ Cable model [21] Wideband / two parallel controlled resistances: RSC models the non-linear
Solid behaviour of equation (1) and RNSC the temperature dependent
/ Fault type /
pole-ground resistor after the quench (T > Tc).

2
 Table 3: Table of specifications for the SFCL tape.
Description Value Units
kDC Steady-state overcurrent factor 1.5
Inhomogeneity factor [23] 30 %
Ic0(To) Required critical current IDC.kDC / (1-) A
T0 Operating temperature 65 K
TC Critical temperature* 90 K
Tmax Maximum temperature 350 K
Ic0(T1) Ic0(T2) Ic0(T3) Tc Ic0-w Ic0 per width unit at T0 * 900 A/cm-w
l Length 2.25 km
Ic0(To) w Width of 2G HTS tape 25 mm
IDC To
th Thickness of 2G HTS tape ~ 421 m
Fig 2: Electro-thermal behaviour of 2G HTS tapes. LSFCL SFCL coil inductance 1 mH/km
*
Typical values for YBCO-based 2G HTS tapes [25].
VR SFCL(t)
iNSC(t) RSFCL
As mentioned before, the location of the SFCL offers an
VL SFCL(t)
RNSC(t-t) intrinsic selectivity to the protection scheme. Indeed, the
LSFCL iSFCL(t) iSC(t) current from each side of the faulted cable will be higher than
the upstream current contribution. This will produce the
RSC(t-t) quench of the SFCLs enclosing the faulted element,
Initial Conditions automatically isolating it from the healthy parts of the grid.
RSFCL(iSC(t0), T(t0)) = 0 | T(t0) < Tc | iSFCL(t0) < Ic0(T(t0)) This quenching can be easily detected through voltage
measurements. The protection scheme will be based on this
iSC(t) RSC(t-t) principle to rapidly identify the fault, as explained later.
ANALYTICAL
MODEL
iSFCL(t) RNSC(t-t) 3.2 Direct current circuit breaker (DCCB)
The DCCB must interrupt the fault current. Due to the current
Fig 3: SFCL model implementation in EMTP-RV. limitation introduced by the SFCL, the required breaking
capability is lowered within IDC Ic0(To) and the breaking
0 iSC < Ic0(T), T < Tc speed requirement is relaxed. Moreover the surge arrester
RSC(i,T)
energy withstand capability, proportional to the square of the
o
iSC
n
RSFCL(i,T) = T < Tc (1)
RNSC(T) -1 interrupted DC current, is reduced. Among the different CB
iSC Ic0T
technologies able to perform DC fault current
RNSC(T) T Tc
2 interruption [26], the electro-mechanical DCCB with forced
Ploss I RSFCL (2) injection current well suits the grid requirements. As depicted
in Fig 4 this type of breaker uses an LC branch with a pre-
An optimal sizing of the SFCL will ensure an electrical and charged capacitor (COsc) to create a current injection through
thermal stability of the device while meeting the requirements the main branch where the contacts are located. The main
imposed by the DC grid like operating voltage, rated current branch is represented by an ideal switch that can only open
(VDC and IDC from Table 2) and maximum permanent when the current crosses zero. In Table 3, chosen values for
overcurrent (1.5IDC from Table 3). In this work, the size of the DCCB implementation in EMTP-RV are shown.
the cryogenic system will not be discussed. Table 3 shows
the main sizing parameters of the SFCL tape following the Table 4: Table of specifications for the DCCB.
optimal design proposed in [24].
Description Value Units
The value of Ic0(To) will be chosen to be higher than IN VSA Surge arrester reference voltage 1.6 pu
considering a kDC given by the grid and obtained from the tbreak Opening time 15 ms
manufacturer of 2G HTS tapes (the impact of the ICB Breaking capability 4 kA
inhomogeneity factor is explained in [23]). Ic0(To) is adjusted
COsc LOsc
by the tape width (w) according to I c0-w. The tape length (l) +
determines the maximum limitation time and current while Sw
respecting T max to prevent the tape damage. The tape SA
thickness (th) is sized to give thermal stability regarding the
inhomogeneity factor. As the required 2G HTS tape length is
more than 2 km, it is typically wound in order to fit into a
compact vessel, hence, the coil inductance LSFCL is CB
considered. LSFCL could also be adjusted to obtain the
inductance of LDC shown in section 2. Fig 4: Model of forced oscillation DCCB.

3
4 Primary protection scheme START
The flowchart in Fig 5 describes the overall protection
strategy divided into three main stages: fault identification, 1. FAULT
fault isolation and power restoration. The primary protection IDENTIFICATION Measure V SFCL and I SFCL
scheme is performed from the fault appearance to
N - 1 operation. Backup schemes will not be developed in this
paper. In addition, the timeline in Fig 6 gives the Detection
chronological order of the events. For better understanding, algorithm
the primary protection scheme is applied for the pole-to-
ground fault case (F) shown in Fig 1. No
Fault detected ?
4.1 Fault identification: intrinsic selectivity
Yes
As explained in section 3.2, only the SFCLs located on the
Identification
faulty line ends will quench immediately after the fault
algorithm
appearance. For fault F (see Fig 1), the closest SFCLs are
placed at busbar N3, where BM31, BM32 and BM3 are located.
During the first fault current transient, the current magnitude
|i31| will be higher than |i3| and |i32|. Hence, |i31| will exceed Yes
Selectivity SFCL quenched
Ic0(To) before the upstream located BMs producing the backup on healthy zone ?
quench of SFCL31. The voltage across SFCL31 rises up and
reaches VDC. The fault current i31 is thus limited and prevents No
the SFCLs on BM3 and BM32 from quenching. Later, when
the fault reaches the busbar N1, a similar sequence of events
2. FAULT
produces the quench of SFCL13, located at BM13, preventing Open DCCB
ISOLATION
SFCL1 and SFCL12 from quenching as well.

Measurements of ISFCL and VSFCL will allow to perform both Fault clearance
fault detection and identification algorithms. When a fault is verification algorithm
detected, SFCL quenching will indicate if the fault is located
in the protected line. As first approach, a constant voltage Backup No
threshold value Vmin for VSFCL can demonstrate the intrinsic fault current Fault cleared ?
selectivity of this protection scheme. Nevertheless, a interruption
selectivity verification algorithm is required in case of Yes
malfunction of an SFCL leading to a quench on a healthy
zone. This verification could be part of the fault identification SFCL recovery
algorithm, e.g. a differential protection algorithm with
communication between BMs can be performed as a backup. 3. POWER Voltage and power
If a non-selective quench is detected, a selectivity backup RESTORATION flow restoration
scheme starting at t3 will perform corrective DCCB operations
to reach an N 1 operating state.

In Fig 6 the time required for the identification stage (t3) is N-1 OPERATION
shown. Due to the different fault propagation times (t1) the
fault identification instant (t3) will be different for each BM. Fig 5: Overall flowchart of the proposed protection strategy.
The fault detection time (t2 t1) and the fault identification
time (t3 t2) will depend on the measuring sampling rate, 1
signal processing delay and the detection and identification 2
algorithms. Fault propagation 3
Fault detection N-1 Operation
4.2 Fault isolation: clearing the fault current Fault identification
Fault current interruption
Once the faulty line is identified (t3), the DCCBs on BM31 and
Fault clearance verification
BM13 will receive the tripping signal and start the opening
P and V restoring
procedure. The fault current interruption time interval (t4 t3)
correspond to tbreak from Table 4. A fault clearance SFCL recovery
verification algorithm must determine the effective t1 t2 t3 t4 t4' t5 t6 time
interruption at t4' and will be the start point for a backup
scheme in case of DCCB failure. Fig 6: Timeline of the primary protection scheme.

4
4.3 Power and voltage restoring Table 5: Timeline values for BM13 and BM31.
Times [ms]
Due to the contribution of the fault current limiting capability
t1 t2 t3 t4 t4' t5 t6
of the SFCL together with the contribution of the passive
BM13 1.6 2.7 3.9 18.9 23.9 200 > 1000
elements LDC and CDC, the MMC control is ensured during the
BM31 0 1.1 1.3 16.3 21.3 200 > 1000
fault clearing process. While the limiting inductor LDC avoids
the IGBT blocking by reducing the rate of rise of the fault
current; the capacitor CDC reduces the voltage drop to prevent
the MMC voltage from dropping below 0.8*V N. Once the
fault is cleared the power and voltage can be restored by the
MMC control.

Voltage (kV)
The SFCL thermal recovery starts at t4 and can last a few
seconds (until t6) before allowing a line reclosing if required.
However, the recovery time is not a matter of this work
because a cable fault is considered permanent and it will not
require an immediate reclosing.

5 Off-line simulation results Time (ms)

Off-line simulation studies of the primary protection scheme Fig 7: VSFCL measured at each BM in the grid.
for the MTDC test grid presented in Fig 1 were performed in
EMTP-RV. The results are shown in Fig 8. In Table 5, an
estimation for the times of Fig 6 is presented. A fault appears
at t = 0 and it arrives at t1 to the different BM according to a
cable propagation velocity of around 200 km/ms. A
Voltage (kV)

measuring sampling rate of 10 kHz and a signal processing vMMC1 A

delay of 1 ms were assumed to estimate t2 and t3. vMMC2
vMMC3
A fault is detected at time t2 at different BMs, however, only
BM13 and BM31 detect the quench of the SFCL (VSFCL > Vmin)
at t3 = 1.3 ms and t3 = 3.9 ms respectively (see Fig 7). This
demonstrates the ultra-fast speed of the quench-based fault
identification method with respect to other techniques
Voltage (kV)

requiring signal-processing at faster sampling rates.

v1
B
v2
In Fig 8, curves A and B, the voltages VMMC3 and V3 reach
v3
respectively the lowest values at the first instants of the fault:
0.8 and 0.6 pu. Nevertheless, the voltage VMMC3 still respects
the 0.8 pu limit to keep a proper converter control. In curve C,
MMC1 reaches the highest current peak value: 7 kA. This
happens after the first fault current transient and is related to i1
the voltage increase rate imposed by the MMC controller. By i2
Current (kA)

consequence, a more efficient MMC control strategy should i3

C
allow to reduce this peak value.

In curve D, the limited and prospective fault currents i 13 and

i31 are superimposed. From time t3, the limitation is already
effective and the DCCB breaks the current 15ms later at t 4.
The fault current is selectively interrupted by BM13 and BM31.
i13
Current (kA)

After the faulty line isolation, MMC and busbar voltages and i31
currents recover to their new values imposed by the new D
power flow condition. As seen again in Fig 8, curves A, B
and C, the rated values are recovered around t5 = 200 ms,
when the system reaches the steady-state under
N - 1 operating conditions.
Time (ms)

Fig 8: I and V waveforms during primary protection scheme.

5
 6 Conclusions
SM SM SM

SM SM SM
A novel full-selective protection strategy based on SFCLs
SM SM SM
was presented. Thanks to a detailed understanding of the
SFCL electro-thermal model, a quench-based ultra-fast fault
SM SM SM

identification criterion has been developed. As the quench of

SM SM SM the SFCL directly depends on the current, it is intrinsically
SM SM SM
selective and allows identifying the faulted zone during the
SM SM SM
first fault current transient. Only measurements on ISFCL and
SM
VSFCL are required for this mean.
SM SM

- iup_A - iup_B - iup_C - ilow_A - ilow_B - ilow_C Moreover, the limitation of the fault current within
IDC - Ic0(To) allows to use electro-mechanical DC circuit
breakers with longer fault clearing times and lower breaking
capability requirements compared to hybrid technologies.
Current (kA)

Selective protection strategies with other fault identification

Time (ms)
Fig 9: MMC arm currents flowing though the IGBTs.
Arm currents are shown in Fig 9 to validate the continuous
operation of MMC converters. AC current (with a
DC component) flows through each arm where one IGBT
(upper or lower) per sub-module (SM) will conduct under
normal control conditions. Fig 9 shows that the maximum
short-circuit current of an IGBT (ISC-IGBT), set at 4 kA
(in Table 2), is respected. This value is slightly lower than
real values tested by manufacturers according to [20].
methods would require ultrafast DCCBs with current
breaking capabilities between 20 30 kA for the MTDC test
grid studied here. An optimum sizing of the SFCL taking into
account the breaking speed of the DCCB was validated by
computation of the temperature rise during the limitation.
Adding passive components to the DC grid can ensure a
continuous operation of the MTDC grid from the fault
apparition to the power restoring. Series reactors (LDC) reduce
the fault current rate of rise and prevent IGBTs blocking of
the MMC converters. In addition, busbar capacitors (CDC)
reduce the voltage drop seen by MMC converters and allow
maintaining the voltage higher than 0.8 p.u preventing the
converter control loss. Furthermore, the SFCL help reducing
the required values for LDC and CDC (by a factor of 10) in
comparison to other protection strategies without SFCL
where a continuous operation is also aimed.

The temperature of SFCLs located on each BM of the test 7 Further Work

grid was calculated assuming homogeneous quenching of the
tape. As shown in Fig 10, the SFCL optimally sized proves to
withstand the total limitation time window of the primary
protection scheme as the maximum final temperature is under
Tmax of 350 K. For the time shown in Fig 10, the SFCL
recovery is not seen as it has a much longer time constant.
Temperature (K)
The impact of LDC and CDC to the DC grid during normal
conditions is not yet assessed. However, as selective MTDC
protection probably requires them regardless the strategy, this
will become an interesting research topic.
Further studies are being held to develop a complete
protection algorithm including backups for DC breaker failure
and selectivity failures. Concerning the SFCL modelling,
assuming a homogeneous quenching is a strong hypothesis.
Indeed, the SFCL inhomogeneity can cause localized
quenching that cannot be detected by voltage measurements

at the SFCL terminals. A detailed model of the SFCL where

the inhomogeneity is taken into account will be included in
further simulation studies. This will allow testing the backup
selectivity failure algorithm developed to detect localized
quenching caused by different types of DC transient
overcurrent.

Acknowledgements
This research work was held at the SuperGrid Institute,
Time (ms)
funded by the French National Research Agency.
Fig 10: SFCL mean temperatures.

6
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