Chapter 6

Functions of Combinational Logic

By Taweesak Reungpeerakul

241-208 CH6 1
 Contents

Adders

Comparators

Decoders

Encoders

Code Converters

Multiplexers

Demultiplexers

Parity Generators

241-208 CH6 2
 5.1 Basic Adders
Full Adder
Half Adder
A B Cin SUM Cout
A B SUM Cout 0 0 0 0 0
0 0 0 0 0 0 1 1 0
0 1 1 0 0 1 0 1 0
1 0 1 0 0 1 1 0 1
1 1 0 1 1 0 0 1 0
1 0 1 0 1
SUM = AB
1 1 0 0 1
Cout = AB 1 1 1 1 1
SUM = ABCin
Cout = AB+(AB)Cin
241-208 CH6 3
 Logic Symbol and Diagram
Half Adder Full Adder

A
B
Cin Cout

A
B
SUM
Cin

Cout

241-208 CH6 4
 Full Adder by 2 Half Adders
Half Adder Full Adder

SUM = ABCin
Cout = AB+(AB)Cin

AB

AB

241-208 CH6 5
 5.2 Parallel Binary Adder
A2A1 A full adder is required for each
+ B2B1 bit in the numbers.
S3S2S1

241-208 CH6 Question: 4-bit numbers 6

 4-bit Parallel Adders

An Bn Cn-1 Sn Cn
A4 B4 A3 B3 A2 B2 A1 B1 C0 0 0 0 0 0
A B Cin A B Cin A B Cin A B Cin
0 0 1 1 0
0 1 0 1 0
Cout Cout Cout Cout 0 1 1 0 1
C4 S4
C3
S3
C2
S2
C1
S1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

241-208 CH6 7
 IC:4-bit Parallel Adder
Example: 74LS83A (or 74LS283)

74LS83A
74LS283

Question: Show circuit diagram of

A+B by using 74LS83A. A = 00001111
and B = 01011100
241-208 CH6 8
 6.3 Comparators

Equality
Inequality

IC: 74LS85

Comparing A and B: AB
 If A=B, output = 0 COMP
A0 0
 If AB, output = 1 A1 A
A2

HIGH indicates equality: AB A3 3
(XNOR) Cascading A>B A>B
A=B A=B Outputs

A1A0 ? B1B0 inputs
A<B A<B
B0 0
B1 B
B2
B3 3

Question: Show circuit diagram in

order to compare two 8-bit numbers
241-208 CH6 by using 74LS85. 9
 Two 74LS85 Cascaded Arrangement
LSBs MSBs

A0 COMP A4 COMP
A1 0 A5 0
A2 A A6 A
A3 A7
3 3
A>B A>B A>B A>B
+5.0 V A=B A=B A=B A=B Outputs
A<B A<B A<B A<B
B0 0 B4 0
B1 A B5 A
B2 B6
B3 3 B7 3

241-208 CH6 10
 74HC85 Truth Table

241-208 CH6 11
 6.4 Decoders

A decoder is a logic circuit that detects
the presence of a specific combination
of bits at its input.
A0 A0
A1 OUT A1 OUT

A2 A2

A3 A3

Active HIGH decoder for 0011 Active LOW decoder for 0011

241-208 CH6 1
 4-to-16 Decoder
0
1
2
Bin/Dec 3
0 1
1 1 4
2 1 5
3 1 A0 1 6
4 1 A1
5 1 2 7
1 A0 A2
6 1 4 8
4-bit binary 1 A1 7 1 Decimal A3 8 9
input 0 A2 8 1 outputs
9 1 10
1 A3 10 1 11
11 0 12
12 1
13 1 13
14 1 14
15 1 CS1 & 15
CS2

IC: 74HC154

Question: Use 74HC154 to implement the logic in

241-208 CH6 order to support a 5-bit number. 2
 BCD-to-Decimal Decoder

BCD-to-decimal decoders accept a binary coded decimal input
and activate one of ten possible decimal digit indications.

IC: 74HC42
Question: Assume the inputs to the
BCD/DEC (1)
0 74HC42 decoder are the sequence
(2) 0101, 0110, 0011, and 0010.
1
(3) Describe the output.
2
(15) (4)
A0 1 3
A1 (14) 2 4
(5) Answer: All lines are HIGH except
A2 (13) 4 5
(6)
for one active output, which is LOW.
(12) (7)
A3 8 6 The active outputs are 5, 6, 3, and 2
(9)
7 in that order.
(10)
8
(11)
9
Question: Write truth table of
74HC42 output 0.
241-208 CH6 3
 BCD-to-7-Segment Decoder

IC: 74LS47 VCC

BCD Inputs (D-A) (16)

BCD/7-seg

7-segment Outputs (a -g) BI/RBO
(4)
BI/RBO
(13)

Ripple Blanking Input (7)
1
a
(12)
(1) b
(RBI) BCD
(2)
2
c
(11)
Outputs
inputs 4 (10) to seven

Blanking Input/Ripple (6)
8
d
(9) segment
e
Blanking Output LT (3)
LT f
(15) device

(BI/RBO) RBI
(5)
RBI g
(14)

Lamp Test (LT) 74LS47 (8)

Zero Suppression GND

241-208 CH6 4
 Illustration of Leading Zero
Suppression

0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0

RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1

74LS47 74LS47 74LS47 74LS47

g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO

241-208 CH6 5
 Illustration of Trailing Zero
Suppression

0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0

RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1

74LS47 74LS47 74LS47 74LS47

g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO

1 0 0

241-208 CH6 6
 6.5 Encoders

An encoder accepts an active
logic level on one of its inputs
representing a digit, such as a 1
A0
decimal or octal digits, and 2
converts it to a coded output, 3
A1
such as BCD or binary.

IC: 74HC147 16-to-4 encoder 4
5 A2
(decimal-to-BCD) 6
7

IC: 74F148 8-to-3 encoder 8
A3
9

241-208 CH6 7
 Example

Show how the decimal-to-BCD encoder converts the
decimal number 3 into a BCD 0011.

1 0 1
A0
2 0
1
3 1
A1

4 0
5 0 0
6
0
0 A2
7
8 0 0
A3
0
9

241-208 CH6 8
 74HC147
VCC

The 74HC147 is an example of
(16)
an IC encoder. It has ten active- HPRI/BCD
LOW inputs and converts the (11) 1
(12)
active input to an active-LOW (13)
2
3 (9)
BCD output. (1) 1
4 (7)
2

This device offers additional Decimal (2) 5 (6)
BCD
input (3) 4 output
flexibility with a priority (4)
6
8 (14)
encoder. 7
(5) 8
(10) 9
(8)

GND

74HC147

241-208 CH6 9
 A Simplified Keyboard Encoder
VCC

R7 R8 R9

7 8 9

1
R4 R5 R6 2
3
4
1
2
BCD complement
5
6
4
8
of key press
4 5 6 7
8
9

R1 R2 R3

1 2 3

R0 The zero line is not needed by the

encoder, but may be used by other
0
circuits to detect a key press.
241-208 CH6 10
 6.6 Code Converters

BCD-to-BIN Conversion
BIN-to-BCD Conversion

IC: 74184
IC: 74185

241-208 CH6 11
 Code Converters (cont.)

BIN-to-Gray
Gray-to-BIN
LSB
LSB G0
B0 B0
G0

B1 G1
G1 B1

B2
G2 B2
G2
B3 G3
G3 B3
MSB
MSB

Question: Show the conversion of binary 0111 to Gray

241-208 CH6 and vice versa. 12
 6.7 Multiplexers (MUX)

A multiplexer has several data-
input lines and a single output
line.

It also has data-select inputs, 0
MUX

which permit digital data on S0 0

Data 1
1
any one of the inputs to be select S1
switched to the output line. D0 Data
0

Another name is a data D1 1 output
Data
selector. D
inputs D2 2
3

IC: 74HC157 Quad 2-input 3

MUX

IC: 74HC151 8-input MUX
Question: Which data line is
selected if S1S0 = 10?

241-208 CH6 13
 ICs

74HC157 Quad 2-input MUX
74HC151 8-input MUX

241-208 CH6 14
 6.8 Demultiplexers (DEMUX)
74LS138

A DEMUX basically reverses the DEMUX
multiplexing function. Data
0
A0
Y
0

1 Y
It takes data from one input A1 1

select
0 Y
lines A2 2

line and distributes to one of Y

3
Data
outputs
output lines depending on the G1
Y
4

select lines. Enable G2A

Y
5

Y

Another name is a data inputs G2B 6

Y
7

distributor.

IC: 74LS138 8-output DEMUX
Question: Which data output is
selected if A2A1A0 = 010?

241-208 CH6 15
 A0
A1
Example (DEMUX) A2
G1

Determine the outputs, G2A LOW
given the inputs shown. G2B LOW

Y0
DEMUX
Y Y1
Data A0 0

Y
select A1 1

Y2
lines Y
A2 2

Data
Y
3
Y3
outputs
Y
Enable G1 4

Y4
Y
5
G2A
inputs Y Y5
G2B 6

Y
7

Y6
74LS138
Y7

241-208 CH6 16
 6.9 Parity Generators/Checkers
74LS280

One method of error
(8)
detections is to use parity. A
(9)
B

A parity bit is attached to a (10)
C
group of data in order to make Data
(11)
D (5)
(12) Even
the total number of 1s either inputs (13)
E (6)
Odd
even or odd. (1)
F
G

IC: 74LS280 9-bit parity (2)
H
(4)
generator/checker I

Checker:
# of 1s on inputs Even Odd Generator: To generate even parity,
0,2,4,6,8 H L the parity bit is taken from the odd
1,3,5,7,9 L H parity output. To generate odd parity,
the output is taken from the even parity
output.
241-208 CH6 17