Combinational Logic Design

Pune Vidyarthi Grihas
COLLEGE OF ENGINEERING, NASHIK 3.
Design of Combinational Logic
By
Prof. Anand N. Gharu
(Assistant Professor)
PVGCOE Computer Dept.
30th June 2017

.
CONTENTS :-
1. Code Converter
- BCD
- EXCESS-3
- Gray Code
- Binary Code
2. Half Adder, Full Adder, Half Substractor, Full Substractor
3. Binary Adder (IC 7483)
4. BCD Adder
5. Look Ahead Carry Generator
6. Multiplexers (MUX) (IC 74151, 74153)
7. Demultiplexers (DEMUX) (IC 74138, 74154)
8. Comparators
9. Parity Generator and Checker
INTRODUCTION OF COMBINATIONAL CIRCUITS
Logic circuits for digital systems may be combinational or sequential.
A combinational circuit consists of input variables, logic gates, and output

variables
1. Combination Circuits :
- The output of combinational circuit at any instant, depends only on the levels
present at input terminals.
- It does not use any memory
- it can have number inputs and outputs.
Example:
1. Adder, Substractor
2. Comparator
3. Code Converters
4. Encoders, Decoders 5. Multiplexers and Demutiplexers
Code Converters
Code converters take an input code, translate to its
equivalent output code.
Input Code Output

code converter code
Example: BCD to Excess-3 Code Converter.

Input: BCD digit
Output: Excess-3 digit
4
Binary Codes
An n-bit binary code is a group of n bits that assume up to 2n
distinct combinations of 1s and 0s, with each combination
representing one element of the set being coded
For the 10 digits need a 4 bit code. One code is called Binary
Coded Decimal (BCD)
5
Binary Coded Decimal
Decimal
0 1 2 3 4 5 6 7 8 9
Digit
BCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
Note: 1010, 1011, 1100, 1101, 1110, and 1111 are INVALID CODE!
Lets crack these
ex1: dec-to-BCD ex2: BCD-to-dec
(a) 35 (a) 10000110
(b) 98 (b) 001101010001
(c) 170 (c) 1001010001110000
(d) 2469
Excess-3 BCD Code
Decimal digits Excess-3 BCD code
0 0011
1 0100
2 0101
3 0110
4 0111
5 1000
6 1001
7 1010
8 1011
9 1100
Excess-3 Code (XS-3)
Decimal No. BCD Code Excess-3 Code=
BCD + Excess-3
0 0000 0011
1 0001 0100
2 0010 0101
3 0011 0110
4 0100 0111
5 0101 1000
6 0110 1001
7 0111 1010
8 1000 1011
9 1001 1100
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Example 1: Obtain Xs-3 Code for 428 Decimal

Example 1: Obtain Xs-3 Code for 428 Decimal
4 2 8
0100 0010 1000

+ 0011 0011 0011
0111 0101 1011

Exercise
Convert following Decimal Numbers into Excess-

3 Code
1. (40)10
2. (88) 10
3. (64) 10
4. (23) 10

BCD-to-Excess-3 Code Converter
Truth table:
BCD Excess-3
A B C D W X Y Z
0 0 0 0 0 0 0 1 1 W = S m(5,6,7,8,9)
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0 x = S m(1,2,3,4,9)
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1 y = S m(0,3,4,7,8)
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
10 1 0 1 0 X X X X
z = S m(0,2,4,6,8)
11 1 0 1 1 X X X X
12 1 1 0 0 X X X X
13 1 1 0 1 X X X X
14 1 1 1 0 X X X X
15 1 1 1 1 X X X X
12
W = Sm(5,6,7,8,9)+ x =Sm(1,2,3,4,9)+
Sd(10,11,12,13,14,15) Sd(10,11,12,13,14,15)
= a+bc+bd = a+b(c+d) bcd+bd+bc=bcd+b(c+d)
AB AB
00 01 11 10 00 01 11 10 Underlined
CD CD
00 x 18 00 0
1 4 x 12 0 8 terms are
0 4 12
01 15 x 19 01 1 x 13 1 9
1 13 1 5 common
11 1 x15 x 11 11 1 x x
3 7 3 7 15 11
10 1 x 14 x10 10 12 6
x 14 x10
2 6
z = Sm(0,2,4,6,8)+
y = Sm(0,3,4,7,8)+ Sd(10,11,12,13,14,15)
Sd(10,11,12,13,14,15)
= d
AB = cd+cd AB
00 01 11 10
00 01 11 10 CD
CD
00 1 0 1 4 x 1 8
00 1 0 1 4 x 1 8 12
12
01 x
01 x 1 5 13 9
1 5 13 9
11 x x
11 1 1 x15 x 11 3 7 15 11
3 7
10 1 1 x 14 x10 13
10 2 6
x 14 x10 2 6
The Excess-3 BCD system is formed by adding 0011 to each
BCD value as in Table 2. For example, the decimal number 7,
which is coded as 0111 in BCD, is coded as 0111+0011=1010
in Excess-3 BCD.
Decimal Numerals Excess-3
0 0011
1 0100
2 0101
3 0110
4 0111
5 1000
6 1001
7 1010
8 1011
9 1100
THE BCD TO EXCESS 3 CODE CONVERTER
BCD Excess-3 circuit will convert numbers from their binary
representation to their excess-3 representation. Hence our truth
table is as below:
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
E2=B2^(B1+B0)
E1=(B1^B0)
E0=B0
Block diagram
Applications
Excess-3 was used on some older computers
Cash registers
Hand held portable electronic calculators

BCD to XS 3 code converter- Design (1)...
TRUTH TABLE FOR BCD TO XS3 CODE CONVERTER:
Input ( Std BCD code) Output ( XS3 Code)

A B C D w x y z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 X X X X
1 0 1 1 X X X X
1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 X X X X
21
K-maps for simplification and simplified Boolean expressions
22
After the manipulation of the Boolean expressions

for using common gates for two or more outputs,
logic expressions can be given by
z=D
y=CD+CD = (C+D)
x= BC + BD + BCD = B(C+D) + BCD
w= A + BC + BD = A + B (C+D)
23
BCD to XS 3 code converter- Design (4)
24
The Gray Code
The Gray code is unweighted and is not an arithmetic code.
o There are no specific weights assigned to the bit positions.
Important: the Gray code exhibits only a single bit change

from one code word to the next in sequence.
o This property is important in many applications, such as shaft position encoders.
The Gray Code
Decimal Binary Gray Code Decimal Binary Gray Code
0 0000 0000 8 1000 1100
1 0001 0001 9 1001 1101
2 0010 0011 10 1010 1111
3 0011 0010 11 1011 1110
4 0100 0110 12 1100 1010
5 0101 0111 13 1101 1011
6 0110 0101 14 1110 1001
7 0111 0100 15 1111 1000
The Gray Code
Binary-to-Gray code conversion
o The MSB in the Gray code is the same as corresponding MSB
in the binary number.
o Going from left to right, add each adjacent pair of binary code
bits to get the next Gray code bit. Discard carries.
ex: convert 101102 to Gray code
1 + 0 + 1 + 1 + 0 binary
1 1 1 0 1 Gray
The Gray Code
Gray-to-Binary Conversion
o The MSB in the binary code is the same as the corresponding bit in the
Gray code.
o Add each binary code bit generated to the Gray code bit in the next
adjacent position. Discard carries.
ex: convert the Gray code word 11011 to binary
1 1 0 1 1 Gray
+ + + +
1 0 0 1 0 Binary
Gray Code
The gray code is non-weighted code.
It is not suitable for arithmetic operations.
It is a cyclic code because successive code words

in this code differ in one bit position only i.e.
unit distance code

Binary to Gray Code Conversion
If an n bit binary number is represented by

Bn, Bn 1,.......B1 and its gray code equivalent by
Gn, Gn 1,.......G1 where Bn and Gn are the MSBs,
then gray code bits are obtained from the

binary code as follows;
Gn Bn Gn 1 Bn Bn 1 Gn 2 Bn 1 Bn 2 G1 B2 B1
*where the symbol represents Exclusive-OR operation

Example 1: Convert 1011 Binary Number into Gray Code

Binary Number 1 0 1 1

Example 1: Continue
Gray Code 1

Example 1: Continue
Gray Code 1 1

Example 1: Continue
Gray Code 1 1 1

Example 1: Continue
Gray Code 1 1 1 0

Example 1: Continue
Gray Code 1 1 1 0


Gray Code 1 1 0 1


Gray Code 1 0 0 0


Gray Code 1 1 1 1

Binary and Corresponding Gray Codes
Decimal No. Binary No. Gray Code
0 0000 0000
1 0001 0001
2 0010 0011
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1100
9 1001 1101
10 1010 1111
11 1011 1110
12 1100 1010
13 1101 1011
14 1110 1001
15 1111 1000
Exercise
Convert following Binary Numbers into Gray

Code
1. (1011)2
2. (110110010)2
3. (101010110101)2
4. (100001)2

Gray Code to Binary Conversion
If an n bit gray code is represented by

Gn, Gn 1,.......G1 and its binary equivalent
Bn, Bn 1,.......B1 then binary bits are obtained
from gray bits as follows;
Bn Gn Bn 1 Bn Gn 1 Bn 2 Bn 1 Gn 2 B1 B2 G1
*where the symbol represents Exclusive-OR operation

Example 1: Convert 1110 Gray code into Binary Number.

Gray Code 1 1 1 0

Example 1: Continue
Gray Code 1 1 1 0
Binary Number 1

Example 1: Continue
Gray Code 1 1 1 0
Binary Number 1 0

Example 1: Continue
Gray Code 1 1 1 0
Binary Number 1 0 1

Example 1: Continue
Gray Code 1 1 1 0

Example 1: Continue
Gray Code 1 1 1 0


Gray Code 1 1 0 1


Gray Code 1 1 0 0

Exercise
Convert following Gray Numbers into Binary

Numbers
1. (1111)GRAY
2. (101110) GRAY
3. (100010110) GRAY
4. (11100111) GRAY

FOUR BIT BINARY TO GRAY CODE CONVERTER
DESIGN (1) MSB + + + + Binary code
TRUTH TABLE: 0 1 1 0 1
Gray code
0 1 0 1 1
INPUT ( BINARY) OUTPUTS (GRAY CODE)
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
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1 1 1 1 1 0 0 0
Combinational Logic Circuits
Introduction
Standard representation of canonical forms (SOP & POS), Maxterm
and Minterm , Conversion between SOP and POS forms
K-map reduction techniques upto 4 variables (SOP & POS form),
Design of Half Adder, Full Adder, Half Subtractor & Full Subtractor
using k-Map
Code Converter using K-map: Gray to Binary, Binary to
Gray Code Converter (upto 4 bit)
IC 7447 as BCD to 7- Segment decoder driver
IC 7483 as Adder & Subtractor, 1 Digit BCD Adder
Block Schematic of ALU IC 74181 IC 74381
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Design of Binary to Gray Code Converter
Block Diagram:
B3 G3
B2 Binary to Gray G2
Binary Gray
B1 Code G1
Inputs Outputs
B0 converter G0
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BINARY TO GRAY CONVERSION
K-map for G0:
B1B0 B1B 0 B1B 0 B1B 0 B1B 0

B3B2 00 01 11 10
0 0 1 1 0 3 1 2
B3 B 2 00
B3B 2 01 0 4 1 5 0 7 1 6 G 0 B1B 0 B1B 0

0 12 1 13 0 15 1 14
B3 B 2 11 G 0 B 0 B1
0 8 1 9 0 11 1 10
B3 B 2 10
B1B 0 B1B 0
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K-map for G1:
B1B0 B1B 0 B1B 0 B1B 0 B1B 0

B3B2 00 01 11 10
0 0 0 1 1 3 1 2
B3 B 2 00
B3B 2 01 1 4 1 5 0 7 0 6 G1 B 2B1 B 2 B1
1 12 1 13 0 15 0 14
B3 B 2 11 G1 B 2 B1
0 8 0 9 1 11 1 10
B3 B 2 10
B 2 B1 B 2B1
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K-map for G2:
B1B0 B1B 0 B1B 0 B1B 0 B1B 0

B3B2 00 01 11 10
0 0 0 1 0 3 0 2
B3 B 2 00
B3B 2 01 1 4 1 5 1 7 1 6 G 2 B3B 2 B3 B 2
0 12 0 13 0 15 0 14
B3 B 2 11 G 2 B3 B 2
1 8 1 9 1 11 1 10
B3 B 2 10
B3 B 2 B3B 2
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K-map for G3:
B1B0 B1B 0 B1B 0 B1B 0 B1B 0

B3B2 00 01 11 10
0 0 0 1 0 3 0 2
B3 B 2 00
B3B 2 01 0 4 0 5 0 7 0 6 G 3 B3
B3 B 2 11 1 12 1 13 1 15 1 14
1 8 1 9 1 11 1 10
B3 B 2 10
B3
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Logic Diagram:
B3 B2 B1 B0
G3
G 2 B3 B 2
G1 B2 B1
G 0 B1 B 0
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Design of Gray to Binary Code Converter
Block Diagram:
G3 B3
G2
Gray to Binary B2 Binary
Gray
Inputs G1 Code B1 Outputs
G0 converter B0
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GRAY TO BINARY CONVERSION
K-map for B0: G1G0 G1G 0 G1G 0 G1G 0 G1G 0
G3G2 00 01 11 10
0 0 1 1 0 3 1 2
G 3G 2 00
G 3G 2 01 1 4 0 5 1 7 0 6
G 3G 2 11 0 12 1 13 0 15 1 14
1 8 0 9 1 11 0 10
G 3G 2 10
B 0 G 3G 2G1G 0 G 3G 2G1G 0 G 3G 2G1G 0 G 3G 2G1G 0

G 3G 2G1G 0 G 3G 2G1G 0 G 3G 2G1G 0 G 3G 2G1G 0
B 0 G 3 G 2 G1 G 0
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G3G2 00 01 11 10
0 0 0 1 1 3 1 2
G 3G 2 00
G 3G 2 01 1 4 1 5 0 7 0 6
G 3G 2 11 0 12 0 13 1 15 1 14
1 8 1 9 0 11 0 10
G 3G 2 10
B1 G 3G 2G1 G 3G 2G1 G 3G 2G1 G 3G 2G1
B1 G 3 G 2 G1
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G3G2 00 01 11 10
0 0 0 1 0 3 0 2
G 3G 2 00
G 3G 2 01 1 4 1 5 1 7 1 6
G 3G 2 11 0 12 0 13 0 15 0 14
1 8 1 9 1 11 1 10
G 3G 2 10
B 2 G 3G 2 G 3G 2
B1 G 3 G 2
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G3G2 00 01 11 10
0 0 0 1 0 3 0 2
G 3G 2 00
G 3G 2 01 0 4 0 5 0 7 0 6
G 3G 2 11 1 12 1 13 1 15 1 14
1 8 1 9 1 11 1 10
G 3G 2 10
B3 G 3
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Logic Diagram:
G3 G2 G 1 G0
B3
B2 G 3 G2
B1 G1 G 2 G 3
B 0 G 0 G1 G 2 G 3
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Half Adder
Half adder is a combinational logic circuit with

two inputs and two outputs.
It is a basic building block for addition of two
single bit numbers.
A Sum
Inputs Half Outputs

Adder
B Carry
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Half Adder
K-map for Sum Output:
A
A A
B 0 1
0 1 S AB AB
B 0
1 0
S A B
B 1
K-map for Carry Output:

A
A A
B 0 1
0 0
B 0 C AB
0 1
B 1
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Half Adder
Logic Diagram:
A
S A B
B
C AB
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Half Adder
Logic Diagram using Basic Gates:
A B
S A B
C AB
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Full Adder
Full adder is a combinational logic circuit with

three inputs and two outputs.
A Sum
Inputs B Full Outputs

Adder
Carry
Cin
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TRUTH TABLE
Full Adder
K-map for Sum Output:
BC BC BC BC BC
00 01 11 10
A S ABC ABC ABC ABC
0 1 0 1
A 0 S ABC ABC ABC ABC
1 0 1 0
A 1 S C ( AB AB) C ( AB AB )
Let AB AB X
ABC
ABC ABC S C( X ) C( X )
ABC
S CX
Let X A B
S C A B
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Full Adder
K-map for Carry Output:
BC BC BC BC BC
A 00 01 11 10
0 0 1 0
A 0
C AB BC AC
A 1 0 1 1 1
BC
AB
AC
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Full Adder
Logic Diagram:
A B C
S A B C
C AB BC AC
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Full Adder using Half Adders
A S0 S1 Sum
HA1 HA2
B C0 C1
C
Carry
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Half Subtractor
Half subtractor is a combinational logic circuit

with two inputs and two outputs.
It is a basic building block for subtraction of
two single bit numbers.
A Difference
Inputs Half Outputs

Subtractor
B Borrow
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HALF SUBSTRACTOR
Half Subtractor
K-map for Difference Output:
A
A A
B 0 1
0 1 D AB AB
B 0
1 0
D A B
B 1
K-map for Borrow Output:

A
A A
B 0 1
0 1
B 0 B AB
0 0
B 1
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Half Subtractor
Logic Diagram:
A
D A B
B
B AB
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Half Subtractor
Logic Diagram using Basic Gates:
A B
D A B
B AB
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Full Subtractor
Full subtractor is a combinational logic circuit

with three inputs and two outputs.
A Difference
Inputs B Full Outputs

Subtractor
Borrow
Bin
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FULL SUBSTRATOR
Full Subtractor
K-map for Difference Output:
BC BC BC BC BC
00 01 11 10
A D ABC ABC ABC ABC
0 1 0 1
A 0 D ABC ABC ABC ABC
1 0 1 0
A 1 D C ( AB AB ) C ( AB AB )
Let AB AB X
ABC
ABC ABC D C( X ) C( X )
ABC
DCX
Let X A B
D C A B
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Full Subtractor
K-map for Borrow Output:
BC BC BC BC BC
A 00 01 11 10
0 1 1 1
A 0
B 0 AB BC AC
A 1 0 0 1 0
BC
AB
AC
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Full Subtractor
Logic Diagram:
A B C
D A B C
B 0 AB BC AC
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Full Subtractor using Half Subtractor
A D0 D1
Difference
HS1 HS2
B B0 B1
C
Borrow
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Introduction
using k-Map
Code Converter using K-map: Gray to Binary, Binary to Gray Code
Converter (upto 4 bit)
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Seven Segment Display
f b
g
e c
d dp
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Seven Segment Display
Segments Display Seven Segment
Number Display
a b c d e f g
ON ON ON ON ON ON OFF 0
OFF ON ON OFF OFF OFF OFF 1
ON ON OFF ON ON OFF ON 2
ON ON ON ON OFF OFF ON 3
OFF ON ON OFF OFF ON ON 4
ON OFF ON ON OFF ON ON 5
ON OFF ON ON ON ON ON 6
ON ON ON OFF OFF OFF OFF 7
ON ON ON ON ON ON ON 8
ON8/29/2017 ON ON ON OFFAmit Nevase

ON ON 9 99
Types of Seven Segment Display
Common Cathode Display
Common Anode Display
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+Vcc
R R R R R R R R
a b c d e f g dp
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+Vcc
R
R
b
R
c
R
d
BCD to
R
BCD e
7 Segment
Input
f
R
Decoder
g
R
R
dp
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a b c d e f g dp
R R R R R R R R
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R
b
R
c
R
BCD to d
R
BCD 7 Segment e
Input Decoder
R
f
R
g
R
dp
R
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BCD to 7 Segment Decoder Driver ICs
Sr. No. IC Number Specifications
1 IC 7446, Active Low open collector outputs,

IC 74246 maximum voltage 30 V,
maximum current sinking capability 40mA
2 IC 7447, Active Low open collector outputs,

IC 74247 maximum voltage 15 V,
maximum current sinking capability 40mA
3 IC 7448, Active High open collector outputs,

IC 74248 Pull up resistor 2kohm,
maximum voltage 5.5 V,
maximum current sinking capability 6.4mA
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IC 7447
Pins Description
A,B,C,D BCD Inputs
a to g Active Low Outputs
LT Lamp Test
Ripple Blanking Input

RBI
BI Blanking Input
RBO Ripple Blanking output
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RBI - Ripple Blanking Input
For the normal decoding operation, this input

should be connected to logic 1.
If RBI is connected to ground, then it switches
off the display when BCD inputs
corresponding to 0.
For non-zero BCD inputs, the decoder output
will be normal and the BCD number will be
displayed.
RBI=0 is connected for blanking out the
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leading zeros in multidigit displays.
BI Blanking Input
If BI is connected to 0, then the display will be

switched off irrespective of the BCD input.
This feature is used in the multiplexed display
in order to save power.
In the non-multiplexed displays this input is
permanently connected to Vcc
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RBO Ripple Blanking Output
This output is normally at logic 1. But it goes

to logic 0 during the zero blanking interval
when RBI is forced to a low level.
RBO is used for cascading purpose and it is
connected to RBI of the next stage.
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LT - Lamp Test
This pin can be used to check whether all the

segments of the display are working properly
or not.
If LT is forced low with RBO at logic 1 or open ,
then all the output terminals will be forced to
their active state
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Circuit Diagram
5V
16
3 Vcc 13 R Common
LT a a
5 RBI
12 R a
4 BI / RBO b b
11 R f b
IC 7447
c c g
10 R
LSB 1 d d
A0 9 R e c
2
A1 e e dp
BCD R
6 15
Inputs
A2 f f d dp
7 14 R
A3
MSB Gnd g g
8
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Display Configuration LTS 542
Common
g f a b
a
f b
g
e c
d dp
e d c dp
Common
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Display Configuration
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Introduction
using k-Map
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N Bit Parallel Adder
The full adder is capable of adding two single

digit binary numbers along with a carry input.
But in practice we need to add binary numbers
which are much longer than one bit.
To add two n-bit binary numbers we need to use
the n-bit parallel adder.
It uses a number of full adders in cascade.
The carry output of the previous full adder is
connected to the carry input of the next full
adder..
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N Bit Parallel Adder
An 1 Bn 1 A2 B2 A1 B1 A0 B0
FA-(n-1) FA-2 FA-1 FA-0

C0 Cin
Sn 1 S2 S1 S0
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4 Bit Parallel Adder using full adder
A3 B3 A2 B2 A1 B1 A0 B0
FA-3 FA-2 FA-1 FA-0

C0 Cin
S3 S2 S1 S0
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IC 7483 4 Bit Binary Parallel Adder
A3 B3 A2 B2 A1 B1 A0 B0
FA-3 FA-2 FA-1 FA-0

C0 Cin
S3 S2 S1 S0
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IC 7483 4 Bit Binary Parallel Adder
A Binary number B Binary number

A3 A2 A1 A0 B 3 B 2 B1 B 0
IC 7483 Cin
C0
Carry
Carry
Input
Output
S3 S 2 S1 S 0
Sum Output
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Cascading of IC 7483
If we want to add two 8 bit binary numbers using 4 bit binary parallel adder IC 7483,
then we have to cascade the two ICs in following way
Higher nibble of Lower nibble of Lower nibble of

Higher nibble of
B Binary number A Binary number B Binary number
A Binary number
A7 A6 A5 A4 B 7 B 6 B5 B 4 A3 A2 A1 A0 B 3 B 2 B1 B 0
Cin C0
C0 IC 7483-II IC 7483-I Cin
Carry Carry
Output Input
S7 S6 S5 S4 S3 S 2 S1 S 0
Sum Output
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Design of 1 Digit BCD Adder
Block Diagram: A BCD no. B BCD no.
C0 IC 7483-I
S 3 S 2 S1 S 0 Cin
Logic
Circuit
Add 0110 Command
IC 7483-II
C0 Cin
8/29/2017 S3 S 2 S1 S 0 121
As we know BCD addition rules, we understand that the

4 bit BCD adder should consists of following:
A 4 bit binary adder to add the given two (4 bit
numbers).
A combinational logic circuit to check if sum is
greater than 9 or carry 1.
One more 4 bit binary adder to add 0110 to the
invalid BCD sum or if carry is 1
8/29/2017 122
Logic Table for design of Logic circuit:

Inputs Y Inputs Y
S3 S2 S1 S0 S3 S2 S1 S0
0 0 0 0 0 1 0 0 0 0
0 0 0 1 0 1 0 0 1 0
0 0 1 0 0 1 0 1 0 1
0 0 1 1 0 1 0 1 1 1
Sum is
0 1 0 0 0 1 1 0 0 1
invalid
0 1 0 1 0 1 1 0 1 1
BCD
0 1 1 0 0 1 1 1 0 1 Number
Y=1
0 1
8/29/2017 1 1 0 1 Nevase
Amit 1 1 1 1 123
K-map for Logic circuit:
S1S0 S 1S 0 S 1S 0 S 1S 0 S 1S 0
S3 s 2 00 01 11 10
0 0 0 1 0 3 0 2
S 3S 2 00
S 3S 2 01 0 4 0 5 0 7 0 6
1 12 1 13 1 15 1 14
Y S 3S 2 S 3S 1
S 3S 2 11
0 8 0 9 1 11 1 10
S 3S 2 10
S 3S 2 S 1S 3
8/29/2017 124
4-BIT BCD ADDER
4 Bit Binary Parallel Subtractor using IC 7483
A Binary number B Binary number

A3 A2 A1 A0 B 3 B 2 B1 B 0
NOT gates for 1s
complement of B
Vcc 5V
C0
Carry IC 7483 Cin 1
Output S3 S 2 S1 S 0 It adds 1 to 1s
complement of B
Difference Output
8/29/2017 127
IC 7483 as Parallel Adder/Subtractor
B Binary number
B3 B2 B1 B0
A Binary number
M
A3 A2 A1 A0
Mode
Select
C0
Carry IC 7483
Cin
Output S3 S 2 S1 S 0
Sum or Difference Output Mode Select

M=0 Addition
8/29/2017 M=1 Subtraction
128
Comparators
IC comparators
provide outputs
to indicate
which of the
numbers is
larger or if
COMP
they are equal. A0 0
A1 A
The bits are numbered starting at 0, A2
rather than 1 as in the case of adders. A3 3
A>B A>B
Cascading
A=B A=B Outputs
inputs
A<B A<B
B0 0
Cascading inputs are provided to expand B1 A The IC shown is
the comparator to larger numbers. B2 the 4-bit
B3 3 74HC85/74LS85.
74LS85 (4bit magnitude comparator)
The 74LS85 compares two unsigned 4-bit
binary numbers , the unsigned numbers are
A3, A2, A1, A0 and B3, B2, B1, B0.
Cascading Outputs
Inputs
130
Comparators
Use 74HC85 comparators to compare the magnitudes of two 8-bit

numbers. Show the comparators with proper interconnections.
A=A7A6A5A4A3A2A1A0 and B=B7B6B5B4B3B2B1B0
IC comparators LSBs MSBs
can be expanded A0
0
COMP A4
0
COMP
A1 A5
using the A2 A A6 A
cascading inputs A3 A7
3 3
as shown. The +5.0 V
A>B A>B
A=B A=B
A>B A>B
A=B A=B Outputs
lowest order A<B A<B A<B A<B
B0 0 B4 0
comparator has B1 A B5 A
a HIGH on the B2 B6
B3 3 B7 3
A = B input.
Introduction
using k-Map
Block Schematic of ALU IC 74181, IC 74381
8/29/2017 132
IC 74181 Arithmetic Logic Unit
A very popular & widely used combinational

circuit is ALU which is capable of performing
arithmetic as well as logical operation.
Arithmetic Operating Modes:
Addition
Subtraction
Shift Operation
Magnitude Comparison
12 other arithmetic operations
8/29/2017 133
IC 74181
Logical Function Modes:

Exclusive OR
Comparator
AND, NAND, OR, NOR
10 other arithmetic operations
8/29/2017 134
IC 74181 Pin Diagram
8/29/2017 135
IC 74181 Function Table
8/29/2017 136
IC 74381 4 Bit Arithmetic Logic Unit
Features:
Low input loading minimizes drive requirements
Performs six arithmetic and logic functions
Selectable LOW (clear) and HIGH (preset)
functions
Carry generate and propagate outputs for use
with carry look ahead generator
8/29/2017 137
IC 74381 Pin Configuration
8/29/2017 138
IC 74381 Function Table
8/29/2017 139
Necessity, Applications and Realization of following
Multiplexers (MUX): MUX Tree
Demultiplexers (DEMUX): DEMUX Tree, DEMUX as Decoder
Study of IC 74151, IC 74155
Priority Encoder 8:3, Decimal to BCD Encoder
Tristate Logic, Unidirectional & Bidirectional buffer ICs: IC 74244
and IC 74245
8/29/2017 140
Multiplexers
Multiplexer is a circuit which has a number of

inputs but only one output.
Multiplexer is a circuit which transmits large
number of information signals over a single
line.
Multiplexer is also known as Data Selector
or MUX.
8/29/2017 141
Necessity of Multiplexers
In most of the electronic systems, the digital

data is available on more than one lines. It is
necessary to route this data over a single line.
Under such circumstances we require a circuit
which select one of the many inputs at a time.
This circuit is nothing but a multiplexer. Which
has many inputs, one output and some select
lines.
Multiplexer improves the reliability of the
digital system because it reduces the number
8/29/2017 142
Advantages of Multiplexers
It reduces the number of wires.

So it reduces the circuit complexity and cost.
We can implement many combinational
circuits using Mux.
It simplifies the logic design.
It does not need the k-map and simplification.
8/29/2017 143
Applications of Multiplexers
It is used as a data selector to select one out

of many data inputs.
It is used for simplification of logic design.
It is used in data acquisition system.
In designing the combinational circuits.
In D to A converters.
To minimize the number of connections.
8/29/2017 144
Block Diagram of Multiplexer
D0 D0
D1 D1
Data D2 D2
D3 Y
Inputs D3
. n:1 .
. Output .
Mux Output
. .
Dn-1 . .
Dn-1
. .
E
Enable Input
.... ....
Sm-1 S2 S1 s0 Sm-1 S2 S1 s0
Select Lines
Fig. General Block Diagram Fig. Equivalent Circuit
8/29/2017 145
Relation between Data Input Lines & Select Lines
In general multiplexer contains , n data lines,

one output line and m select lines.
To select n inputs we need m select lines such

m
that 2 =n.
8/29/2017 146
Types of Multiplexers
2:1 Multiplexer
4:1 Multiplexer
8:1 Multiplexer
16:1 Multiplexer
32:1 Multiplexer
64:1 Multiplexer
and so on
8/29/2017 147
2:1 Multiplexer
Data D0
2:1 Y
Inputs D1 Block Diagram
Mux Output
E
Enable Input
s
Select Lines
Enable i/p Select i/p Output
(E) (S) (Y)
0 X 0
1 0 D0
Truth Table
1 1 D1
8/29/2017 148
Realization of 2:1 Mux using gates
S D1 D0
S
SD 0
Y
Output
SD1
E
Enable Input
8/29/2017 149
4:1 MULTIPLEXER
Realization of 4:1 Mux using gates
S1 S0
S 1S 0D 0
D0
S 1S 0 D1
D1 Y
Output
D2 S 1S 0D 2
E
D3 S 1S 0 D 3 Enable Input
8/29/2017 151
16:1 Multiplexer
D0
D1
D2
D3
D4
D5
Data D6 Y
D7 16:1
Inputs D8
D9 Mux Output
D10
D11
D12
D13
D14
D15
E
Block Diagram
Enable Input
S3 S2 S1 S0
8/29/2017 Select Lines 152
Mux Tree
The multiplexers having more number of

inputs can be obtained by cascading two or
more multiplexers with less number of inputs.
This is called as Multiplexer Tree.
For example, 32:1 mux can be realized using
two 16:1 mux and one 2:1 mux.
8/29/2017 153
8:1 Multiplexer using 4:1 Multiplexer
D0
D1
Y1
D2 4:1
D3 Mux
Select S2 ES S0 Y
1
S1
Lines S0 Output
S1 S0
D4
D5
4:1
D6 Mux Y2
D7
E
8/29/2017 154
8:1 Multiplexer using 4:1 Multiplexer
D0
D1
Y1
D2 4:1
D3 Mux
D0
ES S0 2:1 Y
1 D1
S1 Mux
S0 Output
E
S1 S0
D4
D5 S2
4:1
D6 Mux Y2
D7
E
8/29/2017 155
D0
4:1 Y1
16:1 Mux using 4:1 Mux
D1
D2 Mux
D3
S1 S0
S1
S0
D4 S1 S0
D5 4:1 Y2
D6 Mux
D7
D0
4:1 Y
D1
D2 Mux
D3 S S0 Output
D8 1
D9 4:1 Y3
D10 Mux
D11
S1 S0 S3 S2
D12 S1 S0
D13 4:1 Y4
D14 Mux
8/29/2017 D15 156
Realization of Boolean expression using Mux
We can implement any Boolean expression

using Multiplexers.
It reduces circuit complexity.
It does not require any simplification
8/29/2017 157
Example 1
Implement following Boolean expression using multiplexer
f ( A, B, C ) m(0, 3, 5, 6)
Since there are three variables, therefore a

multiplexer with three select input is required
i.e. 8:1 multiplexer is required
The 8:1 multiplexer is configured as below to
implement given Boolean expression
8/29/2017 158
Example 1 continue..
+Vcc f ( A, B, C ) m(0, 3, 5, 6)
D0
D1
D2
D3
Y
D4 8:1
Mux Output
D5
D6
D7
E S2 S1 S0
A B C
8/29/2017 159
Example 2
Implement following Boolean expression using multiplexer
f ( A, B, C , D ) m(0, 2, 3, 6,8, 9,12,14)
Since there are four variables, therefore a

multiplexer with four select input is required
i.e. 16:1 multiplexer is required
The 16:1 multiplexer is configured as below to
implement given Boolean expression
8/29/2017 160
+Vcc f ( A, B, C , D ) m(0, 2, 3, 6,8, 9,12,14)
D0
D1
D2
D3
D4
D5
D6 Y
D7 16:1
D8
D9 Mux Output
D10
D11
D12
D13
D14
D15
S3 S2 S1 S0
E
A B C D
8/29/2017 161
Demultiplexers (DEMUX): DEMUX Tree, DEMUX as
Decoder
and IC 74245
8/29/2017 162
De-multiplexer
A de-multiplexer performs the reverse

operation of a multiplexer i.e. it receives one
input and distributes it over several outputs.
At a time only one output line is selected by
the select lines and the input is transmitted to
the selected output line.
It has only one input line, n number of output
lines and m number of select lines.
8/29/2017 163
Block Diagram of De-multiplexer
Y0 Y0
Y1 Y1
Y2 Y2
Data Y3 Y3
1:n . Data .
Input . Outputs . Outputs
De-mux Input
. .
. Yn-1 . Yn-1
. .
E
Enable
.... ....
Input
Sm-1 S2 S1 s0 Sm-1 S2 S1 s0
Select Lines
Fig. General Block Diagram Fig. Equivalent Circuit
8/29/2017 164
Relation between Data Output Lines & Select Lines
In general de-multiplexer contains , n output

lines, one input line and m select lines.
To select n outputs we need m select lines

m
such that n=2 .
8/29/2017 165
Types of De-multiplexers
1:2 De-multiplexer
1:4 De-multiplexer
1:8 De-multiplexer
1:16 De-multiplexer
1:32 De-multiplexer
1:64 De-multiplexer
and so on
8/29/2017 166
1:2 De-mux
1:2 De-mux using basic gates
E Din S
S
Y0
Y1
8/29/2017 168
1:4 De-mux
1:4 De-mux using basic gates
E Din S 1 S0
S1 S0
Y0
Y1
Y2
Y3
8/29/2017 170
1: 8 De-multiplexer
Y0
Y1
Data Din Y2
1:8 Y3
Input Y4
De-mux Y5
Y6
E Y7
Enable
Input S2 S1 S0
Select Lines
Block Diagram
8/29/2017 171
1: 16 De-multiplexer
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Data Din Y7
Input 1:16 Y8
Y9
De-mux
Y10
Y11
Block Diagram Y12
Y13
Y14
E Y15
Enable
8/29/2017 Input S3 S2 S1 S0 172
De-mux Tree
Similar to multiplexer we can construct the

de-multiplexer with more number of lines
using de-multiplexer having less number of
lines. This is call as De-mux Tree.
8/29/2017 173
1:4 De-mux using 1:2 De-mux
Data Y0 Y0
1:2
Din
Input De-mux Y1 Y1
S1 E S0
Select
Lines S0
S0
Y0 Y2
Din 1:2
De-mux Y Y3
1
E
8/29/2017 174
1:16 De-mux using 1:4 Y0
1:4 Y1
De-mux Din Y2
De-mux Y3
S1 S0
S1 S0 Y4
1:4 Y5
Din Y6
Data Y0 De-mux
Din 1:4 Y7
Y1
Input Y2
De-mux Y3
S1 S0
Y8
1:4 Y9
Din
De-mux Y10
S3 S2 S1 S0 Y11
S1 S0 Y12
Din 1:4 Y13
Y14 S1 S0
8/29/2017 De-mux Y15 175
Decoder
Decoder is a combinational circuit.

It converts n bit binary information at its input
into a maximum of 2n output lines.
For example, if n=2 then we can design upto
2:4 decoder
8/29/2017 176
De-multiplexer as Decoder
It is possible to operate a de-multiplexer as a

decoder.
Let us consider an example of 1:4 de-mux can
be used as 2:4 decoder
8/29/2017 177
1:4 De-multiplexer as 2:4 Decoder
Vcc
Y0 Din Y0
A S1
Data Din 1:4 Y1 Inputs 1:4 Y1
De-mux Y2 B S0 De-mux Y2
Input Y3
E Y3
Enable E Enable
Input S1 S0
Select Lines Input
1: 4 De-multiplexer 1: 4 De-multiplexer as 2:4 Decoder
8/29/2017 178
Realization of Boolean expression using De-mux
We can implement any Boolean expression

using de-multiplexers.
It reduces circuit complexity.
It does not require any simplification
8/29/2017 179
Example 1
Implement following Boolean expression using de-multiplexer
f ( A, B, C ) m(0, 3, 5, 6)
Since there are three variables, therefore a

de-multiplexer with three select input is
required i.e. 1:8 de-multiplexer is required
The 1:8 de-multiplexer is configured as below
to implement given Boolean expression
8/29/2017 180
f ( A, B, C ) m(0, 3, 5, 6)
+Vcc Y0
Y1
Data Y2
Din 1:8 Y3 Y
Input Y4
De-mux Y
5
Y6
E S2 S1 S0 Y7
Enable
Input A B C
8/29/2017 181
Example 2
Implement following Boolean expression using de-multiplexer
f ( A, B, C , D ) m(0, 2, 3, 6,8, 9,12,14)
Since there are four variables, therefore a de-

multiplexer with four select input is required
i.e. 1:16 de-multiplexer is required
The 1:16 de-multiplexer is configured as
below to implement given Boolean expression
8/29/2017 182
Y0
Y1
Y2
+Vcc Y3
Y4
Y5
Y6
Data 1:16 Y7 Y
Input Din De-mux Y8
Y9
Y10
Y11
Y12
Y13
Y14
E S3 S2 S1 SY0 15
Enable
f ( A, B, C , D ) m(0, 2, 3, 6,8, 9,12,14)
Input A B C D
8/29/2017 183
Module III Combinational Logic
Circuits
(8 Marks)
and IC 74245
8/29/2017 184
Multiplexer ICs
IC Number Description Output
IC 74157 Quad 2:1 Mux Same as input
IC 74158 Quad 2:1 Mux Inverted Output
IC 74153 Dual 4:1 Mux Same as input
IC 74352 Dual 4:1 Mux Inverted Output
IC 74151 8:1 Mux Inverted Output
8/29/2017 185
IC 74151 General Description
This Data Selector/Multiplexer contains full

on-chip decoding to select one-of-eight data
sources as a result of a unique three-bit binary
code at the Select inputs.
Two complementary outputs provide both
inverting and non-inverting
Y buffer operation.
A Strobe input is provided which, when at the
high level, disables all data inputs and forces
the Y output to the low state and the
output to the high state.
8/29/2017 186
IC 74151 - Features
Advanced oxide-isolated, ion-implanted

Schottky TTL process
Switching performance is guaranteed over full
temperature and VCC supply range
Pin and functional compatible with LS family
counterpart
Improved output transient handling capability
8/29/2017 187
IC 74151 Pin Diagram VCC GND
D0
D1
D2 Y
Data D3
D4 8:1
Inputs
Mux
D5 Y
D6
D7
E
Enable Input
Pin Diagram
S2 S1 S0
Select Lines
8/29/2017 188
Equivalent Diagram
De-multiplexer ICs
IC Number Description
IC 74138 1:8 De-multiplexer
IC 74139 Dual 1:4 De-multiplexer
IC 74154
1:16 De-multiplexer
IC 74155
Dual 1:4 De-multiplexer
8/29/2017 189
IC 74155 General Description
These monolithic TTL circuits feature dual 1

line to 4 line de-multiplexers with individual
strobes and common binary address inputs in
a single 16 pin package.
The individual strobes permit activating or
inhibiting each of the 4-bit sections as desired.
8/29/2017 190
IC 74155 - Features
Input clamping diodes simplify system design.

Choice of outputs : Totem pole (LS155A) or
open collector (LS156).
Individual strobes simplify cascading for
decoding or de-multiplexing larger words.
Applications:
Dual 2 to 4 Line Decoder
Dual 1: 4 De-multiplexer
3 to 8 line Decoder

8/29/2017 191
1 to 8 line de-multiplexer
IC 7155 Pin Diagram
8/29/2017 192
(8 Marks)
and IC 74245
8/29/2017 193
Encoder
Encoder is a combinational circuit which is

designed to perform the inverse operation of
decoder.
An encoder has n number of input lines and
m number of output lines.
An encoder produces an m bit binary code
corresponding to the digital input number.
The encoder accepts an n input digital word
and converts it into m bit another digital word
8/29/2017 194
Encoder
n m
. Encoder .
inputs . .
outputs
. .
8/29/2017 195
Types of Encoders
Priority Encoder
Decimal to BCD Encoder
Octal to BCD Encoder
Hexadecimal to Binary Encoder
8/29/2017 196
Priority Encoder
This is a special type of encoder.
Priorities are given to the input lines.
If two or more input lines are 1 at the same

time, then the input line with highest priority
will be considered.
8/29/2017 197
Priority Encoder 8:3
Highest Priority
D0
D1 Y2
D2 Priority 3
8 D3 Y1
Encoder outputs
inputs D4 Y0
D5 8:3
D6
D7
Lowest Priority
8/29/2017 198
Decimal to BCD Encoder
D1
D2 A
D3
D4 Decimal to B BCD
9 D5 BCD C
outputs
D6
inputs Encoder D
D7
D8
D9
8/29/2017 200
Tristate Logic, Unidirectional & Bidirectional buffer ICs:
IC 74244 and IC 74245
8/29/2017 201
Tristate Logic
In digital electronics three-state, tri-state, or

3-state logic allows an output port to assume
a high impedance state in addition to the 0
and 1 logic levels, effectively removing the
output from the circuit.
8/29/2017 202
Digital Buffer
Sometimes in digital electronic circuits we

need to isolate logic gates from each other or
have them drive or switch higher than normal
loads, such as relays, solenoids and lamps
without the need for inversion.
One type of single input logic gate that allows
us to do just that is called the Digital Buffer.
8/29/2017 203
Digital Buffer
Unlike the single input, single output inverter or NOT gate
such as the TTL 7404 which inverts or complements its
input signal on the output, the Buffer performs no
inversion or decision making capabilities (like logic gates
with two or more inputs) but instead produces an output
which exactly matches that of its input. In other words, a
digital buffer does nothing as its output state equals its
input state.
Then digital buffers can be regarded as Idempotent gates
applying Booles Idempotent Law because when an input
passes through this device its value is not changed. So the
digital buffer is a non-inverting device and will
therefore give us the Boolean expression of: Q = A.
8/29/2017 204
Tri-state Buffer
As well as the standard Digital Buffer seen above, there is
another type of digital buffer circuit whose output can be
electronically disconnected from its output circuitry
when required. This type of Buffer is known as a 3-State
Buffer or more commonly a Tri-state Buffer.
A Tri-state Buffer can be thought of as an input
controlled switch with an output that can be
electronically turned ON or OFF by means of an
external Control or Enable ( EN ) signal input. This
control signal can be either a logic 0 or a logic 1 type
signal resulting in the Tri-state Buffer being in one state
allowing its output to operate normally producing the
required output or in another state were its output is
blocked or disconnected.
8/29/2017 205
Tri-state Buffer - Equivalent
8/29/2017 206
What is Parity Generator?
A Parity Generator is a Combinational Logic Circuit that
Generates the Parity bit in the Transmitter.
A Parity bit is used for the Purpose of Detecting Errors during

Transmissions of binary Information.
It is an Extra bit Included with a binary Message to Make the

Number of 1s either Odd or Even.
Two Types of Parity
In Even Parity, the added Parity bit will Make the Total
Number of 1s an Even Amount.
In Odd Parity, the added Parity bit will Make the Total
Number of 1s an Odd Amount.
Parity Generator Truth Table and Logic Diagram
3-bit Message Odd Even
X Y Z Parity Parity
Bit Bit
0 0 0 1 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 0 1
Boolean Expression K-Map Simplification
YZ
Even Pair
X 00 01 11 10
P = + + +
0 1 0 1
= + + +
1 0 1 0
= +
=X()
YZ
Odd Pair
X 00 01 11 10
P = + + +
0 1 0 1 0
= + + +
= + 1 0 1 0 1
=()
Parity Checker
A Circuit that Checks the Parity in the Receiver is called
Parity Checker.
The Parity Checker Circuit Checks for Possible Errors in the
Transmission.
Since the Information Transmitted with Even Parity, the
Received must have an even number of 1s.If it has odd
number of 1s, it indicates that there is a Error occurred during
Transmission.
The Output of the Parity Checker is denoted by PEC(Parity
Error Checker).If there is error, that is,if it has odd number of
1s, it will indicate 1.If no then PEC will indicate 0.
Even Parity Checker Truth Table
Decimal Four Bits Received Parity Error
Equivalent P A B C PEC
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 0
10 1 0 1 0 0
11 1 0 1 1 1
12 1 1 0 0 0
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 0
Logic Diagram Boolean Expression
PEC = + + + +
+ + ( + )
= + + +

=( + ) B + +
=() +
K-Map =(P)()
Simplification
BC
PA 00 01 11 10
00 0 1 0 1
01 1 0 1 0
11
0 1 0 1
10
1 0 1 0
Bi-directional Buffer
It is also possible to connect Tri-state Buffers back-to-back

to produce what is called a Bi-directional Buffer circuit with
one active-high buffer connected in parallel but in reverse
with one active-low buffer.
Here, the enable control input acts more like a directional

control signal causing the data to be both read from and
transmitted to the same data bus wire. In this type of
application a tri-state buffer with bi-directional switching
capability such as the TTL 74245 can be used.
8/29/2017 214
References
Digital Principles by
Malvino Leach
Modern Digital
Electronics by R.P. Jain
Digital Electronics,
Principles and Integrated
Circuits by Anil K. Maini
Digital Techniques by A.
Anand Kumar
8/29/2017 215
Online Tutorials
http://nptel.ac.in/video.
php?subjectId=1171060
86
http://www.electronics-
tutorials.ws/combinatio
n/comb_1.html
http://www.electronics-
tutorials.ws/combinatio
n/comb_2.html
Thank You
8/29/2017 217

Combinational Logic Design

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Combinational Logic Design

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Pune Vidyarthi Grihas

COLLEGE OF ENGINEERING, NASHIK 3.

Design of Combinational Logic

30th June 2017

A combinational circuit consists of input variables, logic gates, and output

Input Code Output

Example: BCD to Excess-3 Code Converter.

Example 1: Obtain Xs-3 Code for 428 Decimal

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Example 1: Obtain Xs-3 Code for 428 Decimal

0100 0010 1000

0111 0101 1011

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Convert following Decimal Numbers into Excess-

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Decimal Numerals Excess-3

Hand held portable electronic calculators

Input ( Std BCD code) Output ( XS3 Code)

K-maps for simplification and simplified Boolean expressions

After the manipulation of the Boolean expressions

Important: the Gray code exhibits only a single bit change

The gray code is non-weighted code.

It is not suitable for arithmetic operations.

It is a cyclic code because successive code words

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If an n bit binary number is represented by

then gray code bits are obtained from the

*where the symbol represents Exclusive-OR operation

Example 1: Convert 1011 Binary Number into Gray Code

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Example 1: Convert 1011 Binary Number into Gray Code

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Example 2: Convert 1001 Binary Number into Gray Code

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Example 2: Convert 1001 Binary Number into Gray Code

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Example 3: Convert 1111 Binary Number into Gray Code

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Example 3: Convert 1111 Binary Number into Gray Code

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Example 4: Convert 1010 Binary Number into Gray Code

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Example 4: Convert 1010 Binary Number into Gray Code

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Convert following Binary Numbers into Gray

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If an n bit gray code is represented by

*where the symbol represents Exclusive-OR operation

Example 1: Convert 1110 Gray code into Binary Number.

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Example 1: Convert 1110 Gray code into Binary Number.

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Example 2: Convert 1101 Gray code into Binary Number.