Microprocessors and Microcontrollers 11EC311

Interrupts in 8051
Introduction

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Polling vs Interrupts

Polling Driven Mechanism Interrupt Driven Mechanism

Microcontroller continuously Monitors Device notifies the Controller by

the status of device sending an Interrupt Signal

Microntroller job is to wait for the event Microcontroller keep on doing another
to occur to serve the device, it does jobs until Interrupt Occurs and then
not do anything except wait processes ISR

Polling cannot assign priority as it Interrupts can assign priority among

works in round-robin mechanism devices

Cannot Ignore(Mask) a device We can Ignore(Mask) an Interrupt

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Steps in Executing an Interrupt

When an Interrupt Occurs the Microcontroller,

Finishes the currently executing instruction
PUSHes PC(Program Counter) on Stack (Low Byte First)
Saves status of Interrupts Internally(Not on Stack)
Gets the address of ISR(Interrupt Service Routine) and
loads into PC from IVT(Interrupt Vector Table)
Continues executing ISR until RETI is Executed
POPs back PC From Stack and continues execution

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Interrupt Vector Table (IVT)

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IE(Interrupt Enable) Register

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Programming Timer Interrupts

Progarm IE Register to enable Timer Interrupt

Store the program to run after Timer Overflow occurs in
IVT Address of Timer
000B for Timer 0
001B for Timer 1

Use Ljmp or sjmp to avoid overwriting the main code in

IVT Address Space.

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Example Timer Interrupts

Generate Sqaure Wave of 10Khz in Timer 0 Mode 2

ORG 0000H ; RESET
SJMP MAIN ; AVOIDING OVERLAP ON IVT

ORG 000BH ; TIMER 0 INTERRUPT VECTOR

CPL P1.2
RETI

ORG 0030H
MAIN: MOV TMOD,#02H
MOV TH0,#9CH
MOV IE,#82H ;ENABLE TIMER0 INTERRUPT
SETB TR0
SJMP $
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Programming Serial Communication Interrupt
Program to send 'A'

ORG 0000H
LJMP START
ORG 0023H
CLR TI
RETI
ORG 100H
START:MOV TMOD, #20H
MOV TH1, #0FDH
MOV SCON, #50H
MOV IE,#90H
SETB TR1
MOV A, #'A'
MOV SBUF, A
SJMP $
END
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External Hardware Interrupts

INT0 P3.2
INT1 P3.3
Level Triggered Low-Level Signal triggers Interrupt
INT0,1 Are High By Default
Minimum Low for 4 Machine Cycles

Edge Triggered High to Low Pulse

Minimum High for 1 Machine Cycle

Minimum Low for 1 Machine Cycle

TCON Register controls the type of interrupt

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TCON Register

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Example External Interrupts

Toggle P1.0 when Interrupt INT0 occurs and P1.1 for INT1
ORG 0000H
LJMP MAIN

ORG 0003H
CPL P1.0
RETI

ORG 0013H
CPL P1.1
RETI

MAIN: MOV IE,#85H

SJMP $
END
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Interrupt Priority in 8051

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IP(Interrupt Priority) Register

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Problems for LTC Using Interrupts

Receive 10 Characters Serially and Store the data in

consecutive RAM Locations from 50H Using Interrupts

Serially Receive Data Continuously and Transmit Back the

same using Interrupts

Program to toggle P1.1 With a delay of 60ms using

Interrupts

Switch ON LED at P1.1 at INT0 and OFF at INT1 Interrupt

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References

https://www.sites.google.com/site/sripathroykoganti/my-forms

The 8051 Microcontroller, 3rd Edition, Ayala, CENGAGE

Learning
Microcontrollers[Theory and Applications], Ajay V
Deshmukh, Tata McGraw Hill
The 8051 Microcontroller and Embedded Systems,
Muhammad Ali Mazidi, Pearson Education

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 Thank You

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