Interface Circuits 1987

SLYD002
Interface
Circuits
Data Book
1987
Data Acquisition and Conversion, Display Drivers,

Line Drivers/Receivers, Peripheral Drivers/Actuators,
Memory Interface, Speech Synthesis
."
TEXAS
INSlRUMENTS
~__G_e_n_e_r_a_I_ln_f_o_r_m_a_t_io_n_____________ 1IIIII
Data Acquisition' Circuits
Display Drivers
~---
~_L_in_e_D_r_iv_e_r_s_a_n_d_R_e_c_e_iv_e_r_s_ _ _ 1I
IIiII
~_P_e_r_ip_h_e_r_a_I_D_r_iv_e_r_s_/A_c_t_u_a_t_o_rs_____
~_M_e_m__O_ry__ln_t_e_r_fa_c_e_C_ir_c_u_it_s____ .....I.
_____s_p_e_eC_h_S_y_n_t_h_e_s_is_C_ir_c_u_it_s_ _ _ .....I.
Appendix A Power Derating Curves
Ordering Instructions
Appendix B Mechanical Data
IC Sockets
Explanation of
Appendix C Logic Symbols
Interface Circuits
Data Book
~
TEXAS
INSTRUMENTS
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes in the
devices or the device specifications identified in this publication
without notice. TI advises its customers to obtain the latest version
of device specifications to verify, before placing orders, that the
information being relied upon by the customer is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with Tl's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
such testing necessary to support this warranty. Unless mandated
by government requirements, specific testing of all parameters of each
device is not necessarily performed.
In the absence of written agreement to the contrary, TI assumes no
liability for TI applications assistance, customer's product design, or
infringement of patents or copyrights of third parties by or arising from
use of semiconductor devices described herein. Nor does TI warrant
or represent that any license, either express or implied, is granted
under any patent right, copyright, or other intellectual property right
of TI covering or relating to any combination, machine, or process in
which such semiconductor devices might be or are used.
Specifications contained in this data book supersede all data for these
products published by TI in the United States before September 1986.
ISBN O-B9512-199-9
Copyright 1987, Texas Instruments Incorporated

INTRODUCTION
Texas Instruments offers a broad line of Interface and Speech Products serving analog signal
conditioning/processing and interface applications that may require higher currents and/or higher voltages than
can be achieved with conventional digital devices.
TI's Interface circuits represent technologies from classic bipolar through BIDFET, Advanced low-Power Schottky
(AlS), IMPACT"", LinCMOST., and ADVANCED LinCMOS"" processes. The AlS and IMPACT"" oxide-isolated
technologies provide the Interface family with improved speed-power characteristics. LinCMOS"" and ADVANCED
LinCMOS"" technologies feature a step-function improvement in impedance, speed, power dissipation, and
threshold stability.
TI's Interface products include such devices as data transmission circuits that tie computers and their associated
peripherals together according to a set of industry (EIA) standards that prescribe line length, data rates, and
propagation delays, among other tl1.!ngs. With the recent growth of the flat panel display market, TI's high-
voltage display drivers are providing cost-effective and reliable solutions to the AC-plasma, vacuum-fluorescent,
and electroluminescent display markets. Analog-to-digital and digital-to-analog converters are offered as peripheral
support chips in microprocessor-based systems and DSP (digital signal processing) related analog interfaces.
TI's line of high-current motor/printhead and MOSFET drivers combine logic control and high current-drive
capability on one IC.
During the last decade, TI has produced a wide range of speech-generating devices based on the technique
of pitch-excited linear predictive coding (lPC). This technique extracts data from original recorded speech to
define the control parameters for a mathematical model of the vocal tract .. The speech generated from this model
retains all the inflection and voice characteristics of the original spoken phrase while minimizing digitized data
storage requirements; and it does not exhibit the robotic quality often associated with synthesis-by-rule systems.
This data book provides information on the following types of products:

Analog Switches
High-Current Actuators and Peripheral Drivers
Switched-Capacitor General Purpose Filters
A/D and D/A Converters
High-Voltage Display Drivers
IBM 360/370 I/O Line Drivers
IEEE-488 (GPIB) Octal Bus Transceivers
RS-422-ALine Drivers
RS-422-A, RS-423-A, and RS-485 Line Receivers
lPC 10 and lPC 12 Voice Synthesis Functions on a Chip
One-Chip Speech System
Auxiliary Speech Memories
These products cover the dynamic development of linear circuits from the classical operational amplifier to the
high-performance A/D and D/A converters and speech-generating devices. New surface-mount packages (8
to 84 leads) include both ceramic and plastic chip carriers, and the small-outline (D) plastic packages that optimize
board density with minimum impact on power-dissipation capability.
The Selection Guide includes a functional description of each product, and to assist the design engineer, the
Guide is organized into sections containing information on key parameters and packaging. Ordering information
and mechanical data are in Appendix B.
IMPACT"'. linCMOS"'. and ADVANCED linCMOS'" are trademarks of Texas Instruments Incorporated.
v
During the last decade, TI has produced one of the largest IC socket families. TI's sockets include every type
and size socket in common use today and are available in a wide choice of contact materials and designs. Details
on TI's sockets are presented in Appendix B.
While this volume offers design and specification data only for Interface and Speech components, complete
technical data for any TI semiconductor product is available from your nearest TI Field Sales Office, local
authorized TI distributor, or by writing directly to:
Texas Instruments Incorporated

LITERATURE RESPONSE CENTER
P. O. Box 809066
DALLAS, TEXAS 75380-9066
We sincerely feel that you will discover the new 1987 Interface Circuits Data Book to be a significant addition
to your collection of technical literature.
vi
~__G_e_n_e_ra_I_I_n_fo_r_m__at_io_n____________
Alphanumeric Index
1IIII
Selection Guide
Data Acquisition Circuits

Cross-Reference Guide
Data Sheets
Display Drivers
--I.
Data Sheets
~_L_in_e_D_ri_v_e_rs__a_n_d__R_e_c_e_iv_e_r_s__
Data Sheets
B
____P_e_r_ip_h_e_r_a_1_D_ri_v_e_rs_'_A_c_t_ua_t_o_r_s___
Data Sheets
Memory Interface Circuits

Data Sheets
Speech. Synthesis. Circuits

a . . . . . - . . - -_ _ _

Data Sheets
Instructions
UI"UlerlllU

Ie Sockets
Explanation of
Appendix C Logic Symbols
1-1
1-2
ALPHANUMERIC INQEX
DEVICE PAGE NO, DEVICE P.AGE NO,

II c:
o
ADC0803C ....................... '.' .. . 2-9 SN55188 ............................ . 4-391 0';:;
ADC08031 ........................... . 2-9 SN55189 ............................ . 4-397 CO
ADC0804C ........................... . 2-15 SN55189A ........................... . 4-397 ...E
ADC08041 ............................ .
ADC0805C ........................... .
2-15
2-9
SN5520 .............................. .
SN5522 ............................. .
6-3
6-15 ....o
ADC08051 ............................ . 2-9 SN55234 ............................ . 6-35 .E
ADC0808 ............................ . 2-21 SN5524 ............................. . 6-25
ADC0808M ............................ . 2-29 SN55325 .. , ......................... . 6-45 ~
ADC0809 ............................ . 2-21 SN55326 ............................ . 6-55 CD
ADC0831A ........................... . 2-37 SN55327 ............................ . 6-55
c:
CD
ADC0831B ........................... . 2-37 SN55426B ........................... . 3-3 (!J
ADC0832A ........................... . 2-37 SN55427B ...................... , .... . 3-3
ADC0832B ........................... . 2-37 SN55450B ........................... . 5-81
ADC0834A ........................... . 2-45 SN55451B ........................... . 5-81
ADC0834B ........................... . 2-45 SN55452B ........................... . 5-81
ADC0838A ........................... . 2-45 SN55453B ........................... . 5-81
ADC0838B ............................ . 2-45 SN55454B .......... ',' ............... . 5-81
AM26LS31C .......................... . 4-5 SN55461 ............................ . 5-93
AM26LS31M .......................... . 4-5 SN55462 ............................ . 5-93
AM26LS32AC ......................... . 4-13 SN55463 ............................ . 5-93
AM26LS32AM ........................ . 4-13 SN55464 , .................. , ........ . 5-93
AM26LS33AC ......................... . 4-13 SN55471 ............................ . 5-109
AM26LS33AM ........................ . 4-13 SN55472 ............................ . 5-109
AM26S10C ........................... . 4-23 SN55473 ............................ . 5-109
AM26S10M .......................... . 4-23 SN55474 ........ , ................... . 5-109
AM26S11C ........................... . 4-23 SN55500E ........................... . 3-17
AM26S11M .......................... . 4-23 SN55501!= ........................... , 3-29
DS3680 ............................. . 5-5 SN55551 ............................ . 3-79
L293 ................................. . 5-9 SN55552 ............. , .. , ........... . 3-79
L293D .............................. . 5-13 SN55553 ........... , ................ . 3-95
L298 ................................ . 5-17 SN55554 ............................ . 3-95
MC3446 ............................. . 4-31 SN55ALS192 ......................... . 4-481
MC3450 ............................. . 4-35 SN65176B ........................... . 4-351
MC3452 ............................. . 4-35 SN65500E ........................... . 3-23
MC3453 ............................. . 4-43 SN65501E ........................... . 3-35
MC3486 ............................. . 4-47 SN6550fl ............................ . 3-41
MC3487 ............................. . 4-53 SN65509 ............................ . 3-47
N8T26 .............................. . 4-57 SN65512B ....... , ................... . 3-53
PBL3717A ............................ . 5-19 SN65513B ........................... . 3-59
SN55107A ... , ....................... . 4-73 SN65518 ............................ . 3-71
SN55107B ........................... . 4-73 SN65551 ............................ . 3-87
SN55108A ........................... . 4-73 SN65552 ...... , ..................... . 3-87
SN55108B ......................... , .. 4-73 SN65553 .. , ......................... . 3-101
SN55109A ........................... . 4-89 SN65554 .... , ....................... . 3-101
SN55110A ........................... . 4-89 SN655?5 ............................ . 3-109
SN55113 ............................ . 4-101 SN65556 ............................ . 3-109
SN55114 ............................ . 4-113 $N65557 , ........................... . 3-117
SN55115 ............................ . 4-121 SN65558 ... , ....... , ................ . 3-117
SN55116 ............................ . 4-131 SN65559 ............................ . 3-125
SN55117 ............................ . 4-131 SN65560 ............................ . 3-125
SN55118 ............................ . 4-131 SN65563 ......... , ... , ... , .......... . 3-133
SN55119 ..... , ...................... . 4-131 SN65564 .. , .. , ...................... . 3-133
SN55121 ............................ . 4-143 SN65567 ............................ . 3-141
SN55122 ............................ . 4-147 SIII65568 ............................ . 3-141
SN55138 ............................ . 4-181 SN7p061 ............................ . 4-63
SN55150 ................. '........... . 4-205 SN75064 ............................ . 5-23
SN55152 ............................ . 4-223 SfII75065 ............................ . 5-23
SN55154 ............................ . 4-247 SN75066 ..... , ...................... . 5-23
SN55157 ..... , ...................... . 4-255 SN75067 ............................ . 5-23
SN55158 4-261 SN75068 ........ , ................... . 5-29
SN55182 4-377 SN75069 ............................ . 5-29
SN551~3 4-385 SN75107A ........................... 4-73
, TEXAS-I!1 1-3
IN~RUMENTS
POST OFFice BOX 655012 DALLAS. TeXAS 75265
ALPHANUMERIC INDEX
II DEVICE PAGE NO. DEVICE PAGE NO.

SN75107B ........................... . 4-73 SN75372 5-33
SN75108A ........................... . 4-73 SN75374 ............................ . 5-43
SN75108B ........................... . 4-73 SN75407 ............................ . 5-53
SN75109A ........................... . 4-89 SN75408 ............................ . 5-53
SN75110A ........................... . 4-89 SN75435 ............................ . 5-57
SN75111 ............................ . 4-97 SN75436 ............................ . 5-63
SN75112 ............................ . 4-89 SN75437A ........................... . 5-63
SN75113 ............................ . 4-101 SN75438 ............................ . 5-63
SN75114 ............................ . 4-113 SN75440 ............................ . 5-69
SN75115 ............................ . 4-121 SN754410 .................... ~ ...... . 5c 153
SN75116 ............................ . 4-131 SN754411 ........................... . 5-159
SN75117 ............................ . 4-131 SN75446 ............................ . 5-75
SN75118 4-131 SN75447 ............................ . 5-75
SN75119 4-131 SN75448 ............................ . 5-75
SN75121 4-143 SN75449 5-75
SN75122 4-147 SN75451B 581
SN75123 4-153 SN75452B 581
SN75124 4-157 SN75453B 5-81
SN75125 4-163 SN75454B 581
SN75127 4-163 SN75461 5-93
SN75128 4-169 SN75462 5-93
SN75129 4-169 SN75463 5-93
SN75136 4-175 SN75465 5-101
SN75138 4-181 SN75466 5-101
SN75140 4-191 SN75467 5-101
SN75141 4-191 SN75468 5-101
SN75146 ............................ . 4-199 SN75469 5-101
SN75150 ............................ . 4-205 SN75471 5-109
SN751506 ........................... . 3-153 SN75472 5109
SN751508 ........................... . 3-161 SN75473 5109
SN75151' ............................ . 4-211 SN75476 5117
SN751516 ........................... . 3-153 SN75477 5117
SN751518 ........................... . 3-161 SN75478 5117
SN75152 ............................ . 4-223 SN75479 5117
SN75153 ............................ . 4-211 SN75491 37
SN75154 4-237 SN75491A ........................... . 37
SN75155 4-245 SN75492 ............................ . 37
SN75157 4-255 SN75492A ........................... . 3-7
SN75158 4-261 SN75494 ............................ . 315
SN75159 4-269 SN75500E ........................... . 323
SN75160B 4-281 SN75501E ........................... . 335
SN75i61B 4-289 SN75508 ............................ . 341
SN75162B 4-289 SN75509 ............................ . 347
SN75163B 4-301 SN75512B ........................... . 353
SN75164B 4-309 SN75513B ........................... . 359
SN75172 4-319 SN75514 ............................ . 365
SN75173 4-327 SN75518 ............................ . 371
SN75174 4-335 SN75551 387
SN75175 4-343 SN75552 387
SN75176B 4-351 SN75553 3101
SN75177B 4-361 SN75554 3101
SN75178B 4-361 SN75555 3109
SN75179B 4-371 SN75556 3109
SN75182 ............................ . 4-377 SN75557 3117
SN75183 ............................ . 4-385 SN75558 3117
SN75188 ............................ . 4-391 SN75559 3125
SN75189 ............................ . 4-397 SN75560 3125
SN75189A ........................... . 4-397 SN75563 3133
SN75207 ............................ . 4-405 SN75564 3133
SN75207B ........................... . 4-405 SN75567 3141
SN75208 ............................ . 4-405 SN75568 3141
SN75208B ........................... . 4-405 SN75581 3149
1-4 TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 OALLAS. TEXAS 75265
ALPHANUMERIC INDEX
DEVICE PAGE NO. DEVICE PAGE NO.

II c:
o
SN75603 ............................ . 5-123 TLC10 ............................... . 2-123 ',i:j
SN75604 ............................ . 5-123 TLC1205AI ........................... . 2-181 CO
SN75605 ............................ . 5-123 TLC1205BI ........................... . 2-181
...oE
SN75608 ............................ .
SN75609 ............................ .
5-133
5-143
TLC1225AI ........................... .
TLC1225BI ........................... .
2-181
2-181 ....
SN75ALS126 ......................... . 4-413 TLC14 ............................... . 2-103 .5
SN75ALS130 ......................... . 4-419 TLC15401 ............................ . 2-197
SN75ALS160
SN75ALS161
4-425
4-435
TLC1540M ........................... .
TLC15411 ............................ .
2-197
2-197
CO ...
Q)
SN75ALS162 4-443 TLC1541M ........................... . 2-197
c:
Q)
SN75ALS163 4-453 TLC20 ............................... . 2-123
SN75ALS164 4-461 TLC3204rn . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C!'
2-271
SN75ALS165 4-471 TLC32040M . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-271
SN75ALS192 4-481 TLC40161 ............................ . 2-205
SN75ALS193 4-489 TLC4016M ........................... . 2-205
SN75ALS194 4-501 TLC40661 ............................ . 2-213
SN75ALS195 4-511 TLC4066M ........................... . 2-213
TL0808 .............................. . 2-57 TLC532AI ............................ . 2-139
TL0809 .............................. . 2-57 TLC532AM ........................... . 2-139
TL182C .............................. . 2-65 TLC533AI ............................ . 2-139
TL1821 .............................. . 2-65 TLC533AM ........................... . 2-139
TL182M ............................. . 2-65 TLC5401 ............................. . 2-149
TL185C .............................. . 2-65 TLC540M ............................ . 2-149
TL1851 .............................. . 2-65 TLC541I ............................. . 2-149
TL185M ............................. . 2-65 TLC541M ............................ . 2-149
TL188C .............................. . 2-65 TLC5431 ............................. . 2-157
TL1881 .............................. . 2-65 TLC543M ............................ . 2-157
TL188M ............................. . 2-65 TLC5441 ............................. . 2-157
TL191C .............................. . 2-65 TLC544M ............................ . 2-157
TL1911 .............................. . 2-65 TLC5451 ............................. . 2-165
TL191M ............................. . 2-65 TLC545M ............................ . 2-165
TL376C .............................. . 5-165 TLC5461 ............................. . 2-165
TL4810B ............................. . 3-171 TLC546M ............................ . 2-165
TL4810BI ............................ . 3-171 TLC548C ............................ . 2-173
TL500C .............................. . 2-71 TLC5481 ............................. . 2-173
TL501C .............................. . 2-71 TLC548M ............................ . 2-173
TL502C ............ . 2-71 TLC549C ............................ . 2-173
TL503C .................. '............ . 2-71 TLC5491 ............................. . 2-173
TL505C .............................. . 2-85 TLC549M ............................ . 2-173
TL507C .............................. . 2-91 TLC7135 ............................. . 2-221
TL5071 ................... : .......... . 2-91 TLC7136C ........................... . 2-233
TL5812 ............................... . 3-177 TLC7524C ........................... . 2-243
TL58121 ............................. . 3-177 TLC75241 ............................ . 2-243
TL601C .............................. . 2-97 TLC7528C ........................... . 2-251
TL6011 .............................. . 2-97 TLC75281 ............................ . 2-251
TL601M ............................. . 2-97 TLC7533 ............................. . 2-263
TL604C .............................. . 2-97 TSP50C40A .......................... . 7-3
TL6041 .............................. 2-97 TSP50C50 ........................... . 7-7
TL604M ............................. . 2-97 TSP5110A ........................... . 7-11
TL607C .............................. . 2-97 TSP5220C 7-15
TL6071 .............................. . 2-97 TSP60C20 7-19
TL607M . . . . . . . . . . . . . ............ . 2-97 TSP6100 ............................. . 7-23
TL610C .............................. . 2-97 uA9636AC ........................... . 4-523
TL6101 .............................. . 2-97 uA9637AC ........................... . 4-529
TL610M ............................. . 2-97 uA9637AM ........................... . 4-529
TLC04 ............................... . 2-103 uA9638C ............................ . 4-535
TLC0820AC .......................... . 2-113 uA9639C ............................ . 4-539
TLC0820AI ........................... . 2-113 UCN4810A ........................... . 3-183
TLC0820AM .......................... . 2-113 UDN2841 ............................ . 5-169
TLC0820BC .......................... . 2-113 UDN2845 ............................ . 5-169
TLC0820BI ........................... . 2-113 ULN2001A ........................... . 5-173
TLC0820BM .......................... . 2-113 ULN2002A ............................ . 5-173
TEXAS -II} 1-5

INSTRUMENTS
POST OFFICE BOX 655012 DALLAS. TEXAS 75265
ALPHANUMERIC INDEX
III
G)
DEVICE PAGE NO.
CD
::::J ULN2003A ........................... . 5-173
...
CD ULN2004A ...........................
ULN2005A ...........................
.
.
5-173
5-173
e!.. ULN2064 ............................ . 5-181
....5"
o
ULN2065 ............................
ULN2066
. 5-181
5-181
ULN2067 5-181
3
m
ULN2068
ULN2069
5-187
5-187
r+
o ULN2074
ULN2075
5-193
5-193
::::J
1-6 TEXAS . .
INSTRUMENTS
SELECTION GUIDE
Single-Slope and Dual-Slope AID Converters

DATA ACOUISITION CIRCUITS
II t:
o
',i:i
RESOLUTION
4112 Bits
CONVERSION
SPEED (ms)
FUNCTION
Dual-Slope Analog
TYPE
TL500
PACKAGE
J
PAGE
2-71
I---
......E
CU
o
8-108its Processors TL501 2-71 t:
4 1/2 Digits 80
Digital Processors
with Seven-Segment
Outputs
TL502
N I---
2-71 C6 .
Q)
t:
Digital Processors Q)
4 1/2 Digits
with BCD Outputs
TL503 2-71 e,:,
I---
10-Bits 50 Dual-Slope Analog TL505 2-85
Pulse-Width
Modulator for
7-Bits 1 TL507 P 2-91
Single-Slope
Converter
Dual-Slope ADC
4 1/2 Digits 34 TLC7135 2-221
with BCD Output
Dual-Slope ADC
N -
3 1/2 Digits 333 TLC7136 2-233
with LCD Drivers
DIA Converters (5 to 15 Volts)

RESOLUTION FUNCTION TYPE SETTLING TIME PACKAGE PAGE
8 Bits Single Multiplying DAC TLC7524 D,N 2-243
100 ns
8 Bits Dual Multiplying DAC TLC7528 2-251
N
10 Bits Single Multiplying DAC TLC7533 150 ns I 2-263
TEXAS -I!} 1-7

INSTRUMENTS
POST OFFICE BOX 655012 ' DALLAS. TeXAS 75265
SELECTION GUIDE
~ Successive-Approximation AID Converters

~
ADDRESS
...
CI)
AND
CONVERSION SIGNAL INPUTS UNADJUSTED
ERROR RESOLUTION
POWER
at DATA I/O
SPEEDt ANALOG ANALOG (MAX)
TYPE
BITS
DISSIPATION PACKAGE PAGE
(its) (TYP)
5"
-h
FORMAT DEDICATED DIGlTAL* LSB
o 0.5 ADCOB03 2-9
~
3
D)
1
a 1.0
ADCOB04
ADCOB05
N
r---
2-9
P+ 10mW
o 100
0.75
0.75
ADCOBOB
ADCOBOBM
FN,N
FK,JD
2-21
2-29
~
B 1.25 ADCOB09 2-21
B
0.75 TLOBOB FN,N ~
0.5 mW ~
1.25 TLOB09 2-57
PARALLEL
1.0 TLCOB20A FN,N
1 1 35 mW 2-113
TLCOB20B FK,J
15 0.5 TLC532A 2-139
5 6 6mW FN,N
30 TLC533A I 2-139
1.0 TLC1205A 2-181
0.5 TLC1205B ~
10 1 a 1.0 TLC1225A
12 Plus Sign 25 mW N,J f--
2-181
0.5 TLC1225B ~
1.0 ADCOB31A 2-37
1
0.5 ADC0831B 2-37
1.0 ADCOB32A
P - 2-37
2
84
0.5 ADCOB32B
10mW
2-37
1.0 ADCOB34A 2-45
4 N
0.5 ADCOB34B ""'2-'4'5
1.0 ADCOB3BA 2-45
B
ADC083BB ""'2-'4'5
13 TLC540
FN,N - 2-149
11
SERIAL 25 a TLC541 B 2=149
22 TLC543 2-157
5 D,N c----
25 TLC544 2-157
0.5
13
25
19
TLC545 .
TLC546 6mW
FN,N - 2-165
2-165
22 TLC54B 2-173
1 D,P r---
25 TLC549 2-173
31 TLC1540 2-197
11 10 FN,N
31 1.0 TLC1541 I 2-197
52 2' # TLC32040 14 200 mW N 2-271
t Includes access time.

* Analog/digital inputs can be used either as digital logic inputs or inputs for analog to digital conversion. For example: The TLC532/3A
can have 11 analog inputs, 5 analog inputs and 6 digital inputs, or any combination in between.
Differential Input.
, The TLC32040 has two differential inputs for the 14 bit A/D and a serial port input for the 14 bit D/A. .
#The A/D conversion accuracy for this device is measured in terms of signal-to-quantization distortion and also in LSB over certain converter
ranges. Please refer to the data sheet.
1-8 TEXAS ~
INSTRUMENTS
SELECTION GUIDE
Analog Switches and Multiplexers

DATA ACQUISITION CIRCUITS
II I:
o
.~
TYPICAL VOLTAGE POWER CO

FUNCTION IMPEDANCE RANGE SUPPLIES TYPE PACKAGE PAGE
...oE
(OHM)
100
(V) (V)
TL182 2-65
....I:
TWIN SPDT
150 TL185 2-65
DUAL SPST
TWIN DUAL SPST
100
150
10 15
TL188
TL191
N
2-65
2-65
CO ...
Q)
I:
SPOT TL601 2-97 Q)
100 (.::J
DUAL SPDT TL604 2-97
-17 to +25 25 P
SPST WITH ENABLE 100 TL607 2-97
SPST WITH LOGIC INPUTS 80 TL610 2-97
QUAD BILATERAL 50 TLC4016 2-205
2 to 12 12 N,O,J
ANALOG SWITCH 30 TLC4066 2-213
Switched-Capacitor Filter ICs

POWER
FILTER
FUNCTION SUPPLIES TYPE PACKAGE PAGE
ORDER
(V)
TLC10 2-123
DUAL FILTER, GENERAL PURPOSE 2 4 to 5 FN,N
TLC20 """""2.123
TLC04 2-103
LOW PASS, BUTTERWORTH 4 2.5 to 6 D,P
TLC14 ~
TEXAS ~ 1-9
INSTRUMENTS
SELECTION GUIDE
II
C)
DISpLAY DRIVERS
Electroluminescent Display Drivers

CD
::l
...
CD DESCRIPT
DRVRS
PER PKG
INPUT
COMPATIBILITY
POWER
SUPPLY
PRODUCT FEATURES TYPE PKG PAGE
~
225-V open-drain DMOS outputs SN55551 FD 3-79
....
::l
o
Serial-in, parallel-out architecture SN65551
FN,N 3-87
50-mA current sink output capability SN75551
3 Extremely low steady state power

FD
....
Q) consumption SN55552 3-79
o Left side (SNXX551) and right side

SN65552
::l (SNXX552) drivers enhance
32 FN,N 3-87
VCC1 circuit layout SN75552
ROW (logic) Monolithic BIDFET integrated circuits
SN65557
DRIVER = 10.8 V Very low steady-state power 3-117
CMOS SN75557
to 15 V consumption
-
300-mA output capability SN65558
3-117
High-voltage open-collector N-P-N outputs SN75558
FN -
225-V totem-pole BIDFET output structures
SN65563
70-mA output capability
SN75563
3-133
34 Very low steady-state power consumption
-
3-State capabilities SN65564
3-133
Selectable Open-Source or Open-Drain output SN75564
SN55553 FD 3-95
60-V totem-pole BIDFET output structures
SN65553
Serial-in, parallel-out architecture
SN75553
FN,N 3-101
Top
15-mA sink or source output capability
SN55554 FD 3-95
(SNXX553) and bottom (SNXX554)
SN65554
drivers enhance circuit layout 3-101
SN75554
I--
90-V output voltage swing capability
SN65555
VCC1 15-mA output source and sink current
SN75555
3-109
(logic) capability
FN,N I - -
= 10.8 V High-speed serially-shifted data input
SN65556
to 15 V Totem-pole outputs 3-109
SN75556
COLUMN Latches on all driver outputs
DRIVERS
32 CMOS Energy recovery system compatible
80-V totem-pole BIDFET output structures SN65559

FN,N 3-125
Serial-in, parallel-out architecture SN75559
1 5-mA sink or source output capability

Top (SNXX559) and bottom (SNXX560) SN65560
FN,N 3-125
drivers enhance circuit layout SN75560
Energy recovery system compatible

SN65567
4.5-V to 5.5-V VCC1 operation at 5 MHz 3-141
VCC1 SN75567
Two Parallel high-speed 16-bit shift registers
(logic) I---
= 4.5 V 60-V totem-pole BIDFET output structures FN
to 5.5 V 15-mA sink or source output capability SN65568

3-141
Top (SNXX567) and bottom (SNXX568) SN75568
drivers enhance circuit layout
1-10 TEXAS ~
INSTRUMENTS
SELECTION GUIDE
LED Display Drivers

DISPLAY DRIVERS
II I:
o
'';:;
DRVRS INPUT POWER CO
DESCRIPT
PER PKG COMPATIBILITY SUPPLY
PRODUCT FEATURES TYPE PKG PAGE
...oE
SEGMENT 10 V SN75491 Of-
4 50-mA source/sink capability 3-7
DRIVERS 20 V SN75491A
- .5
10 V SN75492
DIGIT
6
MOS
20 V
250-mA sink capability
SN75492A
N
-
3-7
...
CO
Q)
DRIVERS Variable from 250-mA 'sink capability I:
SN75494 3-15 Q)
3.2 V to 8.8 V Display blanking provisions
~
Vacuum Fluorescent Display Drivers

DRVRS INPUT POWER
DESCRIPT PRODUCT FEATURES TYPE PKG PAGE
PER PKG COMPATlalLiTY SUPPLY
VCC1 (logic) Serial-in. parallel-out architecture
=5 V to 15 V 60-V totem-pole outputs SN65512B
DW.N 3-53
VCC2 (display) 25-mA current source output capability SN75512B
TTL
= 0 V to 60 V On-board latches
VCC1 (logic)
= 5 V to 15 V. All features same as SN65512B except SN65513B
12 VCC2. (display) .. Shift register reset replaces latches SN75513B
DW.N 3-59
= 0 V to 60 V
VCC1 (logic)
= 5 V to 15 V.
All features same as SN65512B except
ANODE. CMOS VCC2. VCC3 S'N75514 DW.N 3-65
GRID (display), = 0 V 125-V totem-pole output
DRIVERS to 60 V
SEGMENT VCC1 (logic)
OR DOT = 5 V to 15 V. All features same as SN65512B except SN65518
32 CMOS. TTL FN.N 3-71
MATRIX VCC2. (display) 32 bits for large format displays SN75518
FORMATS = 0 V to 60 V
VCC1 (logic) Serial-in. parallel-out architecture
10 CMOS. TTL
= 5 V to 15 V .. 60-V totem-pole outputs
UCN4810A N 3-183
VCC2 (display) 40-mA current source output capability
= 0 V to 60 V Second source to Sprague UCN-4810A
Serial-in. parallel-out architecture
10
VCC1 (logic)
60-V totem-pole outputs
40-mA current source output capability
Improved direct replacement for
TL4810B
TL4810BI
DW.N 3-171
CMOS = 5 V to 15 V
UCN4810A and TL481 OA
VCC2 (display)
= 0 V ~o 60 V 70-V output voltage swing capability
20 Drives up to 20 lines TL5812

FN.N. 3-177
Direct replacement for Sprague TL58121
UCN5812A
TEXAS ~ 1-11
INSTRUMENTS
POST OFFICE BOX 655012 ' DALLAS, TEXAS 75265
SELECTION GUIDE
II
Ci)
CD
DISPLAY DRIVERS
DC Plasma Display Drivers
.
:::J
CD
et
DESCRIPT
DRVRS
PER PKG
INPUT
COMPATIBILITY
POWER
SUPPLY

PRODUCT FEATURES
180-V open drain parallel output

TYPE PKG PAGE
.S"3
ROW 220-mA parallel output sink current
~ VCC (logic) SN751506
o DRIVERS
= 4 V to 6 V
Left side (SN751506) and right side
SN751516
3-153
(SN751516) drivers enhance circuit
OJ layout
f-
r+
0' - 120-V open collector P-N-P parallel
:::J 32 CMOS outputs FT

Two parallel high-speed 16-bit
VCC (logic)
COLUMN shift registers SN751508
= 4.5 V to 3-161
DRIVERS Latches on all driver outputs SN751518
5.5 V
Top (SN751508) and bottom
(SN751518) drivers enhance circuit
layout
VCC+ = 4.5 V
to 5.5 V Serial-in, parallel-out architecture
ANODE
DRIVERS
7 TTL VCC- = 100-V output capability SN75581 J,N 3-149
-10.8 V to Alternative driver for VF
-13.2 V
AC Plasma Display Drivers

DRVRS INPUT POWER
DESCRIPT PRODUCT FEATURES TYPE PKG PAGE
PER PKG COMPATIBILITY SUPPLY
Independent addressing of each gate
SN55426B
for serial and parallel applications
VCC1 (logic)
High input impedance 1 MO typically
= 10 V to 14 V
4 30-mA integral clamp diodes on outputs J 3-3
VCC2 (display)
Switches 70 V in 1.2 itS SN55427B
= 40 V to 90 V
3-input AND function (SN55426B)
NAND function (SN55427B)
32 (8-bits High-speed serial-in, parallel-out
SN55500E FD,JD 3-17
with 1 architecture (MHz)
VCC1 (logic)
of 4 Fast output transitions 1 50 ns) SN65500E
= 10.8 V FN,N 3-23
selectors) 25-mA output current capability SN75500E
to 13.2 V
AXIS X-axis driver (SNXX500) FD
CMOS VCC2 (display) SN55501E 3-29
DRIVERS V-axis driver (SNXX501) JD
= 0 V to 100 V
Military temperature packages available SN65501E
FN,N 3-35
(SN55500, SN55501) SN75501E
32
VCC1 (logic)
32 x 1
= 7.65 V
SN65508
to 9.35 V 3-41
SN75508
VCC2 (display) High-speed serial-in, parallel-out
=VCC1 to 90 V X-axis driver (SNCC508) FN
32 (8 bits VCC1 (logic) V-axis driver (SNXX508)
r=---
plus 2 =8 V to 11.4 V SN65509
3-47
select VCC2 (display) SN75509
bits) =VCC1 to 90 V
1-12 TEXAS -II}

INSTRUMENTS
SELECTION GUIDE
Line Drivers
LINE DRIVERS AND RECEIVERS
II c
o
'+=i
DRIVERS DEVICE PAGE co
APPLICATION OUTPUT
PER PACKAGE TYPE
PKG
NUMBER ...E
o
SN55158 JG
4-261 ....
2
SN75158
SN75159
D,JG,P
D,J,N 4-269
.5
uA9638 D,JG,P 4-535 ...
CO
Q)
AM26LS31 D,FK,J,N 4-5
c
Q)
MC3487 D,J,N 4-53
EIA STANDARD RS-422-A DIFFERENTIAL SN75151 DW,J,N C!J
4-211
SN75153 J,N
4 SN75172 J,N 4-319
SN75174 J,N 4-335
SN55ALS192 J,FK
4-481
SN75ALS192 D,J,N
SN75ALS194 D,J,N 4-501
SN75172 J,N 4-319
EIA STANDARD RS-485 DIFFERENTIAL 4
SN75174 J,N 4-335
EIA STANDARD RS-423-A SINGLE-ENDED 2 uA9636A D,JG,P 4-523
SN55150 JG,FK
4-205
2 SN75150 D,JG,P
EIA STANDARD RS-232-C SINGLE-ENDED uA9636A D,JG,P 4-523
SN55188 J,FK
4 4-391
SN75188 D,J
2 SN75123 D,J,N 4-153
IBM 360/370 SINGLE-ENDED SN75ALS126 D,J,N 4-413
4
SN75ALS130 D,J,N 4-419
SN55121 FK,J
GENERAL PURPOSE SINGLE-ENDED 2 4-143
SN75121 D,J,N
MC3453 D,J,N 4-43
SN55109A FK,J
SN75109A D,J,N
4-89
SN55110A FK,J
SN75110A D,J,N
SN75111 D,J,N 4-97
GENERAL PURPOSE DIFFERENTIAL 2 SN75112 D,J,N 4-89
SN55113 FK,J
4-101
SN75113 D,J,N
SN55114 FK,J
4-113
SN75114 D,J,N
SN55183 FK,J
4-385
SN75183 D,J,N
TEXAS 1-13
INSTRUMENTS
SELECTION GUIDE
II
C)
Line Receivers
CD
..eL
:::s
CD APPLICATION OUTPUT
RECEIVERS
PER PACKAGE
DEVICE
TYPE
SN75146
PKG
D,JG,P
PAGE
NUMBER
4-199
....5"o SN55157 JG
.3 2 SN75157
uA9637A
D,JG,P
D,JG,P
4-255
4-529
OJ uA9639 D,JG,P 4-539
~
EIA STANDARD RS-422-A DIFFERENTIAL 4 AM26LS32A D,FK,J,N 4-13
0' MC3486 D,J,N 4-47
:::s
SN75173 D,J,N 4-327
4
SN75175 D,J,N 4-343
SN75ALS193 J 4-489
SN75ALS195 J 4-511
SN75173 D,J,N 4-327
EIA STANDARD RS-485 DIFFERENTIAL 4
SN75175 D,J,N 4-343
SN75146 D,JG,P 4-199
SN75157 D,JG,P 4-255
2
uA9637A D,JG,P 4-529
uA9639 D,JG,P 4-539
AM26LS32A D,FK,J,N 4-13
EIA STANDARD RS-423-A SINGLE-ENDED
.. MC3486 D,J,N 4-47
SN75173 D,J,N 4-327
4
SN75175 D,J,N 4-343
SN75ALS193 J 4-489
SN75ALS195 J 4-511
SN55152 J,FK
2 4-223
SN75152 D,J,N
SN55154 J,FK
4-237
SN75154 D,J,N
EIA STANDARD RS-232-C SINGLE-ENDED
SN55189 J,FK
4
SN75189 D,J,N
4-397
SN55189A J,FK
SN75189A D,J,N
3 SN75124 D,J,N 4-157
SN75125
7 D,J,N 4-163
IBM 360/370 SINGLE-ENDED SN75127
SN75128
8 DW,J,N 4-169
SN75129
SN55122 FK,J
4-147
SN75122 D,J,N
GENERAL PURPOSE SINGLE-ENDED 2
SN75140 D,JG,P
4-191
SN75141 D,JG,P
1-14 TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 ' OALLAS, TEXAS 75265
SELECTION -GUIDE
Line Receivers (Continued)

II c
o
'';:;
RECEIVERS DEVICE PAGE ctJ
APPLICATION OUTPUT
PER PACKAGE TYPE
PKG
NUMBER ...E
SN55107A
SN75107A
FK,J
D,J,N
....c
o
SN55107B FK,J
SN75107B D,J,N
4-73
C6 ...
Q)
SN55108A FK,J
cQ)
SN75108A D,J,N
SN55108B FK,J ~
SN75108B D,J,N
2
SN55115 FK,J
4-121
GENERAL PURPOSE DIFFERENTIAL SN75115 D,J,N
SN55182 FK,J
4-377
SN75182 D,J,N
SN75207 D,J,N
SN75207B D,J,N
4-405
SN75208 D,J,N
SN75208B D,J,N
AM26LS33A D,FK,J,N 4-13
4 MC3450 D,J,N 4-35
MC3452 D,J,N 4-35
TEXAS . . 1-15
INSTRUMENTS
SELECTION GUIDE
II
Ci)
CD
Line Transceivers
::::J TRANSCEIVERS DEVICE PAGE
...
CD APPLICATION BUS 1/0
PER PACKAGE TYPE
PKG
NUMBER
~ EIA STANDARD RS-232-C SINGLE-ENDED 1 SN75155 D,JG,P 4-245
....
::::J
o... EIA STANDARD RS-422-A
SN651768
SN751768
D,JG,P
D,JG,P
4-351
AND DIFFERENTIAL 1 SN751778 D,JG,P

3 EIA STANDARD RS-485 SN751788 D,JG,P
4-361
....
D)
c)' 4
SN751798
MC3446
D,JG,P
D,J,N
4-371
4-31
::::J
SN75160B DW,J,N 4-281
SN75ALS160 DW,J,N 4-425
SN751618 DW,J,N 4-289
SN75ALS161 DW,J,N 4-435
EIA STANDARD 488 GPIB SINGLE-ENDED
8 SN751628 DW,N 4-289
SN75ALS162 DW,N 4-443
SN751648 DW,N 4-309
SN75ALS164 DW,N 4-461
SN75ALS165 DW,J,N 4-471
IEEE 802.3 1 BASE5 DIFFERENTIAL 1 SN75061 DW,J,N 4-63
AM26S10C D,J,N 4-23
AM26S11C D,J,N 4-23
N8T26 D,J,N 4-57
4
SN75136 D,J,N 4-175
SINGLE-ENDED
SN55138 FK,J
4-181
SN75138 D,J,N
SN751638 DW,J,N 4-301
8
SN75ALS163 DW,J,N 4-453
GENERAL PURPOSE
SN55116 FK,J
SN75116 D,J,N
SN55117 FK,JG
SN75117 D,JG,P
DIFFERENTIAL 1 4-131
SN55118 J,FK
SN75118 D,J,N
SN55119 FK,JG
SN75119 D,JG,P
1-16 TEXAS ~
INSTRUMENTS
SELECTION GUIDE
General Purpose Drivers and Actuators

PERIPHERAL DRIVERS/ACTUATORS
II :
o
'';:;
OFF- DELAY ca
SWITCHING OUTPUT DRIVERS OUTPUT E
VOLTAGE
STATE
CURRENT PER CLAMP
INPUT
FUNCTION
TIME
TYPE PKG PAGE ...
MAX (V)
VOLTAGE
MAX (V)
(rnA) PACKAGE DIODES
CAPABILITY TYP ....o
(ns)
SN55450B FK,J 5-81
.5
20 30 300 2 NO TTL AND 20
20 30 300 2 NO TTL AND 18 SN55451B FK,JG ~
I---
...
C6
Q)
20 30 300 2 NO TTL NAND 25 SN55452B FK,JG 5-81
:
20 30 300 2 NO TTL OR 18 SN55453B FK,JG ~ Q)
I--- (!)
20 30 300 2 NO TTL NOR 26 SN55454B FK,JG 5-81
20 30 300 2 NO TTL AND 18 SN75451B D,P ~
I--
20 30 300 2 NO TTL NAND 25 SN75452B D,P 5-81
'--
20 30 300 2 NO TTL OR 18 SN75453B D,P 5-81
20 30 300 2 NO TTL NOR 26 SN75454B D,P ~
24 24 500 2 YES TTL MOS DRIVER 35 SN75372 D,P 5-33
24 24 500 4 YES TTL MOS DRIVER 35 SN75374 D,N '5-33
30 35 300 2 NO TTL AND 28 SN55461 FK,JG 5-93
30 35 300 2 NO TTL NAND 38 SN55462 FK,JG ~
30 35 300 2 NO TTL OR 28 SN55463 FK,JG ~
,...---
30 35 300 2 NO TTL NOR 35 SN55464 FK,JG 5-93
30 35 300 2 NO TTL AND 28 SN75461 D,P ~
,--
30 35 300 2 NO TTL NAND 38 SN75462 D,P 5-93
30 35 300 2 NO TTL OR 28 SN75463 D,P ~
35 70 500 4 YES TTL,CMOS INVERT W ENAB 1050 SN75437A NE 5-63
35 70 600 4 YES TTL,CMOS INVERT W ENAB 750 SN75435 NE 5-57
35 70 600 4 YES CMOS,MOS,TTL BUFFER W ENAB 1450 SN75440 NE
-5-69
35 70 1000 4 YES TTL,CMOS INVERT W ENAB 1050 SN75438 NE 5-63
35 50 1250 4 YES TTL INVERT 500 SN75064 NE
-5-23
35 50 1250 4 YES MOS INVERT 500 SN75066 NE 5-23
35 50 1250 4 YES TTL,5 V MOS INVERT 500 SN75068 NE
-5-29
35 50 1500 4 NO TTL,5 V MOS INVERT 500 UDN2841 NE
-5-169
35 50 1500 4 NO TTL,5 V MOS INVERT 500 UDN2845 NE 5-169
I--
35 50 1250 4 YES TTL INVERT 500 ULN2064 NE 5-181
35 50 1250 4 YES MOS INVERT 500 ULN2066 NE 1
5- 181
I--
35 50 1250 4 YES TTL,CMOS INVERT 500 ULN2068 NE 5-187
35 50 1250 4 NO TTL,CMOS INVERT 500 ULN2074 NE 1
5-193
55 70 350 2 YES TTL,CMOS AND 300 SN75446 D,P 5-75
r---
55 70 350 2 YES TTL,CMOS NAND 300 SN75447 D,P 5-75
I--
55 70 350 2 YES TTL,CMOS OR 300 SN75448 D,P 5-75
I--
55 70 350 2 YES TTL,CMOS NOR 300 SN75449 D,P 5-75
50 70 500 2 YES TTL,CMOS NAND 500 SN75407 D,P ~
I--
50 70 500 4 YES TTL,CMOS INVERT W ENAB 1050 SN75436 NE ~
I--
50 50 350 7 YES TTL,CMOS,PMOS INVERT 250 ULN2001A D,N 5-173
50 50 350 7 YES 25 V PMOS INVERT 250 ULN2002A D,N 5- 173
1
1 _
50 50 350 7 YES TTL,CMOS INVERT 250 ULN2003A D,N 5 173
50 50 350 7 YES 15 V MOS INVERT 250 ULN2004A D,N 5- 173
1
I---
50 50 350 7 YES TTL INVERT 250 ULN2005A D,N 5-173
TEXAS 1-17
INSTRUMENlS
POST OFFICE BOX 655012 DALLAS, TEXAS 75265
SELECTION GUIDE
II PERIPHERAL DRIVERS/ACTUATORS
General Purpose Drivers and Actuators (Continuedf

OFF- DELAY
SWITCHING OUTPUT DRIVERS OUTPUT
STATE INPUT TIME
VOLTAGE CURRENT PER CLAMP FUNCTION TYPE PKG PAGE
VOLTAGE CAPABILITY TYP
MAX (V) (rnA) PACKAGE DIODES
MAX (V) (ns)
50 80 1500 4 YES TTL INVERT 500 SN75065 NE 5-23
50 80 1500 4 YES MOS INVERT 500 SN75067 NE ~
~
50 80 1500 4 YES TTL,5 V MOS INVERT 500 SN75069 NE 5-29
50 80 1500 4 YES TTL INVERT 500 ULN2065 NE 5-1i3"1
-5-181
50 80 1500 4 YES MOS INVERT 500 ULN2067 NE
50 80 1500 4 YES TTL,5 V MOS INVERT 500 ULN2069 NE ~
50 80 1500 4 NO TTL,5 V MOS INVERT 500 ULN2075 NE 5 - 193
1
55 70 300 2 NO TTL AND 28 SN55471 FK,JG 5-109

55 70 300 2 NO TTL NAND 38 SN55472 FK,JG 5 - 109
1
f---
55 70 300 2 NO TTL OR 28 SN55473 FK,JG 5-109
55 70 300 2 NO TTL NOR 35 SN55474 FK,JG 5-109
f---
55 70 300 2 NO TTL AND 28 SN75471 D,P 5-109
55 70 300 2 NO TTL NAND 38 SN75472 D,P 1
5 - 109
f---
55 70 300 2 NO TTL OR 28 SN75473 D,P 5-109
f---
55 70 300 2 YES TTL,CMOS AND 200 SN75476 D,P 5-117
55 70 300 2 YES TTL,CMOS NAND 200 SN75477 D,P 1
5 - 117
f---
55 70 300 2 YES TTL,CMOS NOR .200 SN75479 D,P ~
60 60 100 4 YES TTL,CMOS,MOS TELECOM RY DRV 1000 DS3680 D,J,N 5-5
60 100 350 7 YES TTL INVERT 250 SN75465 D,N 5 - 101
1
60 100 350 7 YES TTL,CMOS,PMOS INVERT 250 SN75466 D,N 1

5 - 101
60 100 350 7 YES 25 V PMOS INVERT 250 SN75467 D,N 1
5 - 101
60 100 350 7 YES TTL,CMOS INVERT 250 SN75468 D,N 1
5 - 101
60 100 350 7 YES 15 V MOS INVERT 250 SN75469 D,N 1
5 - 101
Motor Drivers and Power Actuators

OFF- DELAY
SWITCHING OUTPUT DRIVERS OUTPUT
STATE INPUT TIME
VOLTAGE CURRENT PER CLAMP FUNCTION TYPE PKG PAGE
VOLTAGE CAPABILITY TYP
MAX (V) (rnA) PACKAGE DIODES
MAX (V) (ns)
HALF-H DRIVER NE
18
36
18
36
500
600
3
4
NO
YES
TTL,MOS,CMOS
TTL HALF-H DRIVER 600
TL376C
L293D NE
-5-165
5-13
36 36 1000 4 NO TTL HALF-H DRIVER 600 L293 NE 5-9
36 36 1000 4 YES TTL,CMOS HALF-H DRIVER 600 SN754410 NE 5-153
36 36 1000 4 NO TTL,CMOS HALF-H DRIVER 600 SN754411 NE 5-i59
40 40 2000 1 YES TTL,CMOS HALF-H DRIVER SN75603 KC,KH,K\ 5-i23
40 40 2000 1 YES TTL,CMOS HALF-H DRIVER SN75604
-
KC,KH,K\ 5-123
40 40 2000 1 YES TTL,CMOS HALF-H DRIVER SN75605 KC,KH,K\ 5-i23
46 46 1000 1 YES TTL STEPPER DRIVER PBL3717 NE
-5-19
46 46 2000 2 NO TTL FULL-H DRIVER L298 KV 5-i7"""
60 60 2500 2 YES TTL,CMOS ACTUATOR 800 SN75608 KV 5-i33
60 60 2500 2 YES TTL,CMOS ACTUATOR 800 SN75609 KV 5-143
1-18 TEXAS
INSTRUMENTS
SELECTION GUIDE
Core-Memory Drivers
MEMORY INTERFACE CIRCUITS
II c:
o
+=i
...'oE"
MAX OUTPUT tpD DEVICE PAGE
POWER SUPPLIES OUTPUTS PKG
CURRENT TYP TYPE NUMBER
45 ns
VCC1 = 5 V
DUAL SOURCE, DUAL SINK SN55325 FK,J 6-45 .....
VCC2 = 4.5 V to 24 V c
600 rnA 40 ns VCC =5 V QUADRUPLE SINK SN55326 J 6-55
VCC1 = 5 V
co...
35 ns QUADRUPLE SOURCE SN55327 J 6-55 Q)
VCC2 = 4.5 V to 24 V cQ)
tpD - Propagation Delay Time (!)
Core-Memory Sense Amplifiers

THRESHOLD tpD DEVICE PAGE
UNITS PER PACKAGE TYPE OF OUTPUT PKG
SENSITIVITY TYP TYPE NUMBER
35 ns 1 RESISTOR SN5520 J 6-3
30 ns 1 OPEN COLL OR RESISTOR SN5522 J 6-15
15 rnV
2 RESISTOR SN5524 J 6-25
25 ns
2 RESISTOR SN55234 J 6-35
SN55236 See
7 mV 28 ns 2 TOTEM POLE WC
SN75236 Nate 1
tPD - Propagation Delay Time

NOTE 1: For additional information, contact your nearest TI field sales office.
MOS-Memory Sense Amplifiers

THRESHOLD tpD DEVICE PAGE
UNITS PER PACKAGE TYPE OF OUTPUT PKG
SENSITIVITY TYP TYPE NUMBER
SN55107A FK,J 4-73
17 ns 2 TOTEM POLE
SN75107A D,J,N 4-73
25 mV
SN55108A FK,J 4-73
19 ns 2 OPEN COLLECTOR
SN75108A D,J,N 4-73
25 ns 2 TOTEM POLE SN75207 D,J,N 4-405
10 mV
25 ns 2 OPEN COLLECTOR SN75208 D,J,N 4-405
tpD - Propagation Delay Time
TEXAS . . 1-19
INSTRUMENTS
SELECTION GUIDE
II
G)
CD
SPEECH SYNTHESIS CIRCUITS
PROCESS DESCRIPTION PACKAGE DEVICE TYPE PAGE

::s LPC-10 VOICE SYNTHESIZER, 4-BIT CONTROL BUS TSP5110A 7-11
...
CD
PMOS LPC-10 VOICE SYNTHESIZER, 8-BIT CONTROL BUS N TSP5220C 7-15
eL 128K-BIT ROM FOR TSP511 OA AND TSP5220C TSP6100 7-23
5"
.... MICROPROCESSOR, SYNTHESIZER, 64K-BIT ROM
N
TSP50C40A 7-3
256K-BIT ROM FOR TSP50C4X, TSP50C50 FAMILIES TSP60C20 7-19
o CMOS
3
Q)
LPC-12 HIGH-QUALITY VOICE SYNTHESIZER WITH 6-POLE
LOW-PASS FILTER
J,N TSP50C50 7-7
r+
o
::s
1-20 TEXAS . .
INSTRUMENTS
~_G__e_n_e_ra_I_I_n_fo_r_m_a_t_io_n____________
Alphanumeric Index
1IiII
Selection Guide

Data Sheets
Display Drivers
Data Sheets
'---_Li_n_e_._D_r_iv_e_rs_a_n_d_R_e_c_e_iv_e_r_s_ _ __
Data Sheets
Peripheral Drivers!Actuators
Cross-R~ference Guide
Data Sheets
____
M_e_m_o_rv_'_nt_e_r_fa_c_e_c_i_rc_u_i_ts____
Data Sheets
B
___s_p_e_e_C_h_S_y_n_t_h_e_s_is_C_ir_c_u_it_s____
Data Sheets
B
Ordering .Instructions
IC Sockets
Explanation of
Appendix C . Logic Symbols
2-1
II
G")
CD
.
:l
CD
~
....3'"
o
3
...o
Q)
:l
2-2
CROSSREFERENCE GUIDE
II I:
o
(manufacturers arranged alphabetically) '';:;
co
Replacements were based on similarity of electrical and mechanical characteristics as shown in currently published
E
...
data. Interchangeability in particular applications is not guaranteed. Before using a device as a substitute, the ....I:o
user should compare the specifications of the substitute device with the specifications of the original.
Texas Instruments makes no warranty as to the information furnished and buyer assumes all risk in the use
thereof. No liability is assumed for damages resulting from the use of the information contained in this list.
(ij
...
Q)
I:
Q)
TI TI ~
ANALOG PAGE
DIRECT FUNCTIONAL
DEVICES NO.
REPLACEMENT REPLACEMENT
AD570JN ADC0803CN 2-9
AD7512DIJN TL182CN 2-65
AD7512DIJQ TL1821N 2-65
AD7512DIKN TL182CN 2-65
AD7512DIKQ TL1821N 2-65
AD7512DISD TL182MJ 2-65
AD7512DITD TL182MJ 2-65
AD7533 TLC7533 2-263
AD7524JN TLC7524CN 2-243
AD7524AD TLC75241N 2-243
AD7528LN TLC7528CN 2-251
AD7528CQ TLC75281N 2-251
AD7820 TLC0820 2:113
TI TI
PAGE
BURR-BROWN DIRECT FUNCTIONAL
NO.
AD7533 TLC7533 2-263
AD7820 TLC0820 2-113
ADC82AG TLC0820BIN 2-113
ADC82AM TLC0820AIN 2-113
TI TI
DATEL PAGE
DIRECT FUNCTIONAL
NO.
ADC-830C ADC0803CN 2-9
ADC-EK12DC TLC7135CN or 2-221
TLC7136CN or 2-233
TL500/1/3CN 2-71
ADC-EK12DR TLC7135CN or 2-221
TLC7136CN or 2-233
TL500/1/3CN 2-71
TI
PAGE
FUJITSU FUNCTIONAL
NO.
REPLACEMENT
MB4053P TL5071N 2-91
TEXAS
INSTRUMENTS
l!1 2-3
. '
II
C)
CD
INTERSIL
TI TI
PAGE
::s DIRECT FUNCTIONAL
NO.
...
CD
ADC0803LCD
REPLACEMENT
ADC08031N
REPLACEMENT
2-9
e!. ADC0803LCN ADC0803CN 2-9
::s
.... ADC0804LCD ADC08041N 2-15
ADC0804LCN ADC0804CN 2-15
...
0 DGM182AK TL182MN TL604MP 2-97
3 DGM182BJ TL182CNIIN TL604CP/IP 2-97
...
D)
0'
DGM185AK
DGM185BJ
TL185MN
TL185CNIIN
TL604MP
TL604CP/IP
2-97
2-97
DGM188AK TL188MN TL610MP 2-97
::s DGM188BJ TL188CNIIN TL610CPIIP 2-97
DGM191AK TL191MN TL610MP 2-97
DGM191BJ TL191CNIIN TL610CPIIP 2-97
ICL7106CPL TLC7136CN 2-233
ICL7135CPI TLC7135CN 2-221
TI
PAGE
HARRIS DIRECT
NO.
REPLACEMENT
HF10 TLC10 2-123
TI
LINEAR PAGE
DIRECT
TECHNOLOGY NO.
REPLACEMENT
LTC1060ACN TLC10N 2-123
LTC1060CN TLC20N 2-123
TI
PAGE
MAXIM DIRECT
NO.
REPLACEMENT
MF10BN TLC10N 2-123
MF10CN TLC20N 2-123
ICL7135 TLC7135 2-221
TI
MICRO PAGE
FUNCTIONAL
NETWORKS NO.
REPLACEMENT
TLC0820ACN 2-113
MN5100/5101
TLC0820BCN 2-113
MN5120/5130/5140 TLC0820ACN 2-113
TLC0820BCN 2-113
TI
MICRO PAGE
FUNCTIONAL
POWER SYSTEMS NO.
REPLACEMENT
TLC7135CN 2-221
MP7138AN
TL500/1/3CN 2-71
MP7574AD/BD ADC08051N series 2-9
ADC0804CN or 2-15
MP7574JN/KN
ADC0805CN series 2-9
MP7581/JN/KN/ ADC0808N/ 2-21
AD/BD ADC809N 2-21
2-4 TEXAS
INSTRUMENTS
-II
POST OFFICE BOX 655012 ' DALLAS. TEXAS 75265
TI TI
II c:
0
PAGE .~
MOTOROLA DIRECT FUNCTIONAL
NO. CO
TL500CN 2-71 E
...
MC1405L TL501CN 2-71 0
TL505CN 2-85 '+-
MC14433P
TLC7135CN or 2-221 .5
TL500/1/3CN 2-71
MC14442L TLC533AMJ TLC532AMJ 2-139
CO
...CD
MC14442P TLC533AIN TLC532AIN 2-139
MC14443P TL5071N 2-91
c:
CD
MC14444P TLC5461N 2-165 e,:,
MC14447P TL5071P 2-91
MC145040FN TLC541MFN TLC540MFN 2-149
MC145040L TLC541MJ TLC540MJ 2-149
MC145040P TLC541MN TLC540MN 2-149
MC54HC4016J TLC4016MJ 2-205
MC74HC4016J TLC40161N 2-205
MC74HC4016N TLC40161N 2-205
MC54HC4066J TLC4066MJ 2-213
MC74HC4066J TLC40661N 2-213
MC74HC4066N TLC40661N 2-213
TI TI
PAGE
NATIONAL DIRECT FUNCTIONAL
NO.
ADC0803LCD ADC08031N 2-9
ADC0803LCN ADC08031N 2-9
ADC0804LCD ADC08041N 2-15
ADC0804LCN ADC0804CN 2-15
ADC0805LCN ADC08051N 2-9
ADC0808N 2-21
ADC0808CCJ
TL0808N 2-57
ADC0808N 2-21
ADC0808CCN
TL0808N 2-57
ADC0809N 2-21
ADC0809CCN
TL0809N 2-57
ADC0811BCJ TLC5411N TLC540lN 2-149
ADC0811BCN TLC541iN TLC540lN 2-149
ADC0811BCV TLC5411FN TLC540lFN 2-149
ADC0811BJ TLC541MJ TLC540MJ 2-149
ADC0811CCJ TLC541IN TLC540lN 2-149
ADC0811CCN TLC5411N TLC540lN 2-149
ADC0811CCV TLC5411FN TLC540lFN 2-149
ADC0811CJ TLC541MJ TLC540MJ 2-149
ADC0820BCD TLC0820BIN 2-113
ADC0820BCN TLC0820BCN. 2-113
ADC0820BD TLC0820BMJ 2-113
ADC0820CCD TLC0820AIN 2-113
ADC0820CCN TLC0820ACN 2-113
ADC0820CD TLC0820AMJ 2-113
ADC0829BCN TLC533AIN TLC532AIN 2-139
ADC0829CCN TLC533AIN TLC532AIN 2-139
ADC0830BCN TLC5461N 2-165
ADC0830CCN TLC5461N 2-165
ADC0831BCJ ADC0831BIP TLC5491N 2-173
ADC0831BCN ADC0831BCP TLC5491N 2-173
ADC0831CCJ ADC0831AIP TLC5491N 2-173
ADC0831CCN ADC0831ACP TLC5491N 2-173
ADC0832BCJ ADC0832Bip TLC5441N 2-157
ADC0832BCN ADC0832BCP TLC5441N 2-157
. TEXAS ~ 2-5
INSTRUMENTS
POST OFFICE BOX 655012 DALLAS. TeXAS 75265
II
C)
CD
(continued)
:::l TI TI
...
CD
NATIONAL DIRECT FUNCTIONAL
PAGE
NO.
~ REPLACEMENT REPLACEMENT
ADC0832CCJ ADC0832AIP TLC5441N 2-157
:::l
..... ADC0832CCN ADC0832ACP TLC5441N 2-157
...
0 ADC0834BCJ
ADC0834BCN
ADC0834BIN
ADC0834BCN
2-45
2-45
3
Q)
ADC0834CCJ ADC0834AIN 2-45
r+ ADC0834CCN ADC0834ACN 2-45
O ADC0838BCJ ADC0838BIN 2-45
:::l ADC0838BCN ADC0838BCN 2-45
ADC0838CCJ ADC0838AIN 2-45
ADC0838CCN ADC0838ACN 2-45
ADC1001CCJ TLC15411N 2-197
ADC1005BCJ TLC15411N 2-197
ADC1005CCJ TLC15411N 2-197
ADC1205 TLC1205 2-181
ADC1225 TLC1225 2-181
TLC7135CN or 2-221
ADC3511CCN
TL500/1 /3CN 2-71
TLC7135CN or 2-221
ADC3711CCN
TL500/1/3CN 2-71
TLC7136CN or 2-233
ADD3501CCN
TL500/1/2CN 2-71
TLC7136CN or 2~233
ADD3701CCN
TL500/1/2CN 2-71
MF10BN TLC10CN 2-123
MF10CN TLC20CN 2-123
MM54HC4016J TLC4016MJ 2-205
MM54HC4066J TLC4066MJ 2-213
MM74HC4016N/J TLC40161N 2-205
MM74HC4066N/J TLC40661N 2-213
MF450 TLC04 2-103
MF4-100 TLC14 2-103
TI
PRECISION PAGE
FUNCTIONAL
MONOLITHICS NO.
REPLACEMENT
PM7524HP TLC7524CN 2-243
PM7524FQ TLC75241N 2-243
PM7528 TLC7528 2-251
PM7533 TLC7533 2-263
TI TI
PAGE
RCA DIRECT FUNCTIONAL
NO.
CD4016AD TLC4016MJ 2-205
CD4016AE TLC40161N 2-205
CD4066AD TLC4066MJ 2-213
CD4066AE TLC40661N 2-213
CA3162E TL501 CN/TL503CN 2-71
2-6 TEXAS
INSTRUMENTS
-1!1
TI TI
PAGE
slGNETICs DIRECT FUNCTIONAL
NO.
II
ADC0803/4/5-1 LCN ADC0803/4/51N 2-9
ADC0804-1 CN ADC0804CN 2-15
NE5034F TLC532AIN 2-139
NE5036FE/N/D
NE5037F/N/D
TLC549CN/CD
TLC549CN/CD
2-173
2-173 ...
en
'5
...CJ
SILICON IX
TI
DIRECT
TI
FUNCTIONAL
PAGE C3
NO. C
2-97
0
DG182AP TL182MN TL610MP '';::;
DG182BP TL182CN/IN TL610CP/IP 2-97 'Ci)
DG185AP TL185MN Tl604MP 2-97
DG185BP TL185CN/IN TL604CP/IP 2-97
'5
C"
DG188AP TL188MN TL604MP 2-97 CJ
DG188BP TL188CN/IN TL604CP/IP 2-97 <t
DG191AP
DG191BP
TL191MN
TL191CN/IN
TL604MP
TL604CP/IP
TL503CN or
2-97
2-97
2-71
...caca
LD110CJ
TLC7135CN 2-221 C
TL501CN or 2-71
LLD111ACJ
TLC7135CN 2-221
TL500CN or 2-71
LD120CJ
TLC7135CN 2-221
TL503CN or 2-71
LD121ACJ
TLC7135CN 2-221
ADC0808N 2-21
Si520DJ
ADC0809N 2-21
Si7135CJ TLC7135CN 2-221
TI TI
PAGE
TELEDYNE DIRECT FUNCTIONAL
NO.
TSC7106CPL TLC7136CN 2-233
TSC7126 TLC7136CN 2-233
TSC7126ACPL TLC7136CN 2-233
TSC7135CPI TLC7135CN 2-221
TSC8700 ADC0808N 2-21
TSC8701 TLC15411N 2-197
TSC8703 ADC0808N 2-21
TSC8704 TLC15411N 2-197
TSC14433CN TlC7135CN 2-221
TExAs ~ 2-7
INSTRUMENTS
II
c
...
Q)
Q)
l>
B
c
(ii'
;:;.'
0'
::l
n
~'
n
c
;:;.'
en
2-8
, TEXAS.
INSTRUMENTS
ADC0803, ADC0805
8BIT ANALOGTODlGlTAL CONVERTERS
WITH DIFFERENTIAL INPUTS
D2754, NOVEMBER 1983-REVISED SEPTEMBER 1986
aBit Resolution N DUAL-IN-LiNE PACKAGE

(TOP VIEW)
Ratiometric Conversion
CS VCC (OR REF)
100 p's Conversion Time RD ClK OUT
135 ns Access Time WR

ClK IN
DBO (lSB)
DB1 ...
en
Guaranteed Monotonicity
INTR DB2 ":i
...
(,)
High Reference Ladder Impedance
a kO Typical
IN+
IN-
DB3
DB4
DATA
OUTPUTS C3
ANlG GND DB5 C
No Zero Adjust Requirement REF/2 DB6
"';:
0
OnChip Clock Generator DGTl GND DB7 (MSB)

"en
":i
Single 5Volt Power Supply C"
(,)
Operates with Microprocessor or as

StandAlone
Designed to be Interchangeable with

... CO
CO
National Semiconductor and Signetics C
ADC0803 and ADC0805
description
The ADC0803 and ADC0805 are CMOS 8-bit successive-approximation analog-to-digital converters that
use a modified potentiometric (256R) ladder. These devices are designed to operate from common
microprocessor control buses, with the three-state output latches driving the data bus. The devices can
be made to appear to the microprocessor as a memory location or an 1/0 port. Detailed information on
interfacing to most popular microprocessors is readily available from the factory.
A differential analog voltage input allows increased common-mode rejection and offset of the zero-input
analog voltage value. Although a reference input (REF/2) is available to allow 8-bit conversion over smaller
analog voltage spans or to make use of an external reference, ratio metric conversion is possible with the
REF/2 input open. Without an external reference, the conversion takes place over a span from VCC to
analog ground (ANLG GND). The devices can operate with an external clock signal or, with an additional
resistor and capacitor, can operate using an on-chip clock generator.
The ADC08031 and ADC08051 are characterized for operation from - 40C to 85 C. The ADC0803C
and ADC0805C are characterized from OC to 70 C.
PRODUCTION DATA documents contain information Copyright 1983, Texas Instruments Incorporated
current as of publication date. Products conform to
specifications per the terms of Texas Instruments TEXAS 2-9
~~~~~~~~i~a[~:I~lJ~ ~!~ti~~ti:f :I~o::~:~:t~~s~s not INSTRUMENTS
POST OFFICE BOX 655012 " DALLAS. TEXAS 75265
ADC0803. ADC0805
881T ANALOGTODlGlTAL CONVERTERS
functional block diagram (positive logic)
lEI
c
AD
CS~ ~
(21
I ~ "START"
FlIP.FlOP~r--_ _""I
Q)
r+
Q)
-~
WR.;.;;(3;.:..1____.J
a
\ - - - - - -"'
- - 1 S 10 1---..,
:t>
(") ClKA-p-R elK C1
.c
c
Ci)' ClK (191
OUT -
~~t~A
;:;.'
ci'
::::J ClKIN
(41
ClK GEN ClK B
n DGTl (101 OSC
::::;' GND
(")
C
- elL.
B
::;.' I-+~~
en VCC
(201
--
"""" f--+-
0
lADDER -- SAR
f--+-
f--+- 8BIT
--
(91
...
~
SHIFT
.......--
REF/2 AND lATCH "INTERRUPT"
DECODER f--+- REGISTER
~P
f--+-
~
f--+- ..- R
- .....
lE
f--+- R f.+-
1- ~
R
ANlG (81 1 --
GND DAC INTR
Vcc 10
(61
IN+ ~~
'~~~
.4~ ~
-.. ~
COMP
elK A ~D-~T-t1~
IN
m ~
~~ ~~
lE EN ~ DBO (lSBI
~DB1
~DB2
'--_ _ _ _--1 3STATE ~ DB3
L..-_ _ _ _ _ -I l~-r;~: ~ DB4

~DB5
~DB6
~DB7(MSBI
2-10 . TEXAS"
INSTRUMENTS
ADCOB03, ADCOB05
BBIT ANALOGTODlGlTAL CONVERTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................. 6.5 V
Input voltage range es, RD, WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 18 V
Other inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to Vee +0.3 V
Output voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to Vee + 0.3 V
Operating free-air temperature range: ADe080_1. . . . . . . . . . . . . . . . . . . . . . . . .. -40 oe to 85e ...
':;
tJ)
ADe080_e ............................. ooe to 70 0 e

Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 e to 150 e ...
(,)
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260 0 e C3
E:
NOTE 1: All voltage values are with respect to digital ground (DGTL GND) with DGTL GND and ANLG GND connected together unless o
otherwise noted. '+=i
'en
recommended operating conditions ':;
C"
(,)
MIN NOM MAX UNIT

Supply voltage, VCC
Analog input voltage (see Note 2)
4.5
-0.05
5 6.3
VCC+0.05
V
V ...ca,ca
Voltage at REF/2 (see Note 3), VREF/2,
High-level input voltage at CS, RD, or WR, VIH
0.25
2
2.5
15
V
V
e
Low-level input voltage at CS, RD, or WR, VIL 0.8 V
Analog ground voltage (see Note 4) -0.05 0 1 V
Clock input frequency (see Note 5), fclock 100 640 1460 kHz
Duty cycle for fclock above 640 kHz (see Note 5) 40% 60%
Pulse duration, clock input (high or low) for fclock below 640 kHz, tw(CLK) 275 781 ns
Pulse duration, WR input low, tw(WR) 100 ns
Operating free-air temperature, T A

I ADC080_1 -40 85
c
I ADC080_C 0 70
NOTES: 2. When the differential input voltage (VI + - VI_) is less than or equal to 0 V, the output code is 0000 0000.
3. The internal reference voltage is equal to the voltage applied to REF/2 or approximately equal to one-half of the VCC when
REF/2 is left open. The voltage at REF/2 should be one-half the full-scale differential input voltage between the analog inputs.
Thus, the differential input voltage range when REF/2 is open and VCC = 5 V is 0 V to 5 V. VREF/2 for an input voltage
range from 0.5 V to 3.5 V (full-scale differential voltage of 3 V) is 1.5 V.
4. These values are with respect to DGTL GND.
5. Total unadjusted error is guaranteed only at an fclock of 640 kHz with a duty cycle of 40% to 60% (pulse duration 625 ns
to 937 ns). For frequencies above this limit or pulse duration below 625 ns, error may increase. The duty cycle limits should
be observed for an fclock greater than 640 kHz. Below 640 kHz, this duty cycle limit can be exceeded provided tw(CLK)
remains within limits.
TEXAS ~ 2-11
INSTRUMENTS
ADC0803. ADC0805
8BIT ANALOGTODlGITAL CONVERTERS
electrical characteristics over recommended operating freeair temperature range, Vee 5 V,

fclock = 640 kHz, VREF/2 = 2.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN Typt MAX UNIT
High-level All outputs VCC = 4.75 V, IOH = -360 p.A 2.4
VOH V
output voltage DB and INTR VCC = 4.75 V, IOH = -10 p.A 4.5
c Low-level Data outputs VCC = 4.75 V, 10L = 1.6 mA 0.4
....
Q)
Q) VOL output INTR output VCC = 4.75 V, 10L = 1 mA 0.4 V
= = 360 p.A
(')
voltage
Clock positive-going
CLK OUT VCC 4.75 V, 10L 0.4
V
2.7 3.1 3.5
..c VT+
threshold voltage
c Clock negative-going
Ci)' VT- 1.5 1.8 2.1 V
~' threshold voltage
0' VT + - VT - Clock input hysteresis 0.6 1.3 2 V
:::J IIH High-level input current 0.005 1 p.A
n
::;'
IlL Low-level input current -0.005 -1 p.A
(') Vo = 0 -3
p.A
10Z Off-state output current
C Vo = 5 V 3
~'
t/) Short-current
10HS Output high Vo = 0, TA = 25C -4.5 -6 mA
output current
Short-circuit
10LS Output low Vo = 5 V, TA = 25C 9 16 mA
output current
Supply current plus VREF/2 = open, TA = 25C,
ICC 1.1 1.8 mA
reference current CS = 5 V
Input resistance to
RREF/2 See Note 6 2.5 8 kfl
reference ladder
Ci Input capacitance (control) 5 7.5 pF
Co Output capacitance (DB) 5 7.5 pF
NOTE 6: Resistance is calculated from the current drawn from a 5-volt supply applied to pins 8 and 9.
operating characteristics over recommended operating free-air temperature, Vee = 5 V,

VREF/2 = 2.5 V, fclock = 640 kHz (unless otherwise noted)
Supply-voltage-variation error VCC = 4.5 V to 5.5 V, See Note 7 1116 1/8 LSB
1/4
Total adjusted error ADC0803 With full-scale adjust, See Notes 7 and 8 LSB
1/2
Total unadjusted error ADC0805

VREF/2 = 2.5 V, See Notes 7 and 8 1/2
LSB
VREF/2 open, See Notes 7 and 8 1
DC common-mode error See Notes 7 and 8 1/16 1/8 LSB
ten Output enable time @ 25C TA = 25C, CL = 100 pF 135 200 ns
tdis Output disable time @ 25C, TA - 25C; CL - 10 pF, RL - 10 kfl 125 200 ns
td(lNTR) Delay time to reset INTR.@ 25C TA = 25C 300 450 ns
fclock = 100 kHz to 1.46 MHz, clock
tconv Conversion cycle time @ 25C 66 73
TA = 25C, See Note 9 cycles
CR Free-running conversion rate INTR connected to WR, CS at 0 V 8770 conv/s
-t All typic~1 values are at T A = 25C.

NOTES: 7. These parameters are guaranteed over the recommended analog input voitage range.
8. All errors are measured with reference to an ideal straight line through the end-points of the analog-to-digital transfer characteristic.
9. Although internal conversion is completed in 64 clock periods, a CS or WR low-to-high transition is followed by 1 to 8 clock
periods before conversion starts. After conversion is completed, part of another clock period is required before a high-to-Iow
transition of INTR completes the cycle.
2-12
TEXAS -I/}
INSTRUMENTS
ADC0803, ADC0805
8BIT ANALOGTODlGlTAL ,CONVERTERS
PARAMETER MEASUREMENT INFORMATION
\~----------- _--~--~I
1414----8 CLOCK PERIODS (MINI----~~I
I 1
....f/)
~~O_%------~~
RD .:i
! ... (,)

....... __+1_ _ _ _ _ _ _ _ _ _ _ _ _ _ __
q
..
14
~
ld(lNTRI ~I
c:
1 1 1 1 o
INTR 50'* 1 50% I '
1 I 'en
ten~ 14- -.! !4--tdis
':i
C'
~~~:UTs----------<t= .. =2~~~-_::~::C~S:::E
(,)
<C
....COCO
C
READ OPERATION TIMING DIAGRAM
WR
\~ t~
td(lNTRI~ 1
I If-- 1 TO 8 I 64%--..1
I+---tw(WRI-----+I CLOCK PERIODS ~4 CLOCK PERIODS "'1
1 1 1
1 1 I
INTR
_____
2..%
~;' ~
I
14~--------tCONV----------------~~
~5.% .
WRITE OPERATION TIMING DIAGRAM
TEXAS ~ 2-13
INSTRUMENTS
ADC0803. ADC0805
8,BIT ANALOGTODIGITAL CONVERTERS
PRINCIPLES OF OPERATION
c
....
D)
D)
l>
(")
.c
The ADC0803 and ADC0805 each contain a circuit equivalent to a 256-resistor network. Analog switches
are sequenced by successive-approximation logic to match an analog differential input voltage
(Vin + - Vin -) to a corresponding tap on the 256R network. The most significant bit (MSB) is tested
first; After eight comparisons (64 clock periods), an eight-bit binary code (1111 1111 = full scale) is
transferred to an output latch and the interrupt (INTR) output goes low. The device can be operated in
a free-running mode by connecting the INTR output to the write (WR) input and holding the conversion
statt (C5) input at a low level. To ensure start-up under all conditions. a low-level WR input is required
during the power-up cycle. Taking CS low anytime after that will interrupt a conversion in process.
c When the WR input goes low, the internal successive approximation register (SAR) and eight bit shift register
(j)'
;:;" are reset. As long as both CS and WR remain low, the analog-to-digital converter will remain in a reset
0' state. One to eight clock periods after CS or WR makes a low-to-high transition, conversion starts.
j
When the CS and WR inputs are low, the start flip-flop is set and the interrupt flip-flop and eight bit register
(")
~' are reset. The next clock pulse transfers a logic high to the output of the start flip-flop. The logic high
(") is ANDed with the next clock pulse placing a logic high on the reset input of the start flip-flop. If either
c: CS or WR have gone high, the set signal to the start flip-flop is removed causing it to be reset. A logic
;:;"
en high is placed on the 0 input of the eight-bit shift register and the conversion process is started. If the
CS and WR inputs are still low, the start flip-flop, the eight-bit shift register, and the SAR remain reset.
This action allows for wide CS and WR inputs with conversion starting from one to eight clock periods
after one of the inputs goes high.
When the logic high input has been clocked through the eight-bit shift register, completing the SAR search.
it is applied to an AND gate controlling the output latches and to the 0 input of a flip-flop. On the next
clock pulse, the digital word is transferred to the three-state output latches and the interrupt flip-flop is
set. The output of the interrupt flip-flop is inverted to provide an INTR output that is high during conversion
and low when the conversion is completed.
When a low is at both the CS and RD inputs, an output is applied to the DBO through DB7 outputs and
the interrupt flip-flop is reset. When either the CS or RD inputs return to a high state, the DBO through
DB7 outputs are disabled (returned to the high-impedance state). The interrupt flip-flop remains reset.
2-14 TEXAs
INSTRUMENTS
ADC08041, ADC0804C
8BIT ANALOGTOpIGITAL CONVERTER
. WITH DIFFERENTIAL INPUTS
02755. OCTOBER 1983-REVISED SEPTEMBER 1986
8-Bit Resolution N DUAL-IN-LiNE PACKAGE

(TOP VIEW)

100 p's Conversion Time
135 ns Access Time
No Zero Adjust Requirement
ClK IN
CS
AD
WR
Vcc (OR REF)
ClK OUT
DBD (lSB)
DB1
Ell en
.....
'S(J
On-Chip Clock Generator
INTR
IN+
IN-
DB2
DB3
DB4
DATA
OUTPUTS C3
..
Single 5-Volt Power Supply
ANlG GND DB5 c
Operates with Microprocessor or as REF/2 DB6 o
'.;:i
Stand-Alone DGTl GND DB7 (MSB) '(j)
Designed to be Interchangeable with 'S
National Semiconductor and Signetics c-
(J
ADC0804 <C
CO
description
.....
CO
C
The ADC0804 is a CMOS 8-bit successive-approximation analog-to-digital converter that uses a modified
potentiometric (256R) ladder. The ADC0804 is designed to operate from common microprocessor control
buses, with the three-state output latches driving the data bus. The ADC0804 can be made to appear
to the microprocessor as a memory location or an I/O port. Detailed information on interfacing to most
popular microprocessors is readily available from the factory.
A differential analog voltage input allows increased common-mode rejection and offset of the zero-input
analog voltage value. Although a reference input (REF/2) is available to allow 8-bit conversion over smaller
analog voltage spans or to make use of an external reference, ratiometric conversion is possible with the
REF/2 input open. Without an external reference, the conversion takes place over a span from VCC to
analog ground (AN~G GND). The ADC0804 can operate with an external clock signal or, with an additional
resistor and capacitor, can operate u~ing an on-chip clock generator.
The ADCOa041 is characterized for operation from - 40 C to 85C. The ADC0804C is characterized for
operation from pOC to 70C.
PRO DUCTIO NDATA documents contain information Copyright 1983. Texas Instruments Incorporated
specifications per the terms of Texas Instruments
~~~~~:~~i~ar::I~tJi ~~:~~~ti~r :I~o~:~:~:t::'s~s not
TEXAS "I} 2-15
INSTRUMENTS
ADC08041, ADC0804C
8BIT ANALOGTODIGITAL CONVERTER
ClKB
"INTERRupr'
FLlpFlOP
LE
~~~G .::::(B:..I--------4-:-:l:,--+
VCC . - - - -.....-110
IN+ ;..(61;....._ _. .
-+_..
IN- .:.;.(7:..)_ _
1181 OBO (lSBI

(17) OBI
(16) DB2
L..._ _ _ _ _ --I ~~~~~ (15) 083

(141
lATCH DB4
(13I
DB5
(12) DBB
1111 DB7 (MSBI
2-16
TEXAS~
INSTRUMENTS
ADC08041. ADC0804C
8BIT ANALOG,TODlGITAL CONVERTER
Input voltage range es, RD, WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 18 V
other inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to Vee + 0.3 V
Output voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to Vee + 0.3 V
Operating free-air temperature range: ADe08041 . . . . . . . . . . . . . . . . . . . . . - 40 e to 85e
II
.. en
ADe0804e . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 70 0 e
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 e to 150 0 e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260 0 e
.
'5
C3
CJ
NOTE 1: All voltage values are with respect to digital ground (DGTL GND) with DGTL GND and ANLG GND connected together (unless
:
otherwise noted).
o
';I
'C;;
recommended operating conditions '5
C-
MIN NOM MAX UNIT CJ
Supply voltage, VCC
Voltage at REF/2, VREF/2 (see Note 2)
High-level input voltage at CS, RD, or WR, VIH
Low-level input voltage at CS, RD, or WR, VIL
4.5
0.25
2
5
2.5
6.3
15
0.8
V
V
V
V
..
c:t
ca
ca
C
Analog ground voltage (see Note 3) -0.05 0 1 V
Analog input voltage (see Note 4) -0.05 VCC+0.05 V
Clock input frequency, fclock (see Note 5) 100 640 1460 kHz
Duty cycle for fclock 2: 640 kHz (see Note 5) 40 60 %
Pulse duration clock input (high or low) for fclock < 640 kHz, tw(CLKI (see Note 5) 275 781 ns
Pulse duration, WR input low (start conversion), tw(WR) 100 ns
I ADC08041 -40 85
Operating free-air temperature, T A c
I ADC0804C 0 70
NOTES: 2. The internal reference voltage is equal to the voltage applied to REF/2, or approximately equal to one-half of the VCC when
Thus, the differential input voltage when REF/2 is open and VCC = 5 V is 0 to 5 V. VREF/2 for an input voltage range from
0.5 V to 3.5 V (full-scale differential voltage of 3 V) is 1.5 V.
3. These values are with respect to DGTL GND.
4. When the differential input voltage (VIN + - Vin _) is less than or equal to 0 V, the output code is 0000 0000.
5. Total unadjusted error is guaranteed only at an fclock of 640 kHz with a duty cycle of 40% to 60% (pulse duration 625 ns
to 937 ns). For frequencies above this limit or pulse duration below 625 ns, error may increase. The duty cycle limits should
be observed for an fclock greater than 640 kHz. Below 640 kHz, this duty cycle limit can be exceeded provided tw(CLK)
remains within limits.
TEXAS ~ 2-17
INSTRUMENTS
POST OFFiCE BOX 655012 DALLAS, TEi<AS 75265
ADC08041, ADC0804C
8BIT ANALOGTODIGITAL CONVERTER
electrical characteristics over recommended operating free-air temperature range, Vee 5 V,

fclock = 640 kHz, REF/2 = 2.5 V (unless otherwise noted)
III
c
VOH
PARAMETER
High-level output voltage

All outputs
DB and INTR
Data outputs
VCC
VCC
TEST CONDITIONS
= 4.75
= 4.75
V, IOH
V, IOH
VCC - 4.75 V, 10L - 1.6 mA
= -360 p.A
= - 10 p.A
MIN
2.4
4.5
Typt MAX
0.4
UNIT
....
D)
D)
VOL Low-level output voltage INTR output VCC = 4.75 V, 10L = 1 rnA 0.4 V
CLK OUT VCC = 4.75 V, 10L = 360 p.A 0.4
:t>
(') VT+
Clock positive-going
2.7 3.1 3.5 V
threshold voltage
.c
c VT-
Clock negative-going
1.5 1.8 2.1 V
(ii' threshold voltage
;:;: VT+ -VT- Clock input hysteresis 0.6 1.3 2 V
0' IIH High-level input current 0.005 1 p.A
::::I
IlL Low-level input current -0.005 -1 p.A
n = -3
::;' 10Z Off-state output current
Va 0
p.A
(')
Vo = 5 V 3
C
;:::;.' 10HS Short-circuit output current Output high Vo = 0, TA = 25C -4.5 -6 mA
en 10LS Short-circuit output current Output low Vo =
5 V, TA =
25C 9 16 mA
REF/2 open, CS at 5 V,
ICC Supply current plus reference current 1.9 2.5 mA
TA = 25C
RREF/2 Input resistance to reference ladder See Note 6 1 1.3 kG
Ci Input capacitance (control) 5 7.5 pF
Co Output capacitance (DB) 5 7.5 pF
NOTE 6: The resistance is calculated from the current drawn from a 5-V supply applied to pins 8 and 9.
operating characteristics over recommended operating freeair temperature, Vee = 5 V,

VREF/2 "'" 2.5 V, fclock = 640 kHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TypT MAX UNIT
Supply-voltage-variation error
(See Notes 2 and 7)
VCC = 4.5 V to 5.5 V 1116 1/8 LSB
Total unadjusted error

(See Notes 7 and 8)
VREF/2 = 2.5 V 1 LSB
DC common-mode error
1116 1/8 LSB
(See Note 8)
ten Output enable time CL = 100 pF 135 200 ns
tdis Output disable time CL - 10 pF, RL - 10 kG 125 200 ns
td(lNTR) Delay time to reset INTR 300 450 ns
clock
Conversion cycle time (See Note 9) fclock = 100 kHz to 1.46 MHz 65% 72%
tconv
I cycles
I Conversion time 103 114 p's
INTR connected to WR,
CR Free-running conversion rate 8827 conv/s
CS at 0 V
t All typical values are at T A = 25C.

NOTES: 2. The internal reference voltage is equal to the voltage applied to REF/2, or approximately equal to one-half of the VCC when
Thus, the differential input voltage when REF/2 is open and VCC = 5 V is 0 to 5 V. VREF/2 for an input voltage range from
0.5 V to 3.5 V (full-scale differential voltage of 3 V) is 1.5 V.
7. These parameters are guaranteed over the recommended analog input voltage range.
8. All errors are measured with reference to an ideal straight line through the end-points of the analog-to-digital transfer characteristic.
9. Although internal conversion is completed in 64 clock periods, a CS or WR low-to-high transition is followed by 1 to 8 clock
periods before conversion starts. After conversion is completed, part of another clock period is required before a high-to-Iow
transition of iNiR completes the cycle.
2-18 TEXAS . .
INSTRUMENTS
ADC08041, ADC0804C
8BIT ANALOGTODlGITAL CONVERTER
timing diagrams
14
I
\~----------
8 CLOCK PERIODS
____~--~I
(MINI----~_I
I
II ....
(I)
! ~~O_% ____________ _J~O.

____+-_____________________________
S
...
(J
_,
C3
~
~(lNTRI ~
I I I ..
c
INTR 50% I 50% o
I '';:;
'Ci)
ten~ 14-
'S
DATA
OUTPUTS
----------------~c: 90%
<C
C"
(J
10%
....COCO
READ OPERATION TIMING DIAGRAM C
WR
~O%
td(lNTRI~
1
to.
I
14-- 1T08 64% ~
I 4 - - t (WRI-----+i CLOCK PERIODS-+I4--CLOCK PERIODS ~I
w
I 1
INTERNAL
I j
STATUS OF THE 1 50"10 50'10 I
CONVERTER I I . I 1
------------""""1"'"1------------""T"""------------- I4""-INTERNAL teonv ~ '--+-----
I I 1
INTR ___________ ~;II.roO-%----------~-------------------------------+!~~50.

. ..14--------teonv-------'-:--~"----
: I
I I
% CLOCK PERIOD-+! I+-
WRITE OPERATION TIMING DIAGRAM
TEXAS -I./} 2-19

INSTRUMENTS
ADC08041, ADC0804C
8-BIT ANALOGTODlGlTAL CONVERTER
II
c
The ADC0804 contains a circuit equivalent to a 256-resistor network. Analog switches are sequenced
by successive approximation logic to match an analog differential input voltage (VIN + - Vin -) to a
corresponding tap on the 256-resistor n,etwork. The most-significant bit (MSB) is tested first. After eight
comparisons (64 clock periods), an eight-bit binary code (1111 1111 = full scale) is transferred to an
...
Q)
Q)
output latch and the interrupt (INTR) output goes low. The device can be operated in a free-running mode
by connecting the INTR output to the write (WR) input and holding the conversion start (CS) input at a
low level. To ensure start-up under all conditions, a low-level WR input is required during the power-up
l>
(') cycle. Taking CS low anytime after that will interrupt a conversion in process.
.c
c When the WR input goes low, the ADC0804 successive approximation register (SAR) and eight-bit shift
en'
;::::;" register are reset. As long as both CS and WR remain low, the ADC0804 will remain in a reset state. One
0' to eight clock periods after CS or WR makes a low-to-high transition, conversion starts.
::s
When the CS and WR inputs are low, the start flipflop is set and the interrupt flip-flop and eight-bit register
(')
are reset. The next clock pulse transfers a logic high to the output of the start flip-flop. The logic high
::;'
(') is ANDed with the next clock pulse placing a logic high on the reset input of the start flip-flop. If either
c CS or WR have gone high, the set signal to the start flip-flop is removed causing it to be reset. A logic
;::::;"
en high is placed on the D input of the eight-bit shift register and the conversion process is started. If the
CS and WR inputs are still low, the start flip-flop, the eight-bit shift register, and the SAR remain reset.
This action allows for wide CS and WR inputs with conversion starting from one to eight clock periods
after one of the inputs goes high.
When the logic high input has been clocked through the eight-bit shift register, completing the SAR search,
it is applied to an AND gate controlling the output latches and to the D input of a flip-flop. On the next
clock pulse, the digital word is transferred to the three-state output latches and the interrupt flip-flop is
set. The output of the interrupt flip-flop is inverted to provide an INTR output that is high during conversion
and low when the conversion is completed.
When a low is at both the CS and RD inputs, an output is applied to the DBO through DB7 outputs and
the interrupt flip-flop is reset. When either the CS or RD inputs return to a high state, the DBO through
DB7 outputs are disabled (returned to the high-impedance state). The interrupt flip-flop remains reset:
2-20 TEXAS -I!}

INSTRUMENTS
post d~FlcE BOX 655612 DAlLAS. tExAS 75265
ADcoaoa, ADCOa09
CMOS ANALOGTODlGlTAL CONVERTERS
WITH aCHANNEL MULTIPLEXERS
02642, JUNE 1981-REVISEO FEBRUARY 1986
Total Unadjusted Error ... 0.75 LSB Max N

DUAL-IN-L1NE PACKAGE
for ADC0808 and 1.25 LSB Max for
(TOP VIEW)
II
ADC0809
Resolution of 8 Bits
! o~} INPUTS
100 /-Is Conversion Time INPUTS
{ 675
......(I)' ,I
~}ADDRESS
,

Guaranteed Monotonicity START
EOC
6
ALE
.
'S(J.
C3
No Missing Codes 2-5 2-1 (MSB)
OE 9 2-2
c:
Easy Interface with Microprocessors ClK 2- 3 ..;:;o
VCC 2- 4 "Ui
Latched 3-State Outputs REF+ 2- 8 (lSB) "S
GND REF- C"
Latched Addr~ss Inputs (J
Single 5-Volt Supply

2-7 '-1.._ _, j - ' 2- 6

Low Power Consumption FN PACKAGE
....ctIctI
ITOP VIEW) C
(OLt'l<tC"lN~O
National Semiconductor ADC0808, t-t-t-t-t-t-t-

:::>:::>:::>:::>:::>:::>:::>
ADC0809 Il-Il-Il-Il-Il-Il-Il-
~~~~~~~
4 3 2 1 28 27 26
INP.uT 7 5 25
description 24
The ADC0808 and ADC0809 are monolithic 23
22
CMOS devices with an 8-channel multiplexer, an
21
8-bit analog-to-digital (AID) converter, and
ClK 10 20
microprocessor-compatible control logic. The
VCC 11 19
8-channel multiplexer can be controlled by a 12 13 14 15 16 17 18
microprocessor through a 3-bit address decoder
+01'(0 I iD<t
with address load to select anyone of eight u-ZI I U-Ull
W(!)NNW-IN
single-ended analog switches connected directly a: a:-
co
to the comparator. The 8-bit AID converter uses I
N
the successive-approximation conversion
technique featuring a high-impedance threshold detector, a switched-capacitor array, a sample-and-hold,
and a successive-approximation r'egister (SAR). Detailed information on interfacing to most popular
microprocessors is readily available from the factory.
The comparison and converting methods used eliminate the possibility of missing codes, nonmonotonicity,
and the need for zero or'full-scale adjustment. Also featured are latched 3-state outputs from the SAR
and latched inputs to the multiplexer address decoder. The single 5-volt supply and low power requirements
make the ADC0808 and ADC0809 especially useful for a wide variety of applications. Ratiometric
conversion is made possible by access to the reference voltage input terminals.
The ADC0808 and ADC0809 are characterized for operation from - 40 DC to 85 DC.
PRODUCTION DATA documents contain information CoPyri9ht 1983, Texas Instruments Incorporated
currant as of publication data. Products conform to
spacifications par tha tarms of TexIs Instruments
~~~~~:~~i~8i~:1~1~ ~!:~:~ti:r fJ~o::~:~:t:r~~s not
TEXAS ~ 2-21
INSTRUMENTS
ADC0808, ADC0809
WITH 8CHANNEL MULTIPLEXERS

SAMPLEANDHOLD
II
o (12)
REF+ .,---'-------1
BINARYWEIGHTED
CAPACITORS
SWITCH
....OJOJ REF- ,.;..11_6,-)_ _ _---I
MATRIX
l>
(')
0(26) (17) 2-8 (LSB)
.c 1 (27) (14) 2- 7
c (15) 2-6
0' 2 (28 )
OUTPUT (8) 2-5 DIGITAL
;:;: ANALOG
o:l ANALOG
INPUTS
3 (1)
4 (2)
MULTI-
PLEXER
LATCHES (18) 2--4
(19) 2- 3
OUTPUTS
(20) 2-2
n
::;'
5 (3) TIMING
AND EN (21) 2- 1 (MSB)
(') 6 (4) CONTROL 1--_ _ _ _ _ _--+_ _ _('-'-7) END OF
c 7 (5) CONVERSION IEOC)
;;'
VI
CLOCK..:..(1~0,-)_-+_ _~
START CONVERSION (START) -:1-:6)'-_+-_ _ _ _- . 1
OUTPUT ENABLE (OE)_(:=.9:....)- - i - - - - - - - - - - - - - - - . . J
(25) ,--.....11.-......,
~~~:~~ : (24) ADDRESS

ADDRESS C (23) DECODER
ADDRESS LOAD (22)
ENAaLE (ALE)
MULTIPLEXER FUNCTION TABLE

INPUTS SELECTED
ADDRESS ADDRESS ANALOG
C B A STROBE CHANNEL
L L L t 0
L L H t 1
L H L t 2
L H H t 3
H L L t 4
H L H t 5
H H L t 6
H H H t 7
H = high level, L = low level

t = low-to-high transition
2-22 TEXAS ~
INSTRUMENTS
post OFFICE BOX 655012 OALlAS. TEXAS 75265
ADCOBOB. ADCOB09
CMOS ANALOGTODlGITAL CONVERTERS
WITH BCHANNEL MULTIPLEXERS
operating sequence
CLOCK
START
Ell
+"
en
CONVERSION 50%
'5
... (.)
ADDRESS LOAD
ENABLE
I
I 50% u
I I PI tw(ALC) c
~ADDRESS STABLE o
ADDRESS 50~~50_%_o~i________________~:;_______________________________ '';:;
'u)
tsu~th : '5
ANALOG INPUT --:t.
I.
: I
I
ANALOG VALUE :; x~ __________________________
C'
(.)
INPUTSTABLE 1
I
co
MULTIPLEX OUTPUT
(INTERNAL)
----~~
><I~I--------------~;'~----~
VALU~::
ANALOG )C,--------------------- +"
co
I C
ENDOF
I '\ 50% /50%
CONVERSION I--tdIEOC) -i I......--------of~------------...JI .
I tconv--------II
OUTPUT
ENABLE 50%/. ~
---------------------------fr------------~__1 t"" ten -1 I- tdis
LATCH OUTPUTS _____________________-f~-------------9~0~%t ~
HIZ STATE 10%t.,..------------tf 10%
TEXAS ~ 2-23
INSTRUMENTS
ADCDBUB, ADCDBD9
absolute maximum ratings over operating free-air temperature range (u':1less otherwise noted)
Supply voltage, Vee (see Note 1) ............................................ 6.5 V

Input voltage range: control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to 15 V
all other inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to Vee + 0.3 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40 e to 85e
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260 0 e
NOTE 1: All voltage values are with respect to network ground terminal.
recommended operating conditions

MIN NOM MAX UNIT
Supply voltage. VCC 4.5 5 6 V
Positive reference voltage. Vref + (see Note 2) Vee Vee+ O.l V
Negative reference voltage. Vref- 0 -0.1 V
Differential reference voltage. Vref + - Vref- 5 V
High-level input voltage. VIH Vee- l .5 V
Low-level input voltage. VIL 1.5 V
Start pulse duration. twlS) 200 ns
Address load control pulse duration. tw(ALC) 200 ns
Address setup time. tsu 50 ns
Address hold time. th 50 ns
Clock frequency. fclock 10 640 1280 kHz
Operating free-air temperature. T A -40 85 c
NOTE 2: Care must be taken that this rating is observed even during power-up.
2-24 TEXAS
INSTRUMENTS
-1!1
ADCOBOB, ADCOB09
CMOS ANALOGTODIGITAL CONVERTERS
electrical characteristics over recommended operating free-air temperature range, Vee = 4.75 V to
5.25 V (unless otherwise noted)
total device
VOH High-level output voltage 10 = - 36O I'A VCC-O.4 V ....en
VOL Low-level output voltage
I Data outputs
I
End of conversion
Off-state (high-impedance-state)
10=1.6mA
10 = 1.2 mA
Vo = VCC
0.45
0.45
3
V
5
C3
..
u
10Z I'A
output current Vo = 0 -3 c
II Control input current at maximum input voltage VI = 15 V 1 I'A
.~
o
IlL Low-level control input current VI = 0 -1 I'A .Ci)
ICC Supply current fclock = 640 kHz 0.3 3 mA 5
Ci Input capacitance, control inputs TA = 25C 10 15 pF C'
u
Co Output capacitance, data outputs
Resistance from pin 12 to pin 16
TA = 25C 10
1000
15 pF
kll
....asas
analog multiplexer
C
VI = 5V, fclock = 640 kHz 2
Ion Channel on-state current (see Note 3) I'A
VI = 0, fclock = 640 kHz -2
VCC = 5 V, VI = 5 V 10 200
nA
TA = 25C VI = 0 -10 -200
loff Channel off-state current
VI = 5 V 1
VCC = 5 V I'A
VI = 0 -1
tTypical values are at VCC = 5 V and T A = 25C.

NOTE 3: Channel on-state current is primarily due to the bias current into or out of the threshold detector, and it varies directly with clock
frequency.
TEXAS -1.!1 2-25

INSTRUMENTS
POST oFFiCe eox S55012 bAllA!:, TeXAs 75265
ADC0808, ADC0809
CMOSANALOG-TO-DIGITAL CONVERTERS
WITH 8-CHANNEL MULTIPLEXERS
operating characteristics, T A VREF+ 5 V, VREF- o V, fclock 640 kHz

(unless otherwise noted)
ADC0808 ADC0809
PARAMETER TEST CONDITIONS UNIT
MIN Typt MAX MIN Typt MAX
Supply voltage VCC =Vref+ = 4.75 V to 5.25 V.
O.05 0.05 %/V
c kSVS
sensitivity = -40C to 85C. See Note 4
...
Q)
Q)
Linearity error
(see Note 5)
TA
0.25 0.5 LSB
(")
Zero error (see Note 6) 0.25 0.25 LSB
.c .TA = 25C 0.25 0.5 0.5

Total unadjusted
t: TA = -40C to 85C 0.75 1.25 LSB
C;;' error (See Note 7\
TA = OC to 70C 1
;:;.'
C)" ten Output enable time CL = 50 pF. RL = 10 kfl 80 250 80 250 ns
:l tdis Output disable time CL = 10 pF. RL = 10 kfl 105 250 105 250 ns
(") tconv Conversion time See Note 8 90 100 116 90 100 116 P.s
::;' Delay time.
(")
td(EOC) end of conversion See Notes 8 and 9 0 14.5 0 14.5 p'S
t:
;:;.' output
en
tTypical values for all except supply voltage sensitivity are at VCC = 5 V. and all are at T A = 25C.
NOTES: 4. Supply voltage sensitivity relates to the ability of an analog-to-digital converter to maintain accuracy as the supply voltage
varies. The supply and Vref + are varied together and the change in accuracy is measured with respect to full-scale.
5. Linearity error is the maximum deviation from a straight line through the end points of the AID transfer characteristic.
6. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
7. Total unadjusted error is the maximum sum of linearity error. zero error. and full-scale error.
8. Refer to the operating sequence diagram.
9. For clock frequencies other than 640 kHz. td(EOC) maximum is 8 clock periods plus 2 p.s.
2-26 TEXAS ~
INSTRUMENTS
ADcoaoa, ADCOa09
CMOS ANALOGTODlGITAL CONVERTERS
WITH aCHANNEL MULTIPLEXERS
II
The ADC0808 and ADC0809 each consists of an analog signal multiplexer, an 8-bit successive-
approximation converter, and related control and output circuitry.
multiplexer
The analog multiplexer selects 1 of 8 single-ended input channels as determined by the address decoder.
...en
'S
Address load control loads the address code into the decoder on a low-to-high transition. The output latch (.)
I..
is reset by the positive-going edge of the start pulse. Sampling also starts with the positive-going edge
of the start pulse and lasts for 32 clock periods. The conversion process may be interrupted by a new
C3
C
start pulse before the end of 64 clock periods. The previous data will be lost if a new start of conversion o
occurs before the 64th clock pulse. Continuous conversion may be accomplished by connecting the End- '';:;
'Ci)
of-Conversion output to the start input. If used in this mode an external pulse should be applied after power
up to assure start up.
'S
C"
(.)
converter <2:
The CMOS threshold detector in the successive-approximation conversion system determines each bit ... CO
CO
by examining the charge on a series of binary-weighted capacitors (Figure 1). In the first phase of the o
conversion process, the analog input is sampled by closing switch Sc and all ST switches, and by
simultaneously charging all the capacitors to the input voltage.
In the next phase of the conversion process, all ST and Sc switches are opened and the threshold detector
begins identifying bits'by identifying the charge (voltage) on each capacitor relative to the reference voltage.
In the switching sequence, all eight capacitors are examined separately until all 8 bits are identified, and
then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold
detector looks at the first capacitor (weight = 128). Node 128 of this capacitor is switched to the referel1ce
voltage, and the equivalent nodes of all the other capacitors on the ladder are switched to REF -. If the
voltage at the summing node is greater than the trip-point of the threshold detector (approximately one-
half the VCC voltage), a bit is placed in the output register, and the 128-weight capacitor is switched
to REF -. If the voltage at the summing node is less than the trip point of the threshold detector, this
128-weight capacitor remains connected to REF + through the remainder of the c;apacitor-sampling (bit-
counting) process. The process is repeated for the 64-weight capacitor, the 32-weight capacitor, and so
forth down the line, until all bits are counted.
With each step of the capacitor-sampling process, the initial charge is redistributed among the capacitors.
The conversion process is successive approximation, but relies on charge redistribution rather than a
successive-approximation register (and reference DAC) to count and weigh the bits from MSB to LSB.
OUTPUT
NOo~;t~;t~:tt:;'tt:;'t~~tt:~t~~t~;'~
LATCHES
i
REF- REF- REF- REF- REF- REF- REF- REF- REF-
V;" jT iT iT jT iT jT jT 5
FIGURE 1. SIMPLIFIED MODEL OF THE SUCCESSIVE APPROXIMATION SYSTEM
TEXAS ~ 2-27
INSTRUMENTS
POST OFFICE BOX 655012 ' OALLAS. TEXAS 75265
II
c
...
Q)
Q)

(')
.c
c
iii'
;:;.'
0'
:::s
(")
:;'
(')
c
;:;.'
en
2-28
ADC0808M
CMOS ANALOGTODlGITAL CONVERTER
WITH 8CHANNEL MULTIPLEXER
D2642. NOVEMBER 1986
Total Unadjusted Error ... 0.75 LSB Max JD

DUAl-IN-LiNE PACKAGE
Resolution of 8 Bits (TOP VIEW)
100 p,s Conversion Time
Ratiometric Conversion ! o~} INPUTS
INPUTS
{ 675 ....tn
oS
No Missing Codes :e}ADDRESS ...CJ
START C3
Easy Interface with Microprocessors EOe ALE
c
Latched 3State Outputs 2- 5
OEN
2 - 1 (MSB)
2-2
o
o+:;
Latched Address Inputs elK 2- 3
2- 4
0c;;
oS
Single 5-Volt Supply Vee
REF + 2 - 8 (lSB)
C"
CJ
Low Power Consumption GND REF-
2- 6
Designed to be Interchangeable with 2-7
"""'---~- ....caca
National Semiconductor ADC0808CJ
FK PACKAGE C
(TOP VIEW)
description
CDLO<;t('l)N .... O
The ADC0808M is a monolithic CMOS device 1-1-1-1-1-1-1-
::J::J::J::J::J::J::J
with an 8-channel multiplexer, an 8-bit analog- a.. a.. a.. a.. a.. a.. a..
~~~~~~~
to-digital (AID) converter, and microprocessor-
compatible control logic. The 8-channel 4 3 1 28 27 26
~} ADDRESS
multiplexer can be controlled by a micro- INPUT 7 25
processor through a 3-bit address decoder with START 6 24
address load to select anyone of eight single- EOe 23
ended analog switches connected directly to the 2- 5 8 22 ALE
comparator. The 8-bit AID converter uses the OE 9 21 2- 1 (MSB)
successive-approximation conversion technique elK 10 20 2- 2
featuring a high-impedance threshold detector, Vee 11 19 2- 3
a switched capacitor array, a sample-ancl-hold, 12 13 14 15 1617 18
and a successive-approximation register (SAR).
I iii <;t
Detailed information on interfacing to most u. UJ I
W...JN
popular microprocessors is readily available from 0::-
ex>
the factory. I
N
The comparison and converting methods used
eliminate the possibility of missing codes,
nonmonotonicity, and the need for zero or full-scale adjustment. Also featured are latched 3-state outputs
from the SAR and latched inputs to the multiplexer address decoder. The single 5-volt supply and low
power requirements make the ADC0808M especially useful for a wide variety of applications. Ratiometric
conversion is made possible by access to the reference voltage input terminals.
The ADC0808M is characterized for operation over the full military temperature range of - 55C to 125C.
PRODUCTION DATA documents contain information Copyright 1986. Texas Instruments Incorporated
~~~~~:~~i~a{::1~7e ~!~~~~tigr f,~o::~:~:t:r~~s not
TEXAS
INSTRUMENTS
-1!1 2-29
POST OFFICE BOx 655012 DALLAS. TExAS 75265

ADC0808M
CMOS ANALOGTODIGITAL CONVERTER

SAMPLE-AND-HOLD
II
c (12)
BINARY-WEIGHTED
CAPACITORS
....OJOJ REF+--~------~
RE F- .:..(1_6.:...)---------t
SWITCH
MATRIX
l>
(") THRESHOLD
.c 0(26) DETECTOR (17) 2-8 (LSB)
c: (14) 2- 7
iii' 1 (27)
~' (15) 2-0
2 (281
0' ANALOG
OUTPUT (8) 2-5 DIGITAL
:::J 3 (1) LATCHES (18) 2-4 OUTPUTS
ANALOG MULTI-
n INPUTS (2) PLEXER (19) 2- 3
~' 4 (20) 2-2
(")
(3)
c: 5 TIMING EN (21) 2-1 (MSB)
~' AND
t/) 6 (4) (7) END OF
CONTROL 1------------+------- CONVERSION (EOC)
7 (5)
CLOCK ..:.(1;.,:0.:..)- - f - - - - - - '
START CONVERSION (START) ....;(....;6)~_-+-_ _ _ _ _--'

OUTPUTENABLE(OE)-(.:...9.:..)--~-------------------,
(25)
AODRESS A (24)
ADDRESS B ADDRESS
ADDRESS LOAD (22)
ENABLE (ALE)
INPUTS SELECTED
L L L i 0
L L H i 1
L H L i 2
L H H i 3
H L L t 4
H L H t 5
!-' H L t 6
H H H t 7
H = high level, L = low level

2-30 TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 ' DALLAS. TEXAS 7~265
ADC0808M
operating sequence
CLOCK
fI
START
CONVERSION
ADDRESS LOAD
50%
-...
'5
r.J)
CJ
ENABLE
I I P, tW(ALC)
U
t-T--+-ADDRESS STABLE c
o
ADDRESS
50~50%\ :: '';:
tsu~th : 'en
'5
ANALOG INPUT ) \ ANALOG VALUE ~: X C"
I INPUTSTABLE----------~pl ~--------------------- CJ
I

-
I
___-+..J><;:: VALU~:
~---------------
MULTIPLEX OUTPUT
ANALOG co
(INTERNAL)
CO
I C
ENDOF
CONVERSION
! \50% 150%
I--td(EOC) --1 '----------..f1-----------~ I
I tconv 1
OUTPUT
ENABLE . . . . ________________________~~-----------5--J%t ~
-t I"'" ten -1 I- tdis
LATCH OUTPUTS 90%[
----------------H-I-.Z-S-T-A-TE----f~-------------1-0~%~~-------~~10% ~..
TEXAS 2-31
INSTRUMENTS
POST OFFICE BOX 655012 .. DALLAS. TEXAS 75265
ADC0808M
absolute maximum ratings over operating freeair temperature range (unless otherwise noted)
II
c
Input voltage range: control inputs ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 to 15 V
all other inputs ........................... " -0.3 V to Vee + 0.3 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55C to 125C
Storage temperature range ......................................... - 65C to 150C
....OJ
0).
Case temperature for 60 seconds: FK package .................................. , 260C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JD package ........... 300C
:t>
n NOTE 1: All voltage values are with respect to network ground terminal.
..c
c
iii" recommended operating conditions
;:;'"
c"
~
MIN NOM MAX UNIT
Supply voltage, VCC 4.5. 5 6 V
(") Positive reference voltage, Vref + (see Note 2) VCC Vee+ O. 1 V
::;" Negative reference voltage, Vref- 0 -0.1 V
n
c Differe'ltial reference voltage, Vref + - Vref- 5 V
;:;'"
en High-level input voltage, VIH Vee- 1. 5 V
Low-level input voltage, VIL 1.5 V
Start pulse duration, tw(S) 200 ns
Address load control pulse duration, tw{ALCJ 200 ns
Address setup time, tsu 50 ns
Address hold time, th 50 ns
Clock frequency, fclock 10 640 1280 kHz
Operating free-air temperature, T A -55 125 c
NOTE 2: Care must be taken that this rating is observed even during power-up.
2-32 TEXAS ~
INSTRUMENTS
ADC0808M
CMOS ANALOG-TO-DlGlTAL CONVERTER
WITH 8-CHANNEL MULTIPLEXER
electrical characteristics over recommended operating free-air temperature range, Vee 4.5 V to
5.5 V (unless otherwise noted)
total device
VOH
PARAMETER
I Data outputs
TEST CONDITIONS
10 = -360 p.A
MIN
VCC-O.4
TVpt MAX UNIT
V
II
... en
10 = 1.6mA 0.45 S
VOL
loz
Low-level output voltage
LEnd of conversion
Off-state (high-impedance-state)
10 = 1.2 mA
Va = VCC
0.45
3
V
p.A (J
..
(J
output current Va = 0 -3
Control input current at maximum input voltage V, = 15 V 1 p.A C
" .,tj
o
',L Low-level control input current V, = 0 -1 p.A
.Ci)
ICC Supply current fclock = 640 kHz 0.3 3 mA
Ci Input capacitance, control inputs TA = 25C 10 pF S
I:::T
Co Output capacitance, data outputs TA = 25C 10 pF (J
Resistance from pin 12 to pin 16 1000 kG
analog multiplexer
... CO
CO
Typt
C
PARAMETER TEST CONDITIONS MIN MAX UNIT
V,= VCC, fclock = 640 kHz 2
Ion Channel on-state current (see Note 3) p.A
V,= 0, fclock =
640 kHz -2
VCC = 5 V, V, = 5 V 10 200
nA
TA = 25C V, = 0 -10 -200
V, = 5 V 1
VCC = 5 V p.A.
V, = 0 -1
t Typical values are at VCC = 5 V and T A = 25C.

frequency.
TEXAS ~ 2-33
INSTRUMENTS
ADC0808M
operating characteristics, TA = 25e, Vee VREF+ 5 V, VREF- o V, fclock = 640 kHz

II
c
kSVS
PARAMETER
Supply voltage sensitivity
Linearity error (see Note 5)

VCC
TA =
=
TEST CONDITIONS
Vref + = 4.5 V to 5.5 V,
-55C to 125C, See Note 4
MIN Typt
0.05
0.25
MAX UNIT
%IV
LSB
...
Q)
Q)
Zero error (see Note 6)
TA = 25C
0.25
0.25 0.5
LSB

n
Total unadjusted error (see Note 7)
TA = -55C to 125C 0.75
LSB
.c tpZL Output enable time to low level See Figure 1 90 250 ns

c: tpZH Output enable time to high level See Figure 1 -150 360 ns
;;;' tdis Output disable time See Figure 1 200 405 ns
;:i.'
0' tconv Conversion time See Note 8 and 9 and Figure 1 90 100 116 P.s
::s td(EOC) Delay til\le, end of conversion output See Notes 8 and 10 and Figure 1 0 14.5 p's
n
=i' t Typical values for all except supply voltage sensitivity are at V CC = 5 V, and all are at T A = 25C.
n NOTES: 4. Supply voltage sensitivity relates to the ability of an analog-to-digital converter to maintain accuracy as the supply voltage
c: varies. The supply and Vref+ are varied together and the change in accuracy is measured with respect to full-scale.
;:i.' 5. Linearity error is the maximum deviation from a straight line through the end points of the AID transfer characteristic.
en 6. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
7. Total unadjusted error is the maximum sum of linearity error, zero error, and full-scale error.
9. For clock frequencies other than 640 kHz, tconv is 57 clock cycles minimum and 74 clock cycles maximum.
10. For clock frequencies other than 640 kHz, td(EOC) maximum is 8 clock cycles plus 2 p's.
Vee
TEST
POINT 5 kf!
OUTPUT--~----------~'---~"----~
100 pF 11.7 kf!
FIGURE 1. TEST CIRCUIT
2-34 TEXAS ~
INSTRUMENTS
ADC0808M
The ADC0808M consists of an analog signal multiplexer, an 8-bit successive-approximation converter,

and related control and output circuitry.
multiplexer
....tI)
The analog multiplexer selects 1 of 8 single-ended input channels as determined by the address decoder. ':;
Address load control loads the address code into the decoder on a low-to-high transition. The output latch ...CJ
is reset by the positive-going edge of the start pulse. Sampling also starts with the positive-going edge U
of the start pulse and lasts for 32 clock periods. The conversion process may be interrupted by a new c
'';:
occurs before the 64th clock pulse. Continuous conversion may be accomplished by connecting the End- 'Ci)
of-Conversion output to the start input. If used in this mode an external pulse should be applied after power ':;
up to assure start up. C"
CJ
converter
The CMOS threshold detector in the successive7approximation conversion system determines each bit
....COCO
by examining the charge on a series of binary-weighted capacitors (Figure 2). In the first phase of the C
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference voltage.
detector looks at the first capacitor (weight = 128). Node 128 of this capacitor is switched to the reference
128-weight capacitor remains connected to REF + through the remainder of the capacitor-sampling (bit-
The conversion procesE is successive approximation, but relies on charge redistribution rather than a
successive-approximation register (and reference DAC) to count and weigh the bits from MSB to LS~.
Sc
OUTPUT
NOO:~t't:;tt:~tt:;'tt:;'tt:~tt:~tt:~t~;'[
LATCHES
REF- REF- REF- REF- REF- REF- REF- REF- REF-
~i f f j f i j f i
FIGURE 2. SIMPLIFIED MODEL OF THE SUCCESSIVEAPPROXIMATION SYSTEM
TEXAS . . 2-35
INSTRUMENTS
II
o
...mm

(")
.c
c
;"
;::;."
0"
:s
(")
:::;"
(")
c
;:;'"
en
2-36
ADC0831A. ADC0832A. ADC0831B. ADC0832B
AID PERIPHERALS WITH SERIAL CONTROL
02795, AUGUST 1985 -REVISED JUNE 1986
8-Bit Resolution ADC0831 ... P DUAL-IN-LiNE PACKAGE

(TOP VIEW)
Easy Interface to Microprocessors or
Stand-Aione Operation
C S [ i l l B VCC
IN + 2 7 ClK
Operates Ratiometrically or with 5-V
IN- 3 6 DO
Reference
GNO 4 5 REF ..,en
Single Channel or Multiplexed Twin "5
(.)
Channels with Single-Ended or Differential ADCOB32 .. P DUAL-IN-LiNE PACKAGE ~
Input Options (TOP VIEW) C3

Input Range 0 to 5 V with Single 5-V c
Supply CS [ i l l B VCC/REF o
"';:
CHO 2 7 ClK
Inputs and, Outputs are Compatible with CH1 3 6 DO
"iii
TTL and MOS GNO 4 5 01
"5
C"
(.)
Conversion Time of 32 JlS at c:z:
ClK - 250 kHz
..,ca
Designed to be, Interchangeable with ca
National Semiconductor ADC0831 and C
ADC0832
TOTAL UNADJUSTED ERROR
DEVICE
A-SUFFIX I 8-SUFFIX
ADCOB31 1 LSB Y. LSB
ADC0832 1 LSB . t Y. LSB
description
These devices are 8-bit successive-approximation analog-to-digital converters_ The ADC0831A and
ADC08318 have single' input channels; the ADC0832A and ADC08328 have multiplexed twin input
channels. The serial output is configured to interface with standard shift registers or microprocessors.
Detailed information on interfacing to most popular microprocessors is readily available from the factory.
The, ADC0832 multiplexer is software configured for single-ended or differential inputs. The differential
analog voltage input allows for common-mode rejection or offset of the analog zero input voltage value.
In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.
The operation of the ADC0831 and ADC0832 devices is very similar to the more complex ADC0834 and
ADC0838 devices. Ratiometric conversion can be attained by setting the REF input equal to the maximum
analog input signal value. which gives the highest possible conversion resolution. Typically. REF is set
equal to VCC (done internally on the ADC0832). For more detail on the operation of the ADC0831 and
ADC0832 devices. refer to the ADC0834/ADC0838 data sheet.
The ADC0831 AI, ADC0831 BI. ADC0832AI. and ADC0832BI are characterized for operation from - 40C
to 85 C. The ADC0831 AC. ADC0831 BC. ADC0832AC. and ADC0832BC are characterized for operation
from OC to 70C.
current as of publication date. Products conform
to specifications per the terms of Taxas Instruments
standard warranty. Production processing does not
TEXAS . . 2-37
necessarily include testing of all parameters. INSTRUMENTS
ADC0831A, ADC0832~ ADC0831a ADC0832B
functional block diagram
lEI
START
FLIP-FLOP.
CLK----e-------------------------------~
cs~~+_------------------------__d >-------------.(>CLK
SHIFT REGISTER
c i - - - Di-i-~-t--+-----I 0
ODD/EVEN
....
Q)
Q) : (ADC0832I
L_<:N~Y~_J

n
.c
c:
(ii' TO INTERNAL
;::;.' CIRCUITS
0' SINGLE/DIFFERENTIAL
::l
n
::;' CHO/IN + - - - - - f
n ANALOG COMPARATOR
c: CH1/IN - ---------I
MUX
;::;.'
en EN
CS CS
EN
LADDER DO
REF----f AND
DECODER
2~38
TEXAS -II}
INSTRUMENTS
ADC0831A, ADC0832A, ADC08318, ADC08328
sequence of operation
ADC0831
elK
1 I I
4
I
10
Ell....en
'S
t su --'
1
If- I
~
...
I
....;...------teonv--------tt_I:
I
r- ...CJ
csl ::, I~ C3
c:
I
MUX
SETTLING-+!
I
~,
1f14-----MsB-FIRsTDATA------.t_I' I
I o
'';'
TIME '"
O~:~;O)~~ ~IM~SB~I~~~~~~~~--~~~----:~;~lS-B----~~I
'Ci)
__ ___
H_I-Z___ 'S
4 3 0 C"
CJ
~
ADC0832
....coco
--fl-JlJl--f1-InruVUlflJUlfl-JlJUl
1 2 3 4 5 6 10 11 12 13 14 18 19 20 21
C
C"
~I ~ t I_ teonv -I I
-.. ,.- su I I I
r-
es 1 II
I I
I I
If
I
I
I i,
I
I I
START +SIGN
I I I
BIT SGl ODD I I I -I
~~~~JII~~
~ I DIFEVENII
I6---MSB-FIRST DATA~
MUX I 1- -l4----lSB-FIRST DATA----..j
-+f if-
1.,1 I: I I CI IM.,I .-
SETTLING I
O~:~;O) _TIM----.' i <so

HI-Z
6 0 6
ADC0832 MUX ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS CHANNEL NUMBER

SGL/DIF ODD/EVEN 0 1
L L + -
L H - +
H L +
.H H +
H = high level, L = low level, - or + = polarity of selected input pin
TEXAS
INSTRUMENTS
"'J1 2-39
POST OFFICE BOX 655012 DALLAS. TEX~S 75265
ADC0831A, ADC0832A, ADC08318, ADC08328
absolute maximum ratings over recommended operating free-air temperature range (unless otherwise
noted)
II
c
Supply voltage, Vee (see Note 1) .............................................. 6.5 V
Input voltage range: Logic ................ .'.......................... - 0.3 V to 15 V
Analog ..................................... -0.3 V to Vee+0.3 V
Input current ............................................................. 5 mA
...
D)
D)
Total input current for package .............................................. 20 mA
Operating free-air temperature range: AI and BI suffixes . . . . . . . . . . . . . . . .. . .. - 40C to 85 e

(')
Ae and Be suffixes ...................... ooe to 70C
.c Storage temperature range .......................................... - 65C to 150C
c Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ....................... 260 e
Ci)'
;:;: NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.
0' recommended operating conditions
::l
(") MIN NOM MAX UNIT
:::;' VCC Supply voltage 4.5 5 6.3 V
(')
High-level input voltage 2 V
c VIH
;:;: VIL Low-level input voltage 0.8 V
en fclock Clock frequency 10 400 kHz
Clock duty cycle (see Note 2) 40 60 %
twH(CS) Pulse duration, CS high 220 ns
tsu Setup time, CS low or AOC0832 data valid before clockt 350 ns
th Hold time, AOC0832 data valid after clockt 90 ns
Operating free-air temperature

I AI and BI suffixes -40 85
C
TA
I AC and BC suffixes 0 70
NOTE 2: The clock duty cycle range ensures proper operation at all clock frequencies. If a clock frequency is used outside the recommended
duty cycle range, the minimum pulse duration (high or low) is 1 p.s.
electrical characteristics over recommended range of operating free-air temperature,

Vee = 5 V, fclock = 250 kHz (unless otherwise noted)
digital section
AI, BI SUFFIX AC, BC SUFFIX
PARAMETER TEST CONDITIONSt UNIT
MIN TVP* MAX MIN TVP* MAX
High-level output VCC = 4.75 V, 10H = -:360 p.A 2.4 2.8
VOH V
voltage VCC = 4.75 V, 10H =, -10 p.A 4.5 4.6
Low-level output
VOL VCC = 4.75 V, 10L = 1.6 mA 0.4 0.34 V
voltage
High-level input
IIH VIH = 5 V 0.005 1 0.005 1 p.A
current
Low-level input
IlL VIL = 0 -0.005 -1 -0.005 -1 p.A
current
High-level output
10H VOH = 0, TA = 25C -6.5 -14 -6.5 -14 mA
(source) current
Low-level output
10L VOL = VCC, TA = 25C 8 16 8 16 mA
(sink) current
High-impedance- 0.01
Va = 5 V, TA = 25C 0.01 3 3
10Z state output p.A
current (DO) Va = 0, TA = 25C -0.01 -3 -0.01 -3
Ci Input capacitance 5 5 pF
eo Output capacitance 5 5 pF
t All parameters are measured under open-loop conditions with zero common-mode input voltage.
* All typical values are at Vee = 5 V, T A = 25e.
2-40 TEXAS -Ij}

INSTRUMENTS
ADC0831A, ADC0832A, ADC0831B, ADC0832B
electrical characteristics over recommended range of operating free-air temperature, Vee 5 V,

fclock = 250 kHz (unless otherwise noted)
analog and converter section
PARAMETER TEST CONDITIONS t MIN TYP* MAX UNIT
-0.05
....en
.
VICR Common-mode input voltage range See Note 3 to V
':i
VCC+ 0.05 (,)
On-channel VI - 5 V at on-channel, 1
Standby input (3
Off-channel VI = 0 at off-channel -1
II(stdby) current /lA
On-channel VI = 0 at on-channel, -1 C
(see Note 4) o
Off-channel VI = 5 V at off-channel 1 '';::;
q(REF) Input resistance to reference ladder 1.3 2.4 5.9 HI 'en
':i
total device C"
(,)
I <C
PARAMETER TEST CONDITIONS t I MIN TYP* MAX UNIT
I ICC Supply current II ADC0831 I 1 2.5

rnA
....COCO
ADC0832 I 3 5.2
C
* All typical values are at VCC = 5 V, T A = 25C.
NOTES: 3. If channel IN - is more positive than channel IN + , the digital output code will be 0000 0000. Connected to each analog input
are two on-chip diodes that will conduct forward current for analog input voltages one diode drop above VCC. Care must
be taken during testing at low VCC levels (4.5 V) because high-level analog input voltage (5 V) can, especially at high
temperatures, cause this input diode to conduct and cause errors for analog inputs that are near full-scale. As long as the
analog voltage does not exceed the supply voltage by more than 50 mY, the output code will be correct. To achieve an absolute
o V to 5 V input voltage range requires a minimum VCC of 4.95 volts for all variations of temperature and load.
4. Standby input currents are currents going into or out of the on or off channels when the AID converter is not performing
conversion and the clock is in a high or low steady-state condition.
operating characteristics Vee = REF = 5 V, fclock = 250 kHz, tr tf

BI, BC SUFFIX AI, AC SUFFIX
PARAMETER TEST CONDITIONst UNIT
MIN TYP MAX MIN TYP MAX
Supply-voltage variation error VCC = 4.75 V to 5.25 V 1/16 1/4 1/16 1/4 LSB
Total unadjusted error Vref = 5 V,
1/2 1 LSB
(see Note 5) TA = MIN to MAX
Common-mode error Differential mode 1/16 1/4 1/16 1/4 LSB
MSB-first
Propagation delay time, 650 1500 650 1500
data
tpd output data after CLKt CL = 100pF ns
LSB-first
(see Note 6) 250 600 250 600
data
CC= 10pF,
125 250 125 250
Output disable time, RL = 10 kO
tdis ns
DO after CSt CL = 100 pF,
500
500
RL = 2 kO
t Conversion time (multiplexer clock
8 8
conv addressing time not included) periods
t All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX,
use the appropriate value specified under recommended operating conditions.
NOTES: 5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
6. The most significant-bit-first data is output directly from the comparator and therefore requires additional delay to allow for
comparator response time. Least-significant-bit-first data applies only to ADC0832.
TEXAS -Ij} 2-41

INSTRUMENTS
ADC0831A. ADC0832A. ADC0831B. ADC0832B
c
...
OJ
OJ
l>
ClK
,:x-:-----t-:------
-+I
CS 0.4 V
I
t+- tsu
I
~
I
II
I
t+- tsu
GND
VCC
eLK
~ :.
50%
It---+f-
----GND
tpd
VCC
~
r---VOH
n I I I I GND DATA OUT 50%.
.c I I+*-th I~ (DO) ____ - ' VOL
c I I
C;;' __- - V C C
;:;.' DATA IN
--""\ II
2 V FIGURE 2. DATA OUTPUT TIMING
0' (01)
::s
(')
~' FIGURE 1. ADCOB32 DATA INPUT TIMING
n
c
;:;.' VCC
en
TEST
POINT S11J
FROM
OUTPUT
l ~.---...
UNDER
TEST 1
J CL
(See Note A) ~
S2 '",:,
lOAD CIRCUIT
~ !4-tr
I I
-t! !*-tr
I Vee
---~
~9'='=0%~-- Vee 90%
CS 50% CS 50%1
1------ 10%
GND
_ _"'r 101! - -
- - GND
~tdis ~tdiS
I -Vee
DO AND S1 open 90% DO AND S1 closed I
SARS OUTPUT ..!'!.c~~ _ _ _ _ GND SARS OUTPUT S2 open _1.!!'1'!... _ GND
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
NOTE A: Cl includes probe and jig capacitance.
FIGURE 3. OUTPUT DISABLE TIME TEST CIRCUIT AND VOLTAGE WAVEFORMS
2-42 TEXAS -111

INSTRUMENTS
POST OFFICE BOX 655012 , DALLAS. TEXAS 75265
TYPICAL CHARACTERISTICS
UNADJUSTED OFFSET ERROR LINEARITY ERROR
vs vs
REFERENCE VOLTAGE REFERENCE VOLTAGE
16 1.5
I 1111.1.111 I
VI( +) ... VI( -) ... 0 V
I I I T
Vce = 5 V
I
...rn
'~
-
14 fclock = 250 kHz
1.25 f-TA = 25e (,)
1\
r::a
12
en C3
en ~ 1.0 t:
...J 10 I o
e
I
8
e
w0.75
'';::;
''~m
w
....
Q) 'E C"
6 I (,)
~
O .~ 0.5
4 1\ ...I
... ('CI
o
"r'\.
"-
t--
0.25 C
('CI
o
0.01 0.1 10 o 2 3 4 5
Vref-Reference Voltage-V
Vref-Reference Voltage-V
FIGURE 4 FIGURE 5
LINEARITY ERROR LINEARITY ERROR

vs vs
FREE-AIR TEMPERATURE CLOCK FREQUENCY
0.5 3
1 I . Vref ... 5 V
Vref ... 5 V
fclock = 250 kHz
2.5
VCC'" 5 V J
/
0.45
r::a
en
...J
w
e
I
-:e 0.35
0.4
'" '" ~
~
r::a
en
...J
e
I
w 1.5
.~
2
/II
~ J
~
C'CI
V! b!
Q) Q)
C c 0
::; ::;
85 25C
0.3
"" ..........
r--.. 0.5 f - = -
~
40C ./
~
0.25 o
-50 -25 0 25 50 75 100 o 100 200 300 400 500 600
TA-Free-Air Temperature- C fclock-Clock Frequency-kHz
FIGURE 6 FIGURE 7
TEXAS . . 2-43
INSTRUMENlS
SUPPLY CURRENT SUPPLY CURRENT
lIB
C
Q)
1.5
vs
FREE-AIR TEMPERATURE
fclock - 250 kHz

CS high
1.5
VCC ='5 V
vs
CLOCK FREQUENCY
r+ TA = 25C
Q)
~
:t>
n
E ~
.c ...cI E
.!. 1.0
C ~ c
Ci)' :5 f!
:; l..--- I - - -
u
~
;::::;"
0' u
>- >-
::s c..
c. ii
::l
c.
(') en
::I
~' I '7 0.5

n u u
c $} !d
;::::;"
en
0.5~--~---L--~----L----L--~ o
-50 -25 0 25 50 . 75 100 o 100 200 300 400 500
TA-Free-Air Temperature- C fclock-Clock Frequency-kHz
FIGURE 8 FIGURE 9
OUTPUT CURRENT
vs
25~--~--~--~----~--~--~
20
~
Z
c
~
:; 15
u
...
::I
So
::l
10
0
I
9
O~--~ __-L__ ~ ____L-__-L__ ~
-50 -25 0 25 50 75 100

TA-Free-Air Temperature- C
FIGURE 10
2-44 TEXAS ~
INSTRUMENTS
ADC0834A, ADC0838A, ADC08348, ADC08388
02795. AUGUST 1985-REVISED OCTOBER 1986
8-Bit Resolution ADC0834 ... N DUAL-IN-L1NE PACKAGE

(TOP VIEW)
Easy Interface to Microprocessors or
Stand-Alone Operation
VCC
01
Operates Ratiometrically or with 5-V CHO ClK
Reference CH1 SARS
CH2 00
'~
....en
4- or 8-Channel Multiplexer Options with
Address Logic
CH3 REF
OGTl GNO ~_---,8.-ANlG GNO
...
(,)
Shunt Regulator Allows Operation with C3

High-Voltage Supplies ADC0838 ... I'll DUAL-IN-L1NE PACKAGE c:
(TOP VIEW),
o
".;:i
Input Range 0 to 5 V with Single 5-V
Supply CHO VCC 'en
'~
CH1 V+ 0"
Remote Operation with Serial Data Link CS (,)
CH2
Inputs and Outputs are Compatible with CH3 01
TTL and MOS CH4 ClK
SARS
....COCO
CH5
Conversion Time of 32 p,s at
CH6 00 C
fclock = 250 kHz SE
CH7
Designed to be Interchangeable with COM REF
National Semiconductor ADC0834 and OGTl GNO ANlG GNO
ADC0838
ADC0838 ... FN CHIP CARRIER PACKAGE
TOTAL UNADJUSTED ERROR (TOP VIEW)
DEVICE
A SUFFIX 1 B SUFFIX
ADC0834 1 LSB 1/2 LSB
ADC0838 + 1 LSB I
1/2 LSB
3 2 1 2019
description CH3 4 18 CS
CH4 5 17 01
These devices are 8-bit successive- CH5 6 16 ClK
approximation analog-to-digital converters each CH6 7 15 SARS
with an input-configurable multichannel CH7 8 14 00
multiplexer and serial input/output. The serial 9 1011 1213
input/output is configured to interface with
standard shift registers or microprocessors.
Detailed information on interfacing to most
popular microprocessors is readily available from
the factory.
The ADC0834 (4-channel) and ADC0838
, (8-channel) multiplexer is software configured
for single-ended or differential inputs as well as
pseudo-differential input assignments. The
differential analog voltage input allows for
common-mode rejection or offset of the analog
zero input voltage value. In addition, the voltage
reference input can be adjusted to allow
encoding any smaller analog voltage span to the
full 8 bits of resolution.
The ADC0834AI, ADC0834BI, ADC0838AI, and ADC0838BI are characterized for operation from - 40C
to 85 C. The ADC0834AC, ADC0834BC, ADC0838AC, and ADC0838BC are characterized for operation
from OC to 70C.
to specifications per the terms of Texas Instruments
standard warranty. Production processing does not TEXAS ~ 2-45
necessarily include testing of all parameters. INSTRUMENlS
N
~
en
sJ!n:u!o UO!J!s!nb:lV eJeo I ....
c :ta:ta
-
::l CC
...o
n n
..,,0
mCO
START ::l =W
elK ~
cs
-
III
C"
-~
~?-
Cs ,I d ) ~ ClK 0" Q;;:ta
n C
01
SARS ;II:" :ta
r-n
(See Note AI Co (1)0
5BIT SHIFT REGISTER
Or
:e~
R,
CQ
SELECT 0 SELECT 1 DOD/EVeN SGLlW
Q1 _co
3 ..... :ta
::c.
r:~;-_-l (I):ta
1 ONLY SE I
L ____ J
d m C
=n
_0
.oc_{{~~
:taco
.., r-w
o n~
~
~
cP'
ANAlOGMUX 2:ta
~Z
ADC0838 CH4
CH5 ..... c
cs =n
~~
CH6
Co
CH7 r-co
~iJ~ COM w
co
~C~
;,~ =
l!(TJ
cs cs cs
~Z .....
~~~
~ ClK
cs
... EN
LADDER DO
'"'" REF------------------------~ AND
'"'" DECODER
V C C J F . I f CIRCUITS
TO INTERNAL
7V
V+ ':"'
7V
NOTE A: For the ADC08~4, DI is input directly to the D input of SELECT 1, SELECT 0 is forced to a high.
functional description
The ADC0834 and ADC0838 use a sample data comparator structure that converts differential analog
inputs by a successive-approximation routine. Operation of both devices is similar with the exception of
a select enable (SE) input, analog common input, and multiplexer addressing. The input voltage to be
converted is applied to a channel terminal and is compared to ground (single-ended), to an adjacent input
(differential), or to a common terminal (pseudo-differential) that can be an arbitrary voltage. The input
terminals are assigned a positive ( +) or negative ( - ) polarity. If the signal inputs applied to the assigned
...en
"5
positive terminal is less than the signal on the negative terminal, the converter output is all zeros. ...
CJ
Channel selection and input configuration are under software control using a serial data link from the
i:3
controlling processor. A serial communication format allows more functions to be included in a converter c
o
package with no increase in size. In addition, it eliminates the transmission of low-level analog signals "~
by locating the converter at the analog sensor and communicating serially with the controlling processor. "Ci)
This process returns noise-free digital data to the processor. "5
C"
CJ
A particular input configuration is assigned during the multiplexer addressing sequence. The multiplexer
address is shifted into the converter through the data input (01) line. The multiplexer address selects the
analog inputs to be enabled and determines whether the input is single-ended or differential. When the
input is differential, the polarity of the channel input is assigned. Differential inputs are assigned to adjacent
...CO
CO
C
channel pairs. For example, channel 0 and channel 1 may be selected as a differential pair. These channels
cannot act differentially with any other channel. In addition to selecting the differential mode, the polarity
may also be selected. Either channel of the channel pair may be designated as the negative or positive input.
The common input on the ADC0838 can be used for a pseudo-differential input. In this mode, the voltage
on the common input is considered to be the negative differential input for all channel inputs. This voltage
can be any reference potential common to all channel inputs. Each channel input can then be selected
as the positive differential input. This feature is useful when all analog circuits are biased to a potential
other than ground.
A conversion is initiated by setting the chip select (CS) input low. This enables all logic circuits. The CS
input must be held low for the complete conversion process. A clock input is received from the processor.
On each low-to-high transition of the clock input, the data on the 01 input is clocked into the multiplexer
address shift register. The first logic high on the input is the start bit. A 3- to 4-bit assignment word follows
the start bit. On each successive low-to-high transition of the clock input, the start bit and assignment
word are shifted through the shift register. When the start bit has been shifted into the start location of
the multiplexer register, the input channel has been selected and conversion starts. The SAR Status output
(SARS) goes high to indicate that a conversion is in progress and the 01 input to the multiplexer shift register
is disabled for the duration of the conversion.
An interval of one clock period is automatically inserted to allow for the selected multiplexed channel to
settle. The data output DO comes out of the high-impedance state and provides a leading low for this
one clock period of multiplexer settling time. The SAR comparator compares successive outputs from the
resistive ladder with the incoming analog signal. The comparator output indicates whether the analog input
is greater than or less than the resistive ladder output. As the conversion proceeds, conversion data is
simultaneously output from the DO output pin with the most significant bit (MSB) first.
After eight clock periods the conversion is complete and the SAR Status (SARS) output goes low.
The ADC0834 outputs the least-significant-bit-first data after the MSB-first data stream. If the shift enable
(SE) line is held high on the ADC0838, the value of the least significant bit (LSB) will remain on the data
line. When SE is forced low, the data is then clocked out as LSB-first data. (To output LSB first, the SE
control input must first go low, then the data stored in the 9-bit shift register will output with LSB first.)
When CS goes high, all internal registers are cleared. At this time the output circuits go to the high-impedance
state. If another conversion is desired, the CS line must make a high-to-Iow transition followed by address
information.
. TEXAS" 2-47
INSTRUMENlS
POST OFFICE BOX 666012 CAllAS, TEXAS 75265
functional description (continued)
The 01 and DO pins can be tied together and controlled by a bidirectional processor I/O bit received on
a single wire. This is possible because the 01 input is only examined during the multiplexer addressing
interval and the DO output is still in a high-impedance state.
c Detailed information o,n interfacing to most popular microprocessors is readily available from the factory.
,...
Q)
Q) sequence of operation
l>
(') ADC0834
.c
c 2 3 4 5 6 7 10 11 12 13 14 15 18 19 20 21
iii'
;:;:
O
::s
n
ClK
I
I
-+j j4-tsu I.
JlJU1flJlJlJ1JlJl1Ul
teonv .1
::;'
(')
-ll II 1 1
r~~--------~--~r---
C 1 1
;:;" ,
cs I 1 5f I
en
1 1 1
-+I J.-t su +SIGN SEl~d 1
ISTART BIT CH BIT 1
IBIT SGl ODD 1 1 1 1 1
DI~II_ DIF EVEN 1 I I

1 I 1
I I
HI-Z
SARS1~__________~
I 1
55 ! fI :
I
1 I tt---MSB.FIRST DATA .1. lSBFIRST DATA----J
MAX SETTLING -.I
TIME
~I 1
HI-Z
DO--------------~
IMSBI
76
[ I
2
I LSBI
0 2
CI 67
I MSBi I
HIZ
ADC0834 MUX ADDRESS CONTROL lOGIC TABLE
MUX ADDRESS CHANNEL NUMBER

SGL/DIF ODD/EVEN SELECT BIT 1 0 1 2 3
L L L + -
L L H + -
l H l - +
L H H - +
H L L +
H L H +
H H L +
H H H +
H = high level, L = low level, - or + = polarity of selected input pin
2-48 TEXAS . .
INSTRUMENlS
sequence of operation
II
ADC0838
1 2 3 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
CLK~ I
I I I , I ....rn
Cs
~ iof--l-t su
l'
\I ,
,
I
I
14'4-+1----tconv----~~1
I I
I
,
I
I
I
I
.
"S
U
(,)
I , MUX ' I Sf
, : ~RESS~ c
o
~ i4- t su : +i
I I "w
I
I SEL SELl
I "S
C"
START' SIGN BIT 1 BIT 0 (,)
~
BIT I SGL ODD 1 0' I I
DI~III I Bif~~ ....COCO

01 F EVEN 1 I I I
I I
, I I C
I I :
I I
I I
HIZ : H HI.Z
SARSl~_ _ _ _ _ _~ I ~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~r_
-----~~-------------------------------------
I I SE HELD LOW OR CONNECTED TO CS
Sf . lL_______~iI ~i----~~---------------------------~r-
I H .
I I I4--MSBFIRSTDATA--1~~t4I---LSB.FIRSTDATA~
MUX SETTLING") :.-: I :
DO
HIZ
TIME iLi -1-:...J.1_M_SB..LI_l.Il;J:>--l_...l..---1-1
7
L_~B--lI_...l..---1---L_...l..---1---LI_M_SB..LI _ _ _ _ _ _ _---,Hr
- - - - - - - - -1 7 - - - - - - - - si" USEDTt)CONTROL LsBFIRSTDATA - - - - - - - - - - - - - --

I
I
I
I
I
I
I I
'-----_ _ _---or_
MUX I I t4--MSBFIRST DATA__M__ LSBHELD---i~.---LSBFIRST DATA~
SETTLING-+! *1 I ,
TIME I I :
DO---------~'~j_MS_B~I~I~:~:~--L-~---L-SB---~--L-~-L~--~--'--IM-SB~I ~r_ 3
__
TEXAS . . 2-49
INSTRUMENTS
POST OFFICE BOX 655012 OALLAS, TEXAS 75265
ADC0838 MUX ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS SELECTED CHANNEL NUMBER
lEI
o
m
SGL/DIF
L
L
ODD/EVEN
L
L
SELECT
1
L
L
0
L
H
0
+
0
1
-
+
2
1
3
-
4
2
5 6
3
7
COM
r+ L L H L + -
m L L H H + -
l>
(')
L H L L - +
.c L H L H - +
c L H H L + -
iii' L H H H - +
;:::;"
H L L L + -
ci" H L L H + -
~
-
o
~'
H
H
L
L
H
H
L
H
+
+ -
(')
C
H H L L + -
;:::;" H H L H + -
en H H H L + -
H H H H + -
H = high level, L = low level, - or + = polarity of selected input
absolute maximum ratings over recommended operating free-air temperature range (unless otherwise
noted)
Supply voltage, VCC (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6.5 V
Input voltage range: Logic........................................... - 0.3 V to 15 V
Analog .................................... -0.3 V to VCC+0.3 V
Input current: V + input ................................................... 1 5 mA
Any other input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 mA
Total input current for package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20 mA
Operating free-air temperature range: AI and BI suffixes .................... - 40C to 85 C
AC and BC suffixes ...................... ooC to 70C
Storage temperature range ......................................... - 65 C to 150C
Case temperature for 10 seconds: FN package .........' . . . . . . . . . . . . . . . . . . . . . . . . .. 260C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ............. 260C
NOTES: 1. All voltage values, except differential voltages, are with respect to the network ground terminal.
2. Internal zener diodes are connected from the Vee input to ground and from the V + input to ground. The breakdown voltage
of each zener diode is approximately 7 volts. One zener diode can be used as a shunt regulator and connects to Vee through
a regular diode. When the voltage regulator powers the converter, this zener and re.gular diode combination ensures that the
Vee input (6.4 V) is less than the zener breakdown voltage. A series resistor is recommended to limit current into the V + input.
2-50 TEXAS . .
INSTRUMENlS
ADC0834A, ADC0838A, ADC08348, ADC08388

MIN NOM MAX UNIT
VCC
VIH
VIL
fclock
Supply voltage
High-level input voltage
Low-level input voltage
Clock frequency
.
4.5
2
10
5 6.3
0.8
400
V
V
V
kHz
II
... U)
Clock duty cycle (see Note 3) 40 60 % 'S

twH(CS) Pulse duration, CS high 220 ns ...
(.)
tsu Setup time, CS low, SE low, or data valid before clocki 350 ns C3
th Hold time, data valid after clocki 90 ns c:
IAI and BI suffixes -40 85 o
TA Operating free-air temperature C '';:;
IAC and BC suffixes 0 70 'U;
NOTE 3: The clock duty cycle range ensures proper operation at all clock frequencies. If a clock frequency is used outside the recommended
'S
C'
duty cycle range, the minimum pulse duration (high or low) is 1 /Ls. (.)
<C
Vee = v + = 5 V, fclock == 250 kHz (unless otherwise noted) ...
CO
CO
digital section C
AI, BI SUFFIX AC, Be SUFFIX
MIN TYP* MAX MIN TYP* MAX
VCC = 4.75 V, 10H = -360/LA 2.4 2.8
VOH High-level output voltage V
VCC = 4.75 V, 10H = -10 /LA 4.5 4.6
VOL Low-level output voltage VCC = 5.25 V, 10L = 1.6 mA 0.4 0.34 V
IIH High-level input current VIH = 5 V 0.005 1 0.005 1 /LA
IlL Low-level input current VIL = O -0.005 -1 -0.005 -1 /LA
10H High-level output (source) current VOH = 0, TA = 25C -6.5 -14 -6.5 -14 mA
10L Low-level output (sink) current VOL = VCC, TA = 25C 8 16 8 16 mA
High-impedance-state output Va = 5 V, TA = 25C 0.01 3 0.01 3
10Z /LA
current (DO or SARS) Va = 0, TA = 25C -0.01 -3 -0.01 -3
Ci Input capacitance 5 5 pF
Co Output capacitance 5 5 pF
t All parameters are measured under open-loop conditions with zero common-mode input voltage (unless otherwise specified).
*AII typical values are at Vce = V+ = 5 V, TA = 25e.
TEXAS . . 2-51
INSTRUMENTS
POST OFFice BOX 655012 DALLAS, TeXAS 75265
ADC0834A, ADC0838A, ADC08348, ADC08388

Vee = V + = 5 V, fclock = 250 kHz (unless otherwise noted)
analog and converter section
PARAMETER TEST CONDITIONS t MIN TYP* ,MAX UNIT
-0.05
c
....
Q)
Q)
VICR Common-mode input voltage range See Note 4 to
VCC+ 0,05
V
On-channel = 5 V at on-channel, 1
:t>
(") Standby input current Off-channel
VI
VI = a at off-channel -1
.c Il(stdby)
(see Note 5) On-channel = a at on-channel, -1
p.A
c VI
C;;" Off-channel VI = 5 V at off-channel 1
;::;'" ri(ref) Input resistance to reference ladder 1.3 2.4 5.9 kn
0"
::::J
total device
n
:::;" MAX
PARAMETER TEST CONDITIONSt MIN TYP* UNIT
(").
c II = 15 mA at V+ pin,
Vz Internal zener diode breakdown voltage 6.3 )7 8.5 V
;::;' See Note 2
en ICC Supply current 1 2.5 mA
tAli typical values are at VCC = 5 V, V+ = 5 V, TA = 25C.
NOTES: 2. Internal zener diodes are connected from the VCC input to ground and from the V + input to ground. The breakdown voltage
of each zener diode is approximately 7 volts. One zener diode can be used as a shunt regulator and connects to VCC through
a regular diode. When the voltage regulator powers the converter, this zener and regular diode combination ensures that the
VCC input (6.4 V) is less than the zener breakdown voltage. A series resistor is recommended to limit current into the V + input.
4. If channel IN - is more positive than channel IN +, the digital output code will be 0000 0000. Connected to each analog input
are two on-chip diodes that will conduct forward current for analog input voltages one diode drop above VCC. Care must be
taken during testing at low VCC levels (4.5 V) because high-level analog input voltage (5 V) can, especially at high temperatures,
cause this input diode to conduct and cause errors for analog inputs that are near full-scale. As long as the analog voltage does
a
not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve ail absolute V to 5 V input
voltage range requires a minimum VCC of 4.950 volts for all variations of temperature and load.
5. Standby input currents are currents going into or out of the on or off channels when the AID converter is not performing conversion
and the clock is in a high or low steady-state condition.
2-52 TEXAS . .
INSTRUMENlS
POST OFFice BOX 655012 DALLAS, TeXAs 75265
operating characteristics V + Vee 5 V, fclock = 250kHz, tr = tf 20 ns, TA 25C (unless

otherwise noted)
PARAMETER
Supply-voltage variation error

TEST CONDITIONSt
VCC = 4.75 V to 5.25 V

Vref = 5 V,
BI, BC SUFFIX
MIN TVP
1/16
MAX
1/4
AI, AC SUFFIX
MIN TVP
1/16
MAX
1/4
UNIT
LSB
II....tn
Total unadjusted error (see Note 6)
TA = MIN to MAX
1/2 1 LSB
'S
Common-mode error Differential mode 1/16 1/4 1/16 1/4 LSB ...
(.)
Change in zero-error from

II = 15 mA at V + pin,
C3
Vce = 5 V to internal zener 1 1 LSB s:::::
Vref = 5 V, VCC open
diode operation (see Note 2) o
Propagation delay time, I MSB-first data 650 1500 650 1500
'';::'
'C;;
tpd output data after CLK~
(see Note 7)
I .
LSB-flrst data
CL = 100 pF
250 600 250 600
ns
'S
C"
(.)
Output disable time, CL = 10 pF, RL = 10 k{l 125 250 125 250
tdis
DO or SARS after CSi CL = 100 pF, RL = 2 k{l 500 500'
ns <t
tconv
Conversion time (multiplexer
8 8
clock ....('0
('0
addressing time not included) periods
o
t All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX,
use the appropriate value specified under recommended operating conditions.
NOTES: 2. Internal zener diodes are connected from the VCC input to ground and from the V + input to ground. The breakdown voltage
of each zener diode is approximately 7 volts. One zener diode can be used as a shunt regulator and connects to VCC through
a regular diode. When the voltage regulator powers the converter, this zener and regular diode combination ensures that the
VCC input (6.4 V) is less than the zener breakdown voltage. A series resistor is recommended to limit current into the V + input.
6. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
7. The most significant bit (MSB) data is output directly from the comparator and therefore requires additional delay to allow for
comparator response time.
CLK
I GND
I I
-+\
-+I ~ tsu
I+- tsu
~~:-:-----t-:------VCC
cs O.4V\ I I I
I I GND
I~th
I I ----VCC
DATA IN
(01)
FIGURE 1. DATA INPUT TIMING
TEXAS ~ 2-53
INSTRUMENTS
ADC0834A, ADC0838A, ADC08348, ADC08388
AID PERIPHERALS WITH SERIAL CONTRQL
II
c
,
~tpd tpd----+l ~
GND
Q)
r+
Q)

DATA.
OUT (DO)
___ ..I
~'r---- ------
'l'\5C1'1o
-1""",;;,,1 Vee
i, '--GND
50"10
(')
.c
c
iii'
~'
0'
se------------"',,: --+I tsu I+-
---Vee
j \.----GND
("') FIGURE 2. DATA OUTPUT TIMING

::;'
(')
c
~'
en TEST
POINT
~
FROM
OUTPUT
UNDER 1 l
TEST
J eL
(See Note A)
LOAD CIRCUIT
-tf J4-t r
I 1 V
_~90%
es 50%1
ee
10~ _ _ _ _ GND
~tdiS
, -Vee
DO AND Sl open DO AND Sl closed I
SARS OUTPUT _S2_o..;.p_en_......r-_1~~
SARS OUTPUT
--------
S2 closed
GND
_ GND
NOTE A: CL includes probe and jig capacitance.
FIGURE 3. OUTPUT DISABLE TIME TEST CIRCUIT AND VOLTAGE WAVEFORMS
2-54 TEXAS ~
INSTRUMENTS
ADC0834A, ADC0838A, ADC0834B, 'ADC0838B
Ell
UNADJUSTED OFFSET ERROR LINEARITY ERROR
vs vs
REFERENCE VOLTAGE REFERENCE VOLTAGE
16 1.5
I. I en
.....
r- VI(+) = VI(_) = 0 V VCC = 5 V 'S
14 fclock = 250 kHz
1.25 -TA = 25C ...
(,)
12
C3
1\ al s::::
al
CI)
~ 1.0 o
...J 10 I '.;:i
I
8
e
Iii 0.75
'c;;
'S
Iii
...
ell
~
.;:
<0
C"
(,)
i0 6
.~ 0.5
<C
"
...J CO
4 \ .....
CO
\. 0.25 C
2 ~
i'
o r-- o
0.01 0.1 1.0 10 o 2 3 4 5
Vref-Reference Voltage-V Vref-Reference Voltage-V
FIGURE 4 FIGURE 5
LINEARITY ERROR LINEARITY ERROR

vs vs
FREEAIR TEMPERATURE CLOCK FREQUENCY
0.5 3 I
I
Vref = 5 V
fclock = 250 kHz
L Vref = 5 V
VCC = 5 V I
2.5
al
CI)
0.45
.'" "- al
~ 2
/
/
...J
I 0.4 I.
o
Iii
" .E 1.5 V
'"
~
'E
.~ 0.35
::lc: I
"'-''-..,.
ell
c:
:J
:J
0.3 ......... -40 C

o
85V ~
/
0.5 -.:::::--
= .....-
"
0.25 o
-50 -25 o 25 50 75 100 o 100 200 300 400 500 600
T A-FreeAir Temperature-c fclock - Clock Frequency - kHz
FIGURE 6 FIGURE 7
TEXAS ~ 2-55
INSTRUMENTS
SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
FREEAIR TEMPERATURE
CLOCK FREQUENCY
1.5
I J 1.5
C
...
m
m , V.
fclock = 250
CS = HIGH
kH~ Vcc = 5 V
TA = 25C
> <t
E ~C"s.s"
<t
E
n
..
-- -
I I
J:l
c ... c:: ~ c:: 1.0
fir ~ I
~
~
I--"
::." ........... II. ~
:l
CC"s I"---
c;. 1.0 I'--...
~
(.)
0"
::l
n
Q.
D.
:l
~ r--.. r-
>-
a.c.
:l
::;"
en
I '-..... II. I en
I
n ~"4.5" 0.5
c
;:;."
en
!:i
(.)
0.5
r--:.....
-- r--
(.)
!:i
o
-50 -25 o 25 50 75 100 o 100 200 300 400 500
T A - FreeAir Temperature - c fclock - Clock Frequency - kHz
FIGURE 8 FIGURE 9
OUTPUT CURRENT
vs
FREEAIR TEMPERATURE
25r----r--~r---.---_.----.---~
Vcc =5 V
<t 20
E
I
~ 15 I----+--'==--~
~
(.)
...
:l
E10
o
I
9
OL-__- L_ _ ~~_ _~_ _~_ _ _ _~_ _~
-50 -25 o 25 50 75 100

. T A - FreeAir Temperature - c
FIGURE 10
2-56 TEXAS . .
INSTRUMENTS
Tl0808, Tl0809
lOWPOWER CMOS ANAlOGTODIGITAl CONVERTERS
WITH 8CHANNEl MULTIPLEXERS
02642, FEBRUARY 1986 - REVISED SEPTEMBER 1986
Total Unadjusted Error ... 0.75 lSB Max N DUAL-IN-L1NE PACKAGE

for Tl0808 and 1.25 lSB Max for (TOP VIEW)
II
Tl0809 Over Temperature Range
Ideal for Battery Operated, Portable ~}INPUTS
Instrumentation Applications
Resolution of 8 Bits ~}ADDRESS ...
'S
(I)
100 p's Conversion Time EOe ALE

...
(,)
2- 5 2 - 1 (MSB) C3
OE 2-2
c
Guaranteed Monotonicity CLK 2- 3 o
Vec 2- 4 '+:;
No Missing Codes REF + 2 - 8 (LSB)
'C;;
Easy Interface with Microprocessors
GND REF- 'S
2-7 '-1..._ _.... 2- 6 C'
(,)
latched 3State Outputs cd:
latched Address Inputs
FN PACKAGE ...
CO
CO
Single 5Volt Supply (TOP VIEW) C
Extremely low Power
Consumption ... 0.3 mW Typ
Improved Direct Replacements for 4 3 2 1 28 27 26
ADC0808, ADC0809 INPUT 7 5 25
START 6 24
description EOC 7 23
2-5 8 22
The TL0808 and TL0809 are monolithic CMOS
OE 9 21
devices with an 8-channel multiplexer, an 8-bit CLK 10 20
analog-to-digital (A/D) converter, and Vce 11 19
microprocessor-compatible control logic. The 121314151617 18
8-channel multiplexer can be controlled by a
+ 0"" CDI Cii'<t
microprocessor through a 3-bit address decoder u.ZIIu.UlI
~(!)NN~=N
with address load to select anyone of eight ex)
single-ended analog switches connected directly I

N
to the comparator. The 8-bit A/D converter uses
the successive-approximation conversion
technique featuring a high-impedance threshold detector, a switched-capacitor array, a sample-and-hold, .
and a successive-approximation register (SAR). Detailed information on interfacing to most popular
microprocessors is readily available from the factory. These devices are designed to operate from common
microprocessor control buses, with three-state output latches driving the data bus. The devices can be
made to appear to the microp;ocessor as a memory location or an I/O port.
The comparison and converting methods used eliminate the possibility of missing codes, nonmonotonicity,
and the need for zero or full-scale adjustment. Also featured are latched 3-state outputs from the SAR
and latched inputs to the multiplexer address decoder. The single 3-volt supply and extremely low power
requirements make the TL0808 and TL0809 especially useful for a wide variety of applications including
portable battery and LCD applications. Ratiometric conversion is made possible by access to the reference
voltage input terminals.
The TL0808 and TL0809 are characterized for operation from - 40C to 85 DC.
PROOUCTION DATA documents contain information Copyri9ht 1986, Texas Instruments Incorporated
~~~~~:~~i~a{::1~18 ~~:~:~ti:r fI,o::~:~:t:ros~s not INSTRUMENlS
TL0808. TL0809
LOWPOWER CMOS ANALOGTODIGITAL CONVERTERS
SAMPLEANDHOLD
BINARYWEIGHTED
CAPACITORS
cD) 112)
REF+ - - - - - - t
6 =-)- - - - - t SWITCH
r+ REF_.:..:(1c.::.
MATRIX
D)
l>
(') 0(26) ,....--...., (17) 2-S (LSB)
.c 1 (27) (14) 2- 7
t:
(ii" (15) 2-6
2 (2S)
;:;'" ANALOG
OUTPUT (S) 2-5 DIGITAL
0" ANALOG
3 (1)
MULTI- LATCHES I1S) 2-4 OUTPUTS
::::s INPUTS 4 (2) PLEXER 119) 2-3
n 5 (3)
(20) 2-2
~" EN (211 2-1 (MSB)
(') 6 (4) ~_ _ _ _ _ _~_ _~(~7) END OF
t: CONVERSION (EOC)
;:;'" 7 (5)
en
CLOCK~(1-0,-)_-+_ _~
START CONVERSION (START) ...:(...;6)_ _-t-_ _ _ _--'
OUTPUT ENABLE (OE)...:(:,::.9=-)- - f - - - - - - - - - - - - - - - . . J
(25),....................,
~~~:~~ : (24) ADDRESS

ADDRESS LOAD (22)
ENABLE (ALE)

INPUTS SELECTED
L L L t 0
L L H t 1
L H L t 2
L H H t 3
H L L t 4
H L H t 5
H H L t 6
H H H t 7
H =high level, L = low level

2-58 TEXAS
INSTRUMENTS
-1/1
POST OFFICE BOX 655012 " DALLAS, TEXAS 75265
TL0808, TL0809
LOWPOWER CMOS ANALOGTODlGITAL CONVERTERS
operating sequence
CLOCK
START
50%
III U)
~
CONVERSION 'S
ADDRESS LOAD
...
(,)
ENABLE : ,50% U
I I P, twIALC) c
~ADDRESS STABLE o
ADDRESS 50~~5_0%_o+i________________~:~_____________________________ '~
. tsu +-r-: th :
'en
'S
ANALOG INPUT
=xI I1 ANALOG VALUE ::===--=X~----------------------
INPUT STABLE -----------.~I <t
C"
(,)
I
MULTIPLEX OUTPUT
(INTERNAL)
----~~
><I~I--------------~;~J----~
VALU~:
ANALOG >e:---------------------- CO
~
CO
I C
END OF
CONVERSION
! \50% 150%
I--tdIEOC) ---j ........---------fiJ._-------------',
1 tconv -------------11
OUTPUT
ENABLE 50%/. ~
--------------------------.,J----------------J-j t-' ten -1 I- tdis
LATCH OUTPUTS 9~%f
----------------H-I--Z-S-T-A-T-E----fJ-------------l~0~%~~-------~fl0%
~
TEXAS l!} 2-59

INSTRUMENTS
TL0808. TL0809
LOW-POWER CMOS ANALOG-TO-DlGlTAL CONVERTERS
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
II
c
Input voltage range: control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to 15 V
all other inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to Vee + 0.3 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40 DC to 85 DC
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 DC to 150 DC
...
Q)
Q)
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package. . . . . . . . . . . .. 260 D~
Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260 DC

(') NOTE 1: All voltage values are with respect to network ground terminal.
.c
c
iii' recommended operating conditions
:=;"
0' MIN NOM MAX UNIT
:::l
Supply voltage. VCC
I f clock = 10kHz to 640 kHz 2.75 5.5
V
(")
:::;'
I fclock = 640 kHz to 1280 kHz 4 5.5
(') Clock frequency. fclock (see supply voltage recommendation above) 10 1280 kHz
c Positive reference voltage. Vref + (see Notes 2. 3. and 4) 2.75 Vec Vee+ O;1 V
:=;"
en Negative reference voltage., Vref _ (see Notes 2. 3. and 4) 0 -0.1 V
Differential reference voltage. Vref + - Vref _ (see Note 4) 3 V
High-level input voltage. control inputs. VIH 0.7 Vee V
Low-level input voltage. control inputs. VIL 0.3 Vee V
Start pulse duration. tw(S) 200 ns
Address load control pulse duration. tw(ALC) 200 ns
Address setup time. tsu 50 ns
Address hold time. th 50 ns
Operating free-air temperature. T A (see Note 4) -40 85 c
NOTES: 2., The accuracy of the conversion will depend on the stability of the reference voltages applied .
3. Analog voltages greater than or equal to Vref + convert to all highs. and all voltages less than Vref _ convert to all lows.
4. For proper operation of the TL0808 and TL0809 at free-air temperatures below OoC. V CC and (V ref + - Vref _ ) should not
be less than 3 volts.
2-60 TEXAS.
INSTRUMENTS
TL0808, TL0809
electrical characteristics over recommended operating freeair temperature range, Vee = 3 V to 5.25 V
total device
VOH
PARAMETER
TEST CONDITIONS
10 = -360 JlA
MIN
VCC-O.4
Typt MAX UNIT
V
IItn
.....
I Data outputs 10 = 1.6 mA 0.4 'S
I End of conversion 10=1.2mA 0.4
V
...CJ
10Z
Off-state (high-impedance-state) Va = VCC 1
JlA
i:3
output current Vo = 0 -1 c
II Control input current at maximum input voltage VI = 15 V 1 JlA o
Low-level control input current -1
';:;
IlL VI = 0 JlA
'W
ICC Supply current
VCC = 3 V, fclock = 640 kHz 100 500 JlA 'S
VCC = 5 V, fclock = 640 kHz 0:3 3 mA C-
CJ
Ci
Co
Input capacitance, control inputs
Output capacitance, data outputs
TA = 25C
TA = 25C
10
10
15
15
pF
pF
CO
Resistance from pin 12 to pin 16 1 1000 kO .....
CO
analog multiplexer
C

VI = 3 V, fclock = 640 kHz 2
Ion Channel on-state current (see Note 5) JlA
VI = 0, f clock = 640 kHz -2
VCC = 3 V, VI = 3 V 10 200
nA
TA = 25C VI = 0 -10 -200
VI = 3 V 1
VCC = 3 V JlA
VI = 0 -1
tTypical values are at VCC = 3 V and T A = 25C.

frequency.
TEXAS 2-61
INSTRUMENTS
TL0808, TL0809
operating characteristics, TA = 25e, Vee = 3 V, VREF+ = 3 V, VREF- o V, fclock = 640 kHz

TL0808 TL0809
MIN TYpt MAX MIN TVpt MAX
Supply voltage VCC = Vref+ = 3 V to 5.25 V,
c
Q)
kSVS
sensitivity TA = -40C to 85C, See Note 6
0.05 O.05 %/V
r+ Linearity error
Q) 0.5 1 LSB
(see Note 7)
n
Zero error (see Note 8) 0.5 0.5 LSB
.c Total unadjusted TA = 25C 0.25 0.5 0.5 1

LSB
c error (See Note 9) TA = -40C to 85C 0.75 1.25
en
;:::;'. ten Output enable time CL = 50 pF, RL = 10 kO 80 250 80 250 ns
o
:s
tdis
tconv
Output disable time
Conversion time
CL = 10 pF,
See Note 10
RL = 10 kO
90
105
100
250
116 90
105
110
250
116
ns
p's
(") Delay time,
:::;' td(EOC) end of conversion See Notes 10 and 11 0 14.5 0 14.5 p's
n output
c
;:::;"
til tTypical values for all except supply voltage sensitivity are at VCC = 3 V, and all are at TA = 25C.
NOTES: 6. Supply voltage sensitivity relates to the ability of an analog-to-digital converter to maintain accuracy as the supply voltage
varies. The supply and Vref + are varied together and the' change in accuracy is measured with respect to full-scale.
7. Linearity error is the maximum deviation from a straight line through the end points of the AID transfer characteristic.
9. Total unadjusted error is the maximum sum of linearity error, zero error, and full-scale error.
11. For clock frequencies other than 640 kHz, td(EOC) maximum is 8 clock periods plus 2 p.s.
2-62 TEXAS -1.!1

INSTRUMENTS
TL0808, TL0809
LOW-POWER CMOS ANALOG-TO-DiGITAL CONVERTERS
fI
The TL0808 and TL0809 each consists of an analog signal multiplexer, an 8-bit successive-approximation
converter, and related control and output circuitry.
multiplexer
The analog multiplexer selects 1 of 8 single-ended input channels as determined'by the address decoder.
...
"5
tn
(J
Address load control loads the address code into the decoder on a low-to-high transition. The output latch a..
is reset by the positive-going edge of the start pulse. Sampling also starts with the positive-going edge U
of the start pulse and lasts for 32 clock periods. The conversion process may be interrupted by a new C
-.;:;
occurs before the 64th clock pulse. Continuous conversion may be accomplished by connecting the End- -Cii
of-Conversion output to the start input. If used in this mode an external pulse should be applied after power "5
up to assure start up. 0"
(J
converter
The CMOS threshold detector in the successive-approximation conversion system determines each bit ... CO
CO
by examining the charge on a series of binary-weighted capacitors (Figure 1). In the first phase of the C
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference voltage.
detector looks at the first capacitor (weight = 128). Node 128 of this capacitor is switched to the reference
128-weight capacitor remains connected to REF + through the remainder of the capacitor-sampling (bit-
The conversion process is successive approximation, but relies on charge redistribution rather than a
successive-approximation register (and reference DAC) to count and weigh the bits from MSB to LSB.
Sc
OUTPUT
NOo~;t~;t~~t~~t~;'t~~t~~t~;'t~~~
LATCHES
REF~ REF- REF- REF- REF- REF- REF- REF- REF-
~i f f i f i j i j
FIGURE 1. SIMPLIFIED MODEL OF THE SUCCESSIVE-APPROXIMATION SYSTEM
TEXAS . . 2-63
INSTRUMENTS
c
...
Q)
Q)
(')
.c
c
en'
:=;.'
0'
:l
n
:::;'
(')
c
:=;.'
en
2-64
TL182, TL 185, TL 188, TL1S1
HIMOS SWITCHES
02234. JUNE 1976- REVISED SEPTEMBER 1986
Functionally Interchangeable with Siliconix Uniform On-State Resistance for Minimum

DG182, DG185, DG188, DG191 with Same Signal Distortion
Ell
Terminal Assignments
10-V Analog Voltage Range
Monolithic Construction
o TTL, MOS, and CMOS Logic Control

Adjustable Reference Voltage
JFET Inputs
Compatibility
TL182
N DUALINL1NE PACKAGE
-...
fA
':;
(,)
description
(TOP VIEW) U
The TL 182, TL 185, TL 188, and TL 191 are r::::
15 25 o
monolithic high-speed analog switches using BI- 10 20 '';:;
MOS technology. They comprise JFET-input NC NC 'en
buffers, level translators, and output JFET NC NC
':;
switches. The TL 182 switches are SPST; the C'
1A 2A (,)
TL 185 switches are SPOT. The TL 188 is a pair <t
-
VCC VEE
of complementary SPST switches as is each half CO
VLL Vref
of the TL191. CO
A high level at a control input of the TL 182 turns TL185 C
the associated switch off. A high level at a N DUALINL1NE PACKAGE
(TOP VIEW)
control input of the TL 185 turns the associated
switch on. For the TL 188, a high level at the 101 151
control input turns the associated switches S 1 NC 1A
on and S2 off. 102 VEE
152 Vref
The threshold of the input buffer is determined
251 VLL
by the voltage applied to the reference input
201 Vce
(Vref). The input threshold is related to
NC 2A
the reference input by the equation
202 252
Vth = Vref + 1.4 V. Thus, for TTL compati-
bility, the Vref input is connected to ground. The TL 188
JFET input makes the device compatible with N DUALINLlNE PACKAGE
bipolar, MOD, and CMOS logic families. (TO~ VIEW)
Threshold compatibility may, again, be
NC NC
determined by Vth = Vref + 1.4 V. NC NC
The output switches are junction field-effect 01 02
transistors featuring low on-state resistance and 51 52
high off-state resistance. The monolithic A NC
structure ensures uniform matching. VCC VEE
VLL Vref
BI-MOS technology is a major breakthrough in
linear integrated circuit processing. BI-MOS can TL191
have ion-implanted JFETs, p-channel MOS-FETs, N DUALINL1NE PACKAGE
plus the usual bipolar components all on the (TOP VIEW)
same chip. BI-MOS allows circuit designs that
101 151
previously have been available only as expensive
NC 1A
hybrids to be monolithic.
102 VEE
Devices with an "M" suffix are characterized for 152 Vref
operation from - 55C t0125 DC, those with an 252 VLL
"I" suffix are characterized for operation from 202 VCC
- 25C to 85 DC, and those with a "C" suffix NC 2A
are characterized for operation from a C to 201 -...;~--.;;.;-
251
70C. NC-No internal connection
PRODUCTION DATA documents contain Copyright 1984. Texas Instruments Incorporated
~
information current as of publication date.
~fOd~!!~:onl~:~u~::::ifi;::~~~~ger~~~rt:~~~ TEXAS 2-65
Production processing does not necessariry
include testing of all parameters.
INSTRUMENTS
TL182, TL 185
BIMOS SWITCHES
TL 182 TWIN SPST SWITCH
II schematic (each channel) symbol
...c
OJ
OJ
0
1A
(5)
(1) (2)
18 ~
l>
(')
10
.c 8
(10)
c 2A
iii' A~~~~-+-------r-------r----~~
(14)
~
(13)
:=.' 2S 20
O
::s
n
::::;.
(')
c FUNCTION TABLE
:=.'
en
(EACH HALF)
INPUT SWITCH
A S
L ON (CLOSED)
H OFF (OPEN)
Vref
TL 185 TWIN DPST SWITCH
schematic (each channel) symbol
(15)
1A
(16) (1)
01 181
(4)
--"- (3)
101
1S2 ~- 102
S1 (10)
2A
(5) (6)
A-'~~---r------~------+-----~~ 281 ~- 201
02 (9) (8)
282 ~- 202
S2
FUNCTION TABLE
(EACH HALF)
INPUT SWITCHES
A SW1AND8W2
L OFF (OPEN)
H ON (CLOSED)
Vref
2-66 TEXAS ~
INSTRUMENTS
TL 188, TL191
BIMOS SWITCHES
TL 188 DUAL COMPLEMENTARY SPST SWITCH
schematic symbol
Ell
01
A (5)
- "5
en
...
(.)
S1 (4) ~_ (3) 01 C3
t - ' - - -.....-S1 52 (11) ~ (12) 02 c
o
A-~-~-~--~~---+---~I
"~
02 "Ci)
"5
C"
(.)

-
1 - - - -.....-52
FUNCTION TABLE
co
INPUT SWITCHES co
A SW1 SW2 C
L OFF (OPEN) ON (CLOSED)
H ON (CLOSED) OFF (OPEN)
Vref
TL 191 TWIN DUAL COMPLEMENTARY SPST SWITCH
schematic (each channel) symbol
(15)
1A
01 (t)
1S1 (16)
~- 101
1S2 (4) .--..-r... (3)
102
S1
(10)
2A
A~~~~-+----r------r----~"I (9)
02 2S1 ~- 201
2S2
(5)
~ 202
1 - - - -......-52
FUNCTION TABLE
INPUT SWITCHES
A SW1 SW2
L OFF (OPEN) ON (CLOSED)
H ON (CLOSED) OFF (OPEN)
} TO OTHER HALF
Vref
TEXAS ~ 2-67
INSTRUMENTS
POST OFFICE BOX 655012 " OALLAS. TEXAS 75265
TL 1B2, TL 1B5, TL1BB, TL191
BI-MOS SWITCHES
II o OR 01 02
c
...
Q)
Q)
l>
n
.c
A-D{>- -t--t'
S OR S1 52
r::::
c;;-
;:,:;.' See the preceding two pages for operation of the switches.
0'
j
n Positive supply to negative supply voltage, VCC - VEE ............................. 36 V
~'
n Positive supply voltage to either drain, VCC - VD ................................. 33 V
r::::
;:,:;.' Drain to negative supply voltage, VD - VEE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 33 V
tn
Drain to source voltage, Vo - Vs ...................................... :. . . .. 22 V
Logic supply to negative supply voltage, VLL - VEE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 36 V
Logic supply to logic input voltage, VLL - VI ..................................... ' 33 V
Logic supply to reference voltage, VLL - Vref .................................... 33 V
Logic input to reference voltage, VI - Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 33 V
Reference to negative supply voltage, Vref - VEE ................................. 27 V
Reference to logic input voltage, Vref - VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2 V
Current (any terminal) ..................................................... 30 mA
Operating free-air temperature range: TL 182M, TL 185M, TL 188M, TL 191 M . . .. - 55 C to 125 DC
TL1821, TL1851, TL1881, TL1911 ......... -25 DC to 85 DC
TL182C, TL185C, TL188C, TL191C ......... ODC to 70 DC
Storage temperature range ......................................... - 65 DC to 150 DC
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260 DC
2-68 TEXAS ~
INSTRUMENTS
electrical characteristics, Vee 15 V, VEE == -15 V, VLL == 5 V, Vref == 0 V
TL1_M TL1_1 TL1_C
MIN MAX MIN MAX MIN MAX
High-level control
VIH TA = MIN TO MAX V re f+ 2 V re f+ 2 V re f+ 2 V
input voltage
Low-level control
VIL TA = MIN to MAX V re f+ 0 .8 V re f+ 0 . 8 V re f+ 0 .8 V
input voltage
High-level control TA = 25C 10 10 20
IIH VI = 5 V p.A
input current TA = MAX 20 20 20
Low-level control
IlL VI = 0 TA = MIN to MAX -250 -250 -250 p.A
input current
Vo = 10 V. Vs = -10V. TA = 25C 5 5
10(off) Off-state drain current nA
VIH = 2 V, VIL = 0.8 V TA = MAX 100 100 100
" VO= -10V, Vs = 10 V, TA = 25C 5 5

~ IS (off) Off-state source current
VIH = 2 V, VIL = 0.8 V TA = MAX 100 100 100
nA
~
:!!- On-state channel VO=-10V, VS=-10V, TA = 25C -10 -10
~z 10(oni + IS (ani leakage current VIH = 2 V, VIL = 0.8 V TA = MAX -200 -200 -200
nA
l3CJ) I
~-I TL182, TA = MIN to 25C 75 100 100 I
~;o~ rOS(onl
Orain-to-source Vo = -10V, IS = 1 rnA, TL188 TA = MAX 100 150 150
0
I
~~ c:~
~
on-state resistance VIH = 2 V, VIL = 0.8 V TL185,
TL191
TA = MIN to 25C
TA = MAX
125
250
150
300
150
300
~f'I'1 ICC Supply current from V CC 1.5 1.5 1.5
~z
~ ..
lEE Supply current from VEE -5 -5 -5
Both control inputs at 0 V TA = 25C rnA
ILL Supply current from VLL 4.5 4.5 4.5
Iref Reference current -2 -2 -2
"'"
N
ICC Supply current from VCC 1.5 1.5 1.5
'"'" Supply current from VEE -5 -5 -5
lEE
Both control inputs at 5 V TA = 25C rnA
-
ILL Supply current from VLL 4.5 4.5 4.5
-t
Iref Reference current
- -- -- -- -- -
-2 -2 -2 r-
switching characteristics, Vee - 10 V, VEE - -20 V, VLL - 5 V, Vref =0 V, TA .. 25e

=
N
-t
r-
PARAMETER TEST CONDITIONS TL1_M TL1_1 TL1_C ICCI-
-=
I
UNIT
TYP TYP TYP
i
175
i:!3'
-
ton Turn-on time 175 175
TUrn-off time
RL = 300 D. CL = 30 pF, Figure 1
350 350
ns , C-t
(I) r-
toff 350
(1)=
E!
=t-t
nr-
:e-
I
mea
N (1)-
m
co
TL182. TU85. TU80. TU91
BIMOS SWITCHES
c
Q)
r+
Q)
n
.c
VLL =5 V Vcc = 15 V
c
(ii'
;:;:
0' CL includes probe and jig capacitance
::::J
n Vs = 3 V for ton and -3 V for toft
~' RL
n Vo=Vs - - - -
c RL + rOSlon)
;:;"
en
TEST CIRCUIT
.
:x=
OS;
t f <10ns
INPUT A
,,
I'I '-----H--',I
~n~+ ____
_____
f
)Ctr<10;~----_3V
I
I
~------
VOl
I
OV
3V
OUTPUT .' ~tOft

---~----~ .
0.1 Vo OV
Vo
------------------~V
NOTE: A. The solid waveform applies for TL 185 and SW1 of TL 185 and TL 191; the dashed waveform applies for TL 182 and SW2 of
TL185 and TL191.
B. Va is the steady-state output with the switch on. Feed through via the gate capacitance may result in spikes (not shown) at
the leading and trailing edges of the output waveform.
FIGURE 1. VOLTAGE WAVEFORMS
2-70 TEXAS ~
INSTRUMENTS
TL500C THRU TL503C
ANALOGTODlGITALCONVERTER BUILDING BLOCKS
02477. DECEMBER 1979 - REVISED DECEMBER 1986
TL500C/TL501 C
ANALOG PROCESSORS

True Differential Inputs
Automatic Zero
Automatic Polarity
II
....en
High Input Impedance ... 10 9 Ohms
Typically
.
':;
C3
o
c
TL500C CAPABILITIES TL501 C CAPABILITIES o
'';:;
'Cj)
Resolution ... 14 Bits (with TL502C) Resolution ... 10-13 Bits (with TL502C)
':;
Linearity Error ... 0.001 % Linearity Error ... 0.01 % C-
O
4 1/2-Digit Readout Accuracy with External 3 1/2-Digit Readout Accuracy
Precision Reference ....COCO
TL502C/TL503C TL502C CAPABILITIES C
DIGITAL PROCESSORS
Compatible with Popular Seven-Segment
Fast Display Scan Rates Common-Anode Displays
Internal Oscillator May Be Driven or

Free-Running
High-Sink~Current
Displays
Segment Driver for Large
Interdigit Blanking
TL503C CAPABILITIES
Over-Range Blanking.
4 1/2-Digit Display Circuitry Multiplexed BCD Outputs
High-Sink-Current Digit Driver for Large High-Sink-Current BCD Outputs

Displays
Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
I
description
The TL500C and TL501 C analog processors and TL502C and TL503C digital processors provide the basic
functions for a dual-slope-integrating analog-to-digital converter.
The TL500C and TL501 C contain the necessary analog switches and decoding circuits, reference voltage
generator, buffer, integrator, and comparator. These devices may be controlled by the TL502C, TL503C,
by discrete logic, or by a software routine in a microprocessor.
The TL502C and TL503C each includes oscillator, counter, control logic, and digit enable circuits. The
TL502C provides multiplexed outputs for seven-segment displays, while the TL503C has multiplexed BCD
outputs.
When used in complementary fashion, these devices form a system that features automatic zero-offset
compensation, true differential inputs, high input impedance, and capability for 4 1/2-digit accuracy.
Applications include the conversion of analog data from high-impedance sensors of pressure, temperature,
light, moisture, and position. Analog-to-digital-Iogic conversion provides display and control signals for
weight scales, industrial controllers, thermometers, light-level indicators, and many other applications.
~~~~~~~~i~ar~:I~tl~ ~!~:i~~ti:r :I~o::~:~:t::s~s not INSTRUMENTS
TL500C THRU TL503C
ANALOGTODlGlTALCONVERTER BUILDING BLOCKS
principles of operation
The basic principle of dual-slope-integrating converters is relatively simple. A capacitor, CX, is charged
II
c
through the integrator from VCT for a fixed period of time at a rate determined by the value of the unknown
voltage input. Then the capacitor is discharged at a fixed rate (determined by the reference voltage) back
to VCT where the discharge time is measured precisely. The relationship of the charge and discharge values
are shown below (see Figure 1).
...
Q)
Q)
Vlt1
l> Vcx VCT - - - Charge (1 )
n
.Q RX Cx
c::: Vref t2
Cir VCT Vcx- - - - Discharge (2)
;::;'"
o RX Cx
::l Combining equations 1 and 2 results in:
n
::;. VI t2
n
c:::
;::;'. Vref t1 (3)
en
where:
VCT = Comparator (offset) threshold voltage
VCX = Voltage change across Cx during t1 and during t2 (equal in magnitude)
VI = Average value of input voltage during t1
t1 = Time period over which unknown voltage is integrated
t2 = Unknown time period over which a known reference voltage is integrated.
Equation (3) illustrates the major advantages of a dual-slop converter:

a. Accuracy is not dependent on absolute values of t1 and t2, but is dependent on their ratios. Long-
term clock frequency variations will not affect the accuracy.
b. Offset values, VCT, are not important.
The BCD counter in the digital processor (see Figure 2) and the control logic divide each measurement
cycle into three phases. The BCD counter changes at a rate equal to one-half the oscillator frequency.
autozero phase
The cycle begins at the end of the integrate-reference phase when the digital processor applies low levels
to inputs A and B of the analog processor. If the trigger input is at a high level, a free-running condition
exists and continuous conversions are made. However, if the trigger input is low, the digital processor
stops the counter at 20,000, entering a hold mode. In this mode, the processor samples the trigger input
every 4000 oscillator pulses until a high level is detected. When this occurs, the counter is started again
and is carried to completion at 30,000. The reference voltage is stored on reference capacitor Cref,
comparator offset voltage is stored on integration capacitor CX, and the sum of the buffer and integrator
offset voltages is stored on zero capacitor CZ. During the auto-zero phase, the comparator output is
characterized by an oscillation (limit cycle) of indeterminate waveform and frequency that is filtered and
d-c shifted by the level shifter.
integrateinput phase
The auto-zero phase is completed at a BCD count of 30,000, and high levels are applied to both control
inputs to initiate the integrate-input phase. The integrator charges eX for a fixed time of 10,000 BCD counts
at a rate determined by the input voltage. Note that during this phase, the analog inputs see only the high
impedance of the noninverting operational amplifier input. Therefore, the integrator responds only to the
difference between the analog input terminals, thus providing true differential inputs.
2-72 TEXAS ~
INSTRUMENTS
TL500C THRU TL503C
ANALOGTODlGITALCONVERTER BUILDING BLOCKS
integrate-reference phase
At a BCD count of 39,999 + 1 = 40,000 or 0, the integrate-input phase is terminated and the integrate-
reference phase is begun by sampling the comparator output. If the comparator output is low corresponding
to a negative average analog input voltage, the digital processor applies a low and a high to inputs A and
B, respectively, to apply the reference voltage stored on Cref to the buffer. If the comparator output is
high corresponding to a positive input, inputs A and 8 are made high and low, respectively, and the negative
II
....tn
of the stored reference voltage is applied to the buffer. In either case, the processor automatically selects '5
the proper logic state to cause the integrator to ramp back toward zero at a rate proportional to the reference ...
(,)
voltage. The time required to return to zero is measured by the counter in the digital processor. The phase C3
is terminated when the integrator output crosses zero and the counter contents are transferred to the c:
register, or when the BCD counter reaches 20,000 and the over-range indication is activated. When' o
activated, the over-range indication blanks all but the most significant digit and sign. '+i
'U;
Seventeen parallel bits (4-1/2 digits) of information are strobed into the buffer register at the end of the '5
C'
integration phase. Information for each digit is multiplexed out to the BCD outputs (TL503C) or the seven- (,)
segment drivers (TL502C) at a rate equal to the oscillator frequency divided by 400. cd:
BCb COUNTER VALUES ....coco
20,000 30,000 o 20,000 30,000 o 20,000 C
: AUTO ZERO
I
iI INTEGRATE:
INPUT
INTEGRATE
REFERENCE
I I AUTO ZERO I INTEGRATE
I INPUT
II INTEGRATE
REFERENCE
: I I I I I
I I HOLD I : I
: I : I I I I I
INTEGR~TOR : :
_1 ___ I
1
II I
V(pinlV(pin2) ______ oJI
I
OUTPUT I I I I I (POSITIVE ,ANALOG VOLTAGE)
I I V (pin 1) < V (pin 2) I I I I I
I I (NEGATIVE ANALOG VOLTAGE) I - - r - -- - - - V(pin 2)
: : I 1 I I I
I I I I I I
I I I I 1 I
I I
I I
I I
__ ______~~------------~ __ 0)
I I
mMM~~ ~
: I I I I
I I
i
I
CONTRO,-=L;.;.A~_--,
:- ~-------T--i-----'
I
I
I
I
L-- - --
I
ov
I
I
I
\ I I I I
I I I I \
CONTRO:-:IL_B_ _--'!
I
l-:---J___
I I
---l 1______
I
0)
I
TRIGGER
I
~QS88&l JJ.
I I
--.::~'"7'II:~:-7'I:-7'I:-7'IDO~N.,.~r"'7'C~t'"A..,.Rt'"E~~~"7'II:....,.. i
I
oj
I
*This step is the voltage at pin 2 with respect to analog ground.
FIGURE 1. VOLTAGE WAVEFORMS AND TIMING DIAGRAM
TEXAS
INSTRUMENTS
-1!1 2-73
'"
.!..J
.j:>.
ANALOG PROCESSOR
sl!n:lJ!3 UO!l!S!nb:lV elea
DIGITAL PROCESSOR
II :t:--4
TL500 OR TLSOl TL502 OR TLS03 (See Note A) Z ...
:t:- UI
Cx
r------------~-v~+-, ...
c=
=
OSCILLATOR
i i~i 'I ~ I C)n
J
INTEGRATOR INPUT
I --_ ... _.. I Q T:~3~ER ':"'-4
r---- ------,I
OUTPUT
(See Note B)
c=
:11:1
5!c:
I 52-4
I I -4 ...
:t:-U"I
ANALOG 1 ~ ... =
INPUT1-Y-O
ANALOG~
INPUT 2 --y-'" .
an
z
CI.)
(18)
<
m
:11:1
-4
Cz m
-c
0
:11:1
~ ANALOG SWITCH CCI
c:
~-
LOGIC CONTROL
r:iz
C,ef i=
c
~~ I
I
) :2

) C)
~iOr;;1
I"'~:H ...c
I
I
;;C:~
IL _ _ _ _ CCI
I
~~ I I I
'
~
-~z~
~ ~
!TI
-.
L ____ _
L-.e..Nv------J ---
ANALOG
GROUND
- - - fi '
-
DIGITAL
COMMON
_J
I1.. __ _
--ll-------J
DIGIT-ENABLE
OUTPUTS
COMMON
n
;II:;
en
~ (01 THRU 05)
... NOTE5: A. Pin 18 of the TL502 provides an output of fosc (oscillator frequency) + 20,000.
'"'"en B. The trigger input assumes a high level if not externally connected.
'"
FIGURE 2. BLOCK DIAGRAM OF BASIC ANALOG-TO-DIGITAL CONVERTER USING TL500C or TL501C and TL502C or TL503C
ANALOG CONTROLS ANALOG SWITCHES
MODE COMPARATOR
INPUT A AND B CLOSED
Auto Zero
X Oscillation L L 53,54,57,.59,510
Hold t
Integrate Positive H
H H 51,52
Input Negative L
Integrate Lt L H 53, 56, 57
X
Reference Ht H L 53, 55, 58
-
H E High, L E low, X E Irrelevant
t If tl:le trigger input is low at the beginning of the autozero cycle, the system will enter the hold mode. A high level (or open circuit) will signal the digital processor
to continue or resume normal operation.
t This is the state of the comparator output as determined by the polarity of the analog input during the integrate input phase.
TL500C, TL501C
ANALOG PROCESSORS
description of analog processors J DUAL-IN-LlNE PACKAGE

(TOP VIEW)
The TL500C and TL501 C analog processors are
designed to automatically compensate for
internal zero offsets, integrate a differential
voltage at the analog inputs, integrate a voltage
at the reference input in the opposite direction,
ANALOG INPUT 1
ANALOG INPUT 2
REF OUTPUT
REF INPUT
ANALOG GND
VCC+
BUFFER OUTPUT
INTEGRATOR INPUT
III
....en
":l
-
and provide an indication of zero-voltage
Cref+ INTEGRATOR OUTPUT (.)
crossing. The external control mechanism may
Cref- VCC-
be a microcomputer and software routing,
CONTROL B INPUT DIGITAL COMMON
U
discrete logic, or a TL502C or TL503C controller. I:
CONTROL A INPUT ........._ _..r- COMPARATOR OUTPUT o
The TL500C and TL501 C are designed primarily
"';;
for simple, cost-effective, dual-slope analog-to- "C;;
digital converters. Both devices feature true ":l
differential analog inputs, high input impedance, C"
(.)
and an internal reference-voltage source. The TL500C provides 4-1 /2-digit readout accuracy when used
with a precision external reference voltage. The TL501 C provides 100-ppm linearity error and 3-1 /2-digit
accuracy capability. These devices are manufactured using TI's advanced technology to produce JFET, ....COCO
MOSFET; and bipolar devices on the same chip. The TL500C and TL501 C are intended for operation over
the temperature range of OoC to 70C.
C
schematics of inputs and outputs

CONTROL A AND CONTROL B INPUTS' COMPARATOR OUTPUT
OUTPUT
INPUT
DIGITAL
COMMON
Positive supply voltage, VCC + (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. + 18 V
Negative supply voltage, VCC ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-18 V
Input voltage, VI .......................................................... VCC
Comparator output voltage range (see Note 2) ............................. , 0 V to VCC +
Comparator output sink current (see Note 2) .................................... 20 mA
Buffer, reference, or integrator output source current (see Note 2) .................... 10 mA
Total dissipation at (or below) 25C free-air temperature (see Note 3) . . . . . . . . . . . . . .. 1025 mW
Operating free-air temperature range ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - ooC to 70C
Lead temperature 1,6 mm (1/1 6 inch) from case for 60 seconds. . . . . . . . . . . . . . . . . . . . .. 300C
NOTES: 1. Voltage values, except differential voltages, are with respect to the analog ground common pin tied together.
2. Buffer, integrator, and comparator outputs are not short-circuit protected.
3. For operation above 25C free-air temperature, refer to Dissipation Derating Curves, Appendix A. TL500C and TL501 C chips
are glass mounted.
TEXAS . . 2-75
INSTRUMENTS
TL500C, TL501C
ANALOG PROCESSORS

MIN NOM MAX UNIT
III
c
C)
Positive supply voltage, Vcc +
Negative supply voltage, VCC-
Reference input voltage, Vref(l)
Analog input voltage, VI
7
-9
0.1
12
-12
15
-15
5
5
V
V
V
V
r+ Differential analog input voltage, VID 10 V
C)
High-level input voltage, VIH I Control inputs' 2 V

(')
Low-level input voltage, VIL I Control inputs 0.8 V
.c Peak positive. integrator output voltage, YOM + +9 V
I: Peak negative integrator output voltage, VOM- -5 V
(ii'
Full scale input voltage 2 Vref
;::;"
0' Autozero and reference capacitors, Cz and Cref 0.2 "F
::s Integrator capacitor, Cx 0.2 "F
(") Integrator resistor, RX 15 100 kfl
:;' See
(') Integrator time constant, RXCX
I: Note 4
;::;" Free-air operating temperature, T A a 70 C
en Maximum conversion rate with TL502 or TL503 3 12.5 conv/sec
system electrical characteristics at VCC = 12 V, Vref = 1,000 0.03 mV, TA = 25C

(unless otherwise noted) (see Figure 3)
TL501C TL500C
Zero error 50 300 10 30 "V
Linearity error relative to full scale VI = -2 V to 2 V 0.005 0.05 0.001 0.005 %FS
Full scale temperature coefficient TA = ooC to 70C 6 6 ppm/DC
Temperature coefficient of zero error TA = Ooc to 70C 4 1 ltV/DC
Rollover error t 200 500 30 100 "V
Equivalent peak-to-peak input noise voltage 20 20 "V
Analog input resistance Pin 1 or 2 109 109 fl
Common-mode rejection ratio VIC = - 1 V to + 1 V 86 90 dB
Current into analog input VI = 5 V 50 50 pA
Supply voltage rejection ratio 90 90 dB
tRoliover error is the voltage difference between the conversion results of the full-scale positive 2 volts and the full-scale negative 2 volts.
NOTE 4. The minimum integrator time constant may be found by use of the following formula:
VID (full scale) t1

Minimum RXCX =IVOM-I-VI(pin 2)
where
VID = voltage at pin with respect to pin 2

VI(pin 2) = voltage at pin 2 with respect to analog ground
t1 = input integration time seconds
2-76 TEXAS
INSTRUMENTS
-111
TL500C, TL501C
ANALOG PROCESSORS
electrical characteristics at Vee = 12 V, Vref 1 V, TA 25e (see Figure 3)
integrator and buffer operational amplifiers

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input offset voltage 15 mV
VIO
liB Input bias current 50 pA ...
tn
VOM+
VOM-
AVO
Positive output voltage swing
Negative output voltage swing
Voltage amplification
9
-5
11
-7
110
V
V
dB
.
'5
Co)
C3
B1 Unity-gain bandwidth 3 MHz :
CMRR Common mode rejection VIC = -1 V to + 1 V 100 dB o
'';:;
SR Output slew rate 5 V/p.s
';j)
'5
comparator C"
Co)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT <t
VIO
liB
Input offset voltage
Input bias current
15
50
mV
pA
... CO
CO
AVO Voltage amplification 100 dB C
VOL Low-level output voltage IOL - l.ti mA ZUU 400 mV
IOH High-level output current VOH = 3 V 5 20 nA
voltage reference output

Vref(O) Reference voltage 1.12 1.22 1.32 V
Reference-voltage
aVref TA = ooC to 70C 80 ppm/oC
temperature coefficient
ro Reference output resistance 3 n
logic control section

PARAMETER TEST CONDITIONS MIN TYP MAX
IIH High-level input current VIH = 2 V 1 10
IlL Low-level input current VIL - 0.8 V -40 300
total device
ICC+ Positive supply current 15 20
ICC- Negative supply current 12 18
TEXAS "'!} 2-77

INSTRUMENTS
TL500C, TL501C
ANALOG PROCESSORS

12 V -12V 5V
IIfJ
C
Q)
PRECISION
100kn (1)
}
(16)
VCC+
ANALOG
(12)
VCC-
COMPARATOR (10)
OUTPUT
2
kn
MPU
r+ VOLTAGE 100kn (2) INPUTS (9) LOGIC
Q) SOURCE CONTROL A CONTROLLER
Vref = (See Note C)
l>
(')
1.000 0.03 mV REF
CONTROL B
(S)
.c -= (4) INPUT
c::: (7)
(ii' Cref+ (15)
;::;.' Cref = 1 #IF BUFFER D
(See Note D) OUTPUT t1 = 100 ms
S' (6)
Cref- from
:::l (1Sl INTEGRATOR VIC(fuil scale)t1
(") Cz
Cz = 1 #IF INPUT RXCX = VOM-VI/PIN 2)
::;' (see Note D) Cx = 1 #IF
(') INTEGRATOR
Cz (see Note D)
c::: (17) OUTPUT (13)
;::;.' ANALOG DIGITAL
en
NOTES: C. Tests are started approximately 5 seconds after power-on.

D. Capacitors used are TRW's X363UW polypropylene or equivalent for CX. Cref. and CZ; however for Cref and Cz film-dielectric
capacitors may be substituted.
FIGURE 3. TEST CIRCUIT CONFIGURATION
external-component selection guide

The autozero capacitor Cz and reference capacitor Cref should be within the recommended range of
operating conditions and should have low-leakage characteristics. Most film-dielectric capacitors and some
tantalum capacitors provide acceptable results. Ceramic and aluminum capacitors are not recommended
because of their relatively high-leakage characteristics.
The integrator capacitor Cx should also be within the recommended range and must have good voltage
linearity and low dielectric absorption. A polypropylene-dielectric capacitor similar to TRW's X363UW is
recommended for 4-1 /2-digit accuracy. For 3-1 /2-digit applications, polyester, polycarbonate, and other
film dielectrics are usually suitable. Ceramic and electrolytic capacitors are not recommended.
Stray coupling from the comparator output to any analog pin (in order of importance 17, 18, 14, 7, 6,
13, 1, 2, 15) must be minimized to avoid oscillations. In addition, all power supply pins should be bypassed
at the package, for example, by a O.01-",F ceramic capacitor.
Analog and digital common are internally isolated and may be at different potentials. Digital common can
be within 4 volts of positive or negative supply with the logic decode still functioning properly.
The time constant RXCX should be kept as near the minimum value as possible and is given by the formula:
VID (full scale) 11

Minimum RXCX = IVOM VI(pin2) -1-
where:
VID(fuli scale) = Voltage on pin 1 with respect to pin 2

t1 = Input integration time in seconds
Vl(pin 2) = Voltage on pin 2 with resepct to analog ground
2-78 TEXAS "'I}

INSTRUMENTS
TL502C, TL503C
DIGITAL PROCESSORS
description of digital processors TL502 ... N DUAL-IN-LiNE PACKAGE

(TOP VIEW)
The TL502C and TL503C are control logic
CONTROL B OUTPUT VCC
devices designed to complement the TL500C
01 (LSB) CONTROL A OUTPUT
and TL501 C analog processors. They feature
DIGIT 02 20,OOot
interdigit blanking, over-range blanking, an
internal oscillator, and a fast display scan rate.
The internal-oscil.lator input is a Schmitt trigger
circuit that can be driven by an external clock
ENABLE
OUTPUTS{
03
04
05 (MSB)+
OSCILLATOR INPUT
TRIGGER
COMPARATOR INPUT
-...
'5
en
(J
pulse or provide its own time base with the 7-SEGMENT{A

DRIVER B
G}7-SEGMENT
F DRIVER
u
addition of a capacitor. The typical oscillator c
OUTPUTS C DE OUTPUTS
frequency is 120 kHz with a 470-picofarad DIGITAL COMMON ~_---'r-
o
'';:
capacitor connected between the oscillator input 'U;
and ground. '5
TL503 ... N DUAL-INLINE PACKAGE C'
The TL502C provides seven-segment-display (TOP VIEW) (J
output drivers capable of sinking 100 ~
milliamperes and compatible with popular
common-anode displays. The TL503C has four
BCD output drivers capable of 100-milliampere
sink currents. The code (see next page and
E;;;'R{OL Bg~~~~ I
OUTPUTS 04
4
1 U16
2
3
15
14
13
VCC
CONTROL A OUTPUT
OSCILLATOR INPUT
TRIGGER
-
C
CO
CO
Figure 4) for each digit is multiplexed to the 5 12 COMPARATOR INPUT

05 (MSB)+ 6 11 03
output drivers in phase with a pulse on the
00 7 10 02
appropriate digit-enable line at a digit rate equal
to fos c . divided by 200. Each digit-enable output
DIGITAL COMMON 8 90 01
is capable of sinking 20-milliamperes. t Pin 18 of TL502 provides an output of fos c (oscillator frequencies)
320,000. I
The comparator input of each device, in addition
+05, the most significant bit, is also the sign bit.
to monitoring the output of the zero-crossing
detector in the analog processor, may be used
in the display test mode to check for wiring and
display faults. A high logic level (2 to 6.5 volts)
at the trigger input with the comparator input at
or below 6.5 volts starts the integrate-input
phase. Voltage levels equal to or greater than 7.9
volts on both the trigger and comparator inputs
clear the system and set the BCD counter to
20,000. When normal operation resumes, the
conversion cycle is restarted at the auto zero
phase.
These devices are manufactured using 12L and
bipolar techniques. The TL502C and TL503C are
intended for operation from OOC to 70C.
TABLE OF SPECIAL FUNCTIONS

VCC - 5 V 10%
TRIGGER COMPARATOR
FUNCTION
INPUT INPUT
VI I :s0.8 V VI:s6.5 V Hold at auto-zero cycle after completion of conversion
2 V:sVI:s6.5 V VI:s6.5 V Normal operation (continuous conversion)
VI:s6.5 V Vp~:7.9 v Display Test: All BCD outputs high
VI?::7.9 V VI:s6.5 V Internal Test
Both inputs to go VI?:: 7.9 V System clear: Sets BCD counter to 20,000.
simultaneously When normal operation is resumed, cycle begins with Auto Zero.
TEXAS . . 2-79
INSTRUMENTS
TL502C. TL503C
DIGITAL PROCESSORS
DIGIT 5 (MOST SIGNIFICANT DIGIT) CHARACTER CODES
TL502C SEVEN-SEGMENT LINES TL503C BCD OUTPUT LINES

CHARACTER 03 02 01 00
A B C D E F G
8 4 2 1
+ H H H H L L L H L H L
c
S
+1 H L L H L L L H H H L
r+ - L H H L H H L H L H H
S -1 L L L L H H L H H H H
l>
n DIGITS 1 THRU 4 NUMERIC CODE (See Figure 41
.c
c TL502C SEVEN-SEGMENT LINES TL503C BCD OUTPUT LINES
C;;"
::;'" NUMBER 03 02 01 00
A B C D E F G
0" 8 4 2 1
:::J 0 L L L L L L H L L L L
(') 1 H L L H H H H L L L H
:::;" 2 L L H L L H L L L H L
n
c 3 L L L L H H L L L H H
::;'"
en 4 H L L H H L L L H L L
5 L H L L H L L L H L H
6 L H L L L L L L H H L
7 L L L H H H H L H H H
8 L L L L L L L H L L L
9 L L L L H L L H L L H
H = high level. L = low level

COMPARATOR AND TRIGGER INPUT SEGMENT DRIVERS-TL502C
BCD DRIVERS-TL503C
r---~~----~--------------VCC VCC - - - ---------------~
DISPLAY 750fl
. / " " " - - - - - - -- TEST OR
SYSTEM
CLEAR
5kfl 1kfl
INPUl
~~~~~~~------COMMON
rh~.........- - - - I
COMMON - - - ----------~--.....
CONTROL A AND B OUTPUTS DIGIT-ENABLE OUTPUTS

VCC
VCC- - - - -.......- - - - - - - - ,
1kfl
16.8 kfl 10kfl PUT
OUTPUT
1kfl ~
v
110 fl *
V'
.....
4.4 kfl 5kfl
1 kfl
COMMON--~---~------~
COMMON-
~
Shorted on TL503C
2-80 TEXAS . .
INSTRUMENTS
TL502C, TL503C
DIGITAL PROCESSORS
absolute maximum ratings

Supply voltage, Vcc (see Note 5) 7 V
Input voltage, VI
Output current
Oscillator
Comparator or Trigger
BCD or Segment drivers
Digit-enable outputs
5.5
9
120
40
V
mA
Ell
....en
Pin 18 (TLC502 only) 20 'S
Total power dissipation at (or below) 30C free-air temperature (see Note 6) 1100 mW ...
(J
Operating free-air temperature range o to 70 C U

Storage temperature range -65 to 150 C c
Lead temperaturee 1,6 mm (1116 inch) from case for 10 seconds 260 C o
'.;:i
'Ci)
NOTES: 5. Voltage values are with respect to the network ground terminal.
6. For operation above 30C free-air temperature, derate linearly at the rate of 9.2 mW/oC. 'S
0"
(J
CO
MIN NOM MAX UNIT ....CO
Supply voltage, VCC 4.5 5 5.5 V
C
High-level input voltage, VIH I Comparator and trigger inputs 2 V
Low-level input voltage, VIL I Comparator and trigger inputs 0.8 V
Operating free-air temperature 0 70 c
TEXAS 2-81
INSTRUMENTS
N
Sl!n:>J!:l UO!l!S!nb:>v elea
00
N
CI-I
-r-
electrical characteristics at 2-5C free-air temperature C)Ut
=t~
PARAMETER TERMINAL TEST CONDITIONS
MIN
TL502C
TYP MAX MIN
TL503C
TYP MAX
UNIT ~~
-0-1
VIK Input clamp voltage All inputs VCC = 4.5 V, II = -12 rnA -0.8 -1.5 -0.8 -1.5 V :::a r-
oUt
Positive-going input nCl
VT+
threshold voltage
Oscillator VCC = 5V 1.5 1.5 V mW
enn
Negative-going input
=
en
VT-
threshold voltage
Oscillator VCC 5 V 0.9 0.9 V o
:::a
VT+ - VT- Hysteresis Oscillator VCC = 5 V 0.4 0.6 0.8 0.4 0.6 0.8 en
Input current at
IT+ positive-going input Oscillator VCC = 5 V -40 -94 -170 -40 -94 -170 p.A
threshold voltage
Input current at
-a
0 IT- negative-going input Oscillator VCC = 5 V 40 117 170 40 117 170 p.A
~ threshold voltage
~-
i:iz
Digit enable 4.15 4.4 4.15 4.4
VOH High-level output voltage Pin 18 (TL502C only) VCC = 4.5 V, IOH = 0 4.25 4.4 V
~~ Control A and B 4.25 4.4 4.25 4.4

~;o~ Digit enable IOL = 20 rnA 0.2 0.5
c:~
::;~ VOL Low-level output voltage
Pin 18 (TL502C only)
Control A and B VCC = 4.5 V
IOL
IOL
=
=
10mA
2 rnA
0.15
0.088
0.4
0.4 0.088 0.4 V
~ !T1 Segment drivers IOL = 100 rnA 0.17 0.3
~z
~ ~.ct
BCD drivers IOL = 100 rnA 0.17 0.3
Comparator, Trigger 65 100 65 100 p.A
~ II Input current VCC = 5.5 V, VI = 5.5 V
.... Oscillator 1 1 rnA
'"'"en Comparator, Trigger -0.6 -1 -0.6 -1
'" IIH High-level input current VCC = 5.5 V, VI = 2.4 V rnA
Oscillator 0.5 0.5
Oscillator -0.1 -0.17 -0.1 -0.17
IlL Low-level input voltage VCC = 5.5 V, VI = 0.4 V
-1
rnA
Comparator, Trigger -1 -1.6 -1.6
Digit enable Vo = 0.5 V, -2.5 -4 -2.5 -4
Pin 18 (TL502C only) Vo = 0.5 V -0.5 -0.9
High-level output current
IOH Control A and B VCC = 4.5 V Vo = 0.5 V -0.25 -0.4 -0.25 -0.4 rnA
(Output transistor off)
Segment drivers Vo = 5.5 V 0.25
BCD drivers Vo = 5.5 V 0.25
Low-level output current
IOL Digit enable VCC = 4.5 V, Vo = 3.55 V 18 23 rnA
(Output transistor on)
ICC Supply current
- - - -
VCC ____ ~C = 5.5V - - -
73 110 73 110 rnA
TL502C, TL503C
DIGITAL PROCESSORS
special functions t operating characteristics at 25C free-air temperature

PARAMETER TEST CONOITIONS MIN TYP MAX
Input current into
comparator or trigger inputs
Vee
Vee
= 5.5
=
V.
5.5 V.
V, = 8.55 V
V, = 6.25 V
1.2 1.8
0.5
tThe comparator and trigger inputs may be used in the normal mode or to perform special functions. See the Table of Special Functions.
fI ....
t/)
'5
...
(,)
TYPICAL APPLICATION DATA U

t:
o
'';:;
01 --------~
I --I~~--~~~~--~~--------------------------------------------
-- 16.7 /JS (see Note E) 'm
'5
~316.7 /Js-----t : C'
(,)
I
02-----------------------, ....COCO
C
03----------------------------------~
04-----------------------------------------------------,
05--------------------------------------------------------------------, r--
L.....-----t l
NOTE E: The BCD or seven-segment driver outputs are present for a particular digit slightly before the falling edge of that digit enable.
FIGURE 4. TL502C, TL503C DIGIT TIMING WITH 120-kHz CLOCK SIGNAL AT OSCILLATOR INPUT
TEXAS 2-83
INSTRUMENTS
II
c
C)
r+
C)
l>
(')
.c
c
;"
;::;.."
0"
::J
(")
::;"
(')
c
;::;..-
o
2-84
TL505C
ANALOG-TO-DIGITAL CONVERTER
02366. OCTOBER 1977 - REViSED SEPTEMBER 1986
N DUAL-IN-lINE PACKAGE
3-Digit Accuracy (0.1 %)
(TOP VIEW)
FJ
10-Bit Resolution
VCC ZERO CAP 2
Automatic Zero ANALOG IN ZERO CAP 1
Internal Reference Voltage REF OUT INTEG RES
t/)
REF IN INTEG IN +oJ
Single-Supply Operation GND INTEG OUT S
High-Impedance MOS Input BIN GND ...o
AIN CaMP OUT C3
Designed for Use with TMS1000 Type
c
Microprocessors for Cost-Effective o
High-Volume Applications '';:'
'en
BI-MOS Technology 'S
C-
Only 40 mW Typical Power Consumption O
<3:
CO
+oJ
Caution. This device has limited built-in gate protection. The leads should be shorted together or the device CO
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. C
description
The TL505C is an analog-to-digital converter building block designed for use with TMS1000 type
microprocessors. It contains the analog elements (operational amplifier, comparator, voltage reference,
analog switches, and switch drivers) necessary for a unipolar automatic-zeroing dual-slope converter. The
logic for the dual-slope conversion can be performed by the associated MPU as a software routine or it
can be implemented with other components such as the TL502 logic-control device.
The high-impedance MOS inputs permit the use of less expensive, lower value capacitors for the integration
and offset capacitors and permit conversion speeds from 20 per second to 0.05 per second.
The TL505C is a product of TI's BI-MOS process, which incorporates bipolar and MOSFET transistors on
the same monolithic circuit. The TL505C is characterized for operation from OOC to 70C.
PRODUCTION DATA documents contain information Copyright 1983. Texas instruments incorporated
=~~~~:~~i~ai~:I~lj8 ~!~~~~ti:r fI~o::::~:t:~~s not
TEXAS 2-85
INSTRUMENTS
TL505C
ANALOGTODlGlTAL CONVERTER
RX
II
c
(121 (111
------r-----:
(101 VCCI1I
I
I
....
Q)
Q)
I
1(81
>-........- - - Q COMP
:t>
(")
OUT
.c
c
Cij"
~
0" Cz
::::s
o
:::;" (21'
I
S3A
B
(") ANALOG~ 1(71

A
c INPUT I
I I
;:;: (311 I
C/l
L ______________________ ~---e-J
(51 (91
GND GND
NOTE: Analog and digital GND are internally connected together.
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 18 V
Input voltage, pins 2, 4, 6, and 7 .............................................. VCC
Continuous total dissipation at (or below) 25 DC free-air temperature (see Note 2). . . . . . .. 875 mW
Operating free-air temperature range ..................................... , ooC to 70 DC
Storage temperature range ..................... ~ . . . . . . . . . . . . . . . . . .. - 65 DC to 150 DC
NOTES: 1. Voltage values are with respect to the two ground terminals connected together.
2. For operation above 25e free-air temperature, derate linearly to 560 mW at 70 0 e at the rate of 7.0 mW/oe.

MIN NOM MAX UNIT
Supply voltage, Vee 7 9 15 V
Analog input voltage, VI 0 4 V
Reference input voltage, Vref(l) 0.5 3 V
High-level input voltage at A or B, VIH 3.6 Vee+ 1 V
Low-level input voltage at A or B, VIL 0.2 1.8 V
Integrator capacitor, eX See "component selection"
Integrator resistor, RX 0.5 2 M!l
Integration time, tl ) 16.6 500 ms
Operating free-air temperature, T A 0 70 e
2-86 TEXAS . .
INSTRUMENTS
TL505C
ANALOGTODIGITAL CONVERTER
electrical characteristics, Vee = 9 V, Vref(l) 1 V, TA 25C, connected as shown in Figure 1

VOH
IOH
VOL
PARAMETER
High-level output voltage at pin 8
High-level output current at pin 8
Low-level output voltage at pin 8
IOH = 0
TEST CONDITIONS
VOH = 7.5V
IOL = 1.6 mA
MIN
7.5
TYP
8.5
-100
200
MAX
400
UNIT
V
p.A
mV
Ell ....en
YOM
Vref(O)
Maximum peak output voltage
swing at integrator output
Reference output voltage
RX ~ 500 kf!
Iref = -100 p.A

VCC-2 VCC-l
1.15 1.22 1.35

V
V
.
"5
C3
(J
Temperature coefficient of
aVref T A = OoC to 70C 100 ppm/oC c
reference output voltage o
"';::;
IIH High-level input current into A or B VI = 9 V 1 10 p.A
Low-level input current into A or B VI = 1 V 10 200 p.A
"C;;
IlL
II Current into analog input VI = 0 to 4 V, A input at 0 V 10 200 pA
"5
C-
lIB Total integrator input bias current 10 pA (J
ICC Supply current No load 4.5 8 mA

system electrical characteristics, Vee 9 V, Vref(l) 1 V, T A = 25C, connected as shown in
....COCO
Figure 1 (unless otherwise noted) C
Zero error VI = 0 0.1 0.4 mV
Linearity error VI = 0 to 4 V 0.02 0.1 %FS
Ratiometric reading VI = Vref(l) "" 1 V 0.998 1.000 1.002
Temperature coefficient of Vref(1) constant and "" 1 V,
10 ppm/oC
ratiometric reading TA = OC to 70C
DEFINITION OF TERMS
Zero Error
The intercept (b) of the anolog-to-digital converter system transfer function y = mx + b, where y is the
digital output, x is the analog input, and m is the slope of the transfer function, which is approximated
by the ratiometric reading.
Linearity Error
The maximum magnitude of the deviation from a straight line between the end points of the transfer function.
Ratiometric Reading
The ratio of negative integration time (t2) to positive time (q).
TEXAS ~ 2-87
INSTRUMENlS
POST OFFICE BOX 655012 DAl~AS, TEXAS 75265
TL505C
A block diagram of an MPU system utilizing the TL505C is shown in Figure 1. The TL505C operates in
lEI
C
a modified positive-integration three-step dual-slope conversion mode. The AID converter waveforms during
the conversion process are illustrated in Figure 2.
VCC
,..r RX Cx
r

(')
(1-01---- (1")---]
I
.c I
c I
'(8)
C;;' ~",-----c~--+--1IN
;=;.'
0'
::s S2C
MPU
('") CONTROLLER
~' Cz :
(') 'I'F '
c (14): S3A LOGIC DECODE
;::;.' ANALOG~ AND
en INPUT (2): SWITCH DRIVERSI--<r--.:------4~B
(3). :
L----------------------;q.(51-~-J
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF TL505C INTERFACE WITH A MICROPROCESSOR SYSTEM
FUNCTION TABLE
A-------4 I
I
CONTROLS ANALOG
I A B SWITCHES CLOSED
B------~
I I L L 51.52
I
I I H H 53
-V2 I L H 51.54
H = VIH. L = VIL
INTEGRATOR V,- rVo(ofs)

OUTPUT -.. IT
COMPARATOR 111.1I1~\1tll'1Tl1lMImm\
OUTPUT W~~nn'UIlI\IIIUM~Ulli~------~--~I.Mml... "
I I I
--to---+t,I....---t, ,1. t2-.~I,~--to--
v, - V2 - V3" VI + VO(ofs)
FIGURE 2. CONVERSION PROCESS TIMING DIAGRAMS
2-88 TEXAS
INSTRUMENTS
-1!1
TL505C
ANALOGTODlGITAL CONVERTER
The first step of the conversion cycle is the auto-zero period to during which the integrator offset is stored
in the auto-zero capacitor and the offset of the comparator is stored in the integrator capacitor. To
accomplish this, the MPU takes the A and 8 inputs both low. This is decoded by the switch drivers, which
Ell
-...
close S1 and S2. The output of the comparator is connected to the input of the integrator through the
low-pass filter consisting of RZ and CZ. The closed loop of A 1 and A2 will seek a null condition where
en
the offsets of the integrator and comparator are stored in Cz and CX, respectively. This null condition '5
(J
is characterized by a high-frequency oscillation at the output of the comparator. The purpose of S28 is
to shorten the amount of time required to reach the null condition. u
At the conclusion of to, the MPU takes the A and 8 inputs both high closing S3 and opening all other c
o
switches. The input signal VI is applied to the noninverting input of A 1 through CZ. VI is then positively '';:;
integrated by A 1. Since the offset of A 1 is stored in CZ, the change in voltage across Cx will be due to 'u)
only the input voltage. It should be noted that since the input is integrated in a positive integration during '5
t1, the output of A 1 will be the sum of the input voltage, the integral of the input voltage, and the comparator
C'
(J
-
<C
offset, as shown in Figure 2. The change in voltage across capacitor Cx (VCX) during t1 is given by
CO
(1 )
CO
C
where R1 = RX + RS38 and
RS38 is the resistance of switch S38.
At the end of 11, the MPU takes the A input low and the 8 input high closing S1 and S4 and opening
all other switches. In this state, the reference is integrated by A 1 in a negative sense until the integrator
output reaches the comparator threshold. At this point, the comparator output goes high. This change
in state is sensed by the MPU, which terminates t2 by again taking the A and 8 inputs both low. During
t2, the change in voltage across Cx is given by
(2)
where R2 = RX + RS4 + Rref and

Rref is the equivalent resistance of the reference divider.
Since AVCX1 = -AVCX2, equations (1) and (2) can be combined to give
R1 ' t2 (3)
VI = Vref R2 11
This equation is a variation on the ideal dual-slope equation, which is

(4)
Ideally then, the ratio of R1/R2 would be exactly equal to one. In a typical TL505C system where
RX = 1 MO, the scaling error introduced by the difference in R1 and R2 is so small that it can be neglected
and equation (3) reduces to (4).
TEXAS
INSTRUMENTS
-1!1 2-89
TL505C
ANALOGTOD1GITAL CONVERTER
TYPICAL APPLICATION DATA

9V
Cx
RX
c
....
Q)
Q)
ANALOG
COMP
SIGNAL OUT
K(X)
l>
(')
SEE NOTE 3
.Q TMS1000
TL505 10
t: 10kn
SERIES
(ii' kn
;:;"
LOGIC
0'
j
.A
CONTROL
R8
SEGMENT
DRIVE -'1-'1-'
n
::;'
(')
B
LINES
R9
DIGIT
DRIVE
1= 1_11_1
t: FULL-SCALE TIL312 LED
S' ADJUST '::' DISPLAYS
NOTE 3: Connect to either 9 V or 0 V depending on which device in the TMS1 000 series is used and how it is programmed.
FIGURE 3. TL505C IN CONJUNCTION WITH A TMS1000 SERIES MICROPROCESSOR

FOR A 3-DIGITAL PANEL METER APPLICATION
12V 5V
2.2 kn
56 n 1N914 1N914
VCC VCC 02
1 kf! COMP/LAMP
ANALOG COMP 2.2kn TlS91
INPUT TEST 01
FROM OUT A A
AUDIO Sf!
OS REF
IN B B
IJF
SYSTEM OSC
TL505 470 pF INPUT d
TL502
=
GND RX2 J
33kn
b
CZ1
RX1/C X1
6.81JF
0.22 a b c d e f 0,0102
CZ2
/.IF v
CX2 SEGMENT
GND GND TIL807
=
FIGURE 4. AUDIO PEAK POWER METER
2-90 TEXAS
INSTRUMENTS
-III
POST OFFiCe BOX 655012 OALLAS, TeXAS 75265
TL5071, TL507C
D2503, OCTOBER 1979-REVISED SEPTEMBER 1986
DB
o low Cost P DUALIN-L1NE PACKAGE
(TOP VIEW)
7-Bit Resolution

ENABLE
ClK
GND
OUTPUT
2
3
4
6
5
7
RESET
VCC2
VCC1
ANALOG INPUT
fI....
U)
Conversion Speed ... Approximately 1 ms '5

Single-Supply Operation ... Either FUNCTION TABLE
...o
Unregulated 8-V to 18-V (VCC2 Input). or i:3
Regulated 3.5-V to 6-V (VCC1 Input) ANALOG
ENABLE OUTPUT c
INPUT CONDITION o
12 l Technology Lt H
',tj
X 'iii
Power Consumption at 5.V ... 25 mW Typ VI < 200 mV H L '5
V ramp > VI > 200 mV H H C-
Regulated 5.5-V Output (::;; 1 rnA) O
description
VI> V ramp H L

The Tl507 is a low-cost single-slope analog-
tLow level on enable also inhibits the reset function.
H = high level, L = low level, X = irrelevant
....coCO
to-digital converter designed to convert analog
A high level on the reset pin clears the counter to zero, which sets
C
input voltages between 0.25 VCC1 and 0.75 the internal ramp to 0.75 Vee. Internal pull down resistors keep
VCC1 into a pulse-width-modulated output the reset and enable pins low when not connected.
code. It contains a 7-bit synchronous counter,
a binary weighted resistor ladder network, an operational amplifier, two comparators, a buffer amplifier,
an internal regulator, and necessary logic circuitry. Integrated-injection logic (l 2 l) technology makes it
possible to offer this complex circuit at low cost in a small dual-in-line 8-pin package.
In continuous operation, it is possible to obtain conversion speeds up to 1000 per second. The Tl507
requires external signals for clock, reset, and enable. Versatility and simplicity of operation, coupled with
low cost, make this converter especially useful for a wide variety of applications.
The Tl507C is characterized for operation from 0 C to 70 C, and the Tl5071 is characterized for operation
from - 40C to 85 C.

COMPARATOR 2
ANALOG~(5~) __________________________________~~
INPUT
CTR
R R
MSB~
2R
~
4R
+ ~
8R
~
16R
~
32R
R ~ REGULATOR
64R
LSB~
(7)
VCC2
0.25 VCC1 (6)

VCC1
(3)
'------GND
Qindicates an n-p-n open-collector output.
specifications per the terms of Texas Instruments 'TEXAS . . 2-91
necessarily include testing of all parameters. INSTRUMENTS '
TL5071, TL507C
II
EQUIVALENT OF ENABLE EQUIVALENT OF CLOCK EQUIVALENT OF ANALOG
AND RESET INPUTS INPUT INPUT
V C C 1 - - - -....-
o 75kn
Dl
r+
Dl
l> INPUT
~---
1 INPUT
~--
'}---J , INPUT
(')
.c
c
iii"
;:;."
0"
::l
o:::j" OUTPUT
(')
c . .- - - + - - - - V C C l
;:;."
C/l
OUTPUT
Supply voltage, VCC1 (see Note 1) ............................................ 6.5 V
Supply volta~e, VCC2 ....................................................... 20 V
Input voltage at analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6.5 V
Input voltage at enable, clock, and reset inputs .......................... . . . . . . .. 20 V
On-state output voltage ...................................................... 6 V
Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20 V
Continuous total dissipation at (or below) 25C free-air temperature (see Note 2) . . . . . . .. 725 mW
Operating free-air temperature range: TL5071 ............................ - 40C to 85 C
TL507C . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0 C to 70C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260C
NOTES: 1. Voltage values are with respect to network ground terminal unless otherwise noted.
2. For operation above 25C free-air temperature, refer to Dissipation Derating Curves, Appendix A.
2-92 TEXAS ~
INSTRUMENTS
TL5071. TL507C

MIN NOM MAX UNIT
Supply voltage, VCCI
Supply voltage; VCC2
Input voltage at analog input
Input voltage at chip enable, clock, and reset inputs
3.5
8
0
15
5 6
18
5.5
18
V
V
V
V
fI
... tn
High-level input voltage, VIH, reset and enable 2 V '3
Low-level input voltage, VIL, reset and enable 0.8
5.5
V
V
...
CJ
On-state output voltage
Off-state output voltage 18 V
U
0 125 150 kHz
c
Clock frequency, fclock o
'';:
electrical characteristics over recommended operating free-air temperature range, 'Ci)
VCC1 = VCC2 = 5 V (unless otherwise noted) '3
C"
CJ
regulator section

VCCI
PARAMETER
Supply voltage (output) VCC2 =
TEST CONDITIONS
10 to 18 V, ICCI = 0 to -1 mA
MIN
5
TYP*
5.5
MAX
6
UNIT
V
... CO
CO
ICCI Supply current VCCI = 5 V. VCC2 open 5 8 mA o
ICC2 Supply current VCC2 = 15 V, VCCI open 7 10 mA
inputs
PARAMETER TEST CONDITIONS MIN TYP* MAX UNIT
VT+ Positive-going threshold voltage 4.5 V

VT- Negative-going threshold voltage Clock Input 0.4 V
Vhvs Hysteresis (VT + - VT - ) 2 2.6 4 V
IIH High-level input current VI = 2.4 V 17 35 p.A

Reset, Enable, and Clock VI = 18 V 130 220 320
IlL Low-level input current
VI = 0 10 p.A
II Analog input current VI = 4 V 10 300 nA
output section
PARAMETER TEST CONDITIONS MIN" TYP* MAX UNIT
10H High-level output current VOH = l8V 0.1 100 p.A
IOL Low-level output current VOL = 5.5 V 5 10 15 mA
VOL Low-level output voltage IOL = 1.6 mA 80 400 mV
operating characteristics over recommended operating free-air temperature range,

VCC1 = VCC2 = 5.12 V
PARAMETER TEST CONDITIONS MIN TYP* MAX UNIT
Overall error 80 mV
Differential nonlinearity See Figure 1 20 mV
Zero error Binary count = 0 80 mV
Scale error Binary count = 127 80 mV
Full scale input voltage Binary count = 127 3.74 3.82 3.9 V
Propagation delay time from reset or enable 2 p's
; All typical values are at T A = 25 ac.

These parameters are linear functions of VCCI.
TEXAS 2-93
INSTRUMENTS
TL5071, TL507C
definitions
zero error
II
C
III
The absolute value of the difference between the actual analog voltage at the 01 H-to-OOH transition and
the ideal analog voltage at that transition.
overall error
r+
III The magnitude of the deviation from a straight line between the endpoints of the transfer function.
>
(')
differential nonlinearity
.c The maximum deviation of an analog-value change associated with a 1-bit code change (1 clock pulse)
t:
iii" from its theoretical value of 1 LSB.
;:;'"
ci"
:::l
(') PARAMETER MEASUREMENT INFORMATION
:::;"
(')
t: SN74191
;:;'"
(Jj
r----<: P.CLOCK
OUTPUTS
,....- DOWN/UP ~
ANALOG DEVICES
SN74191 AD562
RIPPLE P (or equivalent) 5kn TEST
CLOCK POINT
.-- f-<: ~CLOCK

OUTPUTS
~ DOWN/UP
4
'--- BITS 912
BITS 5-8 DAC

OUT
1~ (
TL507
ANALOG
INPUT
r - - - BITS 1-4
rVSINGLE
-::-
CLOCK-
PULSE
OUTPUT
P. CLOCK
-
SN74191
RIPPLE
CLOCK P
100 kHz
CLOCK .r '> CLOCK
INPUT OUTPUTS -4-
~ DOWN/UP
.
FIGURE 1. MONOTONICITY AND NONLINEARITY TEST CIRCUIT
2-94 TEXAS
INSTRUMENTS
-1!1
poSt OFFICE BOX 665012 DALLAS, TEXAS 75265
TL5071, TL507C
II
The TL507 is a single-slope analog-to-digital converter. All single-slope converters are basically voltage-
to-time or current-to-time converters. A study of the functional block diagram shows the versatility of
the TL507.
An external clock signal is applied through a buffer to a negative-edge-triggered synchronous counter. Binary- ....
U)
weighted resistors from the counter are connected to an operational amplifier used as an adder. The 'S
(,)
operational amplifier generates a signal that ramps from 0.75 VCC1 down to 0.25 VCC1. Comparator 1 "-
compares the ramp signal to the analog input signal. Comparator 2 functions as a fault defector. With U
the analog input voltage in the range 0.25 VCC1 to 0.75 VCC1, the duty cycle of the output signal c
is determined by the unknown analog input as shown in Figure 2 and the Function Table. o
'';:::;
For illustration assume VCC1 = 5.12 V, 'Ci)
'S
0.25 VCC1 1.28 V C'
(,)
(0.75 - 0.25) VCC1 <t
1 binary count
128
20 mV
....caca
0.75 VCC1 - 1 count = 3.82 V C
The output is an open-collector n-p-n transistor capable of withstanding up to 18 volts in the off state.
The output is current limited to the 8- to 12-milliampere range; however, care must be taken to ensure
that the output does not exceed 5.5 volts in the on state.
The voltage regulator section allows operation from either an unregulated 8- to 18-volt VCC2 source or
a regulated 3.5- to 6-volt VCC1 source. Regardless of which external power source is used, the internal
circuitry operates at VCC1. When operating from a VCC1 source, VCC2 may be connected to VCC1 or
left open. When operating from a VCC2 source, VCC1 can be used as a reference voltage output.
- - - 3.B2V
_ _ _ _ ANALOG INPUT
LEVEL 1
RAMP INPUT TO
COMPARATOR 1
_ ANALOG INPUT
LEVEL 2
OUTPUT FOR
INPUT LEVEL 1
OUTPUT FOR
INPUT LEVEL 2
J uuL FIGURE 2
TEXAS
INSTRUMENTS
-1!1 2-95
C
Dl
....
Dl
J>
(')
.c
c
(ii"
:=;."
0"
::l
o
~"
(')
C
:=;."
en
2-96
TL601. TL604. TL607. TL610
PMOS ANALOG SWITCHES
02161, JUNE 1976-REVISEO OCTOBER 1986
Switches 10V Analog Signals P PACKAGE

(TOP VIEW)
TTL Logic Capability
TL601
5 to 30 V Supply Ranges
o Low (100 mOn-State Resistance G N D [ ] 8 VCC+
A 2 7 82
High (10 11 m Off-State Resistance B 3 6 81 ....
(/)
8 VCC-
'S
o aPin Functions
4 5
...
(,)
TL604 C3
description c
o
The TL601, TL604, TL607, and TL610 are a ' G N D [ ] 8 VCC+ ',t:j
A 2 7 81 'C;;
family of monolithic P-MOS analog switches that
81 3 6 82 'S
provide fast switching speeds with hig~ roff/ron
ratio and no offset voltage. The p-channel 82 4 5 VCC- C'
(,)
enhancement-type MOS switches will accept
analog signals up to 10 volts and are controlled TL607

by TTL-compatible logic inputs. The monolithi~ ....COCO
structure is made possible by BI-MOS G N D [ ] 8 VCC+ C
A 2 7 82
technology, which combines p-channel MOS
ENABLE 3 6 81
with standard bipolar transistors.
8 4 5 VCC-
These switches are particularly suited for use in
military, industrial, and commercial applications TL610
such as data acquisition, multiplexers, AID and
D/A converters, MODEMS, sample-and-hold G N D [ ] 8 VCC+
systems, signal multiplexing, integrators, pro- A 2 7 C
grammable operational amplifiers, programmable B 3 6 8
voltage regulators, crosspoint switching 8 4 5 VCC-
networks, logic interface, and many other analog
systems.
TYPICAL OF TYPICAL OF
The TL601 is an SPDT switch with two logic ALL INPUTS ALL SWITCHES
control inputs. The TL604 is a dual
complementary SPST switch with a single
control input. The TL607 is an SPDT switch with
one logic control input and one enable input. The
TL610 is an SPST switch with three logic control
inputs. The TL61 0 features a higher roft/ron ratio
than the other members of the family.
The TL601M, TL604M, TL607M, and TL610M
are characterized for operation over the full
military temperature range of - 55 DC to 125 DC,
the TL6011, TL6041, TL6071, and TL6101 are
characterized for operation from - 25 DC to
85 DC, and the TL601 C, TL604C, TL607C, and
TL610C are characterized for operation from
ODC to 70 DC.
PRODUCTION DATA documents contain information CoPyri9ht 1979, Texas Instruments Incorporated
~~~~~~~~i~a[~~I~tJ~ ~!~~~~ti~r :I~o~:~:~:t:~s~s not
TEXAS ~ 2-97
INSTRUMENTS
TL601, TL604, TL607, TL610
P,MOS ANALOG SWITCHES
logic symbols t and switch diagrams
S1~(7)S1
~
TL601
6)51
II
c
X1 .
1 n
5(4)
(6) 51
(7)52
TL602
S2~S2
(7) S1
....
D)
D)
,. n (7)52
~
(')
.c FUNCTION TABLE FUNCTION TABLE
c LOGIC INPUTS ANALOG SWITCH LOGIC INPUT ANALOG SWITCH
iii'
;:;.' A B S1 S2 A S1 S2
0' t. X OFF (OPEN) ON (CLOSED) H ON (CLOSED) OFF (OPEN)
j X L OFF (OPEN) ON (CLOSED) L OFF (OPEN) ON (CLOSED)
(") H H ON (CLOSED) OFF (OPEN)
:::;'
(')
c TL607 TL610
;:;.'
(f) (4) /(6)
S~-S
FUNCTION TABLE FUNCTION TABLE
INPUTS ANALOG SWITCH INPUTS ANALOG SWITCH

A ENABLE S1 S2 A B C S
X L OFF (OPEN) OFF (OPEN) L X X OFF (OPEN)
L H OFF (OPEN) ON (CLOSED) X L X OFF (OPEN)
H H ON (CLOSED) OFF (OPEN) X x L OFF (OPEN)
H H H ON (CLOSED)
t'rhese symbols are in accordance with ANSI/IEEE Std 91-1984.
TL607 logic diagram (positive logic)

(3)
ENABLE - - - -.......
A (2)
S (4)
2-98 TEXAS ~
INSTRUMENTS
TL601, TL604, TL607, TL610
P-MOS ANALOG SWITCHES
Supply voltage, Vee + (see Note'1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
Supply voltage, Vee _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 30 V
Vee + to Vee - supply voltage differential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 35 V
eontrol input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vee +
Switch off-state voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30 V
II
Switch on-state current .......................... ' ......................... , 10 mA
Operating free-air temperature range: TL601 M, TL604M, TL607M, TL610M . . .. - 55 e to 125e
TL6011. TL6041, TL6071,TL6101 ......... -25e to 85e
TL601e, TL604e, TL607e, TL610e ......... ooe to 70 0 e
Lead temperature (1,6 mm) 1/16 inch from case for 60 seconds: JG package ........... , 300 0 e
Lead temperature (1,6 mm) 1/16 inch from case for 10 seconds: P package. . . . . . . . . . . .. 260 0 e
NOTE 1: All voltage values are with respect to network ground terminal.

TL601M. TL604M TL6011. TL6041 TL601 C. TL604C
TL607M. TL610M TL6071. TL6101 TL607C. TL610C UNIT
MIN NOM MAX MIN NOM MAX MIN NOM MAX
Supply voltage. Vee + (see Figure 1) 5 10 25 5 10 25 5 10 25 V
Supply voltage, Vee _ (see Figure 1) -5 -20 -25 -5 -20 -25 -5 -20 -25 V
Vee + to Vee _ supply voltage differential (see Figure 1) 15 30 15 30 15 30 V
High-level control input voltage, VIH 2 5.5 2 5.5 2 5.5 V
Low-level control input voltage, VIL All inputs 0.8 0.8 0.8
Voltage at any analog switch (S) terminal Vec- +8 VCC+ VCC- +8 VCC+ VCC- +8 VCC+ V
Switch on-state current 10 10 10 mA
Operating free-air temperature, TA -55 125 -25 85 0 70 e
TEXAS . . 2-99
INSTRUMENTS
TL601, TL604, TL607, TL610
2.4V +10V
OR~~OUTPUT ~
-""' ~--5V
INPUT 50% 50%
I I ' - ____ J I OV
-10 V
- - - -
....J RL =
1 kn = J CL = 35 pF
(See Note B)
OUTPUT
ton~
/'
""'90%
toff~
" I -
~O%
Vo
1kn
TEST CIRCUIT VO" (10 V) - - -
1 kn + ron
NOTES: A. The pulse generator has the following characteristics:
Zout = 500, tr :;; 15 ns, tf :;; 15 ns, tw = 500 ns. VOLTAGE WAVEFORMS
B. CL includes probe and jig cap~itance.
FIGURE 2
SWITCH ON-STATE RESISTANCE SWITCH ON-STATE RESISTANCE

vs vs
FREE-AIR TEMPERATURE SWITCH ANALOG VOLTAGE
1000~~-rr----r-----r-----r---~ 1000r-~--~---.---.--.---.---r-~
700~~-+~----~----+-----+---~ 700
400~~~~----~----~----+---~ ~ 400
I
8c
200r-----~~--+_----+_----+_--~ co
.~
GI
100~--~r_----~~~+_----+_--~
a::
~ 100
70~--~+_----~----_r~ __-~--~ ~ 70~~r-~~~~~--~---~~=--;
C
40~----+-----~----~-----+----~
o 40r--1---+---+~~--~--+---+_~
I
c
VCC+= 10V ~
20 VCC- = -20 V-+---+---+---~ 20 ~--I---+---+-__~---+VCC+ = 10 V
VCC- = -20 V
TA = 25C
IO(sw) = 1 rnA
10~----~----~----~----~--~ 10 '-----'-----'-----'----'-----'----'-.,---'-----'
-15 -10 -5 o 5 10 -75 -50 -25 0 25 50 75 100 125
VI (sw)-Switch Analog Voltage-V T A-Free-Air Ternperature-C
FIGURE 3 FIGURE 4
2-100
INSTRUMENTS
TEXAS "'!1
'POST OFFICE BOX 655012 DALLAS. TEXAS 75265
TL601, TL604, TL607, TL610
electrical characteristics over recommended operating free-air temperature range, Vee + - 10 V,

Vee - = - 20 V, analog switch test current = 1 rnA (unless otherwise noted)
IIH
PARAMETER
High-level input current VI =

TEST CONDITIONSt
5.5 V
TL6 __ M
TL6 __ 1
MIN TYP*
0.5
MAX
10
TL6 __ C
MIN TYP*
0.5
MAX
10
UNIT
/LA
Ell en
~
IlL
loff
Low-level input current
Switch off-state current

VI = 0.4 V
Vl(sw) = -10 V,
See Note 2
TA
TA
=
=
25C
MAXT
-50 -250
-400
-50 -100
-50 -250
-500
-10 -20
p.A
pA
nA
'5
c:;
.
(,)
TL601 C
Vl(sw) = 10 V, TL604 55 100 75 200 o
'~
IO(sw) = -1 rnA TL607
'0
ron Switch on-state resistance
TL610 40 80 40 100
0 S
TL601 C'
(,)
Vl(sw) = -10 V, TL604 220 400 220 600
IO(sw) = -1 rnA TL607
<3:
TL610 120 300 120 400 ca
~
roff Switch off-state resistance 25 20 GO. ca

C
Can Switch on-state input capacitance Vl(sw) = 0 V; f = 1 MHz 16 16 pF
Coff Switch off-state input capacitance Vl(sw) = 0 V, f = 1 MHz 8 8 pF
TL601
5 10 5 10
Logic input(s) TL604
at 5.5 V, Enable
5 10 5 10
ICC + Supply current from VCC + All switch input high rnA
TL607
terminals Enable
3 5 3 5
open input low
TL610 5 10 5 10
TL601
-1.2 -2.5 -1.2 -2.5
Logic input(s) TL604
at 5.5 V, Enable
-2.5 -5 -2.5 -5
ICC - Supply current from VCC- All switch input high rnA
TL607
terminals Enable
-0.05 -0.5 -0.05 -0.5
open input low
TL610 -1.2 -2.5 -1.2 -2.5
tMAX is 125C for M-suffix types, 85C for I-suffix types, and 70 c for C-suffix types.
t All typical values are at T A = 25C except for loff at T A = MAX.
NOTE 2: The other terminal of the switch under test is at V CC + = 10 V.
switching characteristics, Vee 10 V, VCC- - -20 V, TA .... 25C

Switch turn-off time 400 500
Switch turn-on time
RL = 1 kO, CL = 35 pF, See Figure 2
100 150
TEXAS . . 2-101
INSTRUMENTS
TL601, TL604, TL607, TL610
Figure 1 shows power supply boundary conditions for proper operation of the TL601 Series. The range
of operation for supply Vee + from + 5 V to + 25 V is shown on the vertical axis. The range of Vee -
lEI
from - 5 volts to - 25 volts is shown on the horizontal axis. A recommended 30-volt maximum voltage
differential from Vee + to Vee - governs the maximum Vee + for a chosen Vee - (or vice versa). A
minimum recommended difference of 15 volts from Vee + to Vee - and the boundaries shown in Figure 1
allow the designer to select the proper combinations of the two supplies.
c
....OJOJ The designer-selected Vee + for a chosen Vee - supply values limit the maximum input voltage that can
be applied to either switch terminal; that is, the input voltage should be between Vee - + 8 V and Vee +
l>
(')
to keep the on-state resistance within specified limits.
.c
cc;;. RECOMMENDED COMBINATIONS
OF SUPPLY VOLTAGES
::+"
30r----.----T---~----~--~--~
ci"
::l
n
~. 25
(')
c;:::;.. >I
8, 20
en :9
'0
>
> 15
C.
a.
::I
en
I
+ 10
CJ
CJ
>
o~--~----~--~----~--~--~
-30 -25 -20 -15 -10 -5 o
VCC_-Supply Voltage-V
FIGURE 1
2-102
TEXAS . .
INSTRUMENTS
PRODUCT TLC04, TLC14
PREVIEW BUTTERWORTH FOURTH-ORDER LOW-PASS
SWITCHED-CAPACITOR FILTERS
02970, NOVEMBER, 1986
Low Clock-to-Cutoff-Frequency Ratio Error D OR N PACKAGE

TLC04 ... 0.8% . (TOP VIEW)
TLC14 ... 1%
ClK(N [ ] 8 FilTER IN
Filter Cutoff Frequency Dependent Only on ClKR 2 7 VCC+
External-Clock Frequency Stability lS 3 6 AGND
Minimum Filter Response Deviation Due to

VCC - 4 5 FilTER OUT ...en
5
External Component Variations Over Time CJ
a-
and Temperature
U
Cutoff Frequency Range from 0.1 Hz to C
20 kHz o
.~
5-V to 12-V Operation m

5
Self Clocking or TTL-Compatible and CMOS- C"
Compatible Clock Inputs CJ
<t
National MF4-50 and MF4-100 ...
CO
CO
C
description
The TLC04 and TLC 14 are monolithic Butterworth low-pass switched-capacitor filters. Each is designed
as a low-cost, easy-to-use device and to provide accurate fourth-order low-pass filter functions in circuit
design configurations.
Each filter features cutoff frequency stability that is dependent only on the external-clock frequency stability.
The cutoff frequency is clock tunable and has a c1ock-to-cutoff frequency ratio of 50: 1 with less than
0.8% error for the TLC04 and a c1ock-to-cutoff frequency ratio of 100: 1 with less than 1 % error for
the TLC14. The input clock features self-clocking or TTL- or CMOS-compatible options in conjunction with
the level shift (LS) pin.
The TLC04 and TLC 14 are characterized for operation from OOC to 70 o C.

(7)
Vcc+--- LEVEL
(3)
LS----------._----a
~
w
:>w
a:
Q.
FILTER IN _(8_)________________-1
(6) l-
AGND-----------------~ t.)
(4)
VCC---- ::>
c
oa:
Q.
PRODUCT PREVIEW documents contain information Copyright 1986, Texas Instruments Incorporated
on products in the formative or design ~hase of
development. Characteristic data and other
specifications are design goals, Texas Instruments
TEXAS 2-103
reserves the right to change or discontinue these INSTRUMENTS
products without notice. POST OFFICE BOX 655012 DALLAS. TeXAS 75265
TLC04, TLC14 . PRODUCT
BUTTERWORTH FOURTHORDER LOWPASS PREVIEW
SWITCHEDCAPACITOR FILTERS
pin description
PIN
1/0 DESCRIPTION
NAME NO.
AGND 6 I Analog Ground - The non inverting input to the operational amplifiers of the Butterworth fourth-order low-
pass filter.
cOJ ClKIN 1 I Clock In - The clock input terminal for CMOS-compatible clock or self-clocking options. For either option,
....OJ the level Shift (lS) terminal is at VCC _ . For self-clocking, a resistor is connected between the ClKIN and
ClKR terminal pins and a capacitor is connected from the ClKIN terminal pin to ground.
l> ClKR 2 I ~Iock R - The clock input for a TTL-compatible clock. For a TTL clock, the level shift pin is connected
n to mid-supply and the ClKIN pin may be left open, but it is recommended that it be connected to either
.c
c VCC+ or VCC-
(ii' FilTER IN 8 I Filter Input
;::;.' FilTER OUT 5 0 Butterworth fourth-order 10w-pass'Filter Output
0' lS 3 I level Shift - This terminal accommodates the various input clocking options. For CMOS-compatible clocks
::l
or self-clocking, the level-shift terminal is at VCC _ and for TTL-compatible clocks, the level-shift terminal
n
::;' is at mid-supply.
n VCC+ 7 I Positive supply voltage terminal
c
;::;.' VCC- 4 I Negative supply voltage terminal
en
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 70C
Storage temperature range ............. '............................ - 65C to 150C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260C
NOTE 1: All voltage values are with respect to the AGND terminal.
TLC04 TLC14
UNIT
MIN MAX MIN MAX
VCC+ Positive supply voltage 2.5 6 2.5 6 V
VCC- Negative supply voltage -2.5 -6 -2.5 -6 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
fclock Clock frequency (see Note 2) 5 1x10 6 10 1x10 6 Hz
fco Cutoff frequency (see Note 3) 0.1 20x10 3 0.1 10x103 Hz
TA Operating free-air temperature 0 70 0 70 c
"'tJ
NOTES: 2. Above 250 kHz, the input clock duty cycle should be at 50% to allow the operational amplifiers the maximum time to settle
:D
o while processing analog samples.
3. The cutoff frequency is defined as the frequency where the response is 3.01 dB less than the dc gain of the filter.
C
c:
('")
-I
"'tJ
:D
m
~
m
:E
2-104 TEXAS
INSTRUMENTS
PREVIEW BUTTERWORTH FOURTHORDER LOWPASS
electrical characteristics over recommended operating free-air temperature range, Vee + 2.5 V,

Vee - = - 2.5 V, fclock ::5 250 kHz (unless otherwise noted)
filter section
TlC04 . TlC14
VOO Output voltage offset -150 -300 mV
I VOM+ 2 2.3 2 2.3
YOM Peak output voltages RL = 5 kfl V
VOM- -1 -1.5 -1 -1.5
Source TA = 25C, -0.5 -0.5
Short-circuit output current mA
lOS
~ See Note 4 28 28
ICC Supply current fclock = 250 kHz 1.5 2.25 1.5 2.25 mA
NOTE 4: lOS (source current) is measured by forcing the output to its maximum positive voltage and then shorting the output to the negative
supply (VCC _) terminal. lOS (sink current) is measured by forcing the output to its maximum negative voltage and then shorting
the output to the positive supply (VCC +) terminal.
operating characteristics over recommended operating free-air temperature range, Vee + 2.5 V,
Vee - = - 2.5 V (unless otherwise noted)
TlC04 TlC14
Clock-to-cutoff-frequency ratio
fclock :s 250 kHz, TA = 25C 49.27 50.07 50.87 99 100 101
(f clock/f co)
fclock :s 250 kHz -25 0 25 -25 0 25 ppm/DC
clock-to-cutoff frequency ratio
fco = 5 kHz, f = 6 kHz -8.11 -7.57 -7.03
fclk = 250 kHz, dB
Frequency response above and below TA = 25C f = 4.5 kHz -1.7 -1.46 -1.22
cutoff frequency (see Note 5) fco = 2.5 kHz, -7.92 -7.42 -6.92
f = 3 kHz
fclk = 250 kHz, dB
TA = 25C f = 2.25 kHz -1.77 -1.51 -1.25
Dynamic range (see Note 6) TA = 25C 80 78 dB
Stop-band frequency
fclock :s 250 kHz 24 25 24 25 dB
attentuation at 2 fco
DC voltage amplification fclock :s 250 kHz, RS :5 2 kfl -0.15 0 0.15 -0.15 0 0.15 dB
Peak-to-peak clock
TA = 25C 15 15 mV
feedthrough voltage

NOTES: 5. The frequency responses at f are referenced to a dc gain of 0 dB.
6. The dynamic range is referenced to 2.82 V rms (4 V peak) where the wideband noise over a 20-kHz bandwidth is typically $
282 /LV rms for the TLC04 and 355 /LV rms for the TLC14.
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TEXAS ~ 2-105
INSTRUMENTS
TLC04, TLC14 PRODUCT
electrical characteristics over recommended ,operating free-air temperature range, Vee + 5 V,

Vee - = - 5 V, fclock !5; 250 kHz, (unless otherwise noted)
lEI
c
Q)
filter section
VOO
PARAMETER
Output voltage offset

TEST CONDITIONS
MIN
TLC04
Typt
-200
MAX MIN
TLC14
Typt
-400
MAX
UNIT
mV
r+
Q) 4 4.5 4 4,5
VOM+
VOM Peak output voltages RL = 5 kO V

n
VOM-
Source TA = 25e,
-4 ~4.1
-1.5
-4 -4.1
-1.5
.c lOS Short-circuit output current
Sink See Note 4 50 50
mA
s:::::
(ii' lee Supply current fclock = 250 kHz 2.5 3.5 2.5 3.5 mA
;:;"
0' NOTE 4: lOS (source current) is measured by forcing the output to its maximum positive voltage'and then shorting the output to the negative
::l supply (Vee _) terminal. lOS (sink current) is measured by forcing the output to its maximum negative voltage and then shorting
n the output to the positive supply (Vee +) terminal.
::;'
g clocking section
;:;"
en PARAMETER TEST CONDITIONS* MIN Typt MAX UNIT
Vee = 10 V 6.1 7 8.9
VT+ Positive-going input threshold voltage V
Vee = 5 V 3.1 3.5 4.4
Vee = 10 V 1.3 3 3.8
VT- Negative-going input threshold voltage elKIN V
Vee = 5 V 0.6 1.5 1.9
Vee = 10V 2.3 4 7.6
Vhys Hysteresis (VT + - VT-) V
Vee = 5 V 1.2 2 3.8
Vee = 10V 9
VOH High-level output voltage 10 = -10 p.A V
Vee = 5 V 4.5
Vee = 10V 1
Val low-level output voltage 10 = 10p.A V
Vee = 5 V 0.5
Vee = 10V level Shift pin at mid-supply, 2
Input leakage current elKR p.A
Vee = 5 V TA = 25e 2
Vee = 10V -3 -6
Output current elKR shorted to Vee- mA
Vee = 5 V 1-0.75 -1.5
I 2.5 5
Vee = 10V
Output current elKR shorted to Vee+ mA
Vee = 5 V 0.65 1.3
t All typical values are at T A = 25e.

+Vee = Vee+ - Vee-
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2-106 TEXAS
INSTRUMENTS
operating characteristics over recommended operating freeair temperature range, Vee + = 5 V,

Vee - = - 5 V (unless otherwise noted)
PARAMETER
Clock-to-cutoff-frequency ratio
(fclock/fco)
TEST CONDITIONS
fclock :5 250 kHz, TA = 25C

MIN
TLC04
Typt
49.58 49.98
MAX
50.38
MIN
99
TLC14
Typt
100
MAX
101
UNIT
Ell en
+oJ
Temperature coefficient of ':;
clock-to-cutoff frequency ratio
fclock :5 250 kHz -15 0 15 -15 0 15 ppm/DC
...o
fco = 5 kHz, f = 6 kHz -7.84 -7.57 -7.3 U
fclk = 250 kHz, dB :
Frequency response above and below TA = 25C f = 4.5 kHz -1.56 -1.44 -1.32 o
'';:;
cutoff frequency (see Note 5) fco = 2.5 kHz, f = 3 kHz -7.67 -7.42 -7.17 '(j)
fclk = 250 kHz,
f = 2.25 kHz -1.64 -1.51 -1.38
dB
':;
TA = 25C C-
TA = 25C O
Dynamic range (see Note 7)
Stop-band frequency
fclock :5 250 kHz 24
80
25 24
78
25
dB
dB

attentuation at 2 fco CO
+oJ
DC voltage amplification fclock :5 250 kHz, RS :5 2 kO -0.15 0 0.15 -0.15 0 0.15 dB CO
Peak-to-peak clock
C
TA = 25C 25 25 mV
feedthrough voltage

NOTES: 5. The frequency responses at f are referenced to a dc gain of 0 dB.
7. The dynamic range is referenced to 2.82 V rms (4 V peak) where the wideband noise over a 20-kHz bandwidth is typically
282 /LV rms for the TLC04 and 355 /LV rms for the TLC14.
~
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TEXAS ~ 2-107
INSTRUMENTS
5V------------------------~
'r - -'- ~--k)- VCC+

_ ~O~L~4
LEVEL
__,
c I
(3) LS SHIFT I
...
Q)
-+ 5V I I
I
Q)

(')
.c
c
,
CMOS
ill
CLKIN
-5V
(1) ICLKIN
(2)I CLKR
I
I
I
tn"
;:::;." I I
0" I I
:::::J
(") I I
::::;"
(') (8)1 FILTER IN I
c (6)1 AGND FILTER (5)
;:::;."
U) I OUT I
L ______ ~CC-_ _ _ _ _ _ _ _ -.l
(4)
-5V----e--------------------~
FIGURE 1. CMOS-CLOCKDRIVEN, DUALSUPPL Y OPERATION
5V------e------------------~
(7) TLC04/TLC14
r - - - - - VCC+ - -L~L- - - -.,
I
(3) LS SHIFT' I
I I
-= (1) ICLKIN I
TTLill- 5 V (2): CLKR I
CLKR
OV
------.....;.....-------------------' I
I
I
I
."
I
::Jl I
(8) FILTER IN I
FILTER (5)
0 (6)1 AGND OUT I
C I I
c: J
(")
-4
L --- - --J41 -- -- --- VCC-
-5 V
." FIGURE 2. TTLCLOCKDRIVEN, DUAL-SUPPLY OPERATION
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2-108 TEXAS
INSTRUMENlS
TYPICAL APPLICATION OAT A
5V------------------------~
r
1311LS
- - - - __ b __ ~C~T~1~
VCC+ LEVEL
__ ,
II
...
tn
.:;
...
(,)
U
s::::
o
~
'Ci)
':;
C"
(,)

FILTER __+-____I_81_1F_IL_T_ER_I_N____________--I
INPUT
1611 AGND
FILTER I lSI ...
CO
CO
= I OUT I C
L ______VCC-_ _ _ _ _ _ _ _ -.J
141
-5V--~--------------------~
fclock - RC x In ~(VCC - VT-

~ VCC - VT+
For VCC - 10 V.
1
fclock - 1.69 RC
FIGURE 3. SELFCLOCKING THROUGH SCHMITT TRIGGER OSCILLATOR, DUALSUPPLY OPERATION
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TEXAS 2-109
INSTRUMENTS
II
+10V--------~--------------------_,
(71 TlC04/TLC14
r - - - - - VCC+ - - l~E~ - - --1
c I
(31 lS SHIFT
OJ
....
OJ - + 10 V I1JIClKIN
>
(')
.c
c
CMOS
QIL
ClKIN
(SEE NOTE Al
oV
--4-----~~~~--~T
I
I
0'
;:;" -- 5V (21 ClKR
I
I
0'
::s
(')
::;'
QfL
TTL
ClKR
OV
. __+-____~--~----------------~
10 kfl
I
I
(') (81 IFilTER IN
c FilTER IN ~5 VOC ---+------+---:.-'-:--------------------""'"1 FilTER (51
;:;" (SEE NOTE BI (61 I AGND OUT
en
I
L ______VCC-_ _ _ _ _ _ _ _ ..J
10 kfl (4)
NOTES: A. The external clock used must be of CMOS level because the clock is input to a CMOS Schmitt trigger.
B. The Filter input signal should be dc-biased to mid-supply or ac-coupled to the terminal.
C. The AGND terminal must be biased to mid-supply.
FIGURE 4. EXTERNAL-CLOCK-DRIVEN SINGLE-SUPPLY OPERATION
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2-110 TEXAS . .
INSTRUMENTS
+10v------------._------------------------,
r - - - - - -.- - ~C+ -
(7)
LEVEL
- - - - - - - -:1 FI....U)
(3)
(1)
LS
CLKIN
.
'5
C3
(,)
c
R (2) CLKR o
'~
'u;
'5
C"
(,)
10 kO
cd:
(8) FILTER IN FILTER

....coco
OUT (5) C
(6) AGND
0.1/L
F
L ________ VCC.:.. _ _ _ _ _ _ _ _. .J
10 kO (4)
(SEE NOTE A)
1
fclock - "::"R"::-C-x-:-ln---;::f1(7":V-:-C-C--~V-T-_)~(-:-:V:-T"'+)r-or~
~ VCC - VT+ VT- 'J
For VCC - 10 V.
1
fclock - 1.69 RC
NOTE A: The AGND terminal must be biased to mid-supply.
FIGURE 5. SELFCLOCKING THROUGH SCHMITT TRIGGER OSCILLATOR.

SINGLESUPPLY OPERATION
~
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INSTRUMENTS
TEXAS -1!1 2-111
POST OFFle, BDX 655012 DALLAS. TEXAS 75265
II
c
C)
5V--~----------------------------~
.- - - - - -- -
(7)
-VCC+----- - - - - ,
I
r+
C) (3 LS
I
I

(") I
.c CLOCK ---+---t--------'(.....
' )--:-C_L_KI_N__-t
I
c INPUT
0' (2) CLKR I
;;'
0'
j
1
I
()
::;' I
(")
c I
;;' FILTER I
o (8) FILTER IN
OUT 1(5)
(6) AGND
I
'Okfl~-+-" L _________ VCC~ ________ ...JI
0.' pF (4)
-5V--~~~ __ ----------------------~
FIGURE 6. DC OFFSET ADJUSTMENT
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==
2-112 TEXAS ~
INSTRUMENTS
PRODUCT TLC0820A, TLC0820B
PREVIEW ADVANCED LinCMOSTM HIGHSPEED 8BIT ANALOGTODIGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIOUES
D2873. SEPTEM8ER 1986-REVISED OCTOBER 1986
o Advanced LinCMOS Silicon-Gate T

TLC0820AM. TLC0820BM ... J OR N PACKAGE
Technology TLC0820AI. TLC0820BI . N PACKAGE
II
TLC0820AC. TLC0820BC . N PACKAGE
8-Bit Resolution (TOP VIEW)
Differential Reference Inputs ANLG IN Vee

Parallel Microprocessor Interface
(LSB) DO Ne
~
en
D1 OFLW 'S
Conversion Time
Write-Read Mode ... 0.9 p.s and 1.1 p.s
D2
D3
D7 (MSB)
D6
...CJ
Read Mode ... 2.5 p's Max WR/RDY D5
C3
MODE D4 c
No External Clock or Oscillator Components o
RD es '.;::i
Required 'U)
INT REF+
On-Chip Track-and-Hold GND REF- 'S
C"
CJ
Low Power Consumption .... 50 mW Typ
TLC0820AM. TLC0820BM ... FK PACKAGE
TLC0820AI. TLC0820BI ... FN PACKAGE

Single 5-V Supply
TLC0820AC. TLC0820BC . FN PACKAGE ~
co
TLC0820B is Direct Replacement for (TOP VIEW)
co
National Semiconductor ADC0820B/BC and
C
iii~
Analog Devices AD7820L/C/U; ~(,!)
TLC0820A is Direct Replacement for -..J U
,.... 0 Z uu
National Semiconductor ADC0820C/CC and oo>Z
Analog Devices AD7820K/B/T 3 2 1 20 19
18
03 5 17 07 (MSB)
WR/RDY 6 16 D6
MODE 7 15 D5
RD 8 14 D4
9 1011 12 13
I + ICfl
I
f- 0
ZZu.u. U
-(!)ww
a: a:
NC-No internal connection
description
The TLC0820A and TLC0820B are Advanced LinCMOS" 8-bit analog-to-digital converters each consisting
of two 4-bit "flash" converters, a 4-bit digital-to-analog converter, a summing (error) amplifier, control
logic, and a result latch circuit. The modified "flash" technique allows low-power integrated circuitry to
complete an 8-bit conversion in 1 .4 microseconds. The on-chip track-and-hold circuit has a 100-nanosecond
sample window and allows the TLC0820A and TLC0820B to convert continuous analog signals having
sw
slew rates of up to 100 millivolts per microsecond without external sampling components. TTL-compatible
three-state output drivers and two modes of operation allow interfacing to a variety of microprocessors.
:>w
Detailed information on interfacing to most popular microprocessors is readily available from the factory. a:
0.
The TLC0820AM and TLC0820BM are available in both the N plastic and the J ceramic packages and
are characterized for operation over the full military temperature range of - 55 ac to 125 ac. The TLC0820AI I-
and TLC0820BI are characterized for operation from - 40 ac to 85 ac. The TLC0820AC and TLC0820BC U
are characterized for operation from 0 ac to 70 ac. ::J
C
o
Advanced LinCMOS is a trademark of Texas Instruments. a:
0.
on products in the formative or design phase of
development. Characteristic data and other TEXAS
specifications are design goals. Texas Instruments 2-113
reserves the right to change or discontinue these
products without notice.
INSTRUMENTS
TLC0820A. TLC0820B PRODUCT
ADVANCED LinCMOSTM HIGHSPEED 8BIT ANALOGTODlGITAL PREVIEW

4-BIT FLASH
II
(12)
REF+
REF-
(11 )
ANALOG-TO-
DIGITAL
CONVERTER
(4 MSBs)
4 4,
,
----
~
(1B)
OFLW
DO (LSB)
C (3)
....
Q) 4/ - D1
Q) (4)
OUTPUT
- D2

n ~~
~ 4-BIT
DIGITAL-
~
LATCH
AND --ill D3
DIGITAL
.c
TO-ANALOG
3-STATE
c CONVERTER ~ D4 OUTPUTS
BUFFERS
iii'
;:;: ~ D5
0'
::s '--
4-BIT FLASH
ANALOG-TO-
~ D6
n l: - DIGITAL
4,
, r-!!ZL D7 (MSB)
::;i'
n (1)
- -1
.. CONVERTER
(4 LSBs)
c
. ;+.
ANLG IN +1
en
(7)
1t
MODE
WR/RDY
(6) ... . TIMING
AND ~
(13)
CS CONTROL
(8)
RD
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2-114 TEXAS . .
INSTRUMENTS
PREVIEW ADVANCED LinCMOS HIGHSPEED 8BIT ANALOGTODlGlTAL
PIN
DESCRIPTION
Ell
NAME NUMBER
ANLG IN 1 Analog input
CS 13 This input must be low in order for RD or WR to be recognized by the ADC.
DO
01
2
3
Three-state data output, bit 1 (LSB)
Three-state data output, bit 2
...
S
en
02
03
4
5
...o
04 14 Three-state data output, bit 5
U
D5 15 Three-state data output, bit 6 c
o
06 16 Three-state data output, bit 7 '';:;
07 17 Three-state data output, bit 8 (MSB) 'iii
GND 10 Ground 'S
C-
INT 9 In the WRITE-READ mode, the interrupt output, INT, going low indicates that the internal count-down delay time, O
td(int), is complete and the data result is in the output latch. td(int) is typically 800 ns starting after the rising <t
edge of the WR input (see operating characteristics and Figure 3). If RD goes low prior to the end of td(int),
INT goes low at the end of tdRIL and the conversion results are available sooner (see Figure 2). INT is reset by the
...
CO
CO
rising edge of either RD or CS. C
MODE 7 Mode-selection input. It is internally tied to GND through a 50-uA current source, which acts like a pull-down
resistor.
READ mode: Occurs when this input is low.
WRITE-READ mode: Occurs when this input is high.
NC 19 No internal connection
OFLW 18 Normally the OFLW output is a logical high. However, if the analog input is higher than the VREF +, OFLW
will be low at the end of conversion. It can be used to cascade 2 or more devices to improve resolution (9
or 10-bits).
RD 8 In the WRITE-READ mode with CS low, the 3-state data outputs DO through 07 are activated when RD goes
low. RD can also be used to increase the conversion speed by reading data prior to the end of the internal
count-down delay time. As a result, the data transferred to the output latch is latched after the falling edge of RD.
In the READ mode with CS low, the conversion starts with RD going low. RD also enables the three-state
data outputs upon completion of the conversion. The ROY output going into the high-impedance state and
INT going low indicates completion of the conversion.
REF- 11 This input voltage is placed on the bottom of the resistor ladder.
REF+ 12 This input voltage is placed on the top of the resistor ladder.
VCC 20 Power supply voltage
WR/RDY 6 In the WRITE-READ mode with CS low, the conversion is started on the falling edge of the WR input signal.
The result of the conversion is strobed into the output latch after the internal count-down delay time, td(int)'
provided that the RD input does not go low prior to this time. td(int) is approximately 800 ns.
In the READ mode, RDY (an open-drain output) will go low after the falling edge of CS, and will go into the
high-impedance state when the conversion is strobed into the output latch. It is used to simplify the interface
sw
to a microprocessor system. :>w
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TEXAS ~ 2-115
INSTRUMENTS
TLC0820A, TLC0820B PRODUCT
ADVANCED LinCMOS HIGHSPEED 8BIT ANALOGTODlGlTAL PREVIEW
TLC0820AM TLC0820AI TLC0820AC
UNIT
TLC08208M TLC0820BI TLC0820BC
Supply voltage, Vee (see Note 1) 10 10 10 V
-0.2 to -0.2 ~o -0.2 to
c Input voltage range, all inputs (see Note 1)
Vee+ 0 . 2 Vee+ 0 . 2 Vee+ 0 . 2
V
....
Q)
Q) Output voltage range, all outputs (see Note 1)
'-0.2 to -0.2 to -0.2 to
V
Vee+ 0 . 2 Vee+ 0 . 2 Vee+ 0 .2
(")
Operating free-air temperature range -55 to 125 -40 to 85 o to 70 e
.c Storage temperature range -65 to 150 -65 to 150 -65 to 150 e
c Case temperature for 60 seconds: FK package 260 e
(ii'
;:;.' Case temperature for 10 seconds: FN package 260 260 e
0' Lead temperature 1,6 mm (1/16 inch) from case
300 e
:s for 60 seconds: J package
(") Lead temperature 1,6 mm (1/16 inch) from case
260 260 260 e
~' for 10 seconds: N package
(")
c
;:;.' NOTE 1: All voltages are with respect to network ground terminal, pin 10.
en
TLC0820AM TLC0820AI TLC0820AC
TLC0820BM TLC0820BI TLC0820BC UNIT
MIN NOM MAX MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 8 4.5 5 8 4.5 5 8 V
Analog input voltage -0.1 Vee+ O.1 -0.1 Vee +0.1 -0.1 Vee+ 0.1 V
Positive reference voltage, VREF + VREF- Vee VREF- Vee VREF- Vee V
Negative reference voltage, VREF- GND VREF+ GND VREF+ GND VREF+ V
High-level input Vee = 4.75 V es, WR/RDY, RD 2 2 2
V
voltage, VIH to 5.25 V MODE 3.5 3.5 3.5
Low-level input Vee = 4.75 V es, WR/RDY, RD 0.8 0.8 0.8
V
voltage, VIL to 5.25 V MODE 1.5 1.5 1.5
Delay time from WR to RD in write-read mode,
0.6 0.6 0.6 I-'s
tdWR (see Figures 2 and 3)
Write-pulse duration in write-read mode, tww
0.6 50 0.6 50 0.6 50 I-'s
(see Figures 2, 3, and 4)
Operating free-air temperature, T A -55 125 -40 85 0 70 e
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2-116 TEXAS . .
INSTRUMENTS
PREVIEW ADVANCED LinCMOSTM HIGHSPEED 8BIT ANALOGTODIGITAL
electrical characteristics over recommended operating freeair temperature range, Vee = 5 V

PARAMETER
VOH High-level output voltage

Any D, INT,
or OFLW
Any D, OFLW,
Vee
Vee
=
=
TEST CONDITIONS
4.75 V,
4.75 V,
IOH
IOH
=
=
-360 p.A
-10 p.A
MIN
2.4
4.5
Typt MAX UNIT
V Ell ....
(/)
VOL Low-level output voltage Vee = 5.25 V, IOL = 1.6 rnA 0.4 V 'S
INT, or WR/RDY
es or RD 0.005 1
...u
High-level input current WR/RDY VIH = 5 V 0.1 3 p.A
C3
IIH
c
MODE 50 200 o
es, WR/RDY,
'';:
IlL Low-level input current VIL = 0 -0.005 -1 p.A 'Ci)
RD, or MODE
'S
Off-state (high-impedance Any 0 or Vo = 5 V 0.1 3
p.A C'
10Z U
state) output current WR/RDY Vo = 0 -0.1 -3
~
es at 5 V, VI = 5 V 3
II Analog input current
es at 5 V, VI = 0 -3
p.A
....COCO
Any 0, OFLW, INT,
Vo = 5 V, TA = 25C 7 14 C
or WR/RDY
lOS Short-circuit output current rnA
Any 0 or OFLW . -6 -12
Vo = 0, TA = 25e
INT -4.5 -9
Rref Reference resistance 1.25 2.3 6 kG
lee Supply current es, WR/RDY, and RD at 0 V 7.5 15 rnA
Any digital 5
ei Input capacitance pF
Analog (pin 1) 45
eo Output capacitance Any digital 5 pF
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TEXAS . . 2-117
INSTRUMENTS
ADVANCED LinCMOS HIGHSPEED 8BIT ANALOGTODlGlTAL PREVIEW
operating characteristics, Vee'"" 5 V, VREF + ... 5 V, VREF- 0, tr ... tf ... 20 ns, TA ... 25e

TLC0820A TLC0820B
Supply voltage
kSVS VCC = 5 V 5% 1/16 1/4 1/16 1/4 LSB
sensitivity
Total unadjusted error t MODE pin at 0 V 1 1/2 LSB
Read mode
tconvR MODE pin at 0 V, See Figure 1 1.6 2.5 1.6 2.5 p's
conversion time
Internal count- MODE pin at 5 V, CL = 50 pF,
td(int) 800 1300 800 1300 ns
down delay time See Figures 3 and 4
tconvR tconvR tconvR tconvR
taR Access time from RD~ MODE pin at 0 V, See Figure 1 ns
+20 +50 +20 +50
MODE pin at 5 V, CL = 15 pF 190, 280 190 280
taRl Access time from RD~ tdWR < td(int), ns
CL = 100 pF 210 320 210 320
See Figure 2
MODE pin at 5 V, CL = 15 pF 70 120 70 120
taR2 Access time from RD~ tdWR > td(int) ns
CL = 100 pF 90 150 90 150
See Figure 3
taiNT Access time from INT! MODE pin at 5 V, See Figure 4 20 50 20 50 ns

RL = 1 kO, CL = 10 pF,
tdis Disable time from ROt 70 95 70 95 ns
See Figures 1, 2, 3, and 5
Delay time from MODE pin at 0 V, CL = 50 pF,
tdRDY 50 100 50 100 ns
CS~ to RDY~ See Figure 1
Delay time from CL = 50 pF,
tdRIH 125 225 125 225 ns
ROt to INTi See Figures 1, 2, and 3
Delay time from MODE pin at 5 V, tdWR < td(int), 200 290 200 290 ns
tdRIL
RD~ to INn See Figure 2
Delay time from MODE pin at 5 V, CL = 50 pF,
tdWIH 175 270 175 270 ns
WRt to INTi See Figure 4
Delay to next
td(NC) See Figures 1, 2, 3, and 4 500 500 ns
conversion
Slew rate tracking 0.1 0.1 V/p.s
t Total unadjusted error includes offset, full-scale, and linearity errors.
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:e
2-118 TEXAS
INSTRUMENTS
-li1
PREVIEW ADVANCED LinCMOS HIGHSPEED 8BIT ANALOGTODlGlTAL
CS } ' -_ _ _ _ _ _
I
---J! \,
~---- F.I
....tn
: \'----~I- \-~ __ 'S
I i I+- t
d(NCI-4j ...
(,)
~I ~WITH ~XTERNAL C3
--.l r,:
WR/ROV PULL-UP
-4\ l4T~t-dR-O-V _oJ tdRIH . c
o
INT II ~ III
~~__~.
'';:;
'Ci)
I4-- t convR-.I - I 'S
C'
00-07 ------t.=t:"~ ~ ~:;~-n--

(,)
....COCO
FIGURE 1. READ MODE WAVEFORMS (MODE PIN LOW)
C
t:;H ---
CS =-" I _______\.a..-_-""C
twwH
WRJROV ~"'-------\r.-'--_-J-'''''- WR/ROV ~"'---------'""I:\.-_-
tdWR 14 ~14 td(NCI....j I j.--td(NCI----.j
~,-.----
t~w"l1 Jr"l"
RO
tdRIL -+l t+- I

INT I t'\......--1JI
~~
00-07 --------~{
I --.j j.- tdRIH
I }--- 00-07 ________t~:I~_1cb_
taR1----1 Ie- I
-.I
I
r4- t dis
-.II-- --I j.- taR2 tdis
FIGURE 2. WR.ITEREAD MODE WAVEFORMS FIGURE 3. WRITEREAD WAVEFORMS

[MODE PIN HIGH AND tdWR < td(int)] [MODE PIN HIGH AND tdWR > td(int)]
CS LOW - - - - - - - - - - - - - ~
RO LOW -~-_:_--------
tww~_---__.
->ww
WR/ROV
ex:
INT =,
---~!4-~. tdUntl-=ei
0.
I-
U
>-
\.-taiNT
::J
00-07 ---..;.....,.) { e:~~ C
o
FIGURE 4. WRITEREAD MODE WAVEFORMS ex:
(STANDALONE OPERATION, MODE PIN HIGH. AND RD LOW) 0.
TEXAS -Ij} 2-119

INSTRUMENTS
POST OFFICE BOX 655012 DAllAS, 'TEXAS 76265
TLC0820A. TLC0820B PRODUCT
ADVANCED LinCMOSTM HIGHSPEED 8BIT ANALOGTODIGITAL PREVIEW
II
VCC CL - 10 pF
TLC0820
-.,trj+-
VCC - -1-~90~%~--
C INPUT RD
DATA RD 1 50%
II) On
r+ OUTPUT 110%
II) CS GND 1
GND ~ tdisl+-
l>
(') CL 1 krl VOH 1
.c DATA ~O%
C OUTPUTS ~
0' . GND-------~
;::;"
ci"
~
-= tr - 20 ns
0
:::;. VCC CL - 10 pF
(')
C -+ttrJ4-
;::;"
(/) TLC0820
_ VCC~-.l....1
1 90%
1 krl
RD 1 50%
INPUT RD DATA GND 110%
On
OUTPUT I
CS -+t tdis 14-
GND VCC - I
CL DATA ~I
OUTPUTS 10%
VOL
tr - 20 ns
On - 00 .. 07
TEST CIRCUIT VOLTAGE WAVEFORMS
FIGURE 5. TEST CIRCUIT AND VOLTAGE WAVEFORMS
'"tJ
:u
o
c
c
o
-f
'"tJ
:u
m
=5
m
:E
2-120 TEXAS
INSTRUMENTS
'1!1
POST OFFiCe BOX 655012 DALLAS. TeXAS 75265
PRODUCT TLC0820A. TLC0820B
PREVIEW ADVANCED LinCMOS HIGHSPEED 8BIT ANALOGTODlGITAL
The TLC0820A and TLC0820B each employ a combination of "sampled-data" comparator techniques and
"flash" techniques common to many high-speed converters. Two 4-bit "flash" analog-to-digital conversions
are used to give a full 8-bit output.
The recommended analog input voltage range for conversion is - O. 1 V to V CC + O. 1 V. Analog input signals
II
....en
that are less than VREF - + % LSB or greater than VREF + - % LSB convert to 00000000 or 11111111 'S
respectively .. The reference inputs are fully differential with common-mode limits defined by the supply rails. ...
(J
The reference input values define the full-scale range of the analog input. This allows the gain of the ADC to C3
be varied for ratiometric conversion by changing the VREF + and VREF - voltages. c::::
o
The device operates in two modes, read (only) and write-read, which are selected by the MODE pin (pin 7). '';::;
The converter is set to the read (only) mode when pin 7 is low. In the read mode, the WR/RDY pin is used 'ti)
as an output and is referred to as the "ready" pin. In this mode, a low on the "ready" pin while CS is low 'S
C'
indicates that the device is busy. Conversion starts on the falling edge of RD and is completed no more than (J
2.5 microseconds later when INT falls and the "ready" pin returns to a high-impedance state. Data outputs <t
also change from high-impedance to active states at this time. After the data is read, RD is taken high, INT
returns high, and the data outputs return to their high-impedance states.
....
(Q
(Q
The converter is set to the write-read mode when pin 7 is high and WR/RDY is referred to as the "write" pin.
C
Taking CS and the "write" pin low selects the converter and initiates measurement of the input signal.
Approximately 600 nanoseconds after the "write" pin returns high, the conversion is completed. Conversion
starts on the rising edge of WR/RDY in the write-read mode.
The high-order 4-bit "flash" ADC measures the input by means of 16 comparators operating simultaneously.
A high precision 4-bit DAC then generates a discrete analog voltage from the result of that conversion. After
a time delay, a second bank of comparators does a low-order conversion on the analog difference between
the input level and the high-order DAC output. The results from each of these conversions enter an 8-bit latch
and are output to the three-state buffers on the falling edge of RD.
~
->w
W
a:
c..
l-
e.>
::l
C
o
a:
c..
TEXAS -I!} 2-121

INSTRUMENTS
POST OFFice BOX 655012 OALLAS, TeXAS 75265
ADVANCED LinCMOSTM HIGH-SPEED 8BIT ANALOG-TO-DlGlTAL PREVIEW
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
II
c
r\._
es
WR
(13)
(6)
es
WR/ROY ANLG
IN
(20)
Vee ----5 V
(1)
ANLGIN
Q)
~
Q)

rc> ~ RO'
(") DO (2) (7)

.c DO MODE - 5 V
c 01 (3)
01 REF+
(12)
5V
Cii"
fa
"p 02 (4)
;:;: 02
BUS 03 (5)
c)" 03
:l 04 (14)
o
:;" 05 (15)
04
REF-
(11 )
05
t
(") 06 (16)
c 06
;:;: 07 (17)
til 07
08
OFL (18) (10)
~
~
OFLW GNO
~
IL~
(13) (20)
cs Vee ~5V
(6) (1 )
WR/ROY ANLG
IN
~
-
Ro
(2) (7)
DO MODE r-5V
(3) (12)
01 REF+
(4)
02
(5) F
03
."
jJ
(14)
(15)
(16)
04
05
06
REF
(11)
l~-
I"
o (17)
07
~0.1IlF
c (18)
OFLW' GNO
c(")
FIGURE 6. CONFIGURATION FOR 9-BIT RESOLUTION
-t
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~
2-122 TEXAS -I!}

INSTRUMENTS
ADVANCE TLC10, TLC20
INFORMATION UNIVERSAL DUAL SWITCHEDCAPACITOR FILTER
D2952, AUGUST 1986-REVISED SEPTEM8ER 1986
Maximum Clock to CenterFrequency Ratio N DUALINLINE PACKAGE

Error (TOP VIEW)

TLC10 ... 0.6%
TLC20 ... 1.5%
Filter Cutoff Frequency Stability Dependent
Only on External-Clock Frequency Stability
lLP
lBP
lNAH
l1N-
2LP
2BP
2NAH
21N-
II
...
t/)
lAPIN 2APIN ':i

Minimum Filter Response Deviation Due to
External Component Variations over Time
SW AGNO ...
(,)
and Temperature
VCC+ VCC- C3
VOO+ VOO- c::::
Critical-Frequency Times Q Factor Range Up LS CF/CL o
'';:;
to 200 kHz lCLK 2CLK
'w
Critical-Frequency Operation Up to 30 kHz ':i
FN CHIP CARRIER PACKAGE C'
(,)
Designed to be Interchangeable with: (TOP VIEW)
National MF10
<C
Maxim MF10
Linear Technology LTC1 060
I
<!a..a..a..a..
ZCD...J...JCD
.... NN
...
CO
CO
3 2 1 2019
o
description l1N- 4 18 2NAH
lAPIN 5 17 21N-
The TLC 10 and TLC20 are monolithic general-
SW 6 16 2APIN
purpose switched-capacitor CMOS filters each
15 AGNO
containing two independent active-filter VCC+
VOO+ 8 14 VCC-
sections. Each device facilitates configuration of
9 1011 12 13
Butterworth, Bessel, Cauer, or Chebyshev filter
design.
~ ~ ~
u u
d
u:
0
6
Filter features include cutoff frequency stability .... NU>
that is dependent only on the external clock
frequency stability and minimal response
deviation over time and temperature. Features
also include a critical-frequency times filter
quality (Q) factor range of up to 200 kiloHertz.
With external clock and resistors, each filter
section can be used independently to produce :2:
various second-order functions or both sections o
can be cascaded to produce fourth-order ....
functions. For functions greater than fourth-
order, ICs can be cascaded.

~
The TLC10 and TLC20 are characterized for a:
operation from OOC to 70C. oLL
:2:
w
U
:2:

>
c

ADVANCE IIliFORMATION documents contain Copyright 1986, Texas Instruments Incorporated
information on new ~roducts in the samplin9 or
preproduction phase of development Charactenstic
data and other specifications are subject to change
TEXAS -II} 2-123
without notice. INSTRUMENTS
TLC10,TLC20 ADVANCE
UNIVERSAL DUAL SWITCHEDCAPACITOR FILTER INFORMATION
PIN
I/O DESCRIPTION
NAME NO.
II AGND
lAPIN
15
5
I
I
Analog Ground - The noninverting inputs to the input operational amplifiers of both filter sections. This terminal
should be at ground for dual supplies or at mid-supply level for single-supply operation.
All-Pass Inputs - The all-pass input to the summing amplifier of each respective filter section used for all-pass
..
c
Q)
Q)
2APIN
lBP
16
2 0
filter applications in configuration modes 1 a, 4, 5, and 6. This terminal should be driven from a source having
an impedance of less than 1 kilohm. In all other modes, this terminal is grounded. See Typical Application Data .
BandPass Outputs - The band-pass output of each respective filter section provides the secondorder band-

n
2BP
CF/CL
19
12 I
pass filter functions.
Center Frequency/Current Limit - This input terminal provides the option to select the inputclock-tocenter-
.c
c: frequency ratio of 50: 1 or 100: 1 or to limit the current of the IC. For a 50: 1 ratio, the CF/CL terminal is set
(ii' to VOO +. For a 100: 1 ratio, the CF/CL terminal is set to ground for dual supplies or to mid-supply level for
;:;: single-supply operation. For current limiting, the CF/CL terminal is set to VOO _ . This aborts filtering and limits
0' the IC current to 0.5 milliamperes.
::::I
lCLK 10 I Clock Inputs - The clock input to the two-phase nonoverlapping generator of each respective filter section
(")
2CLK 11 is used to generate the center frequency of the complex pole pair second-order function. Both clocks should
=i'
n be of the same level (TTL or CMOS) and have duty cycles close to 50%, especially when clock frequencies
c: (fclock) greater than 200 kiloHertz are used. At this duty cycle, the operational amplifiers have t~e maximum
;:;:
In time to settle while processing analog samples.
l1N- 4 I Inverting Inputs - The inverting input side of the input operational amplifier whose output drives the summing
21N- 17 amplifier of each respective filter section.
lLP 1
0 Low-Pass Outputs - The low-pass outputs of the second-order filters.
2LP 20
LS 9 I Level Shift - This terminal accommodates various input clock levels of bipolar (CMOS) or unipolar (TTL or
other clocks) to function with single or dual supplies. For CMOS ( 5-volt) clocks, VOO _ or ground is applied
to the LS terminal. For TTL and other clocks, ground is applied to the LS terminal.
lNAH 3 0 Notch, All-Pass, or High-Pass Outputs - The output of each respective filter section can be used to provide
2NAH 18 either a second-order notch, all-pass, or high-pass output filter function, depending on circuit configuration.
SW 6 I Switch Input - This input terminal is used to control internal switches to connect either the AGNO input or
the LP output to one of the inputs of the summing amplifier. The terminal controls both independent filter sections
and places them in the same configuration simultaneously. If VCC _ is applied to the SW terminal, the AGNO
input terminal will be connected to one of the inputs of each summing amplifier. If VCC + is applied to the
SW terminal, the LP output will be connected to one of the inputs of the summing amplifier.
VCC+ 7 Analog positive supply voltage terminal
VCC-
J> 14 Analog negative supply voltage terminal
c VOO+ 8 Oigital positive supply voltage terminal
<
J>
VOO- 13 Digital negative supply voltage terminal
2
o
m
2
"o
:xl
S
J>
::!
o
2
2-124 TEXAS
INSTRUMENTS
posr OFFICE BOX 655012 DALLAS. TEXAS 75265
ADVANCE TLC10,TLC20
Ell
1CLK (10) ..... <1>1
LS
(9) l~ NONOVERLAPPING
I---
(12) <1>2
J--- CLOCK GENERATOR
CF/CL ~ CONTROL f...-
...
S
en
IN-
(4) .....
(3)
(3
.
CJ
AGND
(15) I~ (2)
1NAH
C
1BP o
.';::;
};I> II> II> 'en
'-- + L....- '-- 'S
1APIN
(5)
....-- -
---- +
L...--
+ ~~ UP <t
C'
CJ
(6)
~ --4
m
m
...
SW C
1-"---
2CLK
(11 ) .....
<1>1
t.... NONOVERLAPPING
I---
<1>2
~ CONTROL J--- CLOCK GENERATOR
f...-
21N-
(17) ..... (18)
l~ 2NAH
v (19)
2BP
'--- +
};I> L....- II> '-- II>
(16) :2:
2APIN
.-- -
'---
+
L...--
+ ~~ 2LP
o
~ 1---1 i=
'---
<C
2
1-"-->- a:
oLL
:2:
w
(.)
:2:
<C
>
c
<C
TEXAS 2-125
INSTRUMENTS
TLC10,TLC20 ADVANCE
Analog supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Digital supply voltage, VDD ................................................ 7 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 70C
Storage temperature range ............ :............................ - 65C to 150C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package. .... . ... ... 260C
c
D) Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260C
r+
D) NOTE 1: All voltage values are with respect to the AGND terminal.

(')
.c MIN NOM MAX UNIT
c Analog supply voltage, VCC , (see Note 2) 4 5 6 V
en'
;=;.' Digital supply voltage, VDD , (see Note 2) 4 5 6 V
0' Clock frequency, fclock' (see Note 3) 0.008 1.0 MHz
::l
Operating free-air temperature, T A 0 70 c
(")
:::;' NOTES: 2. A common supply voltage source should be used for the analog and digital supply voltages. Although each has separate terminals,
(') they are connected together internally at the substrate. VCC + and VDD + can be connected together at the device terminals
c or at the supply voltage source. The same is true for VCC - and VDD _.
;=;.'
en 3. Both input clocks should be of the same level type (TTL or CMOS), and their duty cycles should be at 50% above 200 kHz
to allow the operational amplifiers the maximum time to settle while processing analog samples.
electricalcharacteristicsatVcc = 5V, VOO + =' 5V, TA" 25C (unless otherwise noted)
TLC10 TLC20
Maximum peak-to-peak output
VOPP RL = 3.5 kfl at all outputs 4 4.1 3.8 3.9 V
voltage swing
lOS
Short-circuit output I Source See Note 4
2 2
mA
current, Pins 3 and 18 I Sink 50 50
ICC Supply current 8 10 8 10 mA
NOTE 4: The short-circuit output current for pins 1, 2, 19, and 20 will be typically the same as pins 3 and 18.
operating characteristics at V CC = 5 V, VOO -= 5 V, T A = 25C (unless otherwise noted)

TLC10 TLC20
c
Critical-frequency range
Maximum clock
frequency, fclock
fo x Q :s 200 kHz
See Note 3
20
1
30
1.5
20
1
30
1.5
kHz
MHz
< Clock to center-frequency fo :s 5 kHz, R3/R2 = 10, Pin 12 at 5 V 49.64 49.94 50.24 49.24 49.94 50.64
2
ratio
Mode 1,
fo :s 5 kHz,
See Figure 1 Pin 12 at 0 V
R3/R2 = 20, Pin 12 at 5 V
98.75 99.35
10
99.95 97.86 99.35 100.84
10
ppm/oC
n center freque~cy Mode 1, See Figure 1 Pin 12 at 0 V 100 100
m Filter Q (quality factor) fo :s 5 kHz, R3/R2 = 20, Pin 12 at 5 V 2% 4% 2% 6%
-2 deviation from 20
Mode 1,
fo :s 5 kHz,
See Figure 1 Pin 12 at 0 V
R3/R2 = 20,
2%
500
3% 2%
5.D0
6%
ppm/oC
'TI measured filter Q Mode 1
o Low-pass output deviation Rl = R2 = 10 kfl
2% 2%
::JJ from unity gain Mode 1, See Figure 1
S Crosstalk attenuation 60 60 dB
Clock feedthrough voltage

Operational amplifier
10 10 mV
::! gain-bandwidth product

2.5 2.5 MHz
o Operational amplifier
7 7 VII'S
2 slew rate
2-126 TEXAS ~
INSTRUMENTS
POST OFFICE BOX 855012 DALLAS, tEXAS 75265
ADVANCE TLC10,TLC20
TYPICAL APPLICA liON DATA
modes of operation
The TLC 10 and TLC20 are switched-capacitor (sampled-data) filters that closely approximate continuous
filters. Each filter section is designed to approximate the response of a second-order variable filter. When
the sampling frequency is much larger than the frequency band of interest, the sampled-data filter is a
Ell ....
t/)
good approximation to its continuous time equivalent. In the case of the TLC 10 and TLC20, the ratio is 'S
about 50: 1 or 100: 1. To fully describe their transfer function, a time domain approach would be appropriate. ...
(,)
Since this may appear cumbersome, the following application examples are based on the well known U
frequency domain. It should be noted that in order to obtain the actual filter response, the filter's response c:
must be examined in the z-domain. o
'';:::;
'C;;
fclock
'S
r-- ---- Yz TLC10. TLC20
--, C'
(,)
NONOVERLAPPING
I <t
R1 CLOCK GENERATOR I ....COCO
NAHI C
~~'---------------------+-~----------~--~--NOTCHOUT
...-""'"'".....---f.:..-
.-4--1-_______....;B;;,;,p....;I:....................._ BAND-PASS OUT

I
APIN
1 I
LPI
a..-.~~-+--+-- LOW-PASS OUT
IR3
VDD+
SW
I R2
I I
I I
L ..J 2:
o
fo = fclock/100 or fclock/50 i=
fnotch = fa
HOLP = - R2/R1 (as f -+ 0) <t
HOSp = -R3/R1 (atf = fo) :?!
H _ . j as f approaches 0 - R2/R 1 a::
ON - notch gain las f approaches 0.5 fclock
a = f o/BW = R3/R2 oLL
Circuit dynamics:
The following expressions determine the swing at each output as a function of the desired a of the second-order function.
HOLP = HOSp/a or HOLP x a = HON x a
HOLP (peak) = a x HOLP (for high as)
-w
2:
U.
FIGURE 1. MODE 1 FOR NOTCH, BAND-PASS, AND LOW-PASS OUTPUTS: fnotch = fo 2:
<t
c>
<t
TEXAS
INSTRUMENTS
l.!1 2-127
TLC10,TLC20 ADVANCE
II fclock
r--
~----------------i
----
NONOVERLAPPING
% TLC10. TLC20
---,
I
CLOCK GENERATOR I
>-......__________________-+--+-_______N_A_H...;.I__--4......_ NONINVERTING
.---~.....__... .:,... BAND-PASS OUT (BP2)
r-t-+-________ B_P-::~J_+_- BAND-PASS OUT (BP1)

};[>
+ I
LP I
~""""'I~+-+_- LOW-PASS OUT
R3
VDD+ SW I R2
I I
I I
L ______ _ _____ .J
fo = fclock/100 or fclock/50
a = R3/R2
HOLP = - 1 HOLP (peak) = a x HOLP (for high as)
HOSP1 = - R3/R2
HOSP2 = 1 (noninverting)
Circuit dynamics:
HOSP1 = a
c
FIGURE 2. MODE 1 a FOR NON INVERTING BAND-PASS AND LOW-PASS OUTPUTS
<
2
om
-2
"T1
o
::c
S
::1
o
2
2-128
TEXAS . .
INSTRUMENTS
ADVANCE TLC10,TLC20
fclock
r--
~----------------4
----
NONOVERlAPPING
Yo TLC10. TLC20
-,
I
I
II
... fA
R1 CLOCK GENERATOR 'S
CJ
~
NAHI
>--e~------------------~~--------~--~~----NOTCHOUT
U
BPi
.....-+-+-----------:-....--t------ BAND-PASS OUT
.
'
'U;
'S
r:
o
I C-
APIN
1 I <t
CJ
lPI
........-.,1,....-+--+-......- lOW-PASS OUT ... CO
CO
C
VDD+ SW r 3
R2
1'14
I 1
IL ___________ _ ....JI
fo = fnotch X yR2/R4 + 1
fnotch = fclock/100 or fclock/50
Q = v' R2/R4 + 1
R2/R3
-R2/R1
HOlP (as f approaches 0) =
R2/R4 + 1
HOSp (at f = fo) = -R3/R1
-R2/R1
HON1 (as f approaches 0) = R2/R4 + 1
2:
HON2 (as f approaches 0.5 fclock) = -R2/R1 o
Circuit dynamics: i=
HOSp = Q YH/;'TO-L-P"""x'-H;"7""O-N-2 = Q HON1 x HON2

FIGURE 3. MODE 2 FOR NOTCH 2, BAND-PASS, AND LOW-PASS OUTPUTS: fnotch ( fo :2E
a:
ou.
-w
2:
(J
2:

>
c

TEXAS "'.!} 2-129
INSTRUMENTS
TLC10,TLC20 ADVANCE
fclock
r-- ---- Yz TlC10, TlC20

--,
c
Q)
NONOVERlAPPING
I
r+
Q)
R1 CLOCK GENERATOR I
(') ~~~--------------------~~----------~--~------NOTCHOUT
NAHI
.c
c:::
iii'
;:;.' BPi
...-t-+-------------'---4.....-+------ BAND-PASS OUT
0'
:::l I
n
::;' APIN
1 I
(')
c::: lPI
Ht-~I--t-+-.....--- lOW-PASS OUT
;:;.'
en ...,
VDD-
SW I R3
R2
R4
I
I
I I I
I I ~C1t
L .J :
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~~~~ I
fo = (fclock/100 or fclock/50) ~
Q = ~ X R3/R2
HOHP (as f approaches 0.5 fclock) = - R2/R 1
HOlP (as f approaches 0) = - R4/R 1
HOBP (at f = fo) = - R3/R1
Circuit dynamics:
R2/R4 = HOHP/HOlP: HOBP = yHOHP x HOlP x Q
c
HOlP (peak) = Q x HOlP (for high Qs)
HOHP (peak) = Q x HOHP (for high Qs)
<
tin this mode, the feedback loop is closed ~round the input summing amplifier; the finite GBW product of this operational amplifier will
cause a slight Q enhancement. If this is a problem, connect a low-value capacitor (10 pF to 100 pF) across R4 to provide some phase lead.
2 FIGURE 4. MODE 3 FOR HIGHPASS, BANDPASS, AND LOW-PASS OUTPUTS
("')
m
-2
."
o
:IJ
S
::!
o
2
2-130 TEXAS ~
INSTRUMENTS
ADVANCE TLC10,TLC20
fclock
r-- ------------, y. TlC10. TlC20
NONOVERLAPPING
I o
R1 L.......;'--_ _ _ _ _ _-I CLOCK GENERATOR </>2
I .....
'5
...
CJ
U
c
BPi o
r-t-+-----~I~._t--+--------BANO-PASS OUT ';:;
'en
It> I EXTERNAL
'5
C'
OPERATIONAL CJ
+ ......---1+
AMPLIFIER
NOTCH OUT

IR3 co
.....
Voo- I R2 co
R4 C
I I ' - - - - - - - - L O W - P A S S OUT
I
L ____ _ _ _ _ _ _ _ _ -1I
fo = (fclock/100 or fclock/50) ,JR2/R4

Q = ,JR2/R4 x R3/R2
HOHP = -R2/R1
HOBP = -R3/R1
HOLP = -R4/R1
fnotch = (fclock/100 or fclock/50) .jRii7Rl
HON (at f = fo) = I Q (Rg/Ri x HOLP - Rg/Rh x HOHP) I
HON1 (as f approaches 0) = Rg/Ri x. HOLP
HON2 (as f approaches 0.5 fclock) = - Rg/Rh x HOHP
FIGURE 5. MODE 3a FOR HIGH-PASS, BANDPASS, LOW-PASS, AND

NOTCH OUTPUTS WITH EXTERNAL OPERATIONAL AMPLIFIER :2:
o
i=
<C
~
a:
oLL
-:2:w
CJ
:2:
<C
>
c
<C
TEXAS "J} 2-131
INSTRUMENTS
TLC10,TLC20 ADVANCE
lEI
fclock
r-- ---- % TLC10, TLC20

--,
I
c NONOVERLAPPING
I
...
Q)
Q)
Rl CLOCK GENERATOR

n
.c
c
iii BPi .....+ _ - BAND-PASS OUT
;; ......-I-+-----~I~
o::s
n APIN I I
~.
n LPI
c Ht-"'-I-+-+-- LOW-PASS OUT
;;
en -'-- R3
VDD+ I R2
I I
I I
L ..J
fo = fclock/l00 or fclock/50
fz = fo t
o = fo/BW = R3/R2
Oz = R3/Rl
HOAP (at 0 :s f :s 0_5 fclock) = - R2/Rl = - 1
(for AP output Rl = R2)
HOLP (as f approaches 0) = - (R2/R 1 + 1) = - 2
HOBP (at f = fo) = - R3/R2 (R2/Rl + 1) = - 2 (R3/R2)

c Circuit dynamics:
= = (HOAP + 1) 0
< HOBP HOLP x 0

2
tOue to the sampled-data nature of the filter, a slight mismatch of fz and fo occurs causing a OA-dB peaking around fo of the all-pass
filter amplitude response (which theoretically should be a straight line)_ If this is unacceptable, Mode 5 is recommended_
(") FIGURE 6. MODE 4 FOR ALLPASS, BANDPASS, AND LOWPASS OUTPUTS

m
-2
'T1
o
:Jl
S

::::j
o
2
2-132
TEXAS
INSTRUMENTS
ADVANCE TLC10,TLC20
VI
J--
fclock
I
r--
IClK
- - - - - - - - -- --,
I
NONOVERlAPPING
~
~ TlC10 TLC20
I II
....en
R1 I CLOCK GENERATOR r/>2 I S
IIN_ ..... NAHI
...CJ
C3
...I~
IAGND COMPLEX ZERO OUT
~I I c
.~
o
I BPi
BAND-PASS OUT 'm
APIN I
I
~
"-+ - Ii> _ J[> - I
I
S

C"
CJ
- "--- I....-
,I lPI ....teltel
----
r--- ~+ + lOW-PASS OUT
~ ~ -
. :,-1-_
L- -'- L......-.- I C
R3
VDD+~ I
R2
R4
I
L ___ _ _ _ _ _ ....J
I
----
fo = .JR2/R4 + 1 x (fclock/100 or fclock/50)
fz = .J1 - R1/R4 x (fclock/100 or fclock/50)
Q = JR2i'R4+1 x R3/R2
Qz = Jl - Rl/R4 x R3/Rl
HOZl (as f approaches 0) = R2 (R4 - Rl )/Rl (R2 + R4)
HOZ2 (as f approaches 0.5 fclock) = R2/Rl
HOBP = (R2/Rl + 1) x R3/R2
HOlP = (R2 + R1)/(R2 + R4) x R4/Rl
2
FIGURE 7. MODE 5 FOR NUMERATOR COMPLEX ZEROS. BAND-PASS. AND LOWPASS OUTPUTS
o
i=
<C
:E
a:
oLL
-2w
(.)
2
<C
>
c
<C
TEXAS -1.!1 2-133

INSTRUMENTS
TLC10,TLC20 ADVANCE
fclock
r--------------, ~ TlC10, TlC20
cQ) NONOVERlAPPING
I
.... R1 L..---------t CLOCK GENERATOR 1/>2
I
Q)

n
.c
c
iii'
::+ .-+-+-_ _ _ _B_p-.:-I-e-+_ lOWPASS OUT
ci"
:::J
I (INVERTED)
E[>
(")
:;. APIN I + I
n lPI
c
::+ IR3
en
VDD- I R2
I
I
_ _ _ _ _ _ _ ...1
fc = R2/R3 (fclock/100 or fclock/50)

HOlP = -R3/R1
HOHP = - R2/R1
FIGURE 8, MODE 6 FOR SINGLE-POLE HIGH-PASS AND LOW-PASS OUTPUT
c
<
z
(")
m
-Z
"o
:c
S
:j
o
z
2-134 TEXAS.
INSTRUMENTS
ADVANCE TLC10,TLC20
TYPICAL APPLICATION DATA"
fclock
r-- ---- y. TLC10. TLC20
--,
'---=--_ _ _ _ _ _~ NONOVERLAPPING
I ..,
U)
CLOCK GENERATOR I 'S

>-...._ _ _ _ _ _ _ _ _-+-+-_ _ _N_A_H...:..'_--4~-
...
(,)
r---:--.--i./
LOW-PASS OUT
(NON INVERTED)
C3
c
o
'';:;
....-+-+-_ _ _---.,;;B;.;..P~'__~-- LOW-PASS OUT 'Ci)
I (INVERTED) 'S
C'
APIN'
I ~
(,)
VI --+~;..;;.;.;;..o""""f--------1
LPI ..,CO
CO
I C
I R1 R2
I
I
L ___ _ _ _ _ _ _ _ _ .J
,
I
fc = R2/R3 x (fclock/100 or fclock/50)

HOlP1 = 1 (noninverting)
HOlP2 = - R3/R2
FIGURE 9. MODE 6a FOR SINGLEPOLE LOWPASS OUTPUT (INVERTED AND NON INVERTED)
2:
o
i=

~
a::
oLL
-w
Z
(.)
2:

c>

TEXAS -I!} 2-135
INSTRUMENTS
TLC10,TLC20 ADVANCE
II
C
D)
vcc+
5V
(61
(91
SW
T TLC10, TLC20 I
vcc+ Voo+
2LP
(201
(191
LOW-PASS
OUTPUT
r+ LEVEL SHIFT 2BP
D) 200kHz _(111 (181

(')
TTL CLOCK
l!.!.!!.
2CLK
1CLK
2NAH
.c (11
c CENTER FREQ/ 1LP
(ii' CURRENT LIMIT (21
;::::;.' ~ CONTROL
1BP
(5) (31
0' INPUT 1APIN 1NAH r-
:::::J (161 (121
CF/CL
r1
2APIN
(') (41
:::;' 11N-
(')
C
..!!Z!. 21N- R2 R3 R2' R3'
;::::;.' VCC- Voo- R2 = 100 kll
en R2 = 100 kll
-5 V
1- I R3 = 53.6 kll
R3 , = 130 kll
FIGURE 10. FOURTHORDER 2kHz LOWPASS BUTTERWORTH FILTER
filter terminology
fc The cutoff frequency of the lowpass or high-pass filter output
fclock The input clock frequency to the device
fnotch The notch frequency of the notch output
fo The center frequency of the complex pole pair second-order function
fz The center frequency of the complex zero pair
HOSp The band-pass output voltage gain (V/v) at the band-pass center frequency
HOHP The high-pass output voltage gain (V/v) as the frequency approaches 0.5 fclock
c
HOlP
HON
The low-pass output voltage gain (V/V) as the frequency approaches 0
The notch output voltage gain (V/v) at the notch frequency
<
HON1
HON2
The low-side notch output voltage gain as the frequency approaches 0
The high-side notch output voltage gain/as the frequency approaches 0.5 fclock
Gain at complex zero output (as f ... 0 Hz)
2 HOZ1
n HOZ2 Gain at complex zero output (as f approaches 0.5 fclock)
m Q The quality factor of the complex pole pair second-order function. Q is the ratio of fo to
the 3-dS bandwidth of the band-pass output. The value of Q also affects the possible
2 peaking of the low-pass and high-pass outputs.
." The quality factor of the complex zero pair, if such a complex pair exists. This parameter is
o used when an all-pass filter output is desired.
II
S
::!
o
2
2-136
TEXAS -II}
INSTRUMENTS
ADVANCE TLC10,TLC20
>
>
Ci
(!J
HOBP~----------~~
; 0.707 HOBP
S
U
....en
...
(J
fL fo fH
f (LOG SCALE)
'
o
'0
'S
.c
FIGURE 11. BANDPASS OUTPUT C'

(J
<t
,. ....coco
C
HOp
.--'-
'""
> HOLP fc = fo x
>
; 0.707 HOLP
Ci
(!J
fp = fo J, - 2~2
HOp = HOLP x --===
fp fc
. 2..), _ ' 2
o 40
f (LOG SCALE)
FIGURE 12. LOW-PASS OUTPUT
HOp~--------~~,
> HOHP~--------~~ :2:
>
; 0.707 HOHP 1-------,(
o
Ci i=
~

HOp = HOHP x -----',--- :2E
2..), _ ' 2 a:
fp
o 40 oLL
f (LOG SCALE) 2:
FIGURE 13. HIGH-PASS OUTPUT w
(.)
:2:

>
c

TEXAS
INSTRUMENTS
l.!J 2-137
IJ
c
....
Q)
Q)

(')
.c
c
Ci)'
~
0'
::s
n
::;'
(')
c
;::;"
en
2-138
TLC532AM, TLC532AI, TLC533AM, TLC533AI
LinCMOSTM 8BIT ANALOGTODlGITAL PERIPHERALS
WITH 5 ANALOG AND 6 DUALPURPOSE INPUTS
0281 NOVEMBER 1983-REVISED SEPTEMBER 1986
linCMOSTM Technology N DUAL-IN-LINE PACKAGE

(TOP VIEW)
8Bit Resolution
REF - REF + (A 1 )
Total Unadjusted Error ... 0.5 LSB Max
GND VCC
Ratiometric Conversion 2 - 1 (MSB) AO }
Access Plus Conversion Time: 2- 2 A2 ANALOG
TLC532A ... 15 p's Max I/O 2- 3 A3 INPUTS
2- 4 A4
TLC533A ... 30 p.s Max DATA
2 -5 A5
BUS
~ =~ ~ ~ ~~~~
3State, Bidirectional 1/0 Data Bus
5 Analog and 6 DualPurpose Inputs }ANAlOG/
2 - 8 (lSB) A 12/D3 DIGITAL
On-Chip 12-Channel Analog Multiplexer READ/WRITE (R/W) A 13/D4 INPUTS
CLOCK (ClK) A 141D5
Three On-Chip 16-Bit Data Registers
REGISTER SELECT (RS) A 151D6
Software Compatible with Larger TL530 and CHIP SELECT (CS) RESET (R)
TL531 (21-lnput Versions) -....----'-
On-Chip Sample-and-Hold Circuit FN CHIP CARRIER PACKAGE
(TOP VIEW)
Single 5-V Supply Operation
OJ
Low Power Consumption ... 6.5 mW Typ en $
~ + U I
Improved Direct Replacements for Texas N 0 U. U.
Instruments TL532 and TL533, National I I Zww UO
N N (!)a:a: >~
Semiconductor ADC0829, and Motorola
4 3 2 1 282726
MC14442
2- 3 5 25 A2
description 2- 4 6 24 A3
2- 5 23 A4
The TLC532A and TLC533A are monolithic 2- 6 8 22 A5
LinCMOSTM peripheral integrated circuits each 2- 7 9 21 Al0/Dl
designed to interface a microprocessor for 2 -8 (lSB) 10 20 All/D2
analog data acquisition. These devices are 11 19 A12/D3
R/W
complete peripheral data acquisition systems on 12 131415 161718
a single chip and can convert analog signals to
digital data from up to 11 external analog :J ~1~1a: <OLn'<t
000
terminals. Each device features operation from U Ln~M
a single 5-volt supply. Each contains a ~~~
12-channel analog multiplexer, an 8-bit
ratiometric analog-to-digital (A/D) converter, a FUNCTION TABLE
sample-and-hold, three 16-bit registers, and ADDRESS/CONTROL
DESCRIPTION
microprocessor-compatible control circuitry. R/W RS CS R CLK
Additional features include a built-in self-test, six X X X Lt Reset
multipurpose (analog or digital) inputs, five Write bus data to control
L H L H ~
external analog inputs, and an 8-pin input/output register
(I/O) data port. The three on-chip data registers Read data from analog
store the control data, the conversion results, H L L H t
conversion register
and the input digital data that can be accesssed Read data from ditigal
via the microprocessor data bus in two 8-bit H H L H t
data register
bytes (most-significant byte first). In this X X H H X No response
manner, a microprocessor can access up to 11
external analog inputs or 6 digital signals and the H = High-level, L = Low-Ie\iel, X = Irrelevant
~ = High-to-Iow transition, t = Low-to-high transition
positive reference voltage that may be used for tFor proper operation, Reset must be low for at least three clock cycles.
self-test. LinCMOS is a trademark of Texas Instruments.
specifications per the terms of Texas Instruments TEXAS . . 2-139
~~~~~:~~i~at~~1~1~ ~!~~~~ti:f :I~o::~:~:t:ros~s not INSTRUMENTS
LinCMOSTM 8"BIT ANALOGTODlGITAL PERIPHERALS
description (continued)
The A/D conversion uses the successive-approximation technique and switched-capacitor circuitry. This
lEI
cD)
method eliminates the possibility of missing codes, nonmonotonicity, and a need for zero or full-scale
adjustment. Anyone of 11 analog inputs (or self-test) can be converted to an 8-bit digital word and stored
in 10 microseconds (TLC532A) or 20 microseconds (TLC533A) after instructions from the microprocessor
have been recognized. The on-chip sample-and-hold functions automatically to minimize errors due to noise
r+ on the analog inputs. Furthermore, differential high-impedance reference inputs are available to help isolate
D)
the analog circuitry from the logic and supply noises while easing ratiometric conversion and scaling.

n The TLC532AM and TLC533AM are available in both the Nand FN plastic packages and are characterized
.c for operation from - 55C to 125C. The TLC532AI and TLC533AI are characterized for operation from
c
C;;" -40C to 85C.
;:::;."
0" functional description
::::I
C') The TLC532A and TLC533A provide direct interface to a microprocessor-based system. Control of the
::;" TLC532A and TLC533A is handled via the a-line TTL-compatible 3-state data bus, the three control inputs
n (Read/Write, Register Select, and Chip Select), and the Clock input. Each device contains three 16-bit internal
c
;:::;." registers. These registers are the control register, the analog conversion data register, and the digital data
en register.
A high level at the Read/Write input and a low level at the Chip Select input set the device to output data
on the a-line data bus for the processor to read. A low level at the Read/Write input and a low level at
the Chip Select input set the device to receive instructions into the internal control register on the 8-line
data bus from the processor. When the device is in the read mode and the Register Select input is low,
the processor will read the data contained in the analog conversion data register. However, when the
Register Select input is high, the processor reads the data contained in the digital data register.
The control register is a write-only register into which the microprocessor writes command instructions
for the device to start A/D conversion and to select the analog channel to be converted. The analog
conversion data register is a read-only register that contains the current converter status and most recent
conversion results. The digital data register is also a read-only register that holds the digital input logic
levels from the six dual-purpose inputs.
Internally each device contains a byte pointer that selects the appropriate byte during two cycles of the
Clock input in a normal 16-bit microprocessor instruction. The internal pointer will automatically point to
the most-significant (MS) byte after the first complete clock cycle any time that the Chip Select is at the
high level for at least one clock cycle. This causes the device to treat the next signal on the a-line data
bus as the MS byte. A low level at the Chip Select input activates the inputs and outputs and an internal
function decoder. However, no data is transferred until the Clock goes high. The internal byte pointer first
points to the MS byte of the selected register during the first clock cycle. After the first clock cycle in
which the MS byte is accessed, the internal pointer switches to the LS byte and remains there for as long
as Chip Select is low. The MS byte of any register may be accessed by either an 8-bit or a 16-bit
microprocessor instruction; however, the LS byte may only be accessed by a 16-bit microprocessor
instruction.
Normally, a two-byte word is written into or read from the controlling processor, but a single byte can
be read by the processor by proper manipulation of the Chip Select input. This can be used to read conversion
status from the analog conversion data register or the digital mUltipurpose input levels from the digital
data register. The format and content of each two-byte word is shown in Figures 1 through 3.
2-140 TEXAS ~
INSTRUMENTS
LinCMOS 8BIT ANALOGTODlGlTAL PERIPHERALS
functional description (continued)

A conversion cycle is started after a two-byte instruction is written into the control register and the start
conversion (SC) bit is a logic high. This two-byte instruction also selects the input analog channel to be
converted. The status (EOC) bit in the analog conversion data register is reset and it remains reset until
the conversion is completed, at that time the status bit is then set again. After conversion, the results
(I)
are loaded into the analog conversion data register. These results remain in the analog conversion data ~
register until the next conversion cylce is completed. If a new conversion command is entered into the 'S
control register while the conversion cycle is in progress, the on-going conversion will be aborted and a ...
(J
new channel acquisition cycle will immediately begin. U

The Reset input allows the device to be externally forced to a known state. When a low level is applied c:
o
to the Reset input for a minimum of three clock periods, the start conversion bit is cleared. The AID converter '';:;
is then idled and all the outputs are placed in the high-impedance off-state. However, the content of the 'Ci)
analog conversion data register is not affected by the Reset input going to a low level. 'S
C'
(J
<C
CO
~
CO
DATA BUS
e
(2-8 _2-1) ~ ,8.;-
RNi
cs ,.. DATA
r BUS
RS CONTROL
,.. LOGIC
R ~"8 . ,v 8 }'8
CLOCK
II I
jr-
~ DIGITAL DATA ~ CONTROL ANALOG
CONVERSION
REGISTER REGISTER REGISTER
~ (READ ONL V) (WRITE ONL V) (READ ONLV)
6
~ ... ANALOG MUX,( 4
ANALOG/DIGITAL ,
j"
INPUT 6
~
I ADDRESS
" 8
(A10/D1 - A15/D6)
;~ 6
, SAMPLE
8BIT
EXTERNAL ANALOG .. 5.... 11.... 12CHANNEL ANALOGTODIGITAL
INPUT , , MULTIPLEXER
I--- AND ~
CONVERTER
HOLD
(AO,A2 -A5) (SWITCHEDCAPACITORS)
~
~A1
REF+
REF
TEXAS . . 2-141
INSTRUMENTS
t;-'
.j::.
Sl!n3J!O UD!l!S! nb3 V elea II
~s-;:::!
r+
N
'<
'0
(=)' -tnn
!!.. ::C3:U"I
o U"IQ~
'0 >en>
CD Zi!3:
m >= .. .
r+
5' ,...'-t
CQ Q=""
289 290 en ==i~
CLOCK
CD
..Q
w
ZZN
C
I I
START CONVERSION CYCLE
I I CD
:::J
cr
,...:-
j4---twl(reset)~ It IF SC BIT IS lOGIC ONE (HIGH) ~I n CftQ
R I I! I ! I
CD
crC?;:::!
.L-_ _ _ _ _ _ _ _..... !4-t--iWRITE CYCLE ~14
I
: READ CYCLE ~I I ! c-tn
>QU"I
I I
tsu(A)-+! i4-: I
:i I
t SU (A)"1
I
~
:
:
i
:
~WRITE~
! Cr
elE
I
,...'w
,crw
"'a->
i
~
Q
:!l_
Rfii :
I
I
I
WDON'T?N
~CARE ~ I _
tM:i
~
:I
=
cE:!3:
-t ..
~~-t
~Z cn"'a~
!3(J) mmU"l
~ -I '
cs -:a w
,3 ;tI~ z-w
"'a "'a>
c::C-
~~ C~
~ -t m
I
en=
~1"'1
~z
RS
I I
I
i I
I
I
I
,...
>
en
~1;; w.ct
I I
-+i I I I I
tsu(bus)---' *-: I.-tsU(bUS):
~ I4-len
!4-ten
I ~ I+ton M-ten
I
-.l
I
-.l f+o
: I
I ! ! I : I t 14- ten -+j ~tsu!US)l.-tSU(bUS)
.... lS MS lS lS
I en MS lS MS lS
I
'"'"
Ol BYTE BYTE BYTE BYTE BYTE I BYTE BYTE BYTE BYTE
'" DATA
BUS
HIZ STATE
HIZ
~STATE1
SEE NOTE A
NOTES: A. This is a 16-bit input instruction from the microprocessor being sent to the control data register.
B. This is the 2-byte (16-bit) content of the digitaL data register being sent to the microprocessor.
C. This is the LS byte (S-bit) content of the analog conversion data register being sent to the microprocessor.
D. This is the LS byte (S-bit) content of the digital data register being sent to the microprocessor. .
E. These are MS byte (S-bit), LS byte (S-bitl. and LS byte (S-bit) content of the analog conversion data register or digital data
register being sent to the microprocessor.
F. This is the 2-byte (16-bit) content of the analog conversion data register being sent to the microprocessor.
LinCMOS 8BIT ANALOGTODIGITAL PERIPHERALS
WITH 5 ANALOG AND 6 DUALPUR~OSE INPUTS
read or write cycle time sequence
trlClK) +I \4- -+I \4-tf(ClK) CLocn. CLOCK.,. 28g

3
Sh~
ClK
I
I I I ~
R lL-___ -..J
I START I END I "S
(See Note A)
CONTROL
~ tsu(A)
It-I CONVERSION
I
CONVERSION -+I
.
I U
E
INPUTS
Riw XXXXxxxxxxm"'-I-+--~!;XXXX~ c
o
RS , I I I "';::;
tsu(CS)-a.i !.- -+ll4-th(CI I "Ci)
-I 1- I I I
"S
~~l____~________-J~
C"
(,)
I I
: I
I
...co
CO
~ I+-ten
I
C
I
DATA BUS
DATA OUT
("READ")
--------------------------t BYT~ HI-Z
lS!
HI-Z
BYT See Note B
I
I I
-+!l4""" t dis ....ll4- t dis
tsu (bus)4! ~ -.! /4- tsu(bus)
r-r "I
DATA BUS I I
HI-Z HIZ HIZ
DATA IN I I
MS lS I
("WRITE") I
BYTE BYTE I
~ "---
th(bus)~j4- -+j j+"thlbus)
1
I
tacq .1
NOTES: A. The reset pulse (R low) is required only during power-up. "
B. The most-significant byte output of Data Out occurs when elK is high. When elK is low, Data Out is in the high-impedance
(off) state. When elK goes high again, the least-significant byte is placed on the data bus. At this point, the least-significant
byte will remain on the bus for as long as elK is kept high.
TEXAS . . 2-143
INSTRUMENTS
LinCMOSTM 8BIT ANALOGTODIGITAL PERIPHERALS
DATA BUS
LINES 2- 1 2-2 2- 3 2- 4 2- 5 2- 6 2- 7 2- 8 2- 1 2-2 2- 3 2- 4 2- 5 2- 6 2- 7 2- 8
I(M~B) I(~S~)I I(M~B)I I I I(~~) I

X X X X X X X X X A3 Al
A2
I I I I I I I I
MOST-S)GNIFICANT BYTE I I~ LEAST-SIGNIFICANT BYTE
c
Q)
r+
Q)
t 16-B)T WRITE
Unused Bits (X)- The MS byte bits 2 - 1 through 2 -7 and LS byte bits 2 -1 through 2 -4 of the control register are not used internally.
:1
Start Conversion (SC) - When the SC bit in the MS byte is set to a logical 1 (high level). analog-to-digital conversion of the specified analog channel
l> will begin immediately after the completion of the control register write.
n
.c Analog Multliplex Address (AO-A3) - These four address bits are decoded by the analog multiplexer and used to select the appropriate analog channel as
c shown below:
(ii'
Hexadecimal Address (A3 = MSB) Channel Select
::+'
0' o AO
::J REF+ (A1)
n
:;i'
2-5 A2-A5
6-9 (not used)
n
c A-F Al0-A15
::+' FIGURE 1. CONTROL REGISTER TWO-BYTE WRITE WORD FORMAT AND CONTENT
en
DATA BUS
LINES 2- 1 2- 2 2- 3 2- 4 2- 5 2- 6 2- 7 2- 8
1~(_~_~_~_)~I__O__L-_o__~_o__~I__o__~I__o__~I__o__~
R5 R4 R3
14---------- MOST-SIGNIFICANT BYTE - - - - - - - I~.----------- LEAST-SIGNIFICANT BYTE---------~

...- - - - - - - - - - - - - - - 8-BIT READ - - - - - - - - - - :1
1 4 - - - - - - - - - - - - - - - - - - - - 1 6 - B I T READ ------------------_+(
AID Status (EOC) - The AID status end-of-conversion (EOC) bit is set whenever an analog-to-digital conversion is successfully completed by the AID converter.
The status bit is cleared by a 16-bit write from the microprocessor to the control register. The remainder of the bits in the MS byte of the analog conversion
data register are always reset to logical 0 to simplify microprocessor interrogation of the AID converter status.
AID Result (RO-Rll - The LS byte of the analog conversion data register contains the result of the analog-to-digital conversion. Result bit R7 is the MSB and
the converter follows the standard convention of assigning a code of all ones (11111111) to a full-scale analog voltage. There are no special overflow
or underflow indications.
FIGURE 2. ANALOG CONVERSION DATA REGISTER ONE-BYTE AND

TWO-BYTE READ WORD FORMAT AND CONTENT
DATA BUS
LINES 2- 1
A15
106
(MSB)
...- - - - - - - - MOST-SIGNIFICANT BYTE ------!~ I. LEAST-SIGNIFICANT BYTE ---------~

14---------------8-BIT READ ---------.t
14----------------------16-BITREAD-------------------~
Shared Digital Port (A 1010 1-A 15/06) - The voltage present on these pins is interpreted as a digital signal and the corresponding states are read from these
bits. A digital value will be given for each pin even if some or all of these pins are being used as analog inputs.
Analog Multiplexer Address (AO-A3) - The address of the selected analog channel presently addressed is given by these bits.
Unused Bits (X)- LS byte bits 2- 3 through 2- 8 of the digital data register are not used.
FIGURE 3. DIGITAL DATA REGISTER ONE-BYTE AND TWO-BYTE READ WORD FORMAT AND CONTENT
2-144 TEXAS -1.!1

INSTRUMENTS
LinCMOSTM 8BIT ANALOGTODlGlTAL PERIPHERALS

Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 6.5 V
Input voltage range: Positive reference voltage. . . . . . . . . . . . . . . . . . . . .. VREF - to VCC + 0.3 V
Negative reference voltage. . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to VREF +
All other inputs ........ . . . . . . . . . . . . . . . . . . . .. - 0.3 V to VCC + 0.3 V
(/)
Input current, II (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10 mA ~
Total input current, (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA 5

Operating free-air temperature range: TLC532AM, TLC533AM .............. - 55C to 125C ...CJ
TLC532AI, TLC533AI ................. - 40C to 85 C C3
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C s::::
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package. . . . . . . . . . . .. 260C o
'~
Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260C '(ii
NOTE 1: All voltage values are with respect to network ground terminal. '5
C"
recommended operating conditions CJ
TLC532A TLC533A

UNIT CO
~
MIN NOM MAX MIN NOM MAX CO
Supply voltage, VCC 4.75 5 5.5 4.75 5 5.5 V C
Positive reference voltage, VREF + (see Note 2) 2.5 vce vee+ O. 1 2.5 Vee vee+ 0 . 1 V
Negative reference voltage, VREF _ (see Note 2) -0.1 0 2.5 -0.1 0 2.5 V
Differential reference voltage, VREF + - VREF- 1 vee vee+ 0 .2 1 Vee Vee+ 0 . 2 V
High-level input voltage, VIH

IClock input vee- O. B Vee- O.B
V
I All other digital inputs 2 2
Low-level input voltage, VIL IAny digital input 0.8 0.8 V
Clock frequency, fCLK 0.1 2 2.048 0.1 1.048 1.06 MHz
CS setup time, tsu(CS) 75 100 ns
Address (R/W and RS) setup time, tsu(A) 100 145 ns
Data bus input setup time, tsu(bus) 140 185 ns
Control (R/W, RS, and CS) hold time, th(C) 10 20 ns
Data bus input hold time, th(bus) 15 20 ns
Pulse duration of control during read, tw(C) 305 575 ns
Clock
Pulse duration, reset low, twL(reset) 3 3
Cycles
Pulse duration of clock high, twH(CLK) 230 440 ns
Pulse duration of clock low, twL(CLK) 200 410 ns
Clock rise time, tr(CLK) 15 25 ns
Clock fall time, tf(CLK) 16 30 ns
Operating free-air ITLC __ AM -55 125 -55 125
ITLC __ AI -40 -40
c
temperature, T A 85 85
NOTE 2: Analog input voltages greater than or equal to that applied to the REF + terminal convert to all ones (11111111), while input
voltages equal to or less than that applied to the REF - terminal convert to all zeros (00000000). For proper operation, the positive
reference voltage, VREF +, must be at least 1-volt greater than the negative reference voltage, VREF _ . In addition, unadjusted
errors may increase as the differential reference voltage, VREF + - VREF _, falls below 4.75 volts.
TEXAS . . 2-145
INSTRUMENTS
TLC532AM, TLC532AI
electrical characteristics over recommended operating free-air temperature range, VREF + VCC,
VREF - at ground, fCLK = 2 MHz (unless otherwise noted)
III
c
VOH
VOL
PARAMETER
low-level output voltage
High-level Any digital or Clock input
TEST CONDITIONS
10H = -1.6 rnA
10L = 1.6 rnA
MIN
2.4
Typt MAX
0.4
10
UNIT
V
V
....
Q)
Q)
IIH
input current Any control input
VIH = 5.5 V
1
p.A
Low-level Any digital or Clock input -10

l> IlL
VIL = 0
-1
p.A
n
.c Off-state (high impedance-state) VO=VCC 10
c 10Z
output current Vo = 0 -10
p.A
Ci)'
;:;" II Analog input current (see Note 3) VI = 0 to VCC 500 nA
0' Leakage current between selected channel VI = 0 to VCC.
400 nA
::J and all other analog channels Clock input at 0 V
(") Digital pins 3 thru 10 4 30
Ci Input capacitance pF
~' Any other input pin 2 15
n
c ICC+IREF+ Supply current plus reference current
VCC = VREF+ = 5.5 V.
1.5 3 rnA
;:;" Outputs open
en
ICC Supply current VCC = 5.5 V 1.4 2 rnA
NOTE 3: Analog input current is an average of the current flowing into a selected analog channel input during one full conversion cycle.
operating characteristics over recommended operating free-air temperature range, VREF + = Vcc,
VREF - at ground, fCLK = 2 MHz (unless otherwise noted)
Linearity error See Note 4 0.5 LSB
Zero error See Note 5 0.5 LSB
Full-scale error See Note 5 0.5 LSB
Total unadjusted error See Note 6 0.5 LSB
Absolute accuracy error See Note 7 1 LSB
Conversion time (including Clock
tconv 30
channel acquisition time) Cycles
Clock
tacq Channel acquisition time prior to starting conversion 10
Cycles
ten Data output enable time (see Note 8) CL = 50 pF. RL = 3 kG. 250 ns
tdis Data output disable time CL = 50 pF. RL = 3 kG 10 ns
Data bus output High-impedance to high-level 150
tr(bus) CL = 50 pF. RL = 3 kG ns
rise time Low to high-level 300
Data bus output High-impedance to low-level 150
tf(bus) CL = 50 pF. RL = 3 kG ns
fall time High to low-level 300
tTypical values are at VCC = 5 V. T A = 25 DC.

NOTES: 4. Linearity error is the deviation from the best straight line through the AID transfer characteristics.
6. Total unadjusted error is the sum of linearity. zero. and full-scale errors.
7. Absolute accuracy error is the maximum difference between an analog value and the nominal midstep value within any step.
This includes all errors including inherent quantization error. which is the 0 .. 5 LSB uncertainty caused by the AID converters
finite resolution.
8. If chip-select setup time. tsu(CS). is less than 0.14 microseconds. the effective data output enable time. ten. may extend
such that tsu(CS) + ten is equal to a maximum of 0.475 microseconds.
2-146
TEXAS -Ij}
INSTRUMENTS
TLC533AM. TLC533AI
LinCMOS 8BIT ANALOGTODlGlTAL PERIPHERALS
electrical characteristics over recommended ranges Vcc, VREF +, and operating free-air temperature,
VREF - at ground, fCLK = 1.048 MHz (unless otherwise noted)
VOH
VOL
PARAMETER
High-level Any digital or Clock input
TEST CONDITIONS
10H = -1.6 rnA
10L = 1.6 rnA
VIH = 5.5 V
MIN
2.4
Typt MAX
0.4
10
UNIT
V
V
p.A
FJI
....
.:;
en
IIH
input current Any control input 1
Low-level Any digital or Clock input -10
p.A
...
(,)
IlL
VIL = 0
-1 U
Off-state (high impedance-state) VO=ycc 10 c
10Z
output current
Analog input current (see Note 3)
Vo = 0
VI = 0 to VCC
-10
500
p.A
nA
..U;.;:o
II
Leakage current between selected channel VI = 0 to VCC, .:;
400 nA
and all other analog channels Clock input at 0 V C"
(,)
Digital pins 3 thru 10 4 30
Ci Input capacitance
Any other input pin 2 15
pF <t
ICC+IREF+ Supply current plus reference current
VCC = VREF + = 5.5 V,
1.3 3 rnA
....COCO
Outputs open
C
ICC Supply current VCC = 5.5 V 1.2 2 rnA
NOTE 3: Analog input current is an average of the current flowing into a selected analog channel input during one full conversion cycle.
operating characteristics over recommended ranges V cc, VREF + ' and operating free-air temperature,
VREF - at ground,fclock = 1.048 MHz (unless otherwise noted)
Zero error See Note 5 0.5 LSB
Full-scale error See Note 5 0.5 LSB
Absolute accuracy error See Note 7 1 LSB
Conversion time (including Clock
tconv 30
channel acquisition time) Cycles
Clock
tacq Channel acquisition time prior to starting conversion 10
Cycles
ten Data output enable time (see Note 8) CL = 50 pF, RL = 3 HI, 335 ns
tdis Data output disable time CL - 50 pF, RL = 3 kfl 10 ns
Data bus output High-impedance to high-level 150
tr(bus) CL = 50 pF, RL = 3 kfl ns
rise time Low to high-level 300
Data bus output High-impedance to low-level 150
tf(bus) CL = 50 pF, RL = 3 kfl ns
fall time High to low-level 300
tTypical values are at VCC = 5 V, TA = 25 DC.

NOTES: 4. Linearity error is the deviation from the best straight line through the AID transfer characteristics.
6. Total unadjusted error is the sum of linearity, zero, and full-scale errors.
7 _ Absolute accuracy error is the maximum difference between an analog value and the nominal midstep value within any step.
This includes all errors including inherent quantization error, which is the O. 5 LSB uncertainty caused by the AID converters
finite resolution.
8. If chip-select setup time, tsu(CS), is less than 0.14 microseconds, the effective data output enable time, ten, may extend
such that tsu(CS) + ten is equal to a maximum of 0.475 microseconds.
. "js
. TEXAS "V 2-147
INSTRUMENTS
III
c
....
Q)
Q)
l>
(")
.c
c
Ci)'
:=;.'
0'
.::J
(")
::;'
(")
c
:=;.'
en
2-148
TLC540M, TLC5401, TLC541 M, TLC5411
LinCMOS 8BIT ANALOGTODlGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
02799, OCTOBER 1983-REVISED DECEMBER 1985
N DUAL-IN-LiNE PACKAGE
LinCMOSTM Technology
(TOP VIEW)
II
8-Bit Resolution AID Converter
INPUT AO VCC
Microprocessor Peripheral or Stand-Alone INPUT A1 SYSTEM CLOCK
Operation INPUT A2 I/O CLOCK
On-Chip 12-Channel Analog Multiplexer INPUT A3
INPUT A4
ADDRESS INPUT
DATA OUT
...
en
oS
Built-In Self-Test Mode INPUT A5 CS ...
(.)
Software-Controllable Sample and Hold INPUT A6 REF+ U

INPUT A7 REF- r:::
Total Unadjusted Error ... 0.5 LSB Max INPUT AS INPUT A10 o
0';::;
TLC54.1 is Direct Replacement for Motorola GND INPUT A9
en
oS
MC145040 and National Semiconductor
FN CHIP CARRIER PACKAGE C"
ADC0811. TLC540 is Capable of Higher
(TOP VIEW) (.)
Speed
<t
...
~
Pinout and Control Signals Compatible with u CO
o- l
TLC 1540 Family of 10-Bit AID Converters U
CO
C
TYPICAL PERFORMANCE TLC540 TLC541
r5
Channel Acquisition Sample Time 2/ls 3.6/ls
uti;
u>-
>(J)
Conversion Time 9/ls 17/ls
Samples per Second 75 x 103 40 x 103
6mW 6 mW 3 2 1 2019
Power Dissipation
INPUT A3 4 18 I/O CLOCK
description INPUT A4 5 17 DATA IN
The TLC540 and TLC541 are LinCMOSTM AID 6 INPUT 16A5 DATA OUT
. peripherals built. around an 8-bit switched- 7 INPUT 15A6
capacitor successive-approximation AID 8 INPUT 14A7 REF+
converter. They are designed for serial interface 9 1011 1213
to a microprocessor or peripheral via a three-
state output with up to four control inputs
[including independent System Clock, I/O Clock,
Chip Select (CS), and Address Input]. A
4-megahertz system clock for the TLC540 and
a 2.1-megahertz system clock for the TLC541
with a design that includes simultaneous
readlwrite operation allow high-speed data
transfers and sample rates of up to 75,180 samples per second for the TLC540 and 40,000 samples per
second for the TLC541 . In addition to the high-speed converter and versatile control logic, there is an on-
chip 12-channel analog multiplexer that can be used to sample anyone of 11 inputs or an internal "self-
test" voltage, and a sample-and-hold that can operate automatically or under microprocessor control.
The converters incorporated in the TLC540 and TLC541 feature dproofifferential high-impedance reference
inputs that facilitate ratio metric conversion, scaling, and analog circuitry isolation from logic and supply
noises. A switched-capacitor design allows guaranteed low-error (0.5 LSB) conversion in 9 microseconds
for the TLC540 and 17 microseconds for the TLC541 over the full operating temperature range.
The TLC540 and the TLC541 are available in both the Nand FN plastic packages. The M-suffix versions
are characterized for operation from - 55 DC to 125 C. The I-suffix versions are characterized for operation
from - 40 DC to 85 DC.
LinCMOS is a trademark of Texas Instruments Incorporated
~~aC~~~~~i~a{~~I~~~ ~~~~i~~ti:r :I~o::~:~~t::s~s not
TEXAS -I!} 2-149
INSTRUMENTS
WITH, SERIAL CONTROL AND 11 INPUTS

REF+ REF-
III SAMPLE
a-BIT
ANALOG-TO-DIGITAL
CONVERTER
AND
(SWITCHED-CAPACITORS)
HOLD
12-CHANNEL
ANALOG ANALOG
INPUTS MULTIPLEXER
DATA
OUTPUT
CONTROL LOGIC
L...._ _+-___-I AND I/O
r---~~--~ COUNTERS
ADDRESS
INPUT - - - - -.....- - - - i
I/O
CLOCK
cs-----.....------------------~
S;c~~~ -----.. . -------------------------------.--~----------------~
operating sequence
I/O
CLOCK---{
cs..., ,
~J~--~~~~--------------~ ~---------------------------~r--
LSB MSB LSB
DON'T CARE ~ DON'T CARE
>----------~-----~(J{'-----~----~-------
HI-ZSTATE
A7 B7
4--PREVIOUSCONVERSION DATA A---. ~CONVERSION DATA B - - - - +
MSB LSB MSB MSB LSB MSB
(See Note B)
NOTES: A. The conversion cycle, which requires 36 System Clock periods, is initiated on the 8th falling edge of the 110 Clock after CS
goes low for the channel whose address exists in memory at that time. If CS is kept low during conversion, the 110 Clock
must remain low for at least 36 System Clock cycles to allow conversion to be completed.
B. The most significant bit (MSB) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining
seven bits (A6-AO) will be clocked out on the first seven 110 Clock falling edges.
C. To minimize errors caused by noise at the CS input. the internal circuitry waits for three System Clock cycles (or less) after
a chip select falling edge is detected before responding to control input signals. Therefore. no attempt should be made to
clock-in address data until the minimum chip-select setup time has elapsed.
2-150 TEXAS ~
INSTRUMENTS
LinCMOSTM 8BIT ANALOGTODlGITAL PERIPHERALS
Supply voltage, VCC (see Note 1) .......................................... . .. 6.5 V
Input voltage range (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to Vce + 0.3 V
Output voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. -0.3 V to Vce + 0.3 V
Peak input current range (any input) .. . . . ... . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. 10 mA
Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30 mA
II
S
....
t/)
Operating free-air temperature range: TLC540l, TLC5411 . . . . . . . . . . . . . . . . . . .. - 40 e to 85C

TLC540M, TLC541 M . . . . . . . . . . . . . . . .. - 55C to 125C ...CJ
Storage temperature range ......................................... - 65C to 150C C3
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package .. . . . . . . . . .. 260C c
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. 260C o
'';:;
NOTE 1: All voltage values are with respect to digital ground with REF - and GND wired together (unless otherwise noted). 'W
recommended operating conditions 'S
C'
CJ
MIN
TLC540
NOM MAX MIN
TLC541
NOM MAX
UNIT

Supply voltage. VCC 4.75 5 5.5 4.75 5 5.5 V ....CUCU
Positive reference voltage. VREF + (see Note 2) 2.5 VCC VCC+O.l 2.5 VCC VCC+O.l V
Negative reference voltage. VREF _ (see Note 2) -0.1 0 2.5 0.1 0 2.5 V
C
Differential reference voltage.
1 VCC VCC+O.2 1 VCC VCC+0.2 V
VREF + - VREF _ (see Note 2)
Analog input voltage (see Note 2) 0 VCC 0 VCC V
High-level control input voltage, VIH 2 2 V
Low-level control input voltage, VIL 0.8 0.8 V
Setup time, address bits at data input
200 400 ns
before I/O CLKi, tsu(A)
Hold time, address bits after I/O CLKi, th(A) 0 0 ns
System
Setup time, CS low before clocking in first
3 3 clock
address bit, tsu(CS) (see Note 3)
cycles
System
CS high during conversion, twH(CS) 36 36 clock
cycles
Input/Output clock frequency, fCLK(I/O) 0 2.048 0 1.1 MHz
System clock frequency, fCLK(SYS) fCLK(I/O) 4 fCLK(I/O) 2.1 MHz
System clock high, twH(SYS) 110 210 ns
System clock low, twL(SYS) 100 190 ns
Input/Output clock high, twH(I/O) 200 404 ns
Input/Output clock low, twL(l/O) 200 404 ns
fCLK(SYS) s 1048 kHz 30 30
System ns
Clock transition time fCLK(SYS) > 1048 kHz 20 20
(see Note 4) fCLK(I/O) s 525 kHz 100 100
I/O ns
fCLK(lfO) > 525 kHz 40 40
Operating free-air TLC540M, TLC541M -55 125 -55 125
c
temperature, T A TLC5401, TLC5411 -40 85 -40 85
NOTES: 2. Analog input voltages greater than that applied to REF + convert as all "1 "s (11111111), while input voltages less than that applied to REF-
convert as all "O"s (00000000). For proper operation, REF + voltage must be at least 1 volt higher than REF - voltage. Also, the total unadjusted
error may increase as this differential reference voltage falls below 4.75 volts.
3. To minimize errors caused by noise at the chip select input, the internal circuitry waits for three System Clock cycles (or less) after a chip select
falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock-in an address until the minimum
chip select setup time has elapsed.
4. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity of normal
room temperature, the devices function with input clock transition time as slow as 2 microseconds for remote data acquisition applications where
the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
TEXAS . . 2-151
INSTRUMENTS
LinCMOSTM BBIT ANALOGTODlGITAL PERIPHERALS
electrical characteristics over recommended operating temperature range,

VCC - VREF + ... 4.75 V to 5.5 V (unless otherwise noted), fCLKU/O) 2.048 MHz for
11
TLC540 or fCLKU/O) = 1.1 MHz for TLC541
VOH High-level output voltage (pin 16) Vee = 4.75 V, 10H = 360 p.A 2.4 V
cD) VOL Low-level output voltage Vee = 4.75 V, 10L = 1.6 mA 0.4 V
r+ Off-state (high-impedance state) Vo = Vee, es at Vee 10
D) 10Z p.A
output current Vo = 0, es at Vee -10
l>
(")
IIH High-level input current VI = Vee 0.005 2.5 p.A
.c IlL Low-level input current VI = 0 -0.005 -2.5 p.A
c ICC Operating supply current es at 0 V 1.2 2.5 mA
en
;:::;'" Selected channel at Vee,
0.4 1
o
:l
Selected channel leakage current
Unselected channel at 0 V
Selected channel at 0 V,
p.A
-0.4 -1
(") Unselected channel at Vee
::;. ICC + IREF Supply and reference current VREF+ = Vee, es at 0 V 1.3 3 mA
(")
C Input capacitance
I Analog inputs 7 55
pF
ei
;:::;'. I Control inputs 5 15
en
t All typical values are at T A = 25 ae.
2-152 TEXAS ~
INSTRUMENTS
operating characteristics over recommended operating freeair temperature range,

VCC = VREF+ = 4.75 V to 5.5 V, fCLK(l/O) = 2.048 MHz for TLC540 or 1.1 MHz forTLC541,
fI
fCLK(SYS) = 4 MHz for TLC540 or 2.1 MHz for TLC541.
TLC540 TLC541
MIN TYP, MAX MIN TYP MAX
Linearity error See Note.5 0.5 0.5 LSB ....
CI)
Zero error
Full-scale error
Total unadjusted error
See Notes 2 and 6
See Notes 2 and 6
See Note 7
0.5
0.5
0.5
0.5
0.5
0.5
LSB
LSB
LSB
.
"5
U
U
Input All address = 1011 01111101 10000011 01111101 10000011 I:

Self-test output code
(See Note 8) (125) (131) (125) (131) o
"';;
Conversion time See Operating Sequence 9 17 p's
tconv
Total access and
"en
See Operating Sequence 13.3 25 p's "5
conversion time a-
I/O U
tacq
Channel acquisition time
See Operating Sequence 4 4 clock
<t
(sample cycle)
cycles ....COCO
Time output data
remains valid after 10 10 ns
C
tv
I/O c10ckl
Delay time, I/O clockl
td 300 400 ns
to data output valid
See Parameter
ten Output enable time 150 150 ns
Measurement
tdis Output disable time 150 150 ns
Information
tr(busl Data bus rise time 300 300 ns
tf(bus) Data bus fall time 300 300 ns
NOTES: 2. Analog input voltages greater than that applied to REF + convert to all "1 "s (11111111), while input voltages less than that
applied to REF - convert to all"O"s (00000000). For proper operation, REF + voltage must be at least 1 volt higher than
REF - voltage. Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 volts.
5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
between 11111111 and the converted for full-scale input voltage.
8. Both the input address and the output codes are expressed in positive logic. The All analog input signal is internally generated
and is used for test purposes.
TEXAS -II} 2-153

INSTRUMENTS
IJ '4: kO
vI:
c
....
OJ
OJ

OUTPUT
UNDER TEST
-1= TEST
POINT
OUTPUT
UNDER TEST I I 3kn
TEST POINT
OUTPUT
UNDER T E S T - +
CL
k:
EST
POINT
l'
CL CL
(') (SEE NOTE A I ; r
(SEE NOTE AI (SEE NOTE AI ; r
.c
c (SEE NOTE BI (SEE NOTE BI
iii'
;:;:
0'
::::I LOAD CIRCUIT FOR LOAD CIRCUIT FOR LOAD CIRCUIT FOR
(") td, t r , AND tf tpZH AND tpHZ tpZL AND tpLZ,
::;'
(')
c VCC
;:;:
en
[50% _ ~ _ _ _ ov
I
I
SYSTEM I
CLOCK 1
I I
--+I tpZL 14- ~ tPLZ !4-
OUTPUT
I
- - - - - - - - - - - - ; - 1~\J
I
. I
I 1/ VCC
~~~~~~:~11 (SEE NOTE BI I \,-5_0"1c_o__-+:__110":" ____ ov

--+I tpZH \4- ~ tPHZ l+-
I I
H
W~~::~~M V50% t'oi" - - -- VoOv
(SEE NOTECI
2 ______________
r' ~
VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES
I/O
CLOCK
\ - - - - -0.8V
OUTPUT
I
~td~
DATA
OUTPUT _ _ _ _ _ _J
X I
. - - - - - - - - - - 2 4V
- - - - - - - - -. 0.8 V
VOLTAGE WAVEFORM FOR DELAY TIME VOLTAGE WAVEFORM FOR

RISE AND FALL TIMES
NOTES: A. CL = 50 pF for TLC540 and 100 pF for TLC541.

B. ten = tpZH or tpZL. tdis = tpHZ or tPLZ
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
2154 TEXAS
INSTRUMENlS
"11
TLC540M, TLC54D1, TLC541 M, TLC5411
The TLC540 and TLC541 are each complete data acquisition systems on a single chip. They include such
functions as analog multiplexer, sample-and-hold, 8-bit A/D converter, data and control registers, and control
logic. For flexibility and access speed, there are four control inputs [two clocks, chip select (CS), and
addressJ. These control inputs and a TTL-compatible 3-state output are intended for serial communications
with a microprocessor or microcomputer. With judicious interface timing, with TLC540 a conversion can
II ....tn
be completed in 9 microseconds, while complete input-conversion-output cycles can be repeated every
13 microseconds. With TLC541 a conversion can be completed in 17 microseconds, while complete input-
conversion-output cycles are repeated every 25 microseconds. Furthermore, this fast conversion can be
..
'5
C3
(,)
executed on any of 11 inputs or its built-in "self-test," and in any order desired by the controlling processor.
c
The System and I/O Clocks are normally used independently and do not require any special speed or phase o
'.;:i
relationships between them. This independence simplifies the hardware and software control tasks for '(ij
the device. Once a clock signal within the specification range is applied to the System Clock input, the '5
control hardware and software need only be concerned with addressing the desired analog channel, reading C'
(,)
the previous conversion result, and starting the conversion by using the I/O Clock. The System Clock will
drive the "conversion crunching" circuitry so that the control hardware and software need not be concerned

with this task. ....COCO
When CS is high, the Data Output pin is in a three-state condition and the Address Input and I/O Clock C
pins are disabled. This feature allows each of these pins, with the exception of the CS pin, to share a
control logic point with their counterpart pins on additional A/D devices when additional TLC540/541 devices
are used. In this way, the above feature serves to minimize the required control logic pins when using
multiple A/D devices.
The control sequence has been designed to minimize the time and effort required to initiate conversion
and obtain the conversion result. A normal control sequence is:
1. CS is brought low. To minimize errors caused by noise at the CS input, the internal circuitry waits
for two rising edges and then a falling edge of the System Clock after a low CS transition, before
the low transition is recognized. This technique is used to protect the device against noise when
the device is used in a noisy environment. The MSB of the previous conversion result will
automatically appear on the Data Out pin.
2. A new positive-logic multiplexer address is shifted in on the first four rising edges of the I/O Clock.
The MSB of the address is shifted in first. The negative edges of these four I/O clock pulses shift
out the second, third, fourth, and fifth most significant bits of the previous conversion result. The
on-chip sample-and-hold begins sampling the newly addressed analog input after the fourth falling
edge. The sampling operation basically involves the charging of internal capacitors to the level
of the analog input voltage.
3. Three clock cycles are then applied to the I/O pin and the sixth, seventh, and eighth conversion
bits are shifted out on the negative edges of these clock cycles. .
4. The final eighth clock cycle is applied to the I/O Clock pin. The falling edge of this clock cycle
completes the analog sampling process and initiates the hold function. Conversion is then performed
during the next 36 System Clock cycles. After this final I/O Clock cycle, CS must go high or the
I/O Clock must remain low for at least 36 System Clock cycles to allow for the conversion function.
CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple
conversion, special care must be exercised to prevent noise glitches on the I/O Clock line. If glitches occur
on the I/O Clock line, the I/O sequence between the microprocessor/controller and the device will lose
synchronization. Also, if CS is taken high, it must remain high until the end of the conversion. Otherwise,
a valid falling edge of CS will cause a reset condition, which will abort the conversion in progress.
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps
1 through 4 before the 36 System Clock cycles occur. Such action will yield the conversion result of the
previous conversion and not the ongoing conversion.
TEXAS 2-155
INSTRUMENTS
principles of operation (continued)

It is possible to connect the System and I/O Clock pins together in special situations in which controlling
circuitry points must be minimized. In this case, the following special points must be considered in addition
to the requirements of the normal control sequence previously described.
1. When CS is recognized by the device to be at a low level, the common clock signal is used as
C an I/O Clock. When CS is recognized by the device to be at a high level, the common clock signal
E
r+
E is used to drive the "conversion crunching" circuitry.
(")
2. The device will recognize a CS low transition only when the CS input changes and subsequently the
System Clock pin receives two positive edges and then a negative edge. For this reason, after
.c a CS negative edge, the first two clock cycles will not shift in the address because a low CS must
c be recognized before the I/O Clock can shift in an analog channel address. Also, upon shifting in
C;;"
::." the address, CS must be raised after the sixth I/O Clock pulse that has been recognized by the
0" device, so that a CS low level will be recognized upon the lowering of the eighth I/O Clock signal
:::J that is recognized by the device. Otherwise, additional common clock cycles will be recognized
o::::;" as I/O Clock pulses and will shift in an erroneous address.
(")
c For certain applications, such as strobing applications, it is necessary to start conversion at a specific point
::."
C/I
in time. This device will accommodate these applications. Although the on-chip sample-and-hold begins
sampling upon the negative edge of the fourth I/O Clock cycle, the hold function is not initiated until the
negative edge of the eighth I/O Clock cycle. Thus, the control circuitry can leave the I/O Clock signal in
its high state during the eighth I/O Clock cycle until the moment at which the analog signal must be
converted. The TLC540/TLC541 will continue sampling the analog input until the eighth falling edge of
the I/O Clock. The control circuitry or software will then immediately lower the I/O Clock signal and hold
the analog signal at the desired point in time and start conversion.
2-156 TEXAS . .
INSTRUMENTS
PRODUCT TLC543M, TLC5431, TLC544M, TLC5441
PREVIEW 8BIT ANALOGTODlGlTAL PERIPHERALS
02799, SEPTEMBER 1986
LinCMOST. Technology D. J. OR N PACKAGE

(TOP VIEWI
o aBit Resolution AID Converter

On-Chip 6-Channel Analog Multiplexer
Built-In Self-Test Mode
Software-Controllable Sample and Hold
AO
A1
A2
A3
VDD
REF+
EOC
ADDRESS IN
II
....en
A4 I/O CLOCK S
Total Unadjusted Error ... 0.5 LSB Max REF- DATA OUT ...
(.)
o Endof-Conversion Output
GND CS U
c
Conversion Time ... 17 p's Max 0
'';::;
Internal System Clock ... 4 MHz Typ 'm
'S
Low Power Consumption ... 6 mW Typ C"
(.)
Total Access and Conversion Cycles:
TLC543 ... 45,500 cIs Min

TLC544 ... 40,000 cIs Min ....COCO
C
description
The TLC543 and TLC544 are LinCMOS'" A/D peripherals built around an a-bit switched-capacitor
successive-approximation A/D converter. They are designed for serial interface to a microprocessor or
peripheral via a three-state output with up to four control lines that include I/O Clock, Chip Select (CS),
Address Input, and End-of-Conversion Output (EOC). A 4-megahertz on-chip system clock and simultaneous
read/write operations permit high-speed data transfer and minimum sample rates of 45,500 cycles per
second for TLC543 and 40,000 cycles for the TLC544. In addition to the high-speed converter and versatile
control logic, there is an on-chip 6-channel analog multiplexer that can be used to sample anyone of five
inputs or an internal "self-test" voltage and a sample-and-hold that can operate automatically or under
processor control.
The converters incorporated in the TLC543 and TLC544 feature differential high-impedance reference inputs
that permit ratiometric conversion, scaling, and analog circuitry isolation from logic and supply noise.
A totally switched-capacitor design allows guaranteed low-error ( O. 5 LSB) conversion in 17 microseconds
maximum for the TLC543 and the TLC544 over the full operating temperature range. The TLC543M and
TLC544M are characterized for operation over the full military temperature range of - 55C to 125C.
The TLC5431 and TLC5441 are characterized for operation from - 40C to 85 C.
~
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a:
c..
I-
o
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o
a:
LinCMOS is a trademark of Texas Instruments Incorporated c..
PRODUCT PREVIEW documents contain information Copyright 1986. Texas Instruments Incorporated
specifications are design goals. Texas Instruments TEXAS . . 2-157
INSTRUMENlS
TLC543M, TLC5431, TLC544M, TLC5441 PRODUCT
BBIT ANALOGTODlGlTAL PERIPHERALS PREVIEW

REF+ REF-
c
...
D)
D)
ANALOG {
INPUTS 6-CHANNEL
ANALOG
(")
MULTIPLEXER
.c
t: DATA
u;. OUTPUT
;:;."
0"
:::l
(")
:::;"
(") END-OF-
t: ADDRESS
INPUT ------i~--__t t-----t---+---t-- CONVERSION
;:;." OUTPUT
en
I/O
CLOCK----------~--------~~------~----~--1l------;:~~
CS-------i~--------------------~
operating sequence
~~-------------------ta+c---------------------H.I
I/O: 12131415161718 ~:
CLOCK ....J.......J DON'T ~,
---,--. I I I I' I I
: I+- ACCESS -.t I+-- SAMPLE ---+Iot------tconv~ If- ACCESS --.j 14-- SAMPLE. ~
CYCLE B CYCLE B (See N~te A) ! CYCLE C CYCLE C
I
-CS -,~,~r__________________________~1 F----i~,r'------------------------~ r-
MSB LSB If--twH(CS)-----+t MSB LSB
ADDRESS ~ DON'T CARE ~ DON'T CARE
INPUT - - { ~-------------------------~ff ~~----------...;..---------
HI-Z STATE
DATA ---1
OUT
B7
"'a ~CONVERSION DATA B-----+
::a END OF MSB . LSB MSB
o CONVERSION -------------..;;;.;;.,;;.-......;.;,
c
c: NOTES: A. The conversion cycle, which requires 36 internal system clock periods, is initiated on the 8th falling edge of the I/O Clock
n after CS goes low for the channel whose address exists in memory at that time. If CS is kept low during conversion, the 1/0
clock must remain low for at least 36 system clock cycles to allow conversion to be completed.
-I B. The most significant bit (MSB) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining
"'a' seven bits (A6-AO) will be clocked out on the'first seven I/O Clock falling edges.
::a C. To minimize errors caused by noise at the CS input, the internal circuitry waits for three internal system clock cycles (1.4 p's
at 2 MHz) after a chip select transition before responding to control input signals. Therefore. no attempt should be made to
m clock-in address data until the minimum chip-select setup time has elapsed.
<
m
:e
2-158 TEXAS
INSTRUMENTS
POS" OFFICE BOX 6~5012 DALLAS. TEXAS 75265
PREVIEW 8-BIT ANALOGTODlGITAL PERIPHERALS
Supply voltage, VCC (see Note 1) ............................................. 6.5 V
Input voltage range (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to VCC + 0.3 V
Output voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to VCC + 0.3 V
Peak input current range (any input) ......................................... 10 rnA
Peak total input current (all inputs) .......................................... 30 rnA
Ell
....
tJ)
Operating freeair temperature range: TLC5431, TLC5441 . . . . . . . . . . . . . . . . . . .. - 40C to 85 C 'S

TLC543M, TLC544M . . . . . . . . . . . . . . . .. - 55C to 125C ...CJ
Storage temperature range ......................................... - 65C to 150C i:J
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ........ 260C t:
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300C o
'';::;
NOTE 1: All voltages are with respect to ground (GND pin) with REF - and GND wired together (unless otherwise noted).
'Ci)
'S
C"
recommended operating conditions CJ
TLC543 TLC544
<2:
MIN NOM MAX MIN NOM MAX
UNIT
....ctIctI
Supply voltage. VCC 3 5 6 3 5 6 V C
Positive reference voltage. VREF + (see Note 2) 2.5 VCC Vee+O. 1 2.5 VCC Vee+O. 1 V
Negative reference voltage. VREF _ (see Note 2) -0.1 2.5 0.1 0 2.5 V
Differential reference voltage. VREF + - VREF _ (see Note 2) 1 VCC Vee+0. 2 1 Vce Vee+0. 2 V
Analog input voltage (see Note 2) 0 VCC 0 VCC V
High-level control input voltage. VIH (for VCC = 4.75 to 5.5 V) 2 2 V
LOW-level control input voltage. VIL (for VCC = 4.75 to 5.5 V) 0.8 0.8 V
Input/Output clock frequency. fCLK(l/O)
0 2.048 0 1.1 MHz
(for VCC = 4.75 to 5.5 V)
System clock frequency. feLKlI/O) (for VCC = 4.75 to 5.5 V) 4 2.1 MHz
Input/Output clock high. twH(I/O) 200 404 ns
Input/Output clock low. twL(I/O} 200 404 ns
I/O clock transition time (see Note 3)

I fCLK(I/O) < 1.1 MHz 100 100
ns
I fCLKfI/O) > 1.1 MHz 40
Duration of CS input high state during conversion. twH(CS) 17 17 p's
Setup time. address bits at data input
200 400 ns
before I/O CLOCKi. tsu(A)
Hold time. address bits after I/O CLOCKt. th(Al 0 0 ns
Setup time. CS low before clocking in first address bits.
1.4 1.4 p's
tsu(CS) (see Note 4)
Operating free-air temperature. TA

I TLC543M. TLC544M -55 125 -55 125
~
c
I TLC5431. TLC5441 -40 85 -40 85
NOTES: 2. Analog input voltages greater than that applied to REF + convert as all "l"s (11111111) and input voltages less than that
w
applied to REF - convert as all "O"s (00000000). For proper operation. REF + voltage must be at least 1 volt higher than
REF - voltage. Also. adjusted errors may increase as this differential reference voltage falls below 4.75 volts.
:>w
3. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In
a:
the vicinity of normal room temperature. the devices function with input clock transitions as slow as 2 microseconds for remote
data acquisition applications where the sensor and the A/D converter are placed several feet away from the controlling
c..
microprocessor.
I-
4. To minimize errors caused by noise at the Chip Select input. the internal circuitry waits for three system clock cycles (1.4 p's
at 2 MHz) after a chip select falling edge is detected before responding to control input signals. Therefore. no attempt should o
be made to clock-in address data until the minimum chip select setup time has elapsed. ::J
C
oa:
c..
TEXAS ~ 2-159
INSTRUMENTS
8BIT ANALOGTODlGlTAL PERIPHERALS PREVIEW

VCC = VREF + = 4.75 V to 5.5 V (unless otherwise noted), fCLK(IIO) = 2.048 MHz for TLC543
II
c
Q)
or fCLKU/O) = 1.1 MHz for TLC544
VOH
PARAMETER
High-level output voltage,
Data out, Eoe
Vee = 4.75 V,
TEST CONDITIONS
IOH = -360 p.A

MIN
2.4
Typt MAX UNIT
....
Q) VOL Low-level output voltage
LData
I EOe out Vee = 4.75 V, IOL = 3.2 mA 0.4
V
Vee = 4.75 V, IOL = 1.6 mA 0.4
>
(')
IOZ
Off-state (high-impedance state) Va = Vee, es at Vee 10
p.A
.c output current Va = 0, es at Vee -10
E:
IIH High-level input current VI = Vee + 0.3 V 0.005 2.5 p.A
Cii"
;::;." IlL Low-level input current VI = 0 -0.005 -2.5 p.A
c)" ICC Operating supply current es at 0 V 1.2 2 rnA
:s Selected channel at Vee,
C') 0.4 1
~" Ilkg Selected channel leakage current See Figure 1 p.A
(') Selected channel at 0 V,
-0.4 -1
E: Unselected channel at Vee
;::;."
en IREF Reference current VREF+ = Vee, es at 0 V 0.1 1 rnA
Input capacitance
II Analog inputs
. 7 55
pF
ei
Control Inputs 5 15
t All typical values are at Vee = 5 V, T A = 25 DC.
VCC
SELECTED
ANALOG
INPUT
OTHER
ANALOG
INPUTS
"'C FIGURE 1. SELECTED CHANNEL LEAKAGE CURRENT

:::D
o
C
c::
("')
'"'"'"
"'C
:::D
m
-<
2-160 TEXAS . .
INSTRUMENTS
""tJ ""tJ
==
mc
operating characteristics over recommended operating free-air temperature range, VCC VREF+ 4.75 to 5.5 V, C::o
fCLK(l/O) = 2.048 MHz for TLC543 or 1.1 MHz for TLC544 me::
:E~
TLC543 TLC544
Linearity error See Note 5 0.5 0.5 LSB
Zero error See Note 6 0.5 0.5 LSB
Full-scale error See Note 6 0.5 0.5 LSB
Total unadjusted error See Note 7 0.5 0.5 LSB
Input A5 address = 10110, 01111101 10000011 01111101 10000011
See Note 8 (125) (131) (125) (131)
tconv Conversion time See Operating Sequence 8 17 12 17 p's
ta+c Total access and conversion time See Operating Sequence 12 22 19 25 p's
I/O
."
Channel acquisition time (sample cycle) See Operating Sequence 4 4 clock
~ tacq
,,-
0
~z tv
Time output data remains valid
after I/O clock!
10 10
cycles
ns
!~ td Delay time, I/O clock! to data output valid 300 400 ns

~;tlr;;i ten Output enable time 1.4 1.4 ns
;;C~
~~
tdis Output disable time 150 150 ns
tr(bus) Data bus and EOC rise time 300 300 ns
~1T1 Data bus and EOC fall time See Figure 2 300 300 ns
tf(bus).
~z :EC:O .....
~~~
tpHL(EOC) Propagation delay, 8th I/O clock! to EOC 400 400 ns _CI:Ir-
Delay time, EOC to DATA OUT (MSB) .....::jC"')
td(EOC) -1 -1 p's ::c U'1
cn~f;
..... (see Note 9)
- - -- -- - '-----_.- - - - -
'"
Ol
m;t:a3:
NOTES: 5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics. ::! r- ~
6. Zero error is the difference between the output of an ideal and an actual AID converter for zero input voltage; full-scale error is that same difference for full- ;t:ac .....
scale input voltage. r-Clr-
7. Total unadjusted error comprises linearity, zero, and full-scale errors. C"')~~
8. Both the input address and the output codes are expressed in positive logic. The A5 analog input signal is internally generated and is used for test purposes. cC?+==-
9. The EOC signal is output after 40 internal clock cycles, while the data is available after 36 internal clock cycles. Thus, the delay time, EOC to DATA OUT,
is a negative value equal to four internal system clock cycles less internal propagation delays.
20W
.....
=Cl~ --
c - .....
r-~r-
;t:ar-~
2""tJ+==-
om+==-
.... 2!:!
_. ""tJ- s:
-::c .....
2mr-
""tJ=C"')
e:::z:aU"l
..... r-+==-
cncn~
~
en
PRODUCT PREVIEW Data Acquisition Circuits II
8BIT ANALOGTODlGlTAL PERIPHERALS PREVIEW
IFJ
c
...
Q)
Q)
OUTPUT
UNDER TEST )
J
1.4:kfl
TEST POINT
CL
(SEE NOTE AI
OUTPUT
UNDER TEST
CL
nl'
(See Note A) -=
TEST POINT
3 kfl
'
OUTPUT
UNDER TEST
V!:
T-
l'
':EST POINT
CL
(See Note A)

C')
(See .Note B) (See Note B)
.c LOAD CIRCUIT FOR LOAD CIRCUIT FOR LOAD CIRCUIT FOR

c td. t r and tf tpZH AND tpHZ tpZL AND tpLZ
(ii'
;:::;.'
c'
:::::I
(')
CS
~
~"'_ _ _ _ _ _ _ _ _-Jt~o/:... ____ Vce
0 V
:::;' I 1
C') INTERNAL
c SYSTEM
;:::;.' CLOCK
til
I f - - tpZL-------.! k-*- tpLZ
OUTPUT I I 1 y,:-I Vce
WAVEFORM 1 I (See Note B) \:... 50% I 1
(See Note C) I '\". --..,If--I 10% - -- 0 V
I4---tPZH---+i I4--*-tPHZ
--11
I
WA~~;~~~ 2 _ _ _ _ _ _ _ _ _
H
50 % "\"90% - - - VoOv
(See Note C) . '----
e~~OCK ~0.8V
I
I4-td~
--------
1,--_ _ _ _ _-
X
DATA 2.4 V
OUTPUT _ _ _ _ _- J
- - - - - - - -O.8V

RISE AND FALL TIMES
"::JJ0 EOC 7'2.4 V
-.I :'---td(EOC)~ I
C
C DATA OUT -------C. 2.4V
0 \ 0.4 V I
-I I4--VALID MSB----+j
""'CJ VOLTAGE WAVEFORMS FOR EOC TIMING

::JJ
m NOTES: A. CL = 50 pF for TLC543 and 100 pF for TLC544.
S
m
B. ten = tpZH or tpZL. tdis = tpHZ or tpLZ
:E FIGURE 2. OPERATING CHARACTERISTICS
2-162 TEXAS ~
INSTRUMENTS
PREVIEW 8BIT ANALOGTODlGITAL PERIPHERALS
introduction
TLC543 and TLC544 are each complete data acquisition systems on a single chip. They include the functions
of analog mUltiplexer, sample and hold, 8-bit A/D converter, data and control registers, and control logic.
Flexible serial communication is achieved with a microprocessor or microcomputer using a TTL-compatible
II
tn
.....
':;
three-state Data Out and four control lines: Chip Select (CS), I/O Clock, Address Input, and End of
Conversion (EOC) output. ...
CJ
To maximize access speed, the device simultaneously writes the previous conversion result, reads a new
c:;
multiplexer address, and acquires the analog signal. This is followed by the A/D conversion, whose end C
is signalled by EOC output going high. These Total Access and Conversion Cycles are completed in a
o
'';::'
minimum of 22 J-LS for the TLC543 and 25 p,S for the TLC544. Conversion can take place, in any order, '(j)
on the five analog inputs or the built-in self-test system. ':;
C-
The system clock, which drives the control logic and the switched-capacitor successive approximation CJ
A/D converter, is internal to the device and typically runs at a frequency of 4 MHz. This internal system
CO
clock runs independently and there are no required phase or frequency relationships with other signals. .....
CO
digital interface C
The I/O clock controls the acquisition of the analog signal as well as all serial data communications between
the TLC543 or TLC544 and the host processor. This I/O clock from the host consists of a burst of eight
pulses separated by the conversion time. Timing may be achieved by chip select (CS) synchronously gating
a continuous I/O clock or directly from the host with CS held low continuously.
With CS high, Data Out is in a high-impedance condition with the Address Input and 110 clock input disabled.
This feature allows the interface pins, with the exception of CS and EOC, to share a common bus with
additional TLC543 or TLC544 devices or other members of the TLC543/544 family of devices.
typical operating sequence

Consider an access and conversion sequence where CS is being used: CS is brought low and recognized
after the time out of the noise-rejection circuitry. The MSB of the previous conversion result appears at
Data Out, whose three-state output is enabled. The MSB of the new multiplexer address should be present
at the Address Input to conform with the setup time, tsu(A), requirements before the first rising edge of
the I/O clock. The multiplexer address is shifted in on the first three rising edges of the I/O clock.
The first seven falling edges of I/O CLOCK shift out the remaining seven bits of the previous conversion
on DATA OUT. The eighth I/O clock falling edge returns the MSB to the Data Out. Optimum serial transfer
takes place with the bit streams being read on the rising edges of the I/O clock for the respective devices
and Data Out and Address In lines.
At the fourth falling edge of the I/O clock, the on-chip sample and hold begins to acquire the newly addressed
3:
w
analog input and continues until the eighth (and final) falling edge. A hold function is initiated by the eighth
I/O clock pulse falling edge. If it is desired to start the conversion at a specific point in time (or lengthen
the acquisition time), the host processor may leave the eighth I/O clock pulse in the high state until the
:>w
moment at which the analog signal must be sampled. After bringing the eighth I/O pulse low, the A/D a::
function is performed in the next 36 internal system clock cycles.
c..
In applications where CS is held low continuously, the bursts of eight I/O clock pulses should be timed t-
to be at least tconv apart. O
::J
C
oa::
c..
TEXAS ~ 2-163
INSTRUMENTS
8BIT ANALOGTODIGITAL PERIPHERALS PREVIEW
CS input
II
To minimize bus contention caused by noise enabling the three-state Data Out, when the CS input is brought
low the device waits for two rising edges and a falling edge of the internal system clock before recognizing
the CS transition. Hence, the setup time tsu(CS) should be observed when using the CS input. This applies
also to a CS high-to-Iow transition, except for disabling of DATA OUT, which goes into a high-impedance
C state immediately within the tdis specification (see Figure 3). If this interruption of CS in the low state
...EDED is less than 1.5 internal system clock cycles, and hence not recognized, DATA OUT will be immediately
enabled with the return of CS to the low state. DATA OUT becomes enabled after a CS high-to-Iow transition

(") in time ten (equivalent to tsu(CS) for this device, see Figure 3).
..Q
C CS can be brought high during a conversion without affecting the ongoing conversion but must remain
(ii' high until the end of conversion. Otherwise, a CS falling edge will cause a reset condition that will abort
~' the conversion in progress. When a new access cycle is started, the previous conversion result will be output.
0'
j A new conversion may be restarted by toggling CS high-to-Iow at least tsu(CS) before the eighth falling
(") edge of the I/O clock. The ongoing access cycle will be aborted. Again, when a new access cycle is started,
::;' the previous conversion result will be output.
(")
c
~' end of conversion output (EOC)
en
EOC goes Iowa propagation delay time tPHL(EOC) after the 8th falling edge of the I/O clock, and goes
high when conversion is complete. At this time the MSB is available at Data Out; however, if CS is high
it will be necessary to bring CS low and wait for the CS recognition time before Data Out is available,
since Data Out is in a high-impedance state when CS is high. Delay time td(EOC) of EOC to Data Out
is a negative value of 4 internal system clock cyCles less internal propagation delay, because the EOC
signal is output after 40 internal system clock cycles whereas conversion is complete with data available
after 36 cycles.
"'C
:l:J
o
C
c:
('")
-I
"'C
:l:J
m
<
m
~
2-164 TEXAS ~
. INSTRUMENTS
ADVANCE TLC545M, TtC5451, TLC546M, TLC5461
INFORMATION LinCMOSTM 8BIT ANALOGTODIGITAL PERIPHERALS
02850. DECEMBER 1985
LinCMOS'M Technology N DUAL-IN-LiNE PACKAGE

(TOP VIEW)
8Bit Resolution AID Converter
INPUT AO VCC
Microprocessor Peripheral or StandAlone
INPUT A1 SYSTEM CLOCK
Operation
INPUT A2 I/O CLOCK
On-Chip 20-Channel Analog Multiplexer INPUT
INPUT
A3
A4
ADDRESS INPUT
DATA OUT
...
S
(I)
Built-In Self-Test Mode INPUT A5 CS ...

CJ
Software-Controllable Sample and Hold INPUT A6 REF+ C3
INPUT A7 REF-
Total Unadjusted Error ... 0.5 LSB Max c
INPUT A8 INPUT A18 o
.,t::
Timing and Control Signals Compatible with
8-Bit TLC540 and 10-Bit TLC 1540 AID
INPUT A9 INPUT A17
INPUT A16
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Converter Families
INPUT A10
INPUT A11 INPUT A15
S
C"
INPUT A12 INPUTA14 CJ
TYPICAL PERFORMANCE TL545 TL546 GND INPUT A13 <C
Channel Acquisition Time
Conversion Time
1.5 IlS
9 IlS
2.7 IlS
17 IlS
...caca
Sampling Rate 76 x 10 3 40 x 10 3
FN CHIP CARRIER PACKAGE C
(TOP VIEW)
Power Dissipation 6mW 6mW
description
The TLC545 and TLC546 are LinCMOS' AID
peripherals built around an 8-bit switched-
capacitor successive-approximation A/D
converter. They are designed for serial interface
to a microprocesor or peripheral via a three-state 4 3 2 1 282726
output with up to four control inputs [including INPUT A4 5 25 ADDRESS INPUT
independent System Clock, I/O Clock, Chip INPUT A5 6 24 DATA OUT
Select (CS), and Address Input). A 4-megahertz INPUT A6 7 23 CS
system clock for the TLC545 and a INPUT A7 8 22 REF+
2.1-megahertz system clock for the TLC546 INPUT A8 9 21 REF-
with a design that includes simultaneous INPUT A9 10 20 INPUT A18
read/write operation allow high-speed data INPUT A10 11 19 INPUT A17
transfers and sample rates of up to 76,923 12 1314151617 18 2
samples per second for the TLC545, and 40,000 o
samples per second for the TLC546. In addition i=
to the high-speed converter and versatile control
logic, there is an on-chip 20-channel analog

multiplexer that can-be used to sample anyone ~
of 19 inputs or an internal "self-test" voltage, a:
and a sample-and-hold that can operate ou.
automatically or under microprocessor control.
The converters incorporated in the TLC545 and
TLC546 feature differential high-impedance
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reference inputs that facilitate ratiometric (.)
conversion, scaling, and analog circuitry isolation 2
from logic and supply noises. A totally switched-
capacitor design allows guaranteed low-error

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( 0.5 LSB) conversion in 9 microseconds for
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LinCMOS is a trademark of Texas Instruments Incorporated <t
ADVANCE INFORMATION documents contain Copyright 1985. Texas Instruments Incorporated
information on new products in the samplin9 or
preproduction phase of development. Characteristic
TEXAS -I/} 2-165
POST OFFICE BOX 655012 DALLAS. ~EXAS 75265
TLC545M, TLC5451, TLC546M, TLC5461 ADVANCE
LinCMOSTM 8BIT ANALOGTODlGlTAL PERIPHERALS INFORMATION
the TLC545, and 17 microseconds for the TLC546 over the full operating temperature range. Detailed
information on interfacing to most popular microprocessors is readily available from the factory.
III
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The TLC545M and the TLC546M are characterized for operation from - 55 DC to 125 DC. The TLC5451
and the TLC5461 are characterized for operation from - 40 DC to 85 DC.

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c 8-BIT
iii' SAMPLE
ANALOG-TO-DIGITAL
::+' AND
CONVERTER
0' HOLD
(SWITCHED-CAPACITORS)
:::I
ANALOG 20-CHANNEL
(') INPUTS
:::;' ANALOG
(") MULTIPLEXER
C
::+' DATA
In OUTPUT
CONTROL LOGIC
'-----1-----1 AND I/O
--~-........, COUNTERS
ADDRESS
INPUT ----~--~
110
CLOCK
~-----~----------------------------~
~Yc;~~--------~----------------------------------~----------------~

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2-166 TEXAS ~
INSTRUMENTS
ADVANCE TLC545M, TLC5451, TLC546M, TLC5461
INFORMATION LinCMOSTM 8-BIT ANALOG-TO-DlGlTAL PERIPHERALS
operating sequence
111213141516171s
1/0
CLOCK---{
CS-"
L7~;-(S-e-e-N-ot-e-c-I------------------~ ....en
0:5
MSB LSB
DON'T CARE
MSB LSB DON'T
CARE ...CJ
U
c
HIZ STATE o
0';::;
B7
0C;;
A7
. +--PREVIOUS CONVERSION DATA A - - . ~CONVERSION DATA B - - - + 0:5
MSB LSB MSB MSB LSS MSB
C-
(See Note BI CJ
NOTES: A. The c~nversion cycle, which requires 36 system clock periods, is initiated with the 8th 1/0 clock! after CS! for the channel
<C
whose address exists in memory at that time.
B. The most significant bit (MSBI will automatically be placed on the DATA OUT bus after Cs is brought low. The remaining
....COCO
seven bits (A6-AOI will be clocked out on the first seven 1/0 ciock falling edges. C
C. To minimize errors caused by noise at the CS input, the internal circuitry waits for three system clock cycles (or lessl after
a chip select transition before responding to control input signals. Therefore, no attempt should be made to clock-in address
data until the minimum chip-select setup time has elapsed.
Supply voltage, VCC (see Note 1) ............................................. 6.5 V
Input voltage range (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to Vce + 0.3 V
Output voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to Vce +0.3 V
Peak input current range (any input) ......................................... 10 mA
Peak total input current (all inputs) ............. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30 mA
Operating free-air temperature range: TLC5451, TLC5461 . . . . . . . . . . . . . . . . . . .. - 40 e to 85C
n.C545M, TLC546M . . . . . . . . . . . . . . . .. - 55C to 125C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . .. 260C
Case temperature for 10 seconds: FN package. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260C
NOTE 1: All voltage values are with respect to network ground terminal. 2:
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TEXAS -II} 2-167

INSTRUMENTS
LinCMOS 8BIT ANALOGTODIGITAL PERIPHERALS INFORMATION
TLC545 TLC546
UNIT
Supply voltage, VCC 4.75 5 5.5 4.75 5 5.5 V
Positive reference voltage, VREF + (see Note 2) 2.5 Vee Vee+ O. 1 2.5 Vee Vee+ 0 . 1 V
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Negative reference voltage, Vref _ (see Note 2)
Differential reference voltage, VREF + - VREF- (see Note 2)
Analog input voltage (see Note 2)
-0.1
1
0
0
Vee
Vee- 2. 5
Vee+ 0. 2
-0.1
0
1
0
Vee
Vee- 2. 5
Vee +0.2
V
V
V
VCC VCC
(')
High-level control input voltage, VIH 2 2 V
.c Low-level control input voltage, VIL 0.8 0.8 V
c Setup time, address bits at data input before I/O CLKt, tsu(A) 200 400 ns
(ii'
Address hold time, th 0 0 ns
;::::;.'
0' Setup time, CS low before clocking in first
System
::J 3 3 clock
address bit, tsu(CS) (see Note 3)
n
:::;'
cycles
System
(')
c Chip select high during conversion, twH(CS) 36 36 clock
;::::;.' cycles
en 0 2.048 1.1 MHz
Input/Output clock frequency, fCLK(I/O) 0
System clock frequency, fCLK(SYS) feLK(I!O) 4 feLK(I/O) 2.1 MHz
System clock high, twH(SYS) 110 210 ns
System clock low, twL(SYS) 100 190 ns
Input/Output clock high, twH(I/O) 200 404 ns
Input/Output clock low, twL(I/O) 200 404 ns
fCLK(SYS) :s 1048 kHz 30 30
System ns
Clock transition time fCLK(SYS) > 1048 kHz 20 20
(see Note 4) fCLK(I/O) :s 525 kHz 100 100
I/O ns
fCLK(I/O) > 525 kHz 40 40
TLC545M, TLC546M -55 125 -55 125
TLC5451, TLC5461 -40 85 -40 85
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NOTES: 2. Analog input voltages greater than that applied to REF + convert as all" 1"s (111 1 1111), while input voltages less than that
applied to REF - convert as all "O"s (00000000). For proper operation, REF + voltage must be at least 1 volt higher than
REF - voltage. Also, total unadjusted errors may increase as this differential reference voltage falls below 4.75 volts.
3. To minimize errors caused by noise at the Chip Select input, the internal circuitry waits for three system clock cycles (or less)
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after a chip select falling edge or rising edge is detected before responding to control input signals. Therefore, no attempt
should be made to clock-in address data until the minimum chip select setup time has elapsed.
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the vicinity of normal room temperature, the devices function with input clock transition time as slow as 2 microseconds
for remote data acquisition applications where the sensor and the A/D converter are placed several feet away from the controlling
microprocessor.
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2-168 TEXAS ~
INSTRUMENTS
ADVANCE TLC545M, TLC5451, TLC546M, TLC5461
INFORMATION LinCMOSTM 8BIT ANALOGTODlGlTAL PERIPHERALS

VCC = VREF + = 4.75 V to 5.5 V (unless otherwise noted), fCLK(l/O) = 2.048 MHz for TLC545
or fCLK(l/O) = 1.1 MHz for TLC546
VOH High-level output voltage (pin 24) Vee = 4.75 V, 10H = -360 JtA 2.4 V
VOL Low-level output voltage Vee = 4.75 V, 10L = 3.2 mA 0.4 V
Off-state (high-impedance state) Vo = Vee, es at Vee 10
10Z JtA
output current Vo = 0, es at Vee -10
IIH High-level input current VI = Vee 0.005 2.5 JtA
IlL Low-level input current VI = 0 -0.005 -2.5 JtA
ICC Operating supply current es at 0 V 1.2 2.5 mA
Selected channel at Vee,
0.4 1
Selected channel leakage current JtA
-0.4 -1
Unselected channel at Ve~
ICC + IREF Supply and reference current VREF+ = Vee, es at 0 V 1.3 3 mA
ei Input capacitance I
Analog inputs 7 55
pF
I Control inputs 5 15

VCC = VREF+ = 4.75 V to 5.5 V, fCLK(l/O) = 2.048 MHz for TLC545 or 1.1 MHz for
TLC546, fCLK(SYS) = 4 MHz for TLC545 or 2.1 MHz for TLC546
TLC545 TLC546
Zero error See Note 6 0.5 0.5 LSB
Input A 19 address = 10011 01111101 10000011 01111101 10000011
(See Note 8) (125) (131) (125) (131)
tconv Conversion time See Operating Sequence 9 17 Jts
Total access and
See Operating Sequence 13 25 Jts
conversion time 2
Channel acquisition
1/0 o
tacq
time (sample cycle)
See Operating Sequence 3 3 clock
cycles
i=
Time output data <C
tv remains valid after 10 10 ns ~
1/0 clock! a:
td
Delay time, 1/0 clock!
300 400 ns
ou..
See Parameter
ten
tdis
Output enable time
Output disable time
tr(bus) Data bus rise time
Measurement
Information
150
150
300
150
150
300
ns
ns
ns
-w
2
tf(bus) Data bus fall time 300 300 ns (.)

NOTES: 5. Linearity error is the maximum deviation from the best straight line through the AID transfer characteristics.
2
6. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference <C
between 11111111 and the converted for full-scale input voltage.
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8. Both the input address and the output codes are expressed in positive logic. The A 19 analog input signal is internally generated
and is used for test purposes. <C
TEXAS -I!} 2-169

INSTRUMENTS
LinCMOSTM 8BIT ANALOGTODIGITAL PERIPHERALS INFORMATION
~:'nT'ST I T'STPO'NT
c OUn>UT vI:':'STPO'NT
OUTPUT
I
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r+
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UNDER TEST UNO'RTEST-+
:t> OUTPUT CL
(SEE NOTE AI
3kn CL
(SEE NOTE AI ~
n UNDER TEST POINT
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cc;;.
;:;:
CL
(SEE NOTE AI l'
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LOAD CIRCUIT FOR LOAD CIRCUIT FOR LOAD CIRCUIT FOR
td. t r AND tf . tpZH AND tpHZ tpZL AND tpLZ
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c VCC
;:;:
UI
\\ {50o;. _____ ov
I
I
SYSTEM I
CLOCK I
I I
--+I tpZL \4- ~ tPLZ !4-
l~
OUTPUT
WAVEFORM 1
(SEE NOTE CI
(SEE NOTE BI
--+I
I
II :
',-5_0"1._0_ _ _J.t.10:" ____
tpZH I+-
+-:
~ tpHZ r.-
VCC
0V
I I
OUTPUT
WAVEFORM 2
(SEE NOTE CI
"0% \::" - --- VOH
-------------. " " " - - - - OV
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1/0
CLOCK
:2 \- - - - -O.8V
OUTPUT
("') I
m I+-td~
l ----------2.4V
:2
"T1
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DATA
OUTPUT
--------' X - -- -
VOLTAGE WAVEFORM FOR DELAY TIME

- ----O.SV
VOLTAGE WAVEFORM FOR

RISE AND FALL TIMES
S
NOTES: A. CL = 50 pF for TLC545 and 100 pF for TLC546
B. ten = tpZH or tpZL. tdis = tpHZ or tpLZ
:::! C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
o Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
:2
2-170 TEXAS ~
INSTRUMENTS
ADVANCE TLC545M. TLC5451. TLC546M. TLC5461
INFORMATION LinCMOSTM 8BIT ANALOGTODlGlTAL PERIPHERALS
The TLC545 and TLC546 are both complete data acquisition systems on single chips. Each includes such
functions as system clock, sample-and-hold, 8-bit A/D converter, data and control registers, and control
logic. For flexibility and access speed, there are four control inputs; Chip Select (CS)' Address Input, I/O
clock, and System clock. These control inputs and a TTL-compatible 3-state output facilitate serial
communications with a microprocessor or microcomputer. The TLC545 and TLC546 can complete
conversions in a maximum of 9 and 17 microseconds respectively, while complete input-conversion-output
cycles can be repeated at a miximum of 13 and 25 microseconds, respectively.
The System and I/O clocks are normally used independently and do not require any special speed or phase
relationships between them. This independence simplifies the hardware and software control tasks for
the device. Once a clock signal within the specification range is applied to the System clock input, the
control hardware and software need only be concerned with addressing the desired analog channel, reading
the previous conversion result, and starting the conversion by using the I/O clock. The System clock will
with this task.
When CS is high, the Data Output pin is in a high-impedance condition, and the Address Input and I/O
Clock pins are disabled. This feature allows each of these pins, with the exception of the CS, to share
a control logic point with their counterpart pins on additional A/D devices when additional TLC545/TLC546
devices are used. Thus, the above feature serves to minimize the required control logic pins when using
multiple A/D devices.
for two rising edges and then a falling edge of the System clock after a CS transition before the
transition is recognized. The MSB of the previous conversion result will automatically appear on
the Data Out pin.
2. A new positive-logic multiplexer address is shifted in on the first five rising edges of the I/O clock.
The MSB of the address is shifted in first. The negative edges of these five I/O clocks shift out
the 2nd, 3rd, 4th, 5th, and 6th most significant bits of the previous conversion result. The on-
chip sample-and hold begins sampling the newly addressed analog input after the 5th falling edge.
The sampling operation basically involves the charging of internal capacitors to the level of the
analog input voltage.
3. Two clock cycles are then applied to the I/O pin and the 7th and 8th conversion bits are shifted
2
out on the negative edges of these clock cycles.
4. The final 8th clock cycle is applied to the I/O clock pin. The falling edge of this clock cycle completes
o
the analog sampling process and initiates the hold function. Conversion is then performed during i=
the next 36 system clock cycles. After this final I/O clock cycle, CS must go high or the I/O clock <C
must remain low for at least 36 system clock cycles to allow for the conversion function. :E
CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple a:
conversion, special care must be exercised to prevent noise glitches on the I/O Clock line. If glitches occur o
LL
synchronization. Also, if CS .is taken high, it must remain high until the end of conversion. Otherwise, 2
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A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps (.)
1 through 4 before the 36 system clock cycles occur. Such action will yield the conversion result of the 2
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TEXAS
INSTRUMENTS
"'!1 2-171

LinCMOSTM aBIT ANALOGTODlGITAL PERIPHERALS INFORMATION
It is possible to connect the system and I/O clocks together in special situations in which controlling circuitry
points must be minimized. In this case, the following special points must be considered in addition to the
II
requirements of the normal control sequence previously described.
1. When CS is recognized by the device to be at a low level, the common clock signal is' used
as an I/O clock. When the CS is recognized by the device to be at a high level, the common
C clock signal is used to drive the "conversion crunching" circuitry.
m
r+ 2. The device will recognize a CS transition only when the CS input changes and subsequently
m the system clock pin receives two positive edges and then a negative edge. For this reason,

(")
after a CS negative edge, the first two clock cycles will not shift in the address because a
low CS must be recognized before the I/O clock can shift in an analog channel address. Also,
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c:::: upon shifting in the address, CS must be raised after the 6th I/O clock, which has been
(ii' .
recognized by the device, so that a CS low level will be recognized upon the lowering of the
;:;"
8th I/O clock signal recognized by the device. Otherwise, additional common clock cycles will
0' be recognized as I/O clocks and will shift in an erroneous address.
;:,
o
~'
For certain applications, such as strobing applications, it is necessary to start conversion at a specific point
(") in time. This device will accommodate these applications. Although the on-chip sample-and-hold begins
c:::: sampling upon the negative edge of the 5th I/O clock cycle, the hold function is not initiated until the negative
;:;"
en edge of the 8th I/O clock cycle. Thus, the control circuitry can leave the I/O clock signal in its high state
during the 8th I/O clock cycle, until the moment at which the analog signal must be converted. The
TLC545/546 will continue sampling the analog input until the 8th falling edge of the I/O clock. The control
circuitry or software must then immediately lower the I/O clock signal to initiate the hold function at the
desired point in time and to start conversion.
Detailed information on interfacing to most popular microprocesors is readily available from the factory.

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2-172 TEXAS . .
INSTRUMENlS
TLC548, TLC549
LinCMOSTM 8BIT ANALOGTODlGlTAL
PERIPHERAL WITH SERIAL CONTROL
D2816. NOVEMBER 1983- REVISED JULY 1986
LinCMOSTM Technology TLC548M. TLC549M ... 0 OR P PACKAGE

TLC5481. TLC5491 ... 0 OR P PACKAGE
Microprocessor Peripheral or Stand-Alone TLC548C. TLC549C ... 0 PACKAGE
Operation (TOP VIEW)
o 8-Bit Resolution AID Converter

R E F + [ ] 8 VCC
Differential Reference Input Voltages ANALOG IN 2 7 I/O CLOCK en
+'"
REF- 3 6 DATA OUT 'S
Conversion Time ... 17 JLs. Max GND 4 5 CS
...CJ
Total Access and Conversion Cycles Per Second C3
TLC548 ... up to 45.500 c
TLC549 ... up to 40.000 o
',t:
On-Chip Software-Controllable Sample-and-Hold 'Ci)
'S
Total Unadjusted Error ... 0.5 LSB Max C"
CJ
4-MHz Typical Internal System Clock <f:
I Wide Supply Range ... 3 V to 6 V CO
+'"
CO
Low Power Consumption ... 6 mW Typ C
Ideal for Cost-Effective. ,High-Performance Applications Including Battery-Operated Portable
Instrumentation
Pinout and Control Signals Compatible with the TLC540 and TLC545 8-Bit AID Converters and with
the TLC 1540 10-Bit AID Converter
description
The TLC548 and TLC549 are LinCMOST. A/D peripheral integrated circuits built around an 8-bit switched-
capacitor successive-approximation ADC. They are designed for serial interface with a microprocessor
or peripheral through a 3-state data output and an analog input. The TLC548 and TLC549 use only the
Input/Output Clock (liD Clock) input along with the Chip Select (CS) input for data control.
The maximum I/O clock input frequency of the TLC548 is guaranteed up to 2.048 megahertz. and the
I/O clock input frequency of the TLC549 is guaranteed to 1.1 megahertz. Detailed information on interfacing
to most popular microprocessors is readily available from the factory.
Operation of the TLC548 and the TLC549 is very similar to that of the more complex TLC540 and TLC541
devices; however. the TLC548 and TLC549 provide an on-chip system clock that operates typically at
4 megahertz and requires no external components. The on-chip system clock allows internal device operation
to proceed independently of serial input/output data timing and permits manipulation of the TlC548 and
TLC549 as desired for a wide range of software and hardware requirements. The I/O Clock together with
the internal system clock allow high-speed data transfer and conversion rates of 45.500 conversions per
second for the TLC548. and 40.000 conversions per second for the TLC549.
Additional TLC548 and TLC549 features include versatile control logic. an on-chip sample-and-hold circuit
that can operate automatically or under microprocessor control. and a high-speed converter with differential
high-impedance reference voltage inputs that ease ratiometric conversion. scaling. and circuit isolation
from logic and supply noises. Design of the totally switched-capacitor successive-approximation converter
circuit allows conversion with a maximum total error of 0.5 least significant bit (LSB) in less than
17 microseconds.
The TLC548M and TLC549M are available in the D or P plastic package and are characterized for operation
over the temperature range of - 55C to 125C. The TLC5481 and TLC5491 are characterized for operation
from - 40C to 85 DC. The TLC548C and TLC549C are characterized for operation from OC to 70C.
LinCMOS is a trademark of Texas Instruments.
~~~~~:~~i~a{::I~~~ ~!~:i~~tigr fl~o::~:~:t~rOs~s not INSTRUMENTS
TLC548, TLC549
LinCMOSTM 8BIT ANALOGTODlGITAL
(1)
REF+
(3) 8-BIT
REF- ANALOG-TO- 8
DIGITAL
--I-
c
....
Q)
ANALOG (2)
INPUT
SAMPLE
AND I CONVERTER
(SWITCHED- OUTPUT
8
I 8-TO-1 DATA
Q) HOLD I r--
CAPACITORS) DATA
REGISTER (+ SELECTOR
~OUTPUT
DATA
AND
l>
(')
.c I ....
- - DRIVER
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0'
;:;:
0'
:l
I'NTERNAL
SYSTEM
CLOCK
~ I
CONTROL
o (5)
""-
LOGIC -
:::;' cs AND
(') 171 OUTPUT
c I/O CLOCK
1
COUNTER
;+
en
operating sequence
111213141516171B 1112131415161718
1/0 - - { DON'T ~
-.l :.- SAMPLE ~ teonv --:-:--+I
#
CLOCK :.- ACCESS I I i.-- ACCESS --.: :.- SAMPLE-':

t su (CS)-I4--+! CYCLE B CYCLE B (See Note A) ~ CYCLE C CYCLE C
I tsu(CS)
CS
4I .f-'_ _ _ _ _ _ _ _~I f~, I
If--twH(CS)~ .~-------------'"
I I
I I
DATA~ HI-Z STATE I
OUT I II
I I I 87
I ~PREVIOUS CONVERSION DATA A~ I I4---CONVERSION DATA B - - . (
ten-lt---+! MSB LSa MSB t en 41 ~SB LSBS MSB
(See Note B)
NOTES: A. The conversion cycle. which requires 36 internal system clock periods (17 p'S maximum). is initiated with the 8th 1/0 clock
pulse trailing edge after CS goes low for the channel whose address exists in memory at the time.
B. The most Significant bit (A7) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining seven
bits (A6-Ao') will be clocked out on the first seven 1/0 clock falling edges. B7-BO will follow in the same manner.
2-174 TEXAS -I/}

INSTRUMENTS
TLC548, TLC549
LinCMOSTM H-BIT ANALOG-TO-DiGITAL
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
Input voltage range at any input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to V CC + 0.3 V
Output voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to V CC + 0.3 V
Peak input current range (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Peak total input current range (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30 mA
II
....
-:;
(J)
Operating free-air temperature range (see Note 2): TLC548M, TLC549M ........ - 55 DC to 125 DC
TLC5481, TLC5491 .......... - 40 DC to 85 DC CJ
a-
TLC548C, TLC549C ........... 0 DC to 70 DC U
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 DC to 150 DC C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260 DC o
'';:;
NOTES: 1. All voltage values are with respect to the network ground terminal with the REF - and GND terminal pins connected together. 'en
unless otherwise noted. ':;
2. The D package is not guaranteed below -40C. C"
CJ

TlC548 TlC549
....caca
UNIT
MIN NOM MAX MIN !\10M MAX C
Supply voltage. VCC 3 5 6 3 5 6 V
Positive reference voltage. VREF + (see Note 3) 2.5 Vee Vee+ O. 1 2.5 Vee Vee+O.l V
Negative reference voltage. VREF _ (see Note 3) -0.1 2.5 -0.1 0 2.5 V
Differential reference voltage. VREF +. VREF _ (see Note 3) 1
Vee Vee+ O.2 1 Vee Vee+0.2 V
Analog input voltage (see Note 3) 0 V
High-level control input voltage. VIH (for VCC = 4.75 V to 5.5 V) 2
Vee

2
Vee
V
Low-level control input voltage. VIL (for VCC = 4.75 V to 5.5 V) 0.8 0.8 V
Input/output clock frequency. fCLK(I/O)
0 2.048 0 1.1 MHz
(for VCC = 4.75 V to 5.5 V)
Input/output clock high. twH(IIO) (for VCC = 4.75 V to 5.5 V) 200 404 ns
Input/output clock low. twL(I/O) (for VCC - 4.75 V to 5.5 V) 200 404 ns
Input/output clock transition time. ttOlO) (see Note 4)
100 100 ns
(for VCC = 4.75 V to 5.5 V)
Duration of CS input high state during conversion. twH(CS)
17 17 p's
(for VCC = 4.75 V to 5.5 V)
Setup time. CS low before first I/O clock. tsu(CS)
1.4 1.4 P.s
(for VCC = 4.75 V to 5.5 V) (see Note 5)
I TLC548M. TLC549M -55 125 -55 125
Operating free-air temperature. T A I TLC5481. TLC5491 -40 85 -40 85 c
I TLC548C. TLC549C 0 70 0 70
NOTES: 3. Analog input voltages greater than that applied to REF + convert to all ones (11 i 11111). while input voltages less than that
applied to REF - convert to all zeros (00000000). For proper operation. the positive reference voltage VREF +. must be at
least 1 volt greater than the negative reference voltage VREF _. In additon. unadjusted errors may increase as the differential
reference voltage VREF + - VREF _ falls below 4.75 V.
4. This is the time required for the input/output clock input signal tD fall from VIH min to VIL max or to rise from VIL max to
VIH min. In the vicinity of normal room temperature. the devices function with input clock transition time as slow as 2 p'S
for remote data acquisition applications in which the sensor and the ADC are placed several feet away from the controlling
microprocessor.
5. To minimize errors caused by noise at the CS input. the internal circuitry waits for two rising edges and one falling edge of
internal system clock after eS! before responding to control input signals. This CS set-up time is given by the ten and tsu(CS)
specifications.
TEXAS 2-175
INSTRUMENTS
TLC548, TLC549
LinCMOSTM 8BIT ANALOGTODIGITAL
electrical characteristics over recommended operating freeair temperature range,

VCC ;", VREF + = 4.75 V to 5.5 V (unless otherwise noted), fCLK(l/O) ... 2.048 MHz for TLC548
II
or 1.1 MHz for TLC549
VOH High-level output voltage Vee = 4.75 V, 10H = -360 p.A 2.4 V
c
OJ
VOL low-level output voltage Vee = 4.75 V, 10l = 3.2 rnA 0.4 V
r+ Off-state (high-impedance Vo = Vee, CS at VCC 10
OJ 10Z V
state) output current Vo = 0, CS at VCC -10
:t>
(') IIH High-level input current, control inputs VI = VCC 0.005 2.5 p.A
.Q IlL Low-level input current, control inputs VI = 0 -0.005 -2.5 p.A
C Analog channel on-state input
(ii' Analog input at V CC 0.4 1
Il(on) p.A
;:t.. current, during sample cycle Analog input at 0 V -0.4 -1
o::s ICC Operating supply current CS at 0 V 1.8 2.5 rnA
ICC + IREF Supply and reference current VREF+ = VCC 1.9 3 rnA
n
~. Ci Input capacitance
I Analog inputs 7 55
pF
(') I Control inputs 5 15
C
;:t..
C/') operating characteritics over recommended operating free-air temperature range,
VCC ... VREF + ... 4.75 V to 5.5 V (unless otherwise noted), fCLK(l/O) ... 2.048 MHz for TLC548
or 1.1 MHz for TLC549
TLC548 TLC549
Zero error See Note 7 0.5 0.5 lSB
tconv Conversion time See Operating Sequence 8 17 12 17 p's
Total access and conversion time See Operating Sequence 12 22 19 25 p's
I/O
tacq See Operating Sequence 4 4 clock
(sample cycle)
cycles
Time output data remains
tv 10 10 ns
valid after 1/0 clock I
Delay time to data
td I/O clock! 300 400 ns
output valid
ten Output enable time 1.4 1.4 p's
tdis Output disable time See Parameter 150 150 ns
tr(bus) Data bus rise time Measurement Information 300 300 ns
tf(bus) Data bus fall time 300 300 ns
tAli typicals are at VCC = 5 V, TA = 25C.

NOTES: 6. Linearity error is the deviation from the best straight line through the A/D transfer characteristics.
2-176 TEXAS -I.!}

INSTRUMENTS
TLC548, TLC549
LinCMOSTM aBIT ANALOGTODlGITAL
fI
~ I vI: ...
OUTPUT k: PO INT en
OUTPUT' : knTEST
OUTPUT
UNDER TEST
CL
I TEST POINT
3kn
UNOERTESTT
CL
EST 'S
...CJ
(SEE NOTE AI ~ (SEE NOTE AI ~ U
UNOER TEST+POINT
(SEE NOTE BI (SEE NOTE BI c
CL
(SEE NOTE AI l' o
'';:
'(j)
'S
C"
td. t r AND tf tpZH AND tpHZ tpZL AND tpLZ CJ
<t
~. VCC ...
nJ
nJ
es "f\"'S_OO_yO__________S_O..lyL ____________ 0 V o
1 1
!+--tPZL -----+l I+- tpLZ -----../
- - - - - -_ _ 1 _ Vee , 1 Vec
OUTPUT
WAVEFORM 1
(SEE NOTE CI
:, . 50 % l /______ VOL
\1-,~._______,, ____.....-f1':!o
OUTPUT
WAVEFORM 2
j.--t
PZH
-1Jt. :
I 1\:0%
-- ____ VOH
(SEE NOTE el
_ _ _ _ _ _ _--J.
F SO% I+-
1
tPHZ~
I
....- - - - 0 V
(SEE NOTE BI
1/0
CLOCK
\-----O.8V
I
~td_+t
OUTPUT
DATA
OUTPUT _ _ _ _ _ _..J
X----------
1_ _ _ _ _ _-
- - - - -
2.4 V
- - - -- 0.8 V

RISE AND FALL TIMES
NOTES: A. CL = SO pF for TLCS48 and 100 pF for TLCS49; CL includes jig capacitance.
B. ten = tpZH or tpZL. tdis = tpHZ or tpLZ'
TEXAS
INSTRUMENTS
.q 2-177
POST OFFICE BOX 6B6012 DALLAS, nXAS 75265

TLC54B. TLC549
LinCMOSTM BBIT ANALOGTODlGITAL
II
The TLC548 and TLC549 are each complete data acquisition systems on a single chip. Each contains an internal
system clock, sample-and-hold, 8-bit A/D converter, data register, and control logic circuitry. For flexibility and
access speed, there are two control inputs: I/O Clock and Chip Select (CS). These control inputs and a TTL-
compatible three-state output facilitate serial communications with a microprocessor or minicomputer. A
C conversion can be completed in 17 microseconds or less, while complete input-conversion-output cycles can
m
r+
m be repeated in 22 microseconds for the TLC548 and in 25 microseconds for the TLC549.

(')
The internal system clock and I/O clock are used independently and do not require any special speed or phase
J:2 relationships between them. This independence simplifies the hardware and software control tasks for the device.
s::::: Due to this independence and the internal generation of the system clock, the control hardware and software
C;;" need only be concerned with reading the previous conversion result and starting the conversion by using the
;:;:
0" I/O clock. In this manner, the internal system clock drives the "conversion crunching" circuitry so that the control
:s hardware and software need not be concerned with this task.
o
::;"
When CS is high, the data output pin is in a high-impedance condition and the I/O clock pin is disabled. This
(') CS control function allows the I/O Clock pin to share the same control logic point with its counterpart pin when
s::::: additional TLC548 and TLC549 devices are used. This also serves to minimize the required control logic pins
;:;:
tn when using multiple TLC548 and TLC549 devices.
The control sequence has been designed to minimize the time and effort required to initiate conversion and
obtain the conversion result. A normal control sequence is:
1. CS is brought low. To minimize errors caused by noise at the CS input, the internal circuitry waits for
two rising edges and then a falling edge of the internal system clock after a CS~ before the transition
is recognized. However, upon a CS rising edge, DATA OUT will go to a high-impedance state within
the tdis specification even though the rest of the IC's circuitry will not recognize the transition until
the tsu(CS) specification has elapsed. This technique is used to protect the device against noise when
used in a noisy environment. The most significant bit (MSB) of the previous conversion result will initially
appear on the DATA OUT pin when CS goes low.
2. The falling edges of the first four 1/9 clock cycles shift out the 2nd, 3rd, 4th, and 5th most significant
bits of the previous conversion result. The on-chip sample-and-hold begins sampling the analog input
after the 4th high-to-Iow transition of the I/O Clock. The sampling operation basically involves the charging
of internal capacitors to the level of the analog input voltage.
3. Three more I/O clock cycles are then applied to the I/O pin and the 6th, 7th, and 8th conversion bits
are shifted out on the falling edges of these clock cycles.
4. The final, (the 8th), Clock cycle is applied to the I/O clock pin. The on-chip sample-and-hold begins the
hold function upon the high-to-Iow transition of this clock cycle. The hold function will continue for
the next four internal system clock cycles, after which the holding function terminates and the conversion
is performed during the next 32 system clock cycles, giving a total of 36 cycles. After the 8th I/O clock
cycle, CS must go high or the I/O clock must remain low for at least 36 internal system clock cycles
to allow for the completion of the hold and conversion functions. CS can be kept low during periods
of multiple conversion. When keeping CS low during periods of multiple conversion, special care must
be exercised to prevent noise glitches on the I/O Clock line. If glitches occur on the I/O Clock line, the
I/O sequence between the microprocessor/controller and the device will lose synchronization. If CS
is taken high, it must remain high until the end of conversion. Otherwise, a valid high-to-Iow transition
of CS will cause a reset condition, which will abort the conversion in progress.
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1
through 4 before the 36 internal system clock cycles occur. Such action will yield the conversion result of the
2-178 TEXAS -1.!1

INSTRUMENTS
TLC548, TLC549
LinCMOSTM 8BIT ANALOGTODlGlTAL
For certain applications, such as strobing applications, it is necessary to start conversion at a specific point
in time. This device will accommodate these applications. Although the on-chip sample-and-hold begins sampling
upon the high-to-Iow transition of the 4th I/O clock cycle, the hold function does not begin until the high-to-Iow
transition of the 8th I/O clock cycle, which should occur at the moment when the analog signal must be converted.
The TLC548 and TLC549 will continue sampling the analog input until the high-to-Iow transition of the 8th ....en
I/O clock pulse. The control circuitry or software will then immediately lower the I/O clock signal and start the
holding functio.n to hold the analog signal at the desired point in time and start conversion. .
':;
U
CJ
Detailed information on interfacing to the most popular microprocessor is readily available from Texas Instruments.
c
o
-..;::;
'm
':;
C"
CJ

....COCO
C
TEXAS -I!} 2-179

INSTRUMENTS

c
....
Q)
Q)
(')
.c
c
Ci)'
:=;.'
0'
::J
(")
~'
(')
c
:=;.'
en
2-180
PRODUCT TLC1205A, TLC1205B, TLC1225A, TLC1225B
PREVIEW SELFCALIBRATING 12BITPLUSSIGN UNIPOLAR OR BIPOLAR
ANALOGTODlGlTAL CONVERTERS
02982. FEBRUARY 1987
o ADVANCED LinCMOSTM Technology TLC120S

J OR N DUAL-IN-L1NE PACKAGE
Self Calibration Eliminates Expensive
Ell
(TOP VIEW)
Trimming at Factory and Offset Adjustment
in the Field ANLG VCC- DGTL VCC
IN- D12/D7/0 (status)
.....
12Bit Plus Sign Unipolar or Bit Bipolar tn
IN+ D12/D6/SARS
~

~ and 1 LSB Linearity Error in Unipolar
Configuration
10 p.s Conversion Time (Mode 2)
ANLG GND
REF
ANLG VCC+
vas
D12/D5/0/015
D 12/D4/0/DI4
D11/D3/0/DI3
D 10/D2/BYST /D12
I/O
BUS -
C3
(,)
t:
(clock ... 2.6 MHz) D9/D 1/EOC/Dl1 0
CLK IN
20 p.s Conversion Time (Mode 1) '.;::i
WR DS/oO/INT/DIO 'U;
(clock = 2_6 MHz)
CS INT '~
Compatible with All Microprocessors RD READY OUT C'
(,)
True Differential Analog Voltage Inputs
DGTL GND STATUS

0 to 5 V Analog Voltage Range with Single
TLC122S
J OR N DUAL-IN-L1NE PACKAGE
....coco
5-V Supply (Unipolar Configuration) C
(TOP VIEW)
- 5 V to 5 V Analog Voltage Range with
ANLG VCC- DGTL VCC
5V Supplies (Bipolar Configuration)
IN- D12
o Low Power ... 25 mW Maximum IN+ D11
ANLG GND D10
Replaces National Semiconductor ADC1205
REF D9
and ADC1225 in Mode 1 Operation
ANLG VCC+ DS
VOD D7
description I/O
CLK IN D6
BUS
The TLC1205 and TLC1225 converters are WR D5/o15
manufactured with Texas Instruments highly CS D4/D14
efficient ADVANCED LinCMOS'" technology. RD D3/D13
Either of the TLC1205 or TLC1225 CMOS DGTl GND D2/D12
analog-to digital converters can be operated as READY OUT D1/D11
a unipolar or bipolar converter. A unipolar input INT ........_ _...r- DO/DIO
(0 to 5 V) can be accommodated with a single
5-volt supply, while a bipolar input (- 5 V to 5 V) requires the addition of a 5-volt negative supply.
Conversion is performed via the successive-approximation method. The 24-pin TLC1205 outputs the
converted data in two 8-bit bytes, while the TLC1225 outputs the converted data in a parallel word and
interfaces directly to a 16-bit data bus. Negative numbers are given in the 2's complement data format.
All digital signals are fully TTL and CMOS compatible.
~
These converters utilize a self-calibration technique by which seven of the internal capacitors in the w
capacitive ladder of the AID conversion circuitry can be automatically or manually calibrated. If the
converters are operated in Mode 1, one of the seven internal capacitors is calibrated during the first part :>w
of the conversion sequence. For example, one capacitor is calibrated during the first conversion. The next
a:
capacitor is calibrated during the second conversion. If the converters are operated in Mode 2, the internal
capacitors are calibrated during a nonconversion, capacitor-calibrate cycle in which all seven of the internal
c..
capacitors are calibrated at the same time. A Mode 2 conversion requires only 10 p's (2.6 MHz clock) after l-
the nonconversion, capacitor-calibrating cycle has been completed. The calibration or conversion cycle t.)
may be initiated at any time by issuing the proper address to the data bus. The self-calibrating techniques :::::>
eliminate the need for expensive trimming of thin-film resistors at the factory and provide excellent c
performance at low cost. oa:
ADVANCED LinCMOS'" is a trademark of Texas Instruments Incorporated c..
specifications are design goals. Texas Instruments
TEXAS . . 2-181
reserves the right to change or discontinue these INSTRUMENTS
products without notice. POST OFFICE BOX 655012 DALLAS. TEXAS 75265
TLC1205A, TLC1205B, TLC1225A, TLC1225B PRODUCT
SELFCALIBRATING 12BITPLUSSIGN UNIPOLAR OR BIPOLAR PREVIEW
ANALOGTODIGITAL CONVERTERS
III r --------------~
I MICROPROCESSOR
I ~ S-SIT S I S S-SIT SWITCH

CALIBRATION
CONTROL
cQ) ANLG Vcc-
13-BIT
DAC I
....
Q) IN+
r---
CAPACITOR DAC ;:~ I r+- S-BIT SAR
AND S/H I

(")
["
ICOMP
I
REGISTER 1
REGISTER 2 S-BIT
.c L
c I l-S ALU
DATA
13-BIT
Ci)'
~'
IN-
CAPACITOR DAC ;:r:: I' PATH
0'
::J
n
REF
~
AND S/H
I
~ '13
Y13 CALIBRATION
881T
DAC
+~+1I
S-WORD
ADDRESS
RAM
ADDRESS
::;' 13 I COUNTER COUNTER
(")
c 5 V - 10 V TRANSLATOR I 1 2
~' 13-BIT SWITCH CONTROL 1 CLOCKS
en I
,.
13 BIT SAR 6
I
INPUT DATA LATCHES
I
13-BIT CALIBRATION
CONTROL LOGIC
I
13
. ,
1-
~
13-BIT DATA LATCH -, -r
, I
, 6
, MUX
I
CONTROL
I
# #. 1 ROM
I/O BUS , I
vas
TLC1205: # - S
TLC1225: # - 13
"' ~I
,-
I
PROGRAM
1
I
I COUNTER 1
INT I
I
CS
WR
I
...
r ~ __ 2_1_1 __ -- __ -1
RD r
READY OUT ~
(TLC1205 ONLY)
STATUS
In Mode 1, these converters are replacements for National Semiconductor ADC1205 and ADC 1225
integrated circuits. The Mode 1 conversion time for guaranteed accuracy is 51 clock cycles. In the Mode 2
"'tJ operation, these devices are no longer true replacements. However, the Mode 2 conversion time for
J3 guaranteed accuracy is only 26 clock cycles:
o The TLC1205AM, TLC1205BM, TLC1225AM, and TLC1225BM are characterized for operation over the
C full military temperature range of -55C to 125C. The TLC1205AI, TLC1205BI, TLC1225AI, and
c: TLC1225BI are characterized for operation from - 40C to 85 DC.
n
-I
"'tJ
J3
m
~
m
~
2-182 TEXAS
INSTRUMENTS
operation description
calibration of comparator offset

The following actions are performed to calibrate the comparator offset:
1. The IN + and IN - inputs are internally shorted together in order that the comparator input is zero .
A course comparator offset calibration is performed by storing the offset voltages of the
...
S
(/)
interconnecting comparator stages on the coupling capacitors, which connect the interconnecting ...
(,)
stages. Refer to Figure 1. The storage of offset voltages is accomplished by closing all switches C3
and then opening switches A and A', then switches Band B', and then C and C'. This process t:
continues until all interconnecting stages of the comparator are calibrated. After this action, some o
.';:
of the comparator offset still remains uncalibrated. .Ci)
S
C"
(,)

...cucu
C
FIGURE 1
2. An AID conversion is done on the remaining offset with the 8bit calibration DACs and 8-bit SAR
and the result is stored in the RAM. I
capacitor calibration of the ADC's Capacitive Ladder

The following actions are performed to calibrate capacitors in the 13-bit DAC's, which comprise the ADC's
capacitive ladder:
1. The IN + and IN - inputs are internally disconnected from the 13-bit capacitive DACs.
2. The most-significant-bit (MSB) capacitor is tied to REF, while the rest of the ladder capacitors are
tied to GND. The AID conversion result for the remaining comparator offset, obtained in step 2
above, is retrieved from the RAM and is input to the 8-bit DACs.
3. Step 1 of the Calibration of Comparator Offset sequence is performed. The 8-bit DAC input is
returned to zero and the remaining comparator offset is then subtracted. Thus, the comparator
offset is completely corrected. ~
4. Now the MSB capacitor is tied to GND, while the rest of the ladder capacitors, Cx , are tied to w
REF. An MSB capacitor voltage error (see Figure 2) on the comparator output will occur if the MSB
capacitor does not equal the sum of the other capacitors in the capacitive ladder. This error voltage
:>w
is converted to an 8-bit word from which a capacitor error is computed and stored in the RAM. a:
5. The capacitor voltage error for the next most significant capacitor is calibrated by keeping the MSB c..
capacitor grounded and then performing the above Steps 1 - 4 while using the next most significant
capacitor in lieu of the MSB capacitor. The seven most significant capacitors can be calibrated l-
e.,)
in this manner.
::>
c
o
a:
c..
TEXAS ~ 2-183
INSTRUMENTS
POST bFFICE BOX 655012 , DALLAS, TEXAS 16265
ANALOGTODlGITAL CONVERTERS
Vref (Step 31
GND (Step 41
~
..L CMSB + ..L Cx
C
m
rot
m MSB CAPACITOR
VOLTAGE ERROR
n
} (Step 41
.c
c
iii'
;:;" ,Cx ,CMSB-
0' '----v--"
:::l
GND (Step 31
o Vref (Step 41
::;'
n
c FIGURE 2
;:;"
C/I
analog-to-digital conversion
The following steps are performed in the analog-to-digital conversion process:
1. Step 1 of the Calibration of Comparator Offset Sequence is performed. The AID conversion result
for the remaining comparator offset, which was obtained in Step 2 of the Calibration of Comparator
Offset, is retrieved from the RAM and is input to the 8-bit DACs. Thus the comparator offset is
completely corrected.
2. IN + and IN - are sampled onto the 13-bit capacitive ladders.
3. The 13-bit analog-to-digital conversion is performed. As the successive-approximation conversion
proceeds successively through the seven most significant capacitors, the error for each of these
capacitors is recovered from the RAM and accumulated in a register. This register controls the '
8-bit DACs so the total accumulated error for these capacitors is subtracted out during the
conversion process.
Supply voltage (ANLG VCC + and DGTL VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Supply voltage, ANLG VCC - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -15 V
Control and Clock input voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to + 15 V
Analog input (IN +, IN -) voltage range,
VI+ and VI_ ......................... ANLG VCC- -0.3 V to ANLG VCC+ + 0.3 V
."
:a Reference voltage range, Vref . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to ANLG VCC + + 0.3 V
o Mode select voltage range, VOS ......................... -0.3 V to ANLG VCC+ + 0.3 V
c Output voltage range ................................... - 0.3 V to DGTL VCC + 0.3 V
c(") Input current' (per pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 mA

Input current (per package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20 mA
Operating free-air temperature range:
-I TLC1205AM, TLC1205BM, TLC1225AM, TL 1225BM . . . . . . . . . . . . . . . . .. - 55 DC to 125 DC
." TLC1205AI, TLC1205BI, TLC1225AI, TLC1225BI ...................... -40 DC to 85 DC
:a Storage temperature range ......................................... - 65 DC to 150 DC
m Lead temperature 1,6 mm (1/16 inch) from the case for 60 seconds: J package . . . . . . . . .. 300 DC
::::
m
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: N package .......... 260 DC
Note 1: All analog voltages are referred to ANLG GND and all digital voltages are referred to DGTL GND.
~
2-184 TEXAS
INSTRUMENTS
-1!1
ANALOG TODlGITAL CONVERTERS

MIN MAX UNIT
Supply voltage
ANLG VCC+
ANLG VCC-
DGTL VCC
High-level input voltage, VIH, all digital inputs except CLK IN
-5.5
4.5
4.5
6
ANLG GND
6
V
fI
... en
(VCC = 4.75 V to 5.25 V)
2 V ':;
Low level input voltage, VIL, all digital inputs except CLK IN
0.8 V
...CJ
(VCC = 4.75 V to 5.25 V) U
Analog input voltage, VI +, VI_
Bipolar range ANLG VCC- - 0.05 ANLG VCC+ + 0.05
V
c
Unipolar range ANLG GND - 0.05 ANLG VCC+ + 0.05 o
'';:;
Clock input frequency, fclock 0.3 2.6 MHz 'Ci)
Clock duty cycle 40% 60% ':;
Pulse duration,CS and WR both low, tw (tS,WR) 350 ns C"
CJ
Setup time before WRt or CSt, tsu 100 ns -d:
Hold time after WRt or cst, th
TLC1205AM, TLC1225AM
-55
20
125
ns
...
CO
CO
TLC1205BM, TLC1225BM C
Operating free-air temperature, T A c
TLC1205AI, TLC1225AI
-40 85
TLC1205BI TLC1225BI
electrical characteristics over recommended operating free-air temperature range,

ANLG Vee+ DGTL Vee = Vref = 5 V, ANLG Vee- = -5 V (for bipolar input range),
ANLG Vee - = ANLG GND (for unipolar input range) (unless otherwise noted) (see Note 1)
-1.8 mA 2.4
VOH High-level output voltage DGTL VCC = 4.75 V : 10 = V
10 = -50/lA 4.5
VOL Low-level output voltage DGTL VCC = 4.75 V, 10 = 8 mA 0.4 V
VT+ Clock positive-going threshold voltage 2.7 3.5 V
VT- Clock negative-going threshold voltage 1.4 2.1 V
VT+min - VT- -max 0.6
Vhys Clock input hysteresis V
VT +max - VT _min 2.1
Rref Input resistance, REF terminal 1 10 MO
IIH High-level input current VI =.5 V 1 /lA
IlL Low-level input current VI = 0 -1 /lA
High-impedance-state Vo = 0 -3
10Z /lA
output leakage current Vo = 5 V 3
~
Vo = 0 -6
10 Output current mA
8
Vo = 5 V
w
DGTL ICC
ANLG ICC+
Supply current from DGTL VCC
Supply current from ANLG V CC +
fclk = 2.6 MHz,
fclk = 2.6 MHz,
CS high
CS high
3
3
mA
mA :>w
ANLG ICC- Supply current from ANLG VCC- fclk = 2.6 MHz, CS high -3 mA a:
NOTE 1: Bipolar input range is defined as: VI + = - 5.05 V to + 5.05 V, VI_ = - 5.05 V to + 5.05 V, and I VI + - VI_ I :$ 5.05 V.
c.
The unipolar input voltage range is defined as: VI + = - 0.05 V to 5.05 V, VI_ = - 0.05 V to 5.05 V, I-
and IVI+ - VI_I :$ 5.05 V.
U
::J
C
oa:
c.
INSTRUMENTS
TEXAS 'Ii1 2-185
paST OFFla BOX 695012 DALLAS. TEXAS 15265

ANLG Vee + = DGTL Vee = Vref = 5 V, ANLG Vee - = - 5 V (for bipolar input range),
ANLG Vee - = ANLG GND (for unipolar input range), fclock = 2.6 MHz (unless otherwise noted)(see
Note 1)
c
Q) Unipolar input range
TLC1205A, TLC1225A 1
r+ TLC1205B, TLC1225B 0.5
Q) Linearity error LSB
TLC1205A, TLC1225A 2

(')
Bipolar input range
TLC1205B, TLC1225B 1.5
.c Zero error 0.5 LSB
c Adjusted positive and negative
en' full-scale error (see Note 2)
Unipolar input range 1 LSB
;::;'
0' Adjusted positive and negative
Bipolar input range 1 LSB
::l full-scale error (see Note 3)
n Temperature coefficient of gain 15 ppm/oC

:::;' Temperature coefficient of offset point 1.5 ppm/oC
(')
c Zero error
ANLG VCC+ = 5 V 5%,
0.75
;::;' Supply voltage Positive and negative
en kSVS sensitivity full-scale error
ANLG VCC- = -5 V 5%, 0.75 LSB
DGTL VCC = 5 V 5%
Linearity error 0.25
Mode 1 51 1
tc Conversion tim
Mode 2 26
-
fclk
Access time (delay from falling edge of
ta CL = 100 pF 210 ns
, CS,RD to data output)
Disable time, output (delay from rising RL = 10 kn, CL = 10 pF 260
tdis ns
edge of RD to high-impedance state RL = 2 kn, CL = 100 pF 290
td(READY) RD or WR to READY OUT delay 400 ns
td(lNT) RD or WR to reset of INT delay 400 ns
NOTES: 1. Bipolar input range is'defined as: VI+ = -5.05Vto+5.05V,VI_ = -5.05Vto+5.05V,andIVI+ -VI_I :55.05V.
The unipolar input voltage range is defined as: VI+ = -0_05 V to 5.05 V, VI_ = -0.05 V to 5.05 V,
and IVI+ - VI_I :5 5.05 V. .
2. See section - Positive and Negative Full-Scale Adjustment, Unipolar Inputs.
3. See section - Positive and Negative FUll-Scale Adjustment, Bipolar Inputs.
"o::xJ
C
C
('")
-I
"
::xJ
m
<
m
~
2-186 TEXAS . .
INSTRUMENTS
CALIBRATE CONVERSION
~
A~~S~~E1 ~~~~::;~E
ClK IN
CAPACITOR
T-+j
r1...flJl.n .fl. n .....f1.f1.fl. fl ..
INPUT
SAMPLING AND ONE
CAPACITOR Ell....en
o 26 2B 35 51 0 1 26 'S
r
(,)
a-
~I tw(CSWR) Htw(CS.WR) U
WR 1--J--------------~L__J
C
o
I I I
I. ~
I
14- tdIREADYI
'~
'Ci)
I td(READYI-.! If- I 'S
C"
I (,)
READY OUT I
I II I I <C
I
I I
-+I 14- tdIREADYI
I
: -+I I+-td(READYI ....COCO
-+t I+- td(READY) td(READYI--.t 14- : C
ItdIlNTI~
I I I I ~I__________
I I I:
I--~--
I
...
"-- CS stays low to address
I I 2nd byte of TlC1205
----------------------------------~IL....--JI I ' __ .JI
L.~
: LRead 2nd byte of TLC1205
I/O BUS ----------------:---K I

I
C-=
1"-
I I \4- t dis--.l L2nd byte of TLC1205
ta--M-+I
FIGURE 3. MODE 1 TIMING DIAGRAM
~
W
>
w
a:
c..
I-
U
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C
oa:
c..
TEXAS -II} 2-187
INSTRUMENTS
~--~I- CONVERSION
\4---+f-INPUT
I ISAMPLING
ClK IN
..nJ1. fl. fl .....f1.f"1..n. fl. n ..
c
Q) HtW(cs.W!'i) HtW(CS'WR) HtW(cs.W!'i)
r+
Q)
-----;L.J ~------~L.J
l>
(')
I I I I I I
.c I I 14- td(REA~Y) -+t ~ td(READY) I -+I ~ td(READY)
c I -+t I I td(READY) ~ j4- I
0' I
READY OUT I
;:;:
0' ---....II
I I
I
I I
j -+I If- td(READY) I I ~ 14- t(READY)
I ~ td(READY)~ 14- I
o If- td(READY)
::;'
(')
I
I :td(lNT)~:
c I I ~I~:------
;:;:
(I) I
I
I
I
I I
------~I------~I-------------~I I~~I~-~I--
.t.._~ ~ ... '---J L~ .. _ oJ
tsu--"--" tsu............... I L Read 2nd byte I
I ~ th I tt--M-th I I of TlC1205
____ ~I ~I______~I wl~_ _ _ _ _ _ _ _ _ _ _~I_~~--~'
I/O BUS r ..
COMMAND TO CALIBRATE
7 CAPACITORS & OFFSET
(REQUIRES 105 CLOCK CYCLES)
FIGURE 4. MODE 2 TIMING DIAGRAM
"'tJ
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C
n
-t
"'tJ
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m
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~
2-188 TEXAS
INSTRUMENTS
-'!1
POST OI'I'ICE BOX 656012 DALLAS. rexAS 75265
PREVIEW SELF-CALIBRATING 12-BIT-PLUS-SIGN UNIPOLAR OR BIPOLAR
ANALOG-TO-OIGITAL CONVERTERS
DGTL
VCC
R o m DATA
VCC---
RD 50% 90%
II ....
(/)
r .
'5
OUTPUT
CL GND 10~%
tdis (J
= = RL VOH
DATA OUTPUT
90%
u
DGTL
GND---- c
VCC
o
'';'
'en
-?-#r
~RL '5
C"
(J
RD DATA
OUTPUT
GND

CL
....CtICtI
VCC-----l~
= DATA OUT C
VOL---~
FIGURE 5. LOAD CIRCUITS AND WAVEFORMS
The following information is 'categorized into Mode 1 and Mode 2 groupings to allow the designer to
concentrate on a particular mode of interest
power-up calibration sequence
Mode 1
When the chip is powered-up, the internal capacitors are automatically calibrated as part of the power-up
sequence. This initial calibration sequence requires 105 clock cycles. The chip will not perform an AID
conversion during this calibration sequence.
Mode 2
Power-Up calibration is not automatic and calibration is initiated by writing control words to the six least
significant bits of the data bus. If addressed or initiated, conversion can begin after the first clock cycle.
However, full AID conversion accuracy is not guaranteed until after internal capacitor calibration.
sw
conversion start sequence
:>w
a:
Mode 1 c..
The conversion sequence is initiated when CS and WR are both low. l-
e.,)
Mode 2 ::J
The writing of the conversion command word to the six least significant bits of the data bus, when either C
CS or WR goes high, initiates the conversion sequence. o
a:
c..
TEXAS .Ji} 2-189
INSTRUMENTS
TLC1205A. TLC1205B. TLC1225A. TLC1225B PRODUCT
analog sampling sequence
lIB
Mode 1
Sampling of the input signal occurs during clock cycles 29 thru 35 of the conversion sequence.
c
D)
Mode 2
r+
D) Sampling of the input signal occurs during clock cycles 4 thru 10 of the conversion sequence.

(') completed AID conversion
.c
c
0' When INT goes low, conversion is complete and the AID result can be read. A new conversion can begin
;:;: immediately.
0'
:s Mode 1
o
::;' The AID conversion is complete at the end of clock cycle 51 of the conversion sequence.
(')
c
;:;: Mode 2
t/)
The AID conversion is complete at the end of clock cycle 26 of the conversion sequence.
aborting a conversion in process and beginning a new conversion
Mode 1 and Mode 2

If a conversion is initiated while a conversion sequence is in process, the ongoihg conversion will be aborted
and a new conversion sequence will begin.
Mode 1
If the new conversion is started before the Analog Sampling begins (see Analog Sampling Sequence section
and the Mode 1 Timing Diagram), the particular internal capacitor that was being calibrated during the
aborted conversion sequence will be calibrated during the new conversion sequence. Otherwise, the next
internal capacitor will be calibrated during the new conversion sequence.
reading the conversion result
TLC1205
Upon activating the required control signals to read the conversion result or status information, the
"'C appropriate pins are brought out of a high-impedance state and drive the data bus with the proper
::c information. These pins are D12/D7/0 through D8/DO/INT/DI0.
oC If STATUS, CS, and RD are all low, status information can be read. The format of the conversion result
and status information and the respective pins for output are presented in Table 1.
C
()
-f
"'C
::c
m
<
m
~
2-190 TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 OALLAS. tEXAS 15265
TABLE 1
1/0 BUS
BYTES STATUS CS RO
0121
071
0
0121
061
SARS
0121
051
01
015
0121
041
01
014
0111
031
01
013
0101
021
BYSTI
012
091
01/
EOCI
011
081
001
INTI
DlO
II
... en
':;
MSB H L L 012 012 012 012 011 010 09 08
LSB H L U 07 06 05 04 03 02 01 00 ...
(,)
STATUS L L L L SARS L L L BYST EOC INT c:;

s::
The status information is described in Table 2. o
'';::;
'Ci)
TABLE 2 ':;
C'
STATUS (,)
BIT DESCRIPTION TO CLEAR BIT
BIT <t
L
SARS
The output has no meaning and is low.
A high indicates that conversion is in progress.

...
CO
CO
C
BYST A low indicates that the next conversion result read will be the By a "status write" or toggled by reading a
most significant conv~rsion byte. A high indicates that the next conversion data byte
conversion result read will be the least significant conversion byte.
The BYST bit is toggled by reading the conversion result bytes. This
bit can be cleared with a "status write" instruction.
EOC A high indicates that conversion is complete and the conversion

data has been transferred to the output latch.
INT A high indicates that conversion is complete and the conversion By reading a conversion data byte, reading
data has been transferred to the output latch and is ready to read. the status byte, or a "status write"
With STATUS high, when CS and RD both go low, the most significant byte (MSB) of the conversion result
can be read. Then by taking'RD high and back low, the least significant byte (LSB) of the conversion
result can be read. Subsequently taking RD high and low causes the alternate reading of the MSB and LSB
of the conversior:J result.
The format of the output is extended sign with 2's complement, right justified data. For both unipolar and
bipolar cases, the sign bit D12 is low if VI + - VI_ is positive and high if VI + - VI_ is negative. The
~
format of the conversion result and the respective output pins are presented in Table 2. The format of
the conversion result and the respective pins for output are presented in Table 1.
W
TLC1225
When both CS and RD go low, all 13 bits of conversion data are output to the I/O bus. The format of
>
w
the output is extended sign With 2's complement, right justified data. Unlike the TLC1205, the TLC1225
a:
Q.
does not have internal status information or a STATUS pin. For both unipolar and bipolar cases, the sign
bit D12 is low if VI + - VI_ is positive and high if VI + - VI_ is negative. ....
(.)
::J
C
oa:
Q.
TEXAS ~ 2-191
INSTRUMENTS
. TLC1205A, TLC1205B, TLC1225A, TLC1225B PRODUCT
SELF-CALIBRATING 12-BIT-PLUS-SIGI\! UNIPOLAR OR BIPOLAR PREVIEW
ANALOG-TO-D1GITAL CONVERTERS
general
IJ
reset INT
When reading the conversion data, the falling edge Qf the first low-going combination of CS and RD will
reset INT. The falling edge of the low-going combination of CS and WR will also reset INT.
c
....
Q)
Q)
ready out
(')
For high-speed microprocessors, READY OUT allows the TLC1205 and the TLC1225 to insert a wait state
in the microprocessor's read cycle.
.c
c status write (TLC1205)
iii'
;:;:
o
j
A status write resets the internal logic and status bits and aborts any conversion in process. A status write
occurs when CS, WR, and STATUS are taken low.
o
::;. reference voltage (V ref)
(')
c This voltage defines the range for I VI + - VI_I. When I VI + - VI_ I equals Vref, the highest conversion
;:;:
(f) data value results. When I VI + - VI_ I equals 0, the conversion data value is zero. Thus, for a given
input, the conversion data changes ratiometrically with changes in Vref.
Vas
This pin is a digital input and is used to select Mode 1 or Mode 2 operation. A logic low selects Mode 1;
a logic high selects Mode 2.
In Mode 1, the ICs are true replacements for National Semiconductor's ADC1205 and ADC1225. The
ADC1205 and ADC1225 use the vas pin to adjust zero error. Since the zero error adjustment voltage
is below the TLC1205's and TLC1225's maximum acceptable level for a logic low signal, the TLC1205
and TLC1225 ICs are true replacements. Even in Mode 1, the TLC1205's and TLC1225's converted data
can be read earlier than the ADC1205's and ADC1225's.
calibration and conversion considerations

Mode 1
Calibration of the seven internal capacitors is an integral part of the AID conversion. One of the seven
internal capacitors is calibrated during the first part of the conversion sequence. For example, one of the
capacitors is calibrated during the first conversion. The next capacitor is calibrated during the second
conversion. After seven conversions, the pattern for calibrating the internal capacitors repeats. A conversion
sequence requires 51 clock cycles.
"'C
::a A conversion is initiated by the low-going combination of CS and WR. The conversion sequence. is
o illustrated in the Mode 1 timing diagram.
c Mode 2
c:
n Calibration of the internal capacitor and AID conversion are two separate actions., Each action is
-I independently initiated. Mode 2 conversion is much faster than Mode 1, since Mode 2 conversion is not
accompanied by the calibration of internal capacitors. In Mode 2, a calibration command that calibrates
"'C
::a all seven internal capacitors is normally issued first. A conversion command then initiates the AID conversion
m without calibrating the internal capacitors. Subsequent conversions can be performed by issuing additional
conversion commands. The calibration and conversion commands are totally independent from one another
S
m
and can be initiated in any order. Calibration and conversion commands require 105 and 26 clock cycles,
respectively.
~
2-192 TEXAS
INSTRUMENTS
The calibrate and conversion commands are initiated by writing control words on the six least signiticant
bits of the data bus. These control words are written into the IC when either CS or WR goes high. The
initiation of these commands is illustrated in the Mode 2 Timing Diagram. The bit patterns for the commands
are shown in Table 3.
TABLE 3. MODE 2 CONVERSION COMMANDS

II ....en
1/0 BUS Required number 'S
COMMANO CS + WR
015 014 013 012 011 010 of clock cycles ...
(J
Conversion f H L X X X L 26 C3
Calibrate t f L X L L L L 105 c
o
tCalibration is lost when clock is stopped. '';::;
'0
analog inputs
'S
C'
(J
differential inputs provide common mode rejection <C
The differential inputs reduce commonmode noise. Commonmode noise is noise common to both IN + ....COCO
and IN - inputs, such as 60Hz noise. There is no time interval between the sampling of the IN + and IN- C
so these inputs are truly differential. Thus, no conversion errors result from a time interval between the
sampling of the IN + and IN - inputs.
input bypass capacitors

Input bypass capacitors may be used for noise filtering. However, the charge on these bypass capacitors
will be depleted during the input sampling sequence when the internal sampling capacitors are charged.
Note that the charging of the bypass capacitors through the differential source resistances must keep pace
with the charge depletion of the bypass capacitors during the input sampling sequence. Note that higher
source resistances reduce the amount of charging current for the bypass capacitors. Also, note that fast,
successive conversion will have the greatest charge depletion effect on the bypass capacitors. Therefore,
the above phenomenon becomes more significant as source resistances and the conversion rate (i.e., higher
clock frequency and conversion initiation rate) increase.
In addition, if the above phenomenon prevents the bypass capacitors from fully charging between
conversions, voltage drops across the source resistances will result due to the ongoing bypass capacitor
charging currents. The voltage drops will cause a conversion error. Also, the voltage drops increase with
higher IVI + - VI_ I values, higher source resistances, and lower charge on the bypass capacitors
(i.e., faster conversion rate).
For low-source-resistance applications (Rsource < 100 m, a O.OO1-itF bypass capacitor at the inputs will
prevent pickup due to the series lead inductance of a long wire. A 1OO-ohm resistor can be placed between
the capacitor and the output of an operational amplifier to isolate the capacitor from the operational amplifier. ~
w
input leads
The input leads should be kept as short as possible, since the coupling of noise and digital clock signals
:>w
to the inputs can cause errors. a:
c..
power supply considerations t-
Noise spikes on the VCC lines can cause conversion error. Low-inductance tantalum capacitors (> 1 itF)
(.)
with short leads should be used to bypass ANLG VCC and DGTL Vcc. A separate regulator for the TLC1205 :::J
or TLC1225 and other analog circuitry will greatly reduce digital noise on the supply line. C
oa:
c..
TEXAS . . 2-193
INSTRUMENTS
TLC1205A. TLC1205B. TLC1225A. TLC1225B PRODUCT
SELFCALIBRATING 12,BITPLUSSIGN UNIPOLAR OR BIPOLAR PREVIEW
positive and negative full-scale adjustment
lEI
c
unipolar inputs
Apply a differential input voltage that is 0.5 LSB below the desired analog full-scale voltage (VFS) and
adjust the magnitude of the REF input so that the output code is just changing from 0.1111 1111 1110
to a 1111 1111 1111. If this transition is desired for a different input voltage. the reference voltage can
...
Q)
Q)
be adjusted accordingly .
~ bipolar inputs
(')
.Q
I: First. follow the procedure for the Unipolar case.
iii' Second. apply a differential input voltage so that the digital output code is just changing from
;=;"
0' 1 0000 0000 0001 to 1 0000 0000 0000. Call this actual differential voltage Vx. The ideal differential
::l voltage for this transition is:
(")
;i'
(')
I:
-VFS +~
8192 (1 )
;=;"
en The difference between the actual and ideal differential voltages is:
VFS
Delta = Vx - (-VFS + 8192) (2)
Then apply a differential input voltage of:
Delta
Vx - (3)
2
and adjust Vref so the digital output code is just changing from 1 0000 0000 0001 to 1 0000 0000 0000.
This procedure produces positive and negative full-scale transitions with symmetrical minimum error.
"'C
::xJ
o
C
C
n
-4
"'C
::xJ
m
S
m
~
2-194 TEXAS
INSTRUMENTS
TYPICAL APPLICATIONS
(4095) 0 1111 1111 1111

(4094) 0 1111 1111 1110
~
OSITIVE
FULL-SCALE
fI
2:
TRANSITION
en
+I
.
S
"5
o
::"//
w (2) 0 0000 0000 0010
U
C
o (1) 0 0000 0000 0001
c
U (0) 0 0000 0000 0000
o
I-
".;:I
::J "0
l= -Vref 1 1111 1111 1111 (-1) +Vref
"5
::J 1 1111 1111 1110 (- 2)
o .""" C-
O
."""
.",
"
.""" CO
.", +I
.", CO
~nVE
C
1 0000 0000 0001 (- 4095)
FULL-SCALE TRANSITION 1 0000 0000 0000 (- 4096)
ANALOG INPUT VOLTAGE [VIN(+) - VIN(-)) ,
FIGURE 6. TRANSFER CHARACTERISTIC
.---------1 IN! + ) DGTL Vcc t--+----.------,
__- - - - - I IN! -) ANLG Vcc 1--+----_---.

J
SEE NOTE A ~
*
.----..----1 Vref
.-----~~ANLG GND
SIGNAL GND ~
~--~~DGTLGND
w
= POWER GND '--_ _ _ _ _ _ ~ :>w
NOTE: A, The analog input must have some current return path to ANALOG GND. a:
B. Bypass capacitor leads must be as short as possible. Q.
FIGURE 7. ANALOG CONSIDERATIONS ....
(.)
::J
C
o
a:
Q.
TEXAS ~ 2-195
INSTRUMENTS
TYPICAL APPLICATIONS (Continued)
II
c
Q)
IN914
5V
r+
Q)
>-----W\l-............--IIN(+) ANLG vcc+
l> +
n ~-=_ 10 p.F
.c TLC1205 .L
c -= TLC1225
en'
;:;:
0'
:::I IN(-)
n
:::;'
n FIGURE 8. INPUT PROTECTION
c
::+
en 5V
4 kO
VXDR
I-S--EE~NO-T--E--B-+----IIN( +) ANLG Vec + 1 - - . . . . - - -..
5000 0.1 p.F +10 p.F
ZERO
ADJ
IN( -) SEE NOTE A
"J
DGTL Vec 1 - - - - - 9 - - -...
+
5000 TLC1205 0.1 p.F ~-= 10p.F '"1"'-=_ 3.9kO
TLS1225 ...L..J..:"
-=
1 kO
1----fIo< FS
ADJ
8.2 kO
."
::a
o NOTE: A. VI_ = 0.15 x ANLG Vee+.
c B. 15% of ANALOG Vee :5 VXDR :5 85% of ANALOG Vee
c(") FIGURE 9. OPERATING WITH RATIOMETRIC TRANSDUCERS
-I
."
::a
m
~
m
:E
2-196
TEXAS -I!}
INSTRUMENTS
TLC1540M, TLC15401, TLC1541 M, TLC15411
LinCMOS 1OBIT ANALOGTODIGITAL PERIPHERALS
02859. DECEM8ER 1985-REVISED OCTOBER 1986
LinCMOSTM Technology N DUAL-IN-LiNE PACKAGE
1 O-Bit Resolution AID Converter

(TOP VIEW)

Microprocessor Peripheral or Stand-Alone
Operation
On-Chip 12-Channel Analog Multiplexer
INPUT AO
INPUT Al
INPUT A2
INPUT A3
VCC
SYSTEM CLOCK
I/O CLOCK
ADDRESS INPUT
fI ....en
S

Built-In Self-Test Mode
Software-Controllable Sample and Hold
INPUT A4
INPUT A5
INPUT A6
DATA OUT
CS
REF+ U
.
CJ
INPUT A7 REF-
Total Unadjusted Error ...
TLC1540: 0.5 LSB Max
INPUT AS INPUT Al0
.~
c
o
GND INPUT A9 .C;;
TLC1541: 1.0LSBMax
S
Pinout and Control Signals Compatible with
TLC540 and TLC549 Families of 8-Bit AID
FN CHIP CARRIER PACKAGE C"
CJ
Converters
(TOP VIEW)

....COCO
TYPICAL PERFORMANCE
Channel Acquisition Sample Time 5.51'S
C
Conversion Time 21 1'S
Samples per Second 32 x 10 3
Power Dissipation 6mW
3 2 1 20 19
description INPUT A3 4 18 I/O CLOCK
The TLC1540 and TLC1541 are LinCMOSTM A/D 5 INPUT
17 ADDRESS INPUT
A4
peripherals built around an 10-bit switched- 6 INPUT
16 DATA OUT
A5
capacitor successive-approximation A/D 7 15 CS
INPUT A6
converter. They are designed for serial interface 8 INPUT
14 REF+ A7
to a microprocessor or peripheral via a three- 9 1011 12 13
state output with up to four control inputs (000)1

[including independent System Clock, I/O Clock, ~~~~tt
Chip Select (CS), and Address Input]. A :::> :::>I-CI:
a.. a..:::>
2.1-megahertz system clock for the TLC1540 Z za..
and TLC 1 541, with a design that includes
-~ -
simultaneous read/write operation, allows high-
speed data transfers and sample rates of up to
32,258 samples per second. In addition to the
high-speed converter and versatile control logic, there is an on-chip 12-channel analog multiplexer that
can be used to sample anyone of 11 inputs or an internal "self-test" voltage, and a sample-and-hold that
can operate automatically or under microprocessor control. Detailed information on interfacing to most
popular microprocessors is readily available from the factory.
The converters incorporated in the TLC 1 540 and TLC 1 541 feature differential high-impedance reference
inputs that facilitate ratiometric conversion, scaling, and analog circuitry isolation from logic and supply
noises. A totally switched-capacitor design allows guaranteed low-error conversion ( O. 5 LSB for the
TLC1540, 1 LSB for the TLC 1541) in 21 microseconds over the full operating temperature range.
The TLC1540 and the TLC1541 are available in both the Nand FN plastic packages. The M-suffix versions
are characterized for operation from - 55 C to 125 C. The I-suffix versions are characterized for operation
from -40 0 C to 85C.
LinCMOS is a trademark of Texas Instruments Incorporated
This documant contains information on products in Copyright 1985. Texas Instruments Incorporated
TEXAS ~
mora than one phase of development. The status of
each device is indicated on the pagels) specifying its
electrical characteristics_ 2-197
INSTRUMENTS
POST OFFICE BOX 655012 DALLAS. TEXAS 75265~
TLC1540M, TLC15401, TLC1541 M, TLC15411

REF+ REF-
II
c
Q) SAMPLE
10-BIT
ANALOGTODIGITAL
CONVERTER
r+ AND
Q) (SWITCHED-CAPACITORS)
HOLD
J>
(') 12-CHANNEL
.c ANALOG ANALOG
c INPUTS MULTIPLEXER
tij"
DATA
;:;" OUTPUT
0"
::s
o
::;"
(')
c
;:;" CONTROL LOGIC
UI '------+-------1 AND I/O
r---~----~ COUNTERS
ADDRESS
INPUT ----------~~----_i
I/O
CLOCK
cs----------~~----------------------------------~
S~~~;: -----------.-----------------------------------------4~------------------~
operating sequence
I1 I2 I 3 I4 I5 I6 I 7 I 8 I 9 I 10
1/0
CLOCK--7 DON'T~
.:.. tconv --+, t4-ACCESS--':
CS-, _. CYCLEB I,~J------..!..-.: I CYCLEC I
'-I'f---;;:ISe'=.:-::N::":o":':t.:-:C::-:I-----------------------' 1w HICSI-.y,f-'______________________________ ..11
MSB LSB MSB LSB
ADDRESS ,~ DDN'TCARE DON'T CARE
INPUT --I. ~..------------'-~.;.....;:,;...;.;..;~-----f,f------<
HI-Z STATE
A9
+--- PREVIOUS CONVERSION DATA-----.
MSB LSB MSB
IS Not. BI
NOTES: A. The conversion cycle, which requires 44 System Clock periods, is initiated on the 1Ott'! falling edge of the liD Clock~ after
CS~ goes low for the channel whose address exists in memory at that time. If CS is kept low during conversion, the 110 Clock
must remain low for at least 44 System Clock cycles to allow conversion to be completed.
B. The most significant bit (MSB) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining
nine bits (AB-AO) will be clocked out on the first nine 110 Clock falling edges.
C. To minimize errors caused by noise at the CS input, the internal circuitry waits for three System Clock cycles (or less) after
a chip-select falling edge is detected before responding to control ,input signals. Therefore, no attempt should be made to
clock-in address data until the minimum chip-select setup time has elapsed.
2-198
TEXAS . .
INSTRUMENTS
TLC1540M, TLC15401, TLC1541 M, TLC15411
LinCMOSTM 1081T ANALOGTODIGITAL PERIPHERALS
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6.5 V
Input voltage range (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to Vce + 0.3 V
Output voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to Vce + 0.3 V
Peak input current range (any input) ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10 mA
Peak total input current (all inputs) ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30 mA
Ell
...
t/)
Operating free-air temperature range: TLC 1 5401, TLC 1 5411 . . . . . . . . . . . . . . . . .. - 40C to 85 C 'S
TLC1540M, TLC1541M ............... -55C to 125C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
...
(.)
Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C

U
c
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: N package .......... 260C o
'';:;
NOTE 1: All voltage values are with respect to digital ground with REF - and GND wired together (unless otherwise noted). 'Ci)
'S
recommended operating conditions C'
(.)
TLC1540, TLC1541
UNIT
Supply voltage, VCC
MIN
4.75
NOM
5
MAX
5.5 V
... CO
CO
Positive reference voltage, VREF + (see Note 2) 2.5 VCC VCC+O.1 V C
Negative reference voltage, VREF _ (see Note 2) -0.1 0 2.5 V
Differential reference voltage, VREF + - VREF - (see Note 2) 1 VCC VCC+ O. 2 V
Analog input voltage (see Note 2) 0 VCC V
High-level control input voltage, VIH 2 V
Low-level control input voltage, VIL 0.8 V
Setup time, address bits before I/O CLKt, tsu(A) 400 ns
Hold time, address bits after I/O CLKi, th(A) 0 ns
System
Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3) 3 clock
cycles
System
CS high during conversion, twH(CS) 44 clock
cycles
Input/Output clock frequency, fCLK(I!O) 0 1.1 MHz
System clock frequency, fCLK(SYS) fCLK(I/O) 2.1 MHz
System clock high, twH(SYS) 210 ns
System clock low, twL(SYS) 190 ns
Input/Output clock high, twH(I/O) 404 ns
Input/Output clock low, twL(I/O) 404 ns
fCLK(SYS) :s 1048 kHz 30
System ns
Clock transition time fCLK(SYS) > 1048 kHz 20
(see Note 4) fCLK(I/O) :s 525 kHz 100.
I/O ns
fCLK(I/O) > 525 kHz 40
Operating free-air TLC1540M, TLC1541M -55 125
DC
temperature, T A TLC1540l, TLC15411 -40 85
NOTES: 2. Analog input voltages greater than that applied to REF + convert as all "1"s (11111111). while input voltages less than that
applied to REF - convert as all "O"s (00000000). For proper operation, REF + voltage must be at least 1 volt higher tnan
REF - voltage. Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 volts.
3. To minimize errors caused by noise at the chip select input, the internal circuitry waits for three System Clock cycles (or less)
after a chip select falling edge is detected before responding to control input signals. Therefore, no attempt should be made
to clock-in an address until the minimum chip select setup time has elapsed.
the vicinity of normal room temperature, the devices function with input clock transition time as slow as 2 microseconds
for remote data acquisition applications where the sensor and the A/D converter are placed several feet away from the controlling
microprocessor.
TEXAS ~ 2-199
INSTRUMENTS
TLC1540M, TLC15401, TLC1541M, TLC154H. PRODUCT
LinCMOS 1OBIT ANALOGTODIGITAL PERIPHERALS PREVIEW
electrical characteristics over recommended operating temperature range, VCC ... VREF +
4.75 V to 5.5 V (unless otherwise noted), fCLKU/O) - 1.1 MHz, fCLK(SYS) - ?1 MHz
II
c
Cl
VOH
VOL
loz
PARAMETER
High-level output voltage (pin 16)
Off-state (high-impedance state)
Vee
TEST CONDITIONS
= 4.75
Vee = 4.75
Vo = Vee,
V,
V,
10H
10L
= 360 p.A
= 3.2 mA
es at Vee
MIN
2.4
Typt MAX
0.4
10
UNIT
V
V
p.A
r+ output current
Cl Vo = 0, es at Vee -10
>
n
IIH
IlL
High-level input current
VI = Vee
VI = 0
0.005
-0.005
2.5
-2.5
p.A
p.A
.c
c ICC Operating supply current es at 0 V 1.2 2.5 mA
(ii' Selected channel at Vee,
;+. 0.4 1
o::l Selected channel leakage current
/lA
-0.4 -1
Unselected channel at Vee
o
::::;. ICC + IREF Supply and reference current VREF+ = Vee, es at 0 V 1.3 3 mA
n Analog inputs
c ei Input capacitance I 7 55
pF
;+. I
Control inputs 5 15
en
V CC ... VREF + ... 4.75 V to 5. 5 V, fCLKU/O) ... 1.1 MHz, fCLK(SYS) ... 2.1 MHz
TLC1540
MIN MAX
Zero error See Notes 2 and 6 0.5 LSB
Full-scale error See Notes 2 and 6 0.5 LSB
0111110100 1000001100
Self-test output code Input A 11 address = 1011 (See Note 8)
(500) (524)
tconv Conversion time See Operating Sequence 21 p'S
Total access and

See Operating Sequence 31 P.s
conversion time
I/O
tacq See Operating Sequence 6 clock
(sample cycle)
cycles
Time output data
tv remains valid after 10 ns
I/O clock~
Delay time, I/O clock~
"'C td 400 ns
:c to data output valid
See Parameter
o ten Output enable time
Measurement
150 ns
c tdis Output disable time

Information
150 ns
c tr(bus) Data bus rise time

tf(bus) Data bus fall time
300 ns
ns
o ae.
300
"""'i t All typical values are at Vee = 5 V, TA = 25

NOTES: 2. Analog input voltages greater than that applied to REF + convert to all "1 "s (11111111). while input voltages less than that
"'C applied to REF - convert to all"O"s (00000000). For proper operation, REF + voltage must be at least 1 volt higher than
:c REF - voltage. Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 volts.
m 5. Linearity error is the maximum deviation from the best straight line through the AID transfer characteristics.
:5
m
7. Total unadjusted error comprises linearity, zero, and full-scale errors.
~
and is used for test purposes.
PRODUCT PREVIEW documents contain information

2-200
development. Characteristic dati ani! other
specifications are design goals. TexIs Instruments
TEXAS
INSTRUMENTS
ADVANCE TLC1540M. TLC15401. TLC1541M. TLC15411
INFORMATION LinCMOSTM 10BIT ANALOGTODlGITAL PERIPHERALS
electrical characteristics over recommended operating temperature range, VCC - VREF +

4.75 V to 5.5 V (unless otherwise noted), fCLK(I/O) = 1.1 MHz, fCLK(SYS) = 2.1 MHz
VOH High-level output voltage (pin 16) Vee = 4.75 V. 10H = 360 JlA 2.4 V
Low-level output voltage = = 3.2 mA
VOL
Off-state (high-impedance state)
Vee
Vo = Vee.
4.75 V. 10L
es at Vee
0.4
10
V
...
U)
10Z
IIH
IlL
output current
Vo = o.
VI = Vee
VI = 0
es at Vee
0.005
-0.005
-10
2.5
-2.5
JlA
JlA
JlA
.
'S
U
CJ
ICC Operating supply current es at 0 V 1.2 2.5 mA

t:
o
Selected channel at Vee. '';:;
0.4 1
Unselected channel at 0 V "Cii
Selected channel leakage current
Selected channel at 0 V.
",A "S
-0.4 -1 C"
Un selected channel at Vee CJ
ICC + IREF Supply and reference current VREF+ = Vee. es at 0 V 1.3 3 mA
ei Input capacitance
I
Analog inputs
I
Control inputs
7
5
55
15
pF ...
CO
CO
C
VCC = VREF+ = 4.75Vto5.5V,fCLK(I/O) = 1.1 MHz,fCLK(SYS) = 2.1 MHz
TLC1541
MIN MAX
Linearity error See Note 5 1 LSB
Zero error See Notes 2 and 6 1 LSB
Full-scale error See Notes 2 and 6 1 LSB
Total unadjusted error See Note 7 1 LSB
0111110100 1000001100
Self-test output code Input A 11 address = 1011 (See Note 8)
(500) (524)
tconv Conversion time See Operating Sequence 21 JlS
Total access and
See Operating Sequence 31 Jls
conversion time
I/O
tacq See Operating Sequence 6 clock
(sample cycle)
cycles
2
tv
Time output data
remains valid after 10 ns
o
I/O clock! i=
td
Delay time. I/O clock!
400 ns
<t
See Parameter ~
ten Output enable time
Measurement
150 ns
a:
tdis Output disable time
tr(bus) Data bus rise time
Information
150
300
ns
ns
oLL
tf(bus) Data bus fall time 300 ns
2
t All typical values are ~t Vee = 5 V. T A = 25C.
NOTES: 2. Analog input voltages greater than that applied to REF + convert to all "1"s (11111111). while input voltages less than that w
applied to REF - convert to all"O"s (00000000). For proper operation. REF + voltage must be at least 1 volt higher than CJ
REF - voltage. Also~ the total unadjusted error may increase as this differential reference voltage falls below 4.75 volts.
5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
2
6. Zero erro'r is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference <t
c>
7. Total unadjusted error comprises linearity. zero. and full-scale errors.
and is used for test purposes. <t
ADVANCE INFORMATION documents contain
information on new ~roducts in the samplinp or
~reproduction phase of development. Characteristic
~ata and other specifications are subject to change TEXAS . . 2-201
POST OFFICE flOX 655012 " DALLAS. TEXAS 75265
TLC1540M. TLC15401. TLC1541 M. TLC15411 ADVANCE
LinCMOSTM 1081T ANALOGTODlGlTAL PERIPHERALS INFORMATION
lEI 'A:.
J
n
c
D)
~
D) OUTPUT
UNDER TEST
TEST
POINT
OUTPUT
UNDER TEST 1 I TEST POINT
OUTPUT
UNDERTEST+
VI:': EST
POINT
CL 3kn CL
C')
.c
c
CL
(SEE NOTE AI l' (SEE NOTE AI~
(SEE NOTE BI
(SEE NOTE AI ~
(SEE NOTE BI
Ci)'
;:;:
0'
::::I
n td. t r AN D tf tpZH AND tpHZ tpZL AND tpLZ
::;'
C')
c
;:;:
en
\\ t5~
I
_____ VCC
ov
I
SYSTEM I
CLOCK I
I
-+I tpZL I+- ~ tpLZ j4-
OUTPUT II : il/ VCC
WAVEFORM 1
(SEE NOTE CI
(SEE NOTE BI
: \50"10
1 """---+-1--'
I .f.10%
-----OV
--+I tpZH I+-- ~ tPHZ l+-
I I
W~~::~~M2 V5rrr. "t 9 oi" -
. (SEE NOTE CI
______________
T; ~
n-VoOvH

c VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES
<
I/O
:2 CLOCK
n \- -
I
- - -O.8V
OUTPUT
m
-
:2
"'T1
DATA
J+-- td--:+t
Xl ---------- 2.4V
o:ll OUTPUT _ _ _ _ _ _--J - - - - - - - - -- 0.8 V

S RISE AND FALL TIMES
NOTES: A. CL = 50 pF
::! B. ten = tpZH or tpZL. tdis = tpHZ or tpLZ.
o C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
:2
2-202 TEXAS -I.!}

INSTRUMENTS
ADVANCE TLC154DM, TLC15401, TLC1541 M, TLC15411
INFORMATION LinCMOSTM 1D-BIT ANALOG-TO-DIGITAL PERIPHERALS
The TLC1540 and TLC1541 are both complete data acquisition systems on single chips. Each includes
such functions as sample-and-hold, 10-bit A/D converter, data and control registers, and control logic.
For flexibility and access speed, there are four control inputs; Chip Select (CS), Address Input,
I/O Clock, and System Clock. These control inputs and a TTL-compatible three-state output are intended
for serial communications with a microprocessor or microcomputer. The TLC1540 and TLC1541 can
Ell
complete conversions in a maximum of 21 microseconds, while complete input-conversion-output cycles
can be repeated at a maximum of 31 microseconds.
The System and I/O Clocks are normally used independently and do not require any special speed or phase
relationships between them. This independence simplifies the hardware and software control tasks for
the device. Once a clock signal within the specification range is applied to the System Clock input, the
control hardware and software need only be concerned with addressing the desired analog channel, reading
the previous conversion result, and starting the conversion by using the I/O Clock. The System Clock will
with this task.
When CS is high, the Data Output pin is in a three-state condition and the Address Input and I/O Clock
pins are disabled. This feature allows each of these pins, vvith the exception of the CS pin, to share a
control logic point with their counterpart pins on additional A/D devices when additional TLC 1540/1541
devices are used. In this way, the above feature serves to minimize the required control logic pins when
using mUltiple A/D devices.
for two rising edges and then a falling edge of the System Clock after a low CS transition, before the
low transition is recognized. This technique is used to protect the device against nois~ when the
device is used in a noisy environment. The MSB of the previous conversion result will automatically
appear on the Data Out pin.
2. A new positive-logic multiplexer address is shifted in on the first four rising edges of the I/O Clock.
The MSB of the address is shifted in first. The negative edges of these four I/O Clock pulses shift
out the second, third, fourth, and fifth most significant bits of the previous conversion result. The
on-chip sample-and-hold begins sampling the newly addressed analog input after the fourth falling
edge. The sampling operation basically involves the charging of internal capacitors to the level
of the analog input voltage.
2:
3. Five clock cycles are then applied to the I/O pin and the sixth, seventh, eighth, ninth, and tenth
conversion bits are shifted out on the negative edges of these clock cycles. o
4. The final tenth clock cycle is applied to the I/O Clock pin. The falling edge of this clock cycle i=
. completes the analog sampling process and initiates the hold function. Conversion is then performed <C
during the next 44 System Clock cycles. After this final I/O Clock cycle, CS must go high or the
I/O Clock must remain low for at least 44 System Clock cycles to allow for the conversion function.
~
a:
CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple
conversion, special care must be exercised to prevent noise glitches on the I/O Clock line. If glitches occur
oLL
synchronization. Also, if CS is taken high, it must remain high until the end of the conversion. Otherwise,
-2:w
(.)
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps
1 through 4 before the 44 System Clock cycles occur. Such action will yield the conversion result of the
2:
previous conversion and not the ongoing conversion. <C
>
c
<C
TEXAS . . 2-203
INSTRUMENTS
TLC1540M, TLC154D1, TLC1541 M, TLC15411 ADVANCE
LinCMOSTM 10BIT ANALOGTODlGITAL PERIPHERALS INFORMATION
It is possible to connect the System and I/O Clock pins together in special situations in which controlling
II
C
circuitry points must be minimized. In this case, the following special points must be considered in addition
to the requirements of the normal control sequence previously described.
1. When CS is recognized by the device to be at a low level, the common clock signal is used as
...m
m an I/O Clock. When CS is recognized by the device to be at a high level, the common clock signal
is used to drive the "conversion crunching" circuitry.

(')
2. The device will recognize a CS low transition only when the CS input changes and subsequently
the System Clock pin receives two positive edges and then a negative edge. For this reason, after
.c a CS negative edge, the first two clock cycles will not shift in the address because a low CS must
c be recognized before the I/O Clock can shift in an analog channel address. Also, upon shifting in
C;;O
;:;: the address, CS must be raised after the eighth I/O Clock that has been recognized by the device,
c)" so that a CS low level will be recognized upon the lowering of the tenth I/O Clock signal that is
~
recognized, by the device. Otherwise, additional common clock cycles will be recognized as I/O
o
::;0
Clock pulses and will shift in an erroneous address.
(')
c For certain applications, such as strobing applications, it is necessary to start conversion at a specific point
;;'
U) in time. This device will accommodate these applications. Although the on-chip sample-and-hold begins
sampling upon the negative edge of the fourth I/O Clock cycle, the hold function is not initiated until the
negative edge of the tenth I/O Clock cycle. Thus, the control circuitry can leave the I/O Clock signal in
its high state during the tenth I/O Clock cycle until the moment at which the analog signal must be converted.
The TLC1540/TLC1541 will continue sampling the analog input until the tenth falling edge of the I/O Clock.
The control circuitry or software will then immediately lower the I/O Clock signal and hold the analog signal
at the desired point in time and start conversion.
c
<
z
(")
m
-Z
i1
o
::c
s:
::!
o
z
2-204 TEXAS . .
INSTRUMENTS
TLC4016M, TLC40161
SILlCONGATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
02922. JANUARY 1986
High Degree of Linearity TLC4016M .. J OR N PACKAGE

TLC40161 .. D OR N PACKAGE
High On-Off Output Voltage Ratio (TOP VIEWI
Low Crosstalk Between Switches 1A VCC

o Low On-State Impedance of 50 Ohms Typ 18 1C
at VCC = 9 V 28
2A
4C
4A S
...en
Individual Switch Controls 2C 48 ...
CJ
Extremely Low Input Current 3C
GND
38
3A
U
c
description 0
'';:;
logic symbol t .U;
The TLC4016 is a silicon-gate CMOS quadruple
analog switch integrated circuit designed to 1C
(131
X1 n S
(\ (21 C"
handle both analog and digital signals. Each (11 1 1B
1A
~
CJ
switch permits signals with amplitudes up to
2C
(51
n
1
n
12 volts peak to be transmitted in either
direction.
2A
3C
(41
(61
n
(31
2B
...
CO
CO
Each switch section has its own enable input 3A
(81 n (91
3B C
control. A high-level voltage applied to this (121 (\
4C
control terminal turns on the associated switch 4A
(111 n (101
4B
section.
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
Applications include signal gating, chopping, lEe Publication 617-12.
modulation or demodulation (modem), and signal
multiplexing for analog-to-digital and digital-to-
analog conversion systems.
The TLC4016M is characterized for operation
from - 55C to 125C, and the TLC40161 is
characterized from - 40C to 85 C.
logic diagram (positive logic)

A
VCC
B
C
specifications per the terms of Texas Instruments TEXAS . " 2-205
~~~~~:~~i~a{::1~1~ ~!:~~~ti:r :1~o::~:~:t::S~s not INSTRUMENTS
TLC4016M, TLC40161
Supply voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 15 V
Control-input diode current (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20 mA
1/0 port diode current (VI < 0 or VIIO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20 mA
On-state switch current (VI/O = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25 mA
c Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 50 mA
...
Q)
Q)
Continuous total dissipation at (or below) 25C free-air temperature (see Note 2):
D package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 950 mW
(')
J package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
.c N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 875 mW
c Operating free-air temperature, T A: TLC4016M ................. . . . . . . . .. - 55C to 125C
(ii'
;:::;"
TLC40161 ............................ -40C to 85C
0' Storage temperature range ......................................... - 65C to 150C
:s Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D and N packages ....... 260C
(") Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . .. 300C
::;'
(') NOTES: 1. All voltages are with respect to ground unless otherwise specified.
c 2. For operation above 25e free-air temperature, see Dissipation Derating Table.
;:::;"
o
DISSIPATION DERATING TABLE
Maximum Power Dissipation Derating

Package
25 DC 85 DC 125 DC Factor
0 950 mW 494 mW 7.6 mW/oC
J 1025 mW 533 mW 205 mW 8.2 mW/oC
N 875 mW 455 mW 175 mW 7.0 mW/oC

MIN NOM MAX UNIT
Supply voltage, Vee 2t 5 12 V
I/O port voltage, VI/O 0 Vee V
Vee = 2 V 1.5 Vee
Vee = 4.5 V 3.15 Vee
High-level input voltage, VIH V
Vee = 9 V 6.3 Vee
Vee = 12V 8.4 Vee
Vee = 2 V 0 0.3
Vee = 4.5 V 0 0.9
Low-level input voltage, VIL V
Vee = 9 V 0 1.8
Vee=12V 0 2.4
Vee = 2 V 1000
Input rise time, tr Vee = 4.5 V 500 ns
Vee = 9 V 400
Vee = 2 V 1000
Input fall time, tf Vee = 4.5 V 500 ns
Vee = 9 V 400
TLe4016M -55 125
Operating free-air temperature, T A De
TLe40161 -40 85
tWith supply voltages at or near 2 volts, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital
signals be transmitted at these low supply voltages.
2-206 TEXAS . .
INSTRUMENTS
TLC4016M, TLC40161
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted).
TLC4016M TLC40161
PARAMETER TEST CONDITIONS VCC UNIT
rSon
On-state switch
resistance
IS = 1 rnA.
VA = 0 to Vee.
See Figure 1
IS = 1 rnA.
4.5 V
9V
12 V
2V
100
120
50
30
220
120
100
240
100
50
30
120
200
105
85
215 f!
-...
oS
rn
(,)
VA = 0 or Vec.
4.5 V 50 120 50 100 U
See Figure 1
9V 35 80 35 75 c
12 V 20 70 20 60 o
0';:;
On-state switch VA = 0 to Vcc.
4.5 V 10 20 10 20 0U)
resistance matching See Figure 1
9V 5 15 5 15 f! oS
12 V 5 15 5 15 C"
(,)
VI = 0 or Vee 2V 1 1

II
ISoff
Control input current
Off-state switch
leakage current
VI = 0 or Vee.
TA = 25C
VS.= Vee,
See Figure 2
to
6V
5.5 V
9V
12 V
10
15
0.1
600
800
20 1000
10
15
0.1
600
800
20 1000
Jl-A
nA
-
C
CQ
CQ
5.5 V 10 150 10 150

On-state switch VA = 0 or Vec.
ISon 9V 15 200 15 200 nA
leakage current . See Figure 3
12 V 20 300 20 300
5.5 V 2 40 2 20
VI = 0 or Vee.
lee Supply current 9V 8 160 8 80 Jl-A
10 = 0
12 V 16 320 16 160
A or B 2 V to 15 15
C 12 V 5 10 5 10
Feedthrough 2 V to
Cf A to B VI = 0 5 5 pF
capacitance 12 V
TEXAS . . 2-207
INSTRUMENlS
POST OFFICE BOll 655Q12 CAllAS. TEXAS 75265
TLC4016M, TLC40161
switching characteristics over recommended operating freeair temperature range, CL == 50 pF (unless

otherwise noted) ,
C"
Dr
r+
m
l>
()
.c
tpd
ton
PARAMETER
Propagation delay time.

A to B or B to A
Switch turn~on time

TEST CONDITIONS
See Figure 4
RL = 1 kn.
VCC
2V
4.5 V
9V
12 V
2V
4.5 V
MIN
"
TLC4016M
Tvpt MAX
25
5
4
3
32
8
75
15
14
13
150
30
TLC40161
MIN TVPt
25
5
4
32
8
3
MAX
62
13
12
11
125
25
UNIT
ns
ns
c See Figures 5 and 6 9V 6 18 6 15
iii" 12 V 5 15 5 13
::;."
2V 45 252 45 210
S"
::::s RL = 1 kn. 4.5 V 15 54 15 45
toff Switch turn-off time ns
o:;" See Figures 5 and 6 9V
12 V
10
8
48
45
10
8
40
38
()
Switch cutoff frequency 4.5 V 100 100
c fco MHz
::;." (channel loss = 3 dB) 9V 120 120
en Control feedthrough voltage
VOCF(PP) See Figure 7 4.5 V 180 180 mV
to any switch. peak to peak
Frequency at which crosstalk
attenuation between any two See Figure 8 ' 4.5 V 1 1 MHz
switches equals 50 dB

VCC
VI - VCC C X1
TEST 1 B
SWITCH
+--IS
FIGURE 1. ONSTATE RESISTANCE TEST CIRCUIT
VCC
TEST B
SWITCH
Vs - VA - VB
CONDITION 1: VA - O. VB - VCC
CONDITION 2: VA - VCC. VB - 0
FIGURE 2. OFF-STATE SWITCH LEAKAGE CURRENT TEST CIRCUIT
2-208 TEXAS . .
INSTRUMENTS
POST oFFice BOX 655012 DALLAS, TeXAS 75265
TLC40 16M, TLC40161

VCC
VI - VIH
C r - - - -.....- - - ,
X1
TEST
SWITCH
B
II ....
f/)
'S
...CJ
(3
c
o
'';:;
FIGURE 3. ONSTATE SWITCH lEAKAGE CURRENT TEST CIRCUIT 'en
'S
VCC C"
CJ
C X1

VI - VIH
TEST B OR A
Vo
....COCO
SWITCH
VI A OR B 1 C
~50PF
TEST CIRCUIT
VI
A OR B
_ _ _ _ _....J
;0%
I
I
I4-+1-tpd
I
I
B~~A ________ ....J~O%

VOLTAGE WAVEFORMS
FIGURE 4. PROPAGATION DELAY TIME. SIGNAL INPUT TO SIGNAL OUTPUT
TEXAS -II} 2-209

INSTRUMENTS
TLC4016M. TLC40161
lEI
VCC
1 kll
c
Q) B
r+ I - - - i . -........-VO
Q)

(") J
50PF
.c
c TEST CIRCUIT
(ii'
;:::;,.'
0'
:s
n::;'
f,.OO-yO--.....;..------------"""'\Zo~ ------
--Vee
(")
c ---- I I OV
;:::;,.' 14 .1 ton - tpZL toft - tpLz 14 .1
I/"
(I) I I
Vo------~~o~ 'Vee
\""_______________---I}'o~ ___ -VOL

VOLTAGE WAVEFORMS
FIGURE 5, SWITCHING TIME (tPZL, tpLZ), CONTROL TO SIGNAL OUTPUT
2-210 TEXAS"
INSTRUMENTS
TLC4016M, TLC40161
SILlCONGATE CMOS OUADRUPLE BILATERAL ANALOG SWITCH

Vcc
B
II en
+-'
A
1--.....----tlI--VO
50 pF 1 kf!
..
'S
U
(J
c:
o
'';:
TEST CIRCUIT
'en
'S
C"
Vcc
------Jt~ __
(J
c3:
CO
+-'
CO
VI -0 V C
I
~ton = tpZH
I
I VOH
VO _ _ _ _ _ _ J~'-l.!O _ _ _ _ _ == 0 V
VOLTAGE WAVEFORMS
FIGURE 6. SWITCHING TIME (tpZH. tpHZI. CONTROL TO SIGNAL OUTPUT
TEXAS ~ 2-211
INSTRUMENTS
TLC4016M. TLC40161

VCC
III
c
Q)
VI X1 TEST
SWITCH
(1 OF 4)
Vo
r+
Q)
150 PF
600 n

(') ':' ':'
.c
c TEST CIRCUIT
(ii'
;:;.'
0' jf90% 90%~-_--- - -----V
~
n:::;'
(')
c
VI __________ ~10~~~Oi,' ! ! \~1..;.OO.;.;.YO ___________ 0 V
I4---M- tr ~tf
;:;.'
rn
,fC------j
Vo--------t _____________ n ____ ~]PPI
VOLTAGE WAVEFORMS
FIGURE 7. CONTROL FEEDTHROUGH VOLTAGE
VCC
X1 TEST
SWITCH V01
(1 OF 4)
X2 TEST ':'
SWITCH 2 V02
(1 OF 4)
15O P'
2
600 n
':' "::' ':'
NOTE: ADJUST f for aX _ V02 - 50 dB.

VOl
FIGURE 8. CROSSTALK BETWEEN ANY TWO SWITCHES, TEST CIRCUIT
2-212 TEXAS -1./1

INSTRUMENTS
TLC4066M, TLC40661
02922. JANUARY 1986
High Degree of Linearity TLC4066M ... J OR N PACKAGE

TLC40661 .. 0 OR N PACKAGE
High OnOff Output Voltage Ratio
II...
(TOP VIEW)
Low Crosstalk Between Switches VCC
Low OnState Impedance ... Typically lC
4C U)
30 Ohms at VCC ... 12 V

Individual Switch Controls
Extremely Low Input Current
2C
3C
4A
48
38
.
"S
C3
(J
GND-. ...... 3A
Functionally Interchangeable with National c
0
Semiconductor MM54/74HC4066, Motorola "+i
logic symbol t
MC54/74HC4066, and RCA CD4066A "w
(13)
"S
description 1C
(1) n
X1
1
n (2)
18
C"
(J
1A 1
The TLC4066 is a silicon-gate CMOS quadruple <C
(5)
n
analog switch integrated circuit designed to
handle both analog and digital signals. Each
2C
2A
(4)
(6)
n (3)
28 ...
C'O
C'O
switch permits signals with amplitudes up to
3C
n n (9)
38
C
(8)
3A
12 volts peak to be transmitted in either (12)
4C (l (10)
direction. (11 ) n 48
4A
Each switch section has its own enable input
control. A high-level voltage applied to this t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
control terminal turns on the associated switch lEe Publication 617-12.
section.
Applications include signal gating, chopping,
modulation or demodulation (modem), and signal
multiplexing for analog-to-digital and digital-to-
analog conversion systems.
The TLC4066M is characterized for operation
from - 55C to 125C. The TLC40661 is
characterized from -40C to 85C.

A
specifications per the terms of Texas Instruments TEXAS -I./} 2-213
~~~~~:~~i~ai~:1~18 ~!=~:~ti~r fJlo::~:~:t:r~~s not INSTRUMENTS
TLC4066M. TLC40661
SILICON-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
Supply voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - O. 5 V to 1 5 V
II
c
Control-input diode current (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20 mA
1/0 port diode current (VI < 0 or Vila > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20 mA
On-state switch current (Vila = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 50 mA
...
D)
D)
Continuous total dissipation at (or below) 25 D C free-air temperature (see Note 2):
D package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 950 mW
~ J package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. 1025 mW
(')
.c N package .................... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 875 mW
c Operating free-air temperature, T A: TLC4066M .......................... - 55 DC to 125 DC
Cij"
TLC40661 ............................ - 40 DC to 85 DC
=*" Storage temperature range ......................................... - 65 DC to 150 DC
0"
:::l Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D and N packages. . . . . .. 260 DC
o Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package. . . . . . . . . . . .. 300 DC
:::;"
(') NOTES: 1. All voltages are with respect to ground unless otherwise specified.
c 2. For operation above 25e free-air temperature, see Dissipation Derating Table.
=*"
UI
Maximum Power Dissipation Derating

Package
25C 85C 125C Factor
D 950 mW 494 mW 7.6 mW/oe
J 1025 mW 533 mW 205 mW 8.2 mW/oe
N 875 mW 455 mW 175 mW 7.0 mW/oe

MIN NOM MAX UNIT
Supply voltage, Vee 2t 5 12 V
110 port voltage, VI/O 0 Vee V
Vee = 2 V 1.5 Vee
Vee = 4.5 V 3.15 Vee
Vee = 9 V 6.3 Vee
Vee=12V 8.4 Vee
Vee = 2 V 0 0.3
Vee = 4.5 V 0 0.9
Vee = 9 V 0 1.8
Vee=12V 0 2.4
Vee = 2 V 1000
Input rise time, tr Vee = 4.5 V 500 ns
Vee = 9 V 400
Vee = 2 V 1000
Input fall time, tf Vee = 4.5 V 500 ns
Vee = 9 V 400
TLe4066M -55 125
Operating free-air temperature, TA e
TLe40661 -40 85
tWith supply voltages at or near 2 volts, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital
signals be transmitted at these low supply voltages.
2-214 . TEXAS ~
INSTRUMENlS
POST OFFICE BOx e65012 DALLAS, TEXAS 76266
TLC4066M, TLC40661
noted)
PARAMETER TEST CONDITIONS
IS = 1 rnA.
VA = 0 to Vee.
VCC
4.5 V
9V
MIN
TLC4066M
Typt
100
MAX
50
220
110
TLC40661
MIN Typt
100
50
MAX
200
105
UNIT
II....tn
See Figure 1 12 V 30 90 30 S5 -5
rSon
On-state switch
resistance IS = 1 rnA.
2V 120 240 120 215 fl ...CJ
VA=OorVee.
4.5 V 50 120
SO
50
35
100
75
C3
9V 35
See Figure 1 c
12 V 20 70 20 60 o
4.5 V 10 20 10 20 '';::
On-state switch VA = 0 to Vee.
9V 5 15 5 15 fl
'en
resistance matching See Figure 1
12 V 5 15 5 15
'5
C"
2V CJ
II Control input current VI = 0 or Vee or 1 1 /lA <t
6V
5.5 V 10 600 10 600
....caca
ISoff
Off-state switch Vs = Vee.
9V 15 SOO 15 SOO nA C
leakage current See Figure 2
12 V 20 1000 20 1000
5.5 V 10 150 10 150
On-state switch VA = 0 or Vee.
ISon 9V 15 200 15 200 nA
leakage current See Figure 3
12 V 20 300 20 300
5.5 V 2 40 2 20
. VI = 0 or Vee.
ICC Supply current 9V S 160 8 SO /lA
10 = 0
12 V 16 320 16 160
A or B 2 V to 15 15
e 12 V 5 10 5 10
Feedthrough 2 V to
ef A to B VI = 0 5 5 pF
capacitance 12 V
t All typical values are at T A = 25 DC.
TEXAS
INSTRUMENTS
'1.!1 2-215
TLC4066M, TLC40661
switching characteristics over recommended operating free-air temperature range, CL == 50 pF (unless

otherwise noted) .
III
c
D) tpd
PARAMETER

TEST CONDITIONS
See Figure 4
VCC
2V
4.5 V
MIN
TLC4066M
Typt
25
5
MAX
75
15
TLC40661
MIN Typt
15
5
MAX
30
13
UNIT
ns
A to B or B to A 9V 4 12 4 10
~
D) 12 V 3 13 3 11

(') RL = 1 kfl.
2V
4.5 V
32
8
150
30
32
8
125
25
.c ton Switch turn-on time ns
c See Figures 5 and 6 9V 6 18 6 15
Cii" 12 V 5 15 5 13
;:;.' 2V 45 252 45 210
S' RL = 1 kfl. 4.5 V 15 54 15 45
::s toff Switch turn-off time ns
See Figures 5 and 6 9V 10 48 10 40
o 12 V 8 45 8 38
:;'
(') Switch cutoff frequency 4.5 V 100 100
C fco MHz
;:;.' (channel loss = 3 d8) 9V 120 120
(I) Control feedthrough voltage
VOCF(PP) See Figure 7 4.5 V 180 180 mV
to any switch. peak to peak
Frequency at which crosstalk
attenuation between any two See Figure 8 4.5 V 1 1 MHz
switches equals 50 dB
t All typical values are at T A = 25 ac.

VCC
VI - VCC
TEST
SWITCH
A 1
+--IS
FIGURE 1. ON-STATE RESISTANCE TEST CIRCUIT
Vcc
VI - 0
TEST B
SWITCH
Vs - VA - VB
CONDITION 1: VA - O. VB - VCC
CONDITION 2: VA - Vcc. VB - 0
FIGURE 2. OFF-STATE SWITCH LEAKAGE CURRENT TEST CIRCUIT
2-216 TEXAS . .
INSTRUMENTS
TLC4066M, TLC40661

VCC
C
X1
TEST
SWITCH
1 B
fI
... rJ)
S
...CJ
C3
s:::::
o
'';::;
FIGURE 3. ONSTATE SWITCH LEAKAGE CURRENT TEST CIRCUIT
'Cii
S
VCC C"
CJ
<C
C X1
TEST
SWITCH
B OR A
Vo ...
CO
CO
VI A OR B C
*,50 PF
TEST CIRCUIT
A ~~ B_ _ _ _ _ ..,/o%
I
I
~tpd
I
I
B~~A _______ ~~O%

VOLTAGE WAVEFORMS
FIGURE 4. PROPAGATION DELAY TIME. SIGNAL INPUT TO SIGNAL OUTPUT
TEXAS -II} 2-217

INSTRUMENTS
TLC4066M, TLC40661

VCC
II
C
VI C X1
TEST
~B~......_
1 kfl
......_VO
....
Dl SWITCH
Dl
A (1 OF 4)
l' 50 pF
(')
.c
c TEST CIRCUIT
(ii'
;:;:
0'
:::J /0% ~o~ - - - - - - - -Vee
(")
::;'
(') ---.I I I OV
c 1<1114f----I~~I-ton - tpZL ~I
;:;: toff - tpLZ 14
(I)
VO-------'~O%
I
!/' I
-Vee
\"'._______________~}O:!! __ --VOL
VOLTAGE WAVEFORMS
FIGURE 5. SWITCHING TIME (tPZL, tPLZI. CONTROL TO SIGNAL OUTPUT
2-218 TEXAS . .
INSTRUMENTS
TLC4066M, TLC40661

VCC
C X1
TEST
fI
... en
SWITCH S
A (1 OF 4)
50 pF 1 kfl
...CJ
C3
c
o
TEST CIRCUIT +=
.c;;
S
C"
-----t: __
VCC ------,. - - - - ---VCC CJ

\0% OV ... CO
CO
VI -0 V C
I J
~ton - tpZH toff - tpHz--k-----+I
J
I VOH -----l;!i0%-- I
-VOH
Vo _ _ _ _ _ _ JLL-
10 %_ _ _ _ _ == OV
. . '---==OV
J
VOLTAGE WAVEFORMS
FIGURE 6. SWITCHING TIME (tPZH, tPHZ), CONTROL TO SIGNAL OUTPUT
TEXAS . . 2-219
INSTRUMENTS
TLC4066M, TLC40661

Vec
II
c
X1 TEST
SWITCH t--......-~t--VO
...
'Ql
(1 OF 4)
Ql
l>
(')
J:l
C TEST CIRCUIT
-r 50PF 600 n
(ii'
;::::j:
0' 90%f\-'- - - - -----V
::s V, ;f90%
o
~' __________~10~o/c~O~ i
r=------j
(')
c 'I \ I 10% OV
;::::j: I4--*"tr I+---M- tf
(I)
Vo----------t ____________ ~]PP' n _____
VOLTAGE WAVEFORMS
FIGURE 7. CONTROL FEEDTHROUGH VOLTAGE
VCC
Xl TEST
SWITCH V01
(1 OF 4)
VI
600 n X2
-=
V02
600 n
-= -= -= -=
V02
NOTE: ADJUST f for aX - - 50 dB.
V01
FIGURE 8. CROSSTALK BETWEEN ANY TWO SWITCHES, TEST CIRCUIT
2-220 TEXAS . .
INSTRUMENTS
PRODUCT TLC7135
PREVIEW Advanced LinCMOSTM 4 1/2DlGIT PRECISION
02851, DECEMBER 1986
ADVANCED LinCMOSTM Technology N

DUAL-IN-LiNE PACKAGE
II
Zero Reading for O-V Input (TOP VIEW)
Precision Null Detection with True Polarity UNDER-RANGE
at Zero OVER-RANGE
1-pA Typical Input Current ANlG COMMON STROBE ....en
INT OUT 4 RUN/HOLD 'S
True Differential Input AUTO ZERO DGTl GND ...
(J
Multiplexed Binary-Coded-Decimal Output BUFF OUT POLARITY U

Low Rollover Error: 1 Count Maximum
Cref- ClK c:
Cref+ BUSY o
'';:;
IN- D1 (lSD)
Control Signals Allow Interfacing with
IN+ D2
'en
UARTs or Microprocessors 'S
VCC+ D3 C'
Autoranging Capability with Over- and (MSD) D5 (J
Under-Range Signals (lSB) B1
D4
B8 (MSB)

TTL-Compatible Outputs B2 B4 ....COCO
Direct Replacement for Teledyne TSC7135, C
Intersi! ICL7135, Maxim ICL7135, and
Siliconix Si7135
Caution. This device has limited built-in gate protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage.
description
The TLC7135 converter is manufactured with Texas Instruments highly efficient ADVANCED LinCMOSTM
technology. This 4 1/2-digit dual-slope-integrating analog-to-digital converter is designed to provide
interfaces to both a microprocessor and a visual display. The digit-drive outputs 01 through D4 and
multiplexed binary-coded-decimal outputs, B1 through B4, provide an interface for LED or LCD
decoder/drivers as well as microprocessors.
The TLC7135 offers 50-ppm (one part in 20,000) resolution with a maximum linearity error of one count.
The zero error is less than 10 p.V and zero drift is less than 0.5 p.V/oC. Source-impedance errors are minimized
by low input current (less than 10 pA). Rollover error is limited to 1 count.
The TLC7135 BUSY, STROBE, RUN/HOLD, OVER-RANGE, and UNDER-RANGE control signals support
microprocessor-based measurement systems. The control signals also can support remote data acquisition
systems with data transfer via universal asynchronous receiver transmitters (UARTs).
~
The TLC7135 is characterized for operation from OOC to 70C. w
:>
w
a:
c..
t-
U
~
C
oa:
ADVANCED LinCMOS'" is a trademark of Texas Instruments Incorporated. c..
specifications are design goals. Texas Instruments TEXAS. 2-221
INSTRUMENlS
TLC7135 PRODUCT
Advanced LinCMOS 4 1/2DlGIT PRECISION. PREVIEW
II
c
POLARITY (23)
FROM ANALOG
SECTION
POLARITY
FLIP-FLOP
(20) 01 (LSB)}
(19)
02
(18) 03
.
DIGIT
DRIVE
...
Q)
Q) ZERO
(17) 04
(12) 05 (MSB)
OUTPUT
CROSS

(')
DETECT
.c
c CLK (22)
_ _ (25)
(ii'
R U N / H O L D - - - - - - - - t CONTROL
;:::;.' MULTIPLEXER
OVER-RANGE (27) LOGIC
0'
:::l UNDER-RANGE..:.;(2;;.;;8~)- - - 4 - - - - - 4
o STROBE~(2~6~)--.---~
:::;' 8USY..:.;(2;..;1.:..)- - . . - - - - - 4
(')
c DGTLGND~(2_4~)-----~
;:::;.'
en
(13)Bl}
(14)
B2 BINARY CODED
(15) B4 . DECIMAL OUTPUT
(16) B8
ANALOG SECTION
Cref
BUFF
r---
(8) ~f!... _ _ C!!!,- (7)
.------,
I
I AIZ
REF~
TO
~ I ~
'"tJ IN+~~~-+---~~---+-~~~ o--+-~~-----+----~
::c I
o I
c
c I AIZ
(") I
-I I
INPUT
LOW
'"tJ I
::c
m
S
m lL _________ _ iNT
IN-~-------'---------~ _______ .___ ..J
:E
2-222
INSTRUMENTS
TEXAS -1!1
post OFFIcE BOX 855012 DALLAS, TeXAS 75266
PRODUCT TLC7135
Supply voltage (Vee + with respect to Vee -) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Analog input voltage (pin 9 or pin 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Vee - to Vee +
Reference voltage range .,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Vee - to Vee +
elock input voltage range ... ;......................................... 0 V to Vee +
Operating free-air temperature range ....... ~ ............................ " ooe to 70 0 e
fI
... en
Storage temperature range ......................................... - 65 e to 150 0 e
S
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260 0 e ...
(.)
U
recommended operating conditions c
o
MIN NOM MAX UNIT "';:;
"C;;
Supply voltage, Vcc + 4 5 6 V
Supply voltage; VCC- -3 -5 -8 V
"S
C"
Reference voltage, V ref 1 V (.)
High-level input voltage, ClK, RUN/Halo, VIH 2.8 V cd:

low-level input voltage, ClK, RUN/HOLD, VIL
Differential input voltage, VID
0.8
VCC+ -0.5
V
V
... CO
CO
VCC- +1 C
Maximum operating frequency, fclock (see Note 1) 1.2 2 MHz
Operating free-air temperature range, T A 0 70 C
NOTE 1: Clock frequency range extends down to 0 Hz.
electrical characteristics, Vee + = 5 V, Vee- -5 V, Vref = 1 V, fclock = 120 kHz, TA = 25e

High-level L 01,05,B1,B2,B4,B8 10 = -1 rnA 2.4 5
V
VOH
output voltage lather outputs 10 = -10 pA 4.9 5
VOL Low-level output voltage 10 = 1.6 rnA 0.4 V
Peak-to-peak output noise voltage
VID = 0, Full Scale = 2 V 15 p.V
(see Note 2)
Zero-reading temperature coefficient
avo of output voltage
VID = 0, o C :$ TA :$ 70C 0.5 2 p.V/oC
IIH High-level input current VI = 5 V, DoC :$ TA :$ 70C 0.1 10 p.A

IlL low-level input current VI = 0 V, o C :$ TA :$ 70C -0.02 -0.1 rnA
TA = 25C 1 10
II Input leakage current, pins 9 and 10 VID = 0 pA
o C :$ TA :$ 70C 250
TA = 25C 1 2
ICC+ Positive supply current fclock = 0 rnA
~
ooC :$ TA :$ 70C 3
TA = 25C -0.8 -2
ICC- Negative supply current fclock = 0
DoC :$ TA :$ 70C -3
rnA w
Cpd Power dissipation capacitance See Note 3 40 pF :>w
NOTES: 2. This is the peak-to-peak value that is not exceeded 95% of the time.
3. Factor relating clock-frequency to increase in supply current. At VCC + = 5 V
a:
Q.
ICC + = ICC + (fclock = 0) + Cpd x 5 V x fclock
I-
o
::J
C
o
a:
Q.
TEXAS 2-223
INSTRUMENTS
TLC7135 PRODUCT
Advanced LinCMOSTM 4 1/2DlGIT PRECISION PREVIEW
operating characteristics, VCC+ - 5 V, VCC- - -5 V, Vref - 1 V, fclock - 120 kHz,

TA - 25C (unless otherwise noted)
lEI
c
D)
G:FS
(see Note 4)
PARAMETER
Full-scale temperature coefficient
Linearity error
VID = 2 V,
TEST CONDITIONS
DoC
-2 V s VID s 2 V
s TA s 70 De
MIN TYP
0.5
MAX
1
UNIT
ppm/DC
count
r+ Differential linearity error (see Note 5) -2 V s VID s 2 V 0.01 LSB
D)
Full-scale symmetry error (see Note 6)

(') (rollover error)
VID = 2 V 0.5 1 count
.c s 70 De .oooo Digital
c Display reading with O-V input VID = 0, oDe s TA -.0000 +.0000
Reading
(;)'
;:i.' VID = Vref, TA = 25 De +.9998 +.9999 + 1.0000 Digital
Display reading in ratiometric operation
e)" DoC s TA s 70 De +.9995 +.9999 +1.0005 Reading
:s
NOTES: 4. This parameter is measured with an external reference having a temperature coefficient of less than 0.01 ppm/ DC.
"
~.
(')
C
;:i.'
5. The magnitude of the difference between the worst case step of adjacent counts and the ideal step.
6. Rollover error is the difference between the absolute values of the conversion for 2 V and - 2 V.
en
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m
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2-224 TEXAS
INSTRUMENTS
PRODUCT TLC7135
PREVIEW Advanced LinCMOSTM 4 1/2DlGlT PRECISION
timing diagrams
~ END OF CONVERSION
BUSyt ~~~,____________________________________
U)
B1-B8 05 04 03 02 01 05
.....
'3
...
(J
u
c
o
05 -.J I__~_ _ _---.III L '';:;
'Ci)
'3
114-4---t~1f-1 201 200 141---..~
....
04 _ _ _
200
I
14
COUNTS
1...._ _ _ _ _ _ _
.1
COUNTS
..Jr C'
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<t
co
.....
COUNTS .___-__ co
C
03 I
200 "'"141---",,~1
02 ____________________~1
COUNTS r----,
~ ____________
200
COUNTS
14 ~I
.___-__
01
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _. J
I
200 141----..
..... ~1
COUNTS
t Delay between BUSY going low and the first STROBE pulse is dependent upon the analog input.
FIGURE 1
DIGIT SCAN I I 11 ,., 05

FOR OVERRANGE I I....--.-.J '-----J I - - - .
~04
~03
~02
~01
14 .1 ~
1000
COUNTS
w
FIGURE 2 :>w
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c
o
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c..
TEXAS ~ 2-225
INSTRUMENTS
TLC7135 PRODUCT
Advanced LinCMOSTM 4 1/20IG1T PRECISION PREVIEW
timing diagrams (continued)
II
c
INTEGRATOR
OUTPUT
....
Q)
Q) AUTO-
ZERO
I SIGNAL
. INT.
I DE-INTEGRATE
l> 10,0011 10,0001 20,001

n COUNTS COUNTS COUNTS MAX.
.c
cCij. I+--- FULL MEASUREMENT CYCLE---+l~1
;:;.. 40,002 COUNTS
o:::J BUSY
(')
:::;.
n OVER-RANGE _
c
;:;.. WHEN APPLICABLE
en
UNDER-RANGE ~
WHEN APPl.ICABLE .I.~.LI.i.I""",,.LI.i.I"--_ _ _ _ _ _ _ _ _"""
FIGURE 3
STROBE IIIII
r-AUTO ZERO
SIGNAL INTEGRATE+!4- DE-INTEGRATE t
DIGIT SCAN
FOR OVER-RANGE
n t
....0..;;5_ _ _ _ _ _ _ -1: .1-'_ _ _ _...n'-_ _....n' L - -
~_D4___________~,(~~______~n rL--
~~D3_________~I.~f______~~n rL-
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c tFirst D5 of AUTO ZERO and DE-INTEGRATE is one count longer.
c FIGURE 4
(")
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2-226
" TEXAS.
INSTRUMENTS
PRODUCT TLC7135
A measurement cycle for the TLC7135 consists of the following four phases.
1. Auto-Zero Phase. The internal IN + and IN - inputs are disconnected from the pins and internally
connected to ANLG COMMON. The reference capacitor is charged to the reference voltage. The
fI
....en
system is configured in a closed loop and the auto-zero capacitor is charged to compensate for offset '5
voltages in the buffer amplifier, integrator, and comparator. The autozero accuracy is limited only ...(J
by the system noise, and the overall offset, as referred to the input, is less than 10 JlV. u
2. Signal Integrate Phase. The auto-zero loop is opened and the internal IN + and IN - inputs are c
connected to the external pins. The differential voltage between these inputs is integrated for a fixed o
'';:
period of time. If the input signal has no return with respect to the converter power supply, IN- 'w
can be tied to ANLG COMMON to establish the correct common-mode voltage. Upon completion '5
of this phase, the polarity of the input signal is recorded. C-
(J
3. Oe-integrate Phase. The reference is used to perform the de-integrate task. The internal IN - is <t
internally connected to ANLG COMMON and IN + is connected across the previously charged reference
capacitor. The recorded polarity of the input signal is used to ensure that the capacitor will be connected
....
C'CS
C'CS
with the correct polarity so that the integrator output polarity will return to zero. The time, which C
is required for the output to return to zero, is proportional to the amplitude of the input signal. The
return time is displayed as a digital reading and is determined by the equation 10,000 x (V'OiVref).
The maximum or full-scale conversion occurs when V,O is two times Vref.
4. Zero Integrator Phase. The internal IN - is connected to ANLG COMMON. The system is configured
in a closed loop to cause the integrator output to return to zero. Typically this phase requires 100
to 200 clock pulses. ~owever, after an over-range conversion, 6200 pulses are required.
description of analog circuits
input signal range

The common mode range of the input amplifier extends from 1 V above the negative supply to 1 V below
the positive supply. Within this range, the common mode rejection ratio (CMRR) is typically 86 dB. Both
differential and common mode voltages cause the integrator output to swing. Therefore, care must be
exercised to assure the integrator output does not saturate.
analog common
Analog common (ANLG COMMON) is connected to the internal IN - during the auto-zero, de-integrate,
and zero integrator phases. If IN - is connected to a voltage which is different than analog common during
the signal integrate phase, the resulting common mode voltage will be rejected by the amplifier. However,
in most applications, IN LO will be set at a known fixed voltage (power supply common for instance). ~
In this application, analog common should be tied to the same point, thus removing the common mode w
voltage from the converter. Removing the common mode voltage in this manner will slightly increase
conversion accuracy.
:>w
a:
reference c..
The reference voltage is positive with respect to analog common. The accuracy of the conversion result t-
is dependent upon the quality of the reference. Therefore, to obtain a high accuracy conversion, a high O
quality reference should be used. ::l
C
o
a:
c..
TEXAS ~ 2-227
INSTRUMENTS
POST OFFICE BOX 655012' DALLAS. TEXAS 75265
TLC7135 PRODUCT
Advanced LinCMOSTM 4 1/2-DlGIT PRECISION PREVIEW
ANALOG-TO-DiGITAL CONVERTER
description of digital circuits
RUN/HOLD input
When the RUN/HOLD input is high or open, the device will continuously perform measurement cycles every
40,002 clock pulses. If this input is taken low, the IC will continue to perform the ongoing measurement
c
-
OJ
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(')
cycle and then hold the conversion reading for as long as the pin is held low. If the pin is held low after
completion of a measurement cycle, a short positive pulse (greater than 300 ns) will initiate a new
measurement cycle. If this positive pulse occurs before the completion of a measurement cycle, it will
not be recognized. The first STROBE pulse, which occurs 101 counts after the end of a measurement
.c cycle, is an indication of the completion of a measurement cycle. Thus, the positive pulse could be used
c to trigger the start of a new measurment after the first STROBE pulse.
(ii'
;:;:
0' STROBE input
:1
Negative going pulses from this input are used to transfer the BCD conversion data to external latches,
("')
:::;' UARTS, or microprocesors. At the end of the measurement cycle, the digit-drive (05) input goes high and
(') remains high for 201 counts. The most significant digit (MSD) BCD bits are placed on the BCD pins. After
c the first 101 counts, halfway through the duration of output 01-05 going high, the STROBE pin goes low
;:;"
en for 1/2 clock pulse width. The placement of the STROBE pulse at the midpoint of the 05 high pulse allows
the information to be latched into an external device on either a low-level or an edge. Such placement
of the STROBE pulse also ensures that the BCD bits for the second MSD will not yet be competing for
the BCD lines and latching of the correct bits is assured. The above process is repeated for the second
MSD and the 04 output. Similarly, the process is repeated through the least significant digit (LSD).
Subsequently, inputs 05 through 01 and the BCD lines will continue scanning without the inclusion of
STROBE pulses. This subsequent continuous scanning causes the conversion results to be continuously
displayed. Such subsequent scanning does not occur when an over-range condition occurs.
BUSY output
The BUSY output goes high at the beginning of the signal integrate phase and remains high until the first
clock pulse after zero-crossing or at the end of the measurement cycle if an over-range condition occurs.
It is possible to use the BUSY pin to serially transmit the conversion result. Serial transmission can be
accomplished by ANDing the BUSY and CLOCK signals and transmitting the ANDed output. The transmitted
output consists of 10,001 clock pulses, which occur during the signal integrate phase, and the number
of clock pulses, which occur during the de-integrate phase. The conver.sion result can be obtained by
subtracting 10,001 from the total number of clock pulses.
OVER-RANGE output
When an over-range condition occurs, this pin goes high after the BUSY signal goes low at the end of
"o
:lJ
the measurement cycle. As previously noted, the BUSY signal remains high until the end of the measurement
cycle when an over-range condition occurs. The OVER-RANGE output goes high at end of BUSY and goes
low at the beginning of the de-integrate phase in the next measurement cycle.
C
C UNDER-RANGE output
("')
At the end of the BUSY signal, this pin goes high if the conversion result is less tha~ or equal to 9% (count
-I of 1800) of the full-scale range. The UNDER-RANGE output is brought low at the beginning of the signal
"m
:lJ
integrate phase of the next measurement cycle.
-<m
~
2-228 TEXAS ~
INSTRUMENTS
PRODUCT TLC7135
PREVIEW Advanced LinCMOSTM 4 1/2DIGIT PRECISION
ANALOG TODIGITAL CONVERTER
POLARITY output
The POLARITY output is high for a positive input signal and is updated at the beginning of each de-integrate
phase. The polarity output is valid for all inputs including a and over-range signals.
....rn
digit-drive (05, 04, 02 and 01) outputs "S
(J
~
Each digit-drive output (01 through 05) sequentially goes high for 200 clock pulses. This sequential process
is continuous unless an over-range occurs. When an over-range occurs, all of the digit drive outputs are
(3
blanked from the end of the strobe sequence until the beginning of the de-integrate phase (when the C
sequential digit drive activation begins again). The blanking activity, during an over-range condition, may
o
"+=
be used to cause the display to flash and indicate the over-range condition. "iii
"S
BCD outputs C"
(J
The BCD bits (B8, B4, B2 and B1) for a given digit are sequentially activated on these outputs.
Simultaneously, the appropriate Digit-drive line for the given digit is activated. ....caca
system aspects C
integrating resistor
The value of the integrating resistor (RINT) is determined by the full scale input voltage and the output
current of the integrating amplifier. The integrating amplifier can supply 20 p,A of current with negligible
non-linearity. The equation for determining the value of this resistor is as follows:
R _ FULL-SCALE VOLTAGE
INT - liNT
Integrating amplifier current, liNT, from 5 to 40 p,Awili yield good results. However, the nominal and
recommended current is 20 p,A.
integrating capacitor
The product of the integrating resistor and capacitor should be selected to give the maximum voltage swing
without causing the integrating amplifier output to saturate and get too close to the power supply voltages.
If the amplifier output is within 0.3 V of either supply, saturation will occur. With 5-V supplies and ANLG
COMMON connected to ground, the designer should design for a 3.5-V to 4-V integrating amplifier
swing. A nominal capacitor value is 0.47 p,F. The equation for determining the value of the integrating
capacitor (CINT) is as follows:
~
. 10,000 x CLOCK PERIOD x liNT w
=
CINT INTEGRATOR OUTPUT VOLTAGE SWING
5>
w
where: liNT is nominally 20 p,A.
a:
11-
Capacitors with large tolerances and high dielectric absorption can induce conversion inaccuracies. A
capacitor, which is too small could cause the integrating amplifier to saturate. High dielectric absorption I-
causes the effective capacitor value to be different during the signal integrate and de-integrate phases. o
Polypropylene capacitors have very low dielectric absorption. Polystyrene and Polycarbonate capacitors ::l
have higher dielectric absorption, but also work well. C
oa:
11-
TEXAS . . 2-229
INSTRUMENTS
TLC7135 PRODUCT
Advanced LinCMOSTM 4 1/2-DlGlT PRECISION PREVIEW
ANALOG-TO-DlGlTAL CONVERTER
II
auto-zero and reference capacitor
Large capacitors will tend to reduce noise in the system. Dielectric absorption is unimportant except during
power-up or overload recovery. Typical values are 1 J.tF.
cQ) reference voltage
r+
Q)
For high-accuracy absolute measurements, a high quality reference should be used.
l>
n
..c rollover resistor and diode
c
0' The TLC71 35 has a small rollover error, however it can be corrected. The correction is to connect the
;+ cathode of any silicon diode to the INT OUT pin and the anode to a resistor. The other end of the resistor
0' is connected to ANLG COMMON or ground. For the recommended operating conditions the resistor value
::s is 100 kO. This value may be changed to correct any rollover error which has not been corrected. In many
(")
::;' non-critical applications, the resistor and diode are not needed.
n
c maximum clock frequency
;;"
VJ
For most dual-slope AID converters, the maximum conversion rate is limited by the frequency response
of the comparator. In this circuit, the comparator follows the integrator ramp with a 3 J.ts delay. Therefore,.
with a 160 kHz clock frequency (6 J.ts period), half of the first reference integrate clock period is lost in
delay. Hence, the meter reading will change from 0 to 1 with a 50 J.tV input, 1 to 2 with a 150 J.tVinput,
2 to 3 with a 250 J.tV input, etc. This transition at midpoint is desirable; however, if the clock frequency
is increased appreciably above 160 kHz, the instrument will flash" 1 " on noise peaks even when the input
is shorted. The above transition points assume a 2-V input range is equivalent to 20,000 clock cycles.
If the input signal is always of one polarity, comparator delay need not be a limitation. Clock rates of 1 MHz
are possible since non-linearity and noise do not increase substantially with frequency. For a fixed clock
frequency, the extra count or counts caused by comparator delay will be a constant and can be subtracted
out digitally.
For signals with both polarities, the clock frequency can be extended above 160 kHz without error by
using a low value resistor in series with the integrating capacitor. This resistor causes the integrator to
jump slightly towards the zero-crossing level at the beginning of the de-integrate phase and thus,
compensates for the comparator delay. This series resistor should be 10 to 50 ohms. This approach allows
clock frequencies up to 480 kHz.
minimum clock frequency

The minimum clock frequency limitations result from capacitor leakage from the auto-zero and reference
"tJ capacitors. Measurement cycles as high as 10 seconds are not influenced by leakage error.
:Jl
o rejection of 50 Hz or 60 Hz pickup
C
c:
(")
To maximize the rejection of 50 Hz or 60 Hz pickup, the clock frequency should be chosen so that an
integral multiple of 50 Hz or 60 Hz periods occur during the signal integrate phase. To achieve rejection
of these signals, some clock frequencies which could be used are as follows:
-I
"tJ 50 Hz: 250, 166.66, 125, 100 kHz, etc.
:Jl 60 Hz: 300, 200, 150, 120, 100, 40, 33.33 kHz, etc.
m
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~
2-230 TEXAS ~
INSTRUMENTS
PRODUCT TLC7135
PREVIEW Advanced LinCMOS 4 1/2DIGIT PRECISION
zero-crossing flip-flop
This flip-flop interrogates the comparator's zero-crossing status. The interrogation is performed after the
Ell
-
previous clock cycle and the positive half of the ongoing clock cycle have occurred so that any comparator
transients which result from the clock pulses do not affect the detection of a zero-crossing. This procedure t/)
delays the zero-crossing detection by one clock cycle. To eliminate the inaccuracy, which is caused by 'S
this delay, the counter is disabled for one clock cycle at the beginning of the de-integrate phase. Therefore,
when the zero-crossing is detected one clock cycle later than the zero-crossing actually occurs, the correct
...CJ
number of counts is displayed.
C3
c
o
noise '';:
'w
The peak-to-peak noise around zero is approximately 15 p.V (peak-to-peak value not exceeded 95% of 'S
the time). Near full scale, this value increases to approximately 30 p.V. Much of the noise originates in C"
CJ
the auto-zero loop, and is proportional to the ratio of the input signal to the reference.
-
<t
CO
analog and digital grounds
CO
For high-accuracy applications, ground loops must be avoided. Return currents from digital circuits must C
not be sent to the analog ground line.
power supplies
The TLC7135 is designed to work with 5-V power supplies. However, 5-V operation is possible if the
input signal does not vary more than 1.5 V from mid-supply.
sw
->
w
a:
a..
....(.)
:;::)
C
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TEXAS 2-231
INSTRUMENTS
III
c
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II)
II)
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(I)
2-232
PRODUCT TLC7136C
ANALOGTODIGITAL CONVERTER AND LCD DRIVER
02849. OCTOBER 1986
ADVANCED LinCMOS Technology N DUAL-IN-LiNE PACKAGE

(TOP VIEW)
Zero Reading for O-V Input on All Scales
Precision Null Detection with True Polarity

at Zero
VCC+ OSC1
OSC2
Ell
-...
1C OSC3

1-pA Typical Input Current
True Differential Input and Reference
UNITS
{D1B
1A
1F
TEST
REF HI
REF LO
en
'S
(.)
Direct LCD Display Drive with No External

Components
1G
1E
Cref+
Cref-
U
e
COMMON 0

{D
Low Noise - 15 ",Vp-p Without Hysteresis '';:;
2C IN HI
or Overrange Hangover 'Ci)
IN LO
TENS 2B 'S
On-Chip Clock Oscillator and Reference 2A
2F
AUTO ZERO
BUFF
C"
(.)

r
Convenient 9-V Battery Operation with Low
-
2E INT
Power Dissipation, Less than 1 mW CO
VCC-
Direct Replacement for Intersil and Maxim 3B 2G (TENS) CO

ICL7136
Pin Compatible with IntersillCL7106;
100's
3E
3F
3C}
3A 100's
C
(1000's) 4AB 3G
ICL7126 and Teledyne TSC7106, TSC7136'
POL (MINUS) BP
Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
description
The TLC7136C is a high-performance, very low-power' 3 112-digit analog-to-digital converter (ADC). The
TLC7136C contains seven-segment decoders, display drivers, a clock, and a reference. This device is
designed to interface with liquid crystal displays and incorporates a backplane drive. The device can easily
be powered with a 9-volt battery because the supply current is less than 100 microamperes.
The TLC7136C provides high accuracy and versatility and such features as auto-zeroing to less than 10
microvolts, zero drift of less than 1 ",V/oC, maximum input bias current of 1 0 picoamperes, and rollover
error of less than 1 count.
The differential input and on-chip reference are particularly useful when measuring load cells, strain gauges,
and other bridge-type transducers. Single-supply operation provides economy in that a high-performance
panel meter can be built with only seven passive components and a display. The TLC7136C is an improved
version of the Intersil ICL 7126 in that overrange hangover and hysteresis effects are eliminated. ~
W
The TLC7136C is characterized for operation from OOC to 70C.
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ADVANCED LinCMOS" is a trademark of Texas Instruments Incorporated. c..
development. Characteristic data an~ other TEXAS . .
specifications are design goals. Texas Instruments 2-233
INSTRUMENTS
TLC7136C PRODUCT
Advanced LinCMOSTM 3 1/2DlGlT PRECISION PREVIEW
ANALOGTODlGlTAL CONVERTER AND LCD DRIVER
functional block diagram (with external components)
c BP
....
Q)
Q)
--,
(211
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c I
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o::s I
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~. 1(1)
n .------.------~--------~------------4_--;_--r_----~--~I--VCC+
c I
;:;: 6.2 v
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1(371
L------4------~-----+--~----+_------------~~~~4_~~~TEST
I
_
___----1..:.;(2=6,1
_____ .J VCC-
(401 (391 (381

OSC1 RT OSC2 OSC3
C,ef
I
r - -
VCC+
(::;\=
C,ef-
(331
~'l~~~ -_--- ~CC> INT
(271
THRESHOLD -
DETECTOR
- iI
~
I TO I
I 1 p.A DIGITAL I
I BUFFER SECTION
1 All & II All & II II
r
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1
"C (3111
IN HII 2.8 V
INT
:.0
o I
C All
6.2
V
C
n
-I (3211
"C COMMON I
:.0 I
m (~~------~---------------+----------------~
IN LOIL
_ _
INT_ _ _ _ _ _ _ _ _ ANALOG SECTION
___________________ J
S ,
(261
m VCC-
~ NOTE: Letters beside switches indicate state of conversion during switch closure.
2-234
TEXAS l!}
INSTRUMENTS
PRODUCT TLC7136C
PREVIEW Advanced LinCMOSTM 3 1/2DIGIT PRECISION
Supply voltage (Vee + with respect to Vee -), Vee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Voltage range for any input except clock (see Note 1) . . . . . . . . . . . . . . .. . . . . .. Vee - to Vee +
elock input voltage range .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Vtest to Vee +
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ooe to 70 0 e
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 e to 150 e
Ell ....tn
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds ...... , . . . . . . . . . . . . . .. 260 0 e 'S
...
(,)
NOTE 1: Input voltages may exceed the supply voltages provided the input current is limited to 100 IlA.
C3
recommended operating conditions t:
o
'';;
MIN NOM MAX UNIT 'm
VCC Supply voltage 9 V 'S
LFS (full scale) VIO = 200 mY, See Note 2 100 mV C"
Vref Reference input voltage (,)
IFS VIO = 2 V 1 V

Full-scale input voltage 2 Vref V
VI Input voltage at IN HI or IN LO VCC- +1 VCC+ -0.5 V ....COCO
Cref Reference capacitor 0.1 1 IlF Q
Cz Auto-zero capacitor 0.033 0.47 IlF
Cx Integrator capacitor 0.047 0.15 IlF
Integrator resistor
I FS = 200 mV 180 k!l
Rs
IFS = 2 V 1.8 M!l
TA Operating free-air temperature 0 70 c
electrical characteristics, Vee 9 V, fclock 16 kHz, TA 25C (unless otherwise noted)

Common-mode rejection ratio

VIC = 1 V,. VIO = 0,
50 IlVN
FS = 200 mV
Noise voltage
VIO = 0, FS = 200 mV 15 IlV
(peak-to-peak value not exceeded 95% of time)
Input leakage current VIO = 0 1 10 pA
VID = 199 mY, TA = 0 to 70C,
Scale factor temperature coefficient 1 5 ppm/oC
See Note 3
Analog common voltage (with respect to VCC+) 250 k!l between COMMON and VCC+ -2.6 -3 -3.2 V
Temperature coefficient of analog common voltage
250 k!l between COMMON and VCC + 150 ppm/oC
(with respect to VCC +)
Peak-to-peak segment drive voltage (see Note 4) 4 5 6 V
Peak-to-peak backplane drive voltage (see Note 4) 4 5 6 V
Supply current (see Note 5)
Power dissipation capacitance
VIO = 0
See Note 6
50
40
100 IlA
pF
~
W
NOTES: 2. VIO is the voltage at IN HI with respect to IN LO.
3. This is measured using a fixed external reference voltage with O-ppm/oC temperature coefficient.
>
W
4. Backplane drive is in phase with segment drive for a turned-off segment, 180 out of phase for a turned-on segment. Backplane
frequency is 20 times the conversion rate. The average de component is less than 50 mY.
a::
c..
5. This does not include current through the common terminal. During the auto-zero phase, current is 10 to 20 IlA higher. Use
of a 48-kHz oscillator increases current by typically 8 IlA. I--
6. This can be used to determine the no-load dynamic power dissipation. Po = C p d,VCC 2 ,f + ICC'VCC' (.)
::>
c
oa::
c..
TEXAS 2-235
INSTRUMENTS
TLC7136C PRODUCT
Advanced LinCMOSTM 3 112D1G1T PRECISION PREVIEW
ANALOGTODIGITAL CONVERTER AND LCD DRIVER
operating characteristics over recommended operating free-air temperature range, Vee, = 9 V

lEI
c
Zero-input digital reading
Ratiometric digital reading
Rollover error (see Note 7)
Linearity error
VID = O. FS = 200 mV
VID = Vref = 100 mV
VID- = VID+ "" 200 mV or 2 V
FS = 200 mV or 2 V
-0,000.
999
O.OOO
999/1000
0,2
O.2
+0,000
1000
1
1
Count
Count
....
Q)
Q) Zero-reading temperature coefficient
VID = O
0.2 1 pV/oC
TA = OOC to 70C

(')
NOTE 7: Rollover error is the difference between the magnitudes of the conversion results for equal positive and negative inputs near full scale .
.c
c:
iii'
:=;.'
o:s PARAMETER MEASUREMENT INFORMATION
(")
~.
(')
c:
:=;.' 240kn
t/)
(1)
VCC+ (20)
(36) (5)
10kn REFHI 1A
(4)
1B
(3)
(35) lC
REF LO (2)
10
(32) (8)
COMMON 1E
ANALOG
INPUT (6)
(30) 1F
VOLTAGE IN LO (7)
lG
O.lIlF
2A
(31)
INHI 2B
(40) 2C
OSCl
20
560kn(39)
OSC2 2E
50 pF (38) 2F
OSC3
2G
(34)
"tJ Cref+ 3A
::Jl
o Cref-
3B
3C
C
c: (29)
AUTO ZERO
3D
C') 3E
-t 180kn(28)
BUFF
3F
"tJ 0.15 1lF
3G
::Jl (27)
m INT 4AB
-< BP
FIGURE 1. TEST CIRCUIT (CLOCK FREQUENCY ... 16 kHz, 1 READING PER SECOND)
2-236 TEXAS ~
INSTRUMENTS
PRODUCT TLC7136C
PREVIEW Advanced LinCMOSTM 3 1/2DlGlT PRECISION
240kn
(1)
fJI(/)
+01
'S(,)
Vee+ (20)
...
10kn
(36)
REFHI 1A
(5) C3
1B
(4) c
(3)
o
1C '';:;
(35)
REF LO (2) 'en
(32)
10 'S
COMMON 1E C"
ANALOG (,)
INPUT (30) 1F ~
VOLTAGE IN LO
1G co
+01
0.11'F co
1Mn (31)
INHI
o
+ 2B
(40) 2C
OSC1
20
180 kn(39)
OSC2 2E
50 pF
(38) 2F
OSC3
2G
(34)
Cref+ 3A
3D
Cref- 3C
(29) 3D
AUTO ZERO
3E
180kn(28)
3F
BUFF
3G
750 n (27)
INT 4AB
BP
0.471'F
FIGURE 2. TEST CIRCUIT (CLOCK FREQUENCY = 48 kHz, 3 READINGS PER SECOND) sw

-
>
w
a:
c..
....
(.)
:::J
C
oa:
c..
TEXAS ~ 2-237
INSTRUMENTS
POST OFFICE BOX 655012 DAllAS. TEXAS 75265
TLC7136C PRODUCT
Advanced LinCMOSTM 3 1/2DIGI1 PRECISION PREVIEW
II
A measurement cycle, for the TLC7136C, consists of four phases. The four phases are as follows:
1. Auto-Zero Phase. The internal IN HI and IN LO inputs are disconnected from the pins and are internally
connected to analog COMMON. The reference capacitor is charged to the reference voltage. The system
c is configured in a closed loop and the auto-zero capacitor is charged to compensate for offset voltages
....
Q)
Q)
in the buffer amplifier, integrator, and comparator. The auto-zero accuracy is I.imited only by the system
noise, and the overall offset, as referred to the input, is less than 10 microvolts.

(')
2. Signal Integrate Phase. The auto-zero loop is opened and the internal IN HI and IN LO inputs are
.c connected to the external pins. The differential voltage between these inputs is integrated for a fixed
c period of time. If the input signal has no return with respect to the converter power supply, IN LO
en
;:+. can be tied to analog COMMON to establish the correct common-mode voltage. Upon completion of
e)" this phase, the polarity of the input signal is recorded.
:l 3. Oeintegrate (reference-integrate) Phase. The reference is used to perform the deintegrating task, which
o is performed in the following manner. The IN LO is internally connected to analog COMMON and IN
::;. HI is connected across the previously charged reference capacitor. The recorded polarity of the input
(')
c signal is used to ensure that the capacitor will be connected with the correct polarity so that the
;:+. integrator output will return to zero. The time that is required for the output to return to zero is
t/)
proportional to the amplitude of the input signal. The return time is displayed as a digital reading and
is determined by the equation 1000 VI ON ref.
4. Zero Integrator Phase. The internal IN LO is connected to analog COMMON. The system is configured
in a closed loop to cause the integrator output to return to zero. Typically this phase requires 11 to
140 clock pulses. However, after an overrange conversion, 740 pulses are required.
description of analog circuits

input signal range
The common-mode range of the input amplifier extends from 1 volt above the negative supply to 0.5 volt
below the positive supply. Within this range, the common mode rejection ratio (CMRR) is typically 86 dB.
The common-mode signal also causes the integrator output to swing and there is a possibility that the
integrator output could saturate. This saturation, which causes an incorrect conversion, is most likely with
the combination of a large positive common mode voltage and a large negative differential voltage. The
negative differential voltage causes the integrator output to go positive when most of the integrator's
positive output swing capability has been used up by the large positive common mode voltage. In such
situations, the integrator swing can be reduced to less than the recommended 2-volt swing with a minimal
reduction in accuracy. The linear range of the integrator output is within 0.3 volts of either supply.
differential reference
"tJ
::c The reference voltage must lie within the device power supply range. The major source of common-mode
o error is caused by the loss or gain of charge from the reference capacitor due to stray capacitances. With
c large common-mode voltages, the reference capacitor will gain charge or voltage while deintegrating a
positive signal and, conversely, lose charge or voltage while deintegrating a negative signal. This gain or
c: loss of reference capacitor voltage will cause a rollover error. The selection of a reference capacitor that
C') is large in comparison to the stray capacitance will reduce the rollover error to less than 0.5 counts (see
-I Component Value Selection).
"tJ
::c analog common
m For battery operation or when the inputs are floating with respect to the TLC7136C power supply, the
S
m
analog COMMON pin is used to set the common mode voltage. The COMMON pin is preset by internal
circuits to a voltage that is approximately 3 volts lessthan the TlC7136C positive supply. This preset
~ voltage will give a 6-volt end-of-battery life.
2-238 TEXAS
INSTRUMENTS
PRODUCT TLC7136C
When the power supply voltage is greater than 7 volts, the TLC7136C zener will be in a regulating mode
and the preset voltage at the COMMON pin will have reference-like qualities. The preset voltage will then
have a low 0.001 %-per-volt voltage coefficient, a low output impedance of approximately 35 ohms, and
a temperature coefficient of less than 80 ppm/oC. Therefore, the preset voltage could be used for an on-
chip reference, however, there are some limitations. For 2C to 8 C temperature changes, a scale factor
II
....en
"S
of one count or more can result. Also, if the power supply voltage drops below 7 volts, the voltage coefficient U
a-
will be poor since the zener will no longer be in a regulating mode.
U
Analog COMMON is connected to the internal IN La during the auto-zero, deintegrate, and zero integrator C
phases. If IN La is connected to a voltage that is different from analog common during the signal-integrate o
phase, the resulting common-mode voltage will be rejected by the amplifier. However, in certain applications, +i
IN La is set at a fixed known voltage, for example the power supply common voltage. For these applications,
"m
"S
the COMMON pin should be tied to IN La to eliminate the common-mode rejection error. The same C"
consideration applies to the reference voltage. Referring the reference voltage to analog COMMON eliminates u
another common-mode error source. Referring the reference voltage to an analog common is accomplished
by connecting COMMON to either REF La or REF HI. ....COCO
test
C
The TEST pin performs two functions. First, it is connected to the internally generated digital supply (negative
side) through a 500-ohm resistor. This connection allows the TEST pin to be used as the negative supply
for external segment drivers, such as decimal points or any LCD segment that requires up to 1-milliampere
load current. Second, the pin performs a test function. When the TEST pin is pulled up to VCC +, all
segments will turn on and the display will read - 1888. In this test mode, a constant DC voltage is applied
to the segments, rather than a square wave, and the segments may be damaged if the test is prolonged.
description of digital circuits

An internal digital ground is generated with a 6-volt zener diode and a large P-channel source follower.
This generated supply can handle the large capacitive currents that result when the backplane (BP) voltage
is switched. Dividing the clock frequency by 800 gives the BP frequency. For 3 readings per second, the
BP signal is a 5-volt, 60-Hz squarewave. The segments that are driven at the same frequency and amplitude
are in phase with BP when off, and out of phase with BP when on. Except in the test mode, a negligible
amount of DC voltage is placed across the segments. For negative-polarity inputs, the polarity indication
will become active. Also, if the placement of IN La and IN HI is switched, the polarity indication can be
switched accordingly. '
system timing
The TLC7136C clock circuit is shown in Figure 3. The three possible clock setups are pin 40 connected
~
to an external oscillator, a crystal between pins 39 and 40, or an RC oscillator with connections to pins w
38, 39, and 40.
The frequency of the clock oscillator is first divided by four and then the resulting clock signal is used
:>w
to clock the decade counters. The divide-by-four clock signal is then further divided to form the four convert- a:
cycle phases, which are as follows: c..
1. 1,000 counts for signal integration. I-
2. a to2,000 counts for reference deintegration. o::;)
c
oa:
c..
TEXAS ~ 2-239
INSTRUMENTS
POST OFFICE BO)( 66501 i1 " DALLAS, TEXAS 75266
TLC7136C PRODUCT
Advanced LinCMOSTM 3 1/2DlGIT PRECISION PREVIEW
II
3. 11 to 140 counts for zero integration (with an overranged conversion of greater than 2,060 counts,
the zero integrator phase will require 740 counts, and auto-zero will require 260 counts).
4. 910 to 2900 counts for auto-zero (for signals less than full-scale, auto-zero gets the unused portion
of reference deintegration and zero integration).
c
....
CI
CI
The total measurement cycle requires 4,000 counts or 16,000 clock pulses. A 48-kilohertz oscillator would
be required for three readings per second.
>
(')
.c
c r-------
iii" FROM I
;::;'" EXTERNAL - " ' I
0"
::J
o
OS;2;_ --~':(401 , I
TO COUNTERS
:::;" l' ~ CRYfTAL

(')
C I I 'I
;::;'" I L __ "'~'__' ; " " - - - - - - - - - - - - - - " ' "
UI I RC NETWORK (39) I
IL ____ +_.L..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...J
13a)L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
NOTE: This figure shows all three external control circuits connected; however, only one external circuit (crystal, RC network or external
oscillator) is connected for proper operation.
FIGURE 3. CLOCK CIRCUITS
component value selection

integrating resistor
The buffer amplifier and integrator class A output stages require approximately 6 microamperes of quiescent
current and can source -1 microampere of current without inducing any significant nonlinearity. The
integrating resistor should be sufficiently large that the buffer amplifier and integrator will remain in this
linear region. However, the resistor must also be small enough that PC board leakage remains insignificant.
Values of 180 kilohms and 1.8 megohms are recommended for the respective 200-millivolt and 2-volt
full-scale voltages.
integrating capacitor
The integrating capacitor should be chosen to give the maximum voltage swing, yet not allow the combined
"0 tolerances of the integrating resistor and capacitor to cause the integrator to saturate. The linear range
:xJ of the integrator extends to within 0.3 volt of VCC _ or VCC +. A + 2-volt full-scale integrator swing works
o fine when analog common is used as the reference. Capacitor values of 0.047 microfarad and 0.1 5 micro-
C farad are recommended for 3 (48-kilohertz oscillator) and 1 (16-kilohertz oscillator) readings per second
C respectively. As the oscillator frequency is increased, the capacitor value must be decreased to maintain
(") the same output swing. Polypropylene capacitors are recommended because of their reasonable cost and
-I low dielectric absorption, which produces low roll-over errors.
"0
:xJ
m
S
m
=E
2-240 TEXAS ~
INSTRUMENTS
PRODUCT TLC7136C
ANALOGTODlGITAL CONVERTER AND LCD DRIVER
;'
;'
..,.,.....
......
......
III
... tn
INTEGRATOR
;' "- '3
OUTPUT - - - - - -..... '--------- ...
(,)
AUTO-
ZERO
SIGNAL-
INTEGRATE
DE-INTEGRATE
(REFERENCE-INTEGRATE)
ZERO
INTEGRATOR
u
s::::
1000 COUNTS 2000 COUNTS (MAX)
o
'';::;
'Ci)
4000 COUNTS
'3
C"
(16.000 OSCILLATOR CYCLES) (,)

FIGURE 4. TIMING DIAGRAM
...coco
auto-zero capacitor C
The size of this capacitor has an effect upon the noise of the system. For 200-millivolt full-scale applications,
in which noise must be kept to a minimum, a 0.47-microfarad capacitor is recommended. The zero-integrator
phase allows the use of a large auto-zero capacitor without the accompanying hysteresis or overrange
hangover problems that can occur with the ICL 7126 or ICL 7106.
reference capacitor
A O. 1-microfarad capacitor is fine for most applications_ However, with large common-mode signals, if
the REF LO pin is not connected to analog COMMON and the full-scale voltage is 200 millivolts, a larger
capacitor is required to prevent rollover error. A 1-microfarad capacitor will hold this rollover error to
0.5 counts.
oscillator components
A 50-pF capacitor is recommended for all frequency ranges. The resistor can be selected from the equation:
f = 0.45/RC
where: R =7 180 kilohms for 48-kilohertz oscillator (3 readings per second) and 560 kilohms for 16-kilohertz
oscillator (1 reading per second).
reference voltage
An input voltage of 2 Vref is required to obtain a full-scale reading of 2,000 counts. Therefore, for a full- ~
W
scale of 200 millivolts and 2 volts, Vref should be 100 millivolts and 1 volt respectively. In many situations,
the designer might like to have a full-scale voltage other than 200 millivolts or 2 volts. In situations where
os:
the designer desires a full-scale voltage of X volts, the designer can select a Vref of X/2 volts. The value w
of the integrating resistor can be determined by the following equation: a:
c..
X volts (desired full-scale)
200 mV
Value of Integrating Resistor for X volts full-scale
180 kO (integrating resistor for 200 mV full-scale) ....
U
If X volts is greater than 200 millivolts, it is better to work with an X/2 volts reference, since dividing ::J
the X volts down to 200 millivolts will cause the input signal to be more susceptible to noise.
C
Sometimes a designer will want a digital reading of zero when VI does not equal zero. This desire can
be met by connecting VI between IN HI and COMMON and the zero-reading VI between COMMON and
oa:
IN LO. c..
TEXAS ~ 2-241
INSTRUMENTS
POST OFFICE BOX 655012 DALLAS, tExAS '5265
III
C
m
....
m
>
(')
.c
c
(ii'
;:;:
0'
::l
o
::;'
(')
c
;:;:
en
2-242
ADVANCE TLC7524
INFORMATION Advanced LinCMOSTM 8BIT MULTIPLVING
DlGITALTOANALOG CONVERTER
D3008. SEPTEMBER 1986
Advanced LinCMOSTM Silicon-Gate D OR N PACKAGE

Technology (TOP VIEW)

e

Easily Interfaced to Microprocessors
On-Chip Data Latches
OUT1
OUT2
GND
DB7
RFB
REF
VDD
WR
II
...
o
DB6 CS 'S
Segmented High-Order Bits Ensure Low-
Glitch Output
DB5 DBO ...CJ
DB4 DB1 U
Designed to be Interchangeable with Analog DB3 DB2 c
Devices AD7524, PMI PM-7524, and Micro o
'~
Power Systems MP7524 'Ci)
Fast Control Signaling for Digital Signal 'S
C"
Processor Applications Including Interface CJ
with TMS320 oCt
KEY PERFORMANCE SPECIFICATIONS
...
CO
CO
Resolution 8 Bits C
Linearity error Y. LSB Max
Power dissipation
5 mW Max
at VOO = 5 V
Settling time 100 ns Max
Propagation delay 80 ns Max
description
The TLC7524 is an Advanced LinCMOSTM 8-bit digital-to-analog converter (DAC) designed for easy interface
to most popular microprocessors.
The TLC7524 is an 8-bit multiplying DAC with input latches and with a load cycle similar to the "write"
cycle of a random access memory. Segmenting the high-order bits minimizes glitches during changes in
the most-significant bits, which produce the highest glitch impulse. The TLC7524 provides accuracy to
Y2 LSB without the need for thin-film resistors or laser trimming, while dissipating less than 5 milliwatts
typically.
Featuring operation from a 5-V to 15-V single supply, the TLC7524 interfaces easily to most microprocessor 2:
buses or output ports. Excellent mUltiplying (2 or 4 quadrant) makes the TLC7524 an ideal choice for many
microprocessor-controlled gain-setting and signal-control applications.
o
i=
The TLC75241 is characterized for operation from- 25 C to 85C, and the TLC7524C is characterized
for operation from OOC to 70C.
<C
~
a:
oLL
-2:w
CJ
2:
<C
>
c
Advanced LinCMOS is a trademark of Texas Instruments Incorporated. <C
preproduction phase of development Charactenstic
TEXAS -I/} 2-243
TLC7524 ADVANCE
Advanced LinCMOSTM HBIT MULTIPL VING INFORMATION
DlGlTALTOANALOG CONVERTER

VDD
II
c
Q)
(14)
2R
r+
Q)
(16) RFB

(') R
.c
c (1)
OUT1
(ii'
;:;." (2)
o::::I OUT2
CS (12)
o
::;.
(3)
GND
WR (13)
(')
c
::+.
en
DB7 DB6 DB5 DBO
(MSB) (LSB)
\
V
DATA INPUTS
operating sequence
!4 tsu(CS) ~~ ~I .th(CS)
CS---------,~ ________________~:--J/
I
\4---t w (WR)---+i
c
< DBO-DB7
~
------------------
jf--tsu(D)--+i
I "~th(D)
)...---------
2
om
-
2
."
o
::Jl
s:
.::!
o
2
2-244 TEXAS -I./}

INSTRUMENTS
POST OF~IC~ BOX 655Q12 bAllAS. TEXAS 752G5
ADVANCE TLC1524
INFORMATION Advanced LinCMOSTM 8BIT MULTIPLYING
II
Supply voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 16.5 V
Digital input voltage, VI ....................................... -0.3 V to VDD+0.3 V
Reference voltage, Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25 V
Peak digital input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10 p.A
Operating free-air temperature range: TLC75241 .......................... - 25C to 85C ....o
S
TLC7524C ............................ OC to 70C
Storage temperature range ......................................... - 65C to 150C ...
(J
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260C U
c
recommended operating conditions o
'';:;
'(j)
voo - 5 V voo - 15V
UNIT 'S
C"
Supply voltage, VOO 4.75 5 5.25 14.5 15 15.5 V (J
Reference voltage, Vref 10 10 V
Low-level input voltage, VIL
2.4
0.8
13.5
1.5
V
V
....coco
CS setup time, tsu(CS) 40 40 ns C
CS hold time, th(CS) 0 0 ns
Data bus input setup time, tsu(O) 25 25 ns
Data bus input hold time, th(O) 10 10 ns
Pulse duration, WR low, tw(WR) 40- 40 ns
. ITLC75241 -25 85 -25 85
Operating free-air temperature, TAl C
/ TLC7524C 0 70 0 70
electrical characteristics over recommend~d operating free-air temperature range, Vref == 10 V,

OUT1 and OUT2 at GND (unless otherwise noted)
Voo - 5 V Voo - 15V
MIN TVP MAX MIN TVP MAX
IIH High-level input current VI = VOO 10 10 /LA
IlL LOW-level input current VI = 0 -10 -10 /LA
Output leakage current, OBO-OB7 at 0 V, WR, CS at 0 V,
400 200 nA
OUT1 (Pin 1) Vref = 10 V
Output leakage current, OBO-OB7 at VOO, WR, CS at 0 V, 2
OUT2 (Pin 2) Vref = 10 V
400 200 nA
o
100
100
Supply current (quiescent)
Supply current (standby)
OBO-OB7 at VIH(min} or VIL(max}
OBO-OB7 at 0 V or VOO
1
500
2
500
mA
/LA
i=
Supply voltage sensitivity, <C
kSVS
<lgain/<lVoo
<lVOO = 10% 0.01 0.16 0.005 0.04 %FSR
:E
Input capacitance, a:
Ci
OBO-OB7, WR, CS
VI = 0 5 5
30
pF
o
LL
OUT1 OBO-OB7 at 0 V, 30
Co Output capacitance, -OUT2 pF
Co Output capacitance
OUT1
"'O'iJT2
WR and CS at 0 V
OBO-OB7 at VOO,
WR and CS at 0 V
120
120
30
120
120
30
pF
-w
2
Reference input impedance

5 20 5 20 kO
U
(Pin 15 to GNO) 2
<C
c>
<C
TEXAS . . 2-245
INSTRUMENTS
TLC7524 ADVANCE
Advanced LinCMOSTM 8BIT MULTIPLYING INFORMATION
DIGITAL-TOANALOG CONVERTER
operating characteristics over recommended operating free-air temperature range, Vref = 10 V,

OUT1 and OUT2 at GND (unless otherwise noted)
IJ
c
Q)
PARAMETER
Linearity error
Gain error
TEST CONDITIONS
See Note 1
VDD - 5 V
MIN Typt MAX
0.5
2.5
VDD - 15 V
MIN Typt MAX
0.5
2.5
UNIT
LSB
LSB
r+ Settling time (to % LSB) See Note 2 100 100 ns
OJ
Propagation delay (from

(') digital input to 90% of See Note 2 BO 80 ns
.c final analog output current)
c Vref = 10 V (100-kHz sinewave)
;' Feedthrough at oun or OUT2
WR and CS at 0 V, DBO-DB7 at 0 V
0.5 0.5 %FSR
;::;.'
o:l Temperature coefficient of gain TA = 25C to MAX O.OO4 O.OOl %FSR/OC
(') tTypical values at T A = 25C. .

::;' NOTES: 1. Gain error is measured using the internal feedback resistor. Nominal Full Scale Range (FSR) = Vref - 1 LSB.
(') 2. oun load = 100 n. Cext = 13 pF, WR at 0 V, CS at 0 V, DBO-DB7 at 0 V to VDD or VDD to 0 V.
C
;::;.'
o principles of operation
The TLC7524 is an a-bit multiplying D/A converter consisting of an inverted R-2R ladder, analog switches,
and data input latches. Binary weighted currents are switched between the OUT1 and OUT2 bus lines,
thus maintaining a constant current in each ladder leg independent of the switch state. The high-order
bits are decoded and these decoded bits, through a modification in the R-2R ladder, control three equally
weighted current sources. Most applications only require the addition of an external operational amplifier
and a voltage reference.
The equivalent circuit for all digital inputs low is seen in Figure 1. With all digital inputs low, the entire
reference current, Iref, is switched to OUT2. The current source 1/256 represents the constant current
flowing through the termination resistor of the R-2R ladder, while the current source Ilkg represents leakage
currents to the substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital
input code. With all digital inputs high, the off-state switch capacitance (30 pF maximum) appears at OUT2
and the on-state switch capacitance (120 pF maximum) appears at OUT1. With all digital inputs low, the
situation is reversed as shown in Figure 1. Analysis of the circuit for all digital inputs high is similar to
Figure 1; however, in this case, Iref would be switched to OUT1.
Interfacing the TLC7524 D/A converter to a microprocessor is accomplished via the data bus and the CS
l>
c and WR control signals. When CS and WR are both low, the TLC7524 analog output responds to the data
activity on the DBO-DB7 data bus inputs. In this mode, the input latches are transparent and input data
<
l>
directly affects the analog output. When either the CS signal or WR signal goes high, the data on the
DBO-DB7 inputs are latched until the CS and WR signals go low again. When CS is high, the data inputs
2: are disabled regardless of the state of the WR signal.
(')
m The TLC7524 is capable of performing 2-quadrant or full4-quadrant multiplication. Circuit configurations
-2: for 2-quadrant or 4-quadrant multiplication are shown in Figures 2 and 3. Input coding for unipolar and
bipolar operation are summarized in Tables 1 and 2, respectively.
."
o
:Xl
S
l>
:::!
o
2:
2-246 TEXAS -111

INSTRUMENTS
POST OFFICi BOX 65501 a ' DALLAS. ",xAs 76265
ADVANCE TLC7524
DIGITALTOANALOG CO NVERTER
!r--
EI
- - - - RFB
R
'Ik. ~,....-t----f-4-=..-3eO-p-F---- OUT1 (/)

.....
':;
...CJ
C3
REF ~If-'-;t:\......------1;t:\---------iI-------- OUT2 c
o
1/256?~ 'Ik'?i 1'20 pF
'';:;
'(j)
':;
C'
CJ
FIGURE 1. TLC7524 EQUIVALENT CIRCUIT WITH ALL DIGITAL INPUTS LOW ~
CO
.....
Vref voo CO
o
RA - 2kG RB
(See Note 3)
OBO-OB7
. > - - -......-OUTPUT
CS----I
WR----I
FIGURE 2. UNIPOLAR OPERATION (2-QUADRANT MULTIPLICATION)
20 kG
z
RA - 2 kG
(See Note 3)
RB 20 kG o
i=
OUTPUT
<C
OBO-OB7 ~
a:
CS - - - - I
WR----I
oLL
-2w
()
FIGURE 3. BIPOLAR OPERATION (4-QUADRANT OPERATION) 2
<C
c>
NOTES:' 3. RA and RB used only if gain adjustment is required.
4. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation.
<C
TEXAS -Ij} . 2-247
INSTRUMENTS
POST OFFICE BOX 65li012 CALLAS. TEXAS 76265
TLC7524 ADVANCE
Advanced LinCMOS HBIT MULTIPLYING INFORMATION
DIGITALTOANALOG CONVERTER

TABLE 2. BIPOLAR (OFFSET BINARY) CODE
II
TABLE 1. UNIPOLAR BINARY CODE
DIGITAL INPUT DIGITAL INPUT

(SEE NOTE 5) ANALOG OUTPUT (SEE NOTE 6) ANALOG OUTPUT
MSB LSB MSB LSB
C
Dl 11111111 -Vref (255/256) 11111111 Vref (127/128)
r+
Dl 10000001 - Vref (129/256) 10000001 Vref (1/128)
10000000 0
l>
C')
10000000 -Vref (128/256) = -Vre f/2
01111111 -Vref (127/256) 01111111 -Vref (11128)
.c
c 00000001 -Vref (1/256) 00000001 -Vref (127/128)
(ii' 00000000 0 00000000 -Vref
::t'
0' NOTES: 5. LSB = 11256 (Vref).
:::s 6. LSB = 11128 (Vref).
(')
::;1.
C') microprocessor interfaces
C
::t'
CIl
0007 DATA BUS
~----------------------------~
Z80A
WR~----~""""'"
~--------------~WR
AOA15 ADDRESS BUS

~----~--------------------------------~
FIGURE 4. TLC7524-Z-80A INTERFACE

:t:-
O
<
:t:-
0007 DATA BUS
~------------------------------~
2 6800
(')
m
0---------------___4 WR
2
."
o VMA ~--....._II-___4
:lJ
S
:t:-
=! AO.A15~-----------------A-D-D~R-ES-S-B-U~S~--------------~
o
2 FIGURE 5. TLC7524-6800 INTERFACE
2-248 TEXAS
INSTRUMENTS
ADVANCE TLC7524
microprocessor interfaces (continued)
A8-A15
8051
EI
...tn
'S
...
(J
U
c
..-----------1 WR o
'';:;
ALE t---+--+---.-..... 'Ci)
WR~~~--------~ 'S
c-
(J
ADO-AD7 ~__________
AD_D_R_ES......;S_ID_A_TA
__ BU_S________________-/
...CO
CO
FIGURE 6. TLC7524-8051 INTERFACE C
:2
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2
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TEXAS 2-249
INSTRUMENTS
POS1 OFFICE Sox esS012 OALLAS, tEXAS 752aS
IJ
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...
Q)
Q)

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;:::;.'
0'
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n
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(/)
2-250
ADVANCE TLC7528
INFORMATION .Advanced LinCMOSTM DUAL 8BIT MULTIPLYING
D2979. JANUARY 1987
ADVANCED linCMOSTM SiliconGate N DUAL-IN-L1NE PACKAGE

Technology (TOP VIEWI

Easily Interfaced to Microprocessors
OnChip Data Latches
AGND
OUTA
RFBA
REFA
OUTB
RFBB
REFB
VDD
II (/)
.....
DGND WR 'S(,)
Designed to be Interchangeable with Analog
Devices ADC7528 and' PMI PM7528
DACA/DACB CS ...
(MSB) DB7 DBO (LSB) C3
Fast Control Signaling for Digital Signal DB6 OB1. I:
Processor Applications Including Interface DB5 DB2 o
'';::;
with TMS320 DB4 OB3 'c;;
'S
KEY PERFORMANCE SPECIFICATIONS C"
(,)
Resolution
Linearity Error
8 bits
1/2 LSB

CO
Power Dissipation at VDD = 5 V 5 mW .....
= CO
Settling Time at VDD
Propagation Delay at VDD
5 V
= 5 V
100 ns
80 ns
o
description
The TLC7528 is a dual 8-bit digital-to-analog converter designed with separate on-chip data latches and
featuring excellent DAC-to-DAC matching. Data is transferred to either of the two DAC data latches via
a common 8-bit input port. Control input DACA/DACB determines which DAC is to be loaded. The "load"
cycle of the TLC7528 is similar to the "write" cycle of a random-access memory, allowing easy interface
to most popular microprocessor busses and output ports. Segmenting the high-order bits minimizes glitches
during changes in the most significant bits, where glitch impulse is typically the strongest.
The TLC7528 operates from a 5-volt to 15-volt power supply and dissipates less than 15 mW (typical).
Excellent 2- or 4-quadrant multiplying makes the TLC7528 a sound choice for many microprocessor-
controlled gain-setting and signal-control applications.
The TLC75281 is characterized for operation from - 25 to 85C. The TLC7528C is characterized for
operation from OOC to 70C.
2:
o
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(.)
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ADVANCED LinCMOS is a trademark of Texas Instruments Incorporated
IIreproduction phase of development. Characteristic
TEXAS 2-251
without notice. INSTRUMENlS
TLC7528 ADVANCE
Advanced LinCMOS DUAL 8BIT MULTIPLYING INFORMATION
11
c

REFA
(4)
(3) RFBA
(2) QUTA
...
Q)
Q)
DATA
INPUTS

INPUT
BUFFER
8

n
.c
c (1) AGND
;n'
;:::;"
0' ~_ _~~1:..;.19;;.:.) RFBB
::J
n "Ir-_~12=O) OUTB
::;' ~/DACB(6)
n WR (16 ) LOGIC
c CONTROL
::;: ~(15)
en
REFB
operating sequence
tsulCS) 14 .1 thlCS)
CS------~I~__________________
!
I
I J
,. tsuiDAC) ~ ~ thIDAC)
I
--~~-\:
DACA/DACB ~ ____________ ~~-JI !
WR-----------~
jf--twIWR)---+i
if,~ -----------
j4--tsUID)~thID)
J>
C DBO-DB7 ________ --JX DATA IN STABLE X,.-------
<
J>
2
"-m
2
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o
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~
J>
::!
o
2
2-252 TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 , DALLAS, TEXAS 75265
ADVANCE TLC7528
INFORMATION Advanced LinCMOS DUAL 8BIT MULTIPLYING
Supply voltage, VDD (to AGND or DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to 16.5 V
Voltage between AGND and DGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. VDD
Input voltage, VI (to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to VDD +0.3
Reference voltage, VrefA or VrefB (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25 V
Output voltage, VOA or VOB (to AGND) ....................................... 25 V ....en
Peak input current ....................................................... " 10 p,A 'S
Operating free-air temperature range: TLC75281 .......................... - 25 DC to 85 DC
TLC7528C ............................ ODCto 70 DC
...
CJ
U
Storage temperature range .......................................... - 65 DC to 150 DC
c
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260 DC o
'';::;
'(j)
'S
voo - 4.75 V to 5.25 V voo - 14.5 V to 15.5 V C'
UNIT CJ
MIN NOM MAX MIN NOM MAX <t
Reference voltage, vrefA or VrefB 10 10 V
High-level input voltage, VIH 2.4 13.5 V ....COCO
Low-level input voltage, VIL 0.8 1.5 V C
CS setup time, tsu(CS) 50 50 ns
CS hold time, th(CS) 0 0 ns
DAC select setup time, tsu(DAC) 50 50 ns
DAC select hold time, th(DAC) 10 10 ns
Data bus input setup time tsu(D) 25 25 ns
Data bus input hold time th(D) 0 0 ns
Pulse duration, WR low, tw(WR) 50 50 ns
I TLC75281 -25 85 -25 85
Operating free-air temperature,.T A I TLC7528C 0 70 0 70
c
2
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TEXAS 2-253
INSTRUMENTS
TLC7528 ADVANCE
electrical characteristics over recommended operating free-air temperature range,

VrefA VrefB
0:::: 10 V, VOA and VOB at 0 V (unless otherwise noted)
0::::
VDD - 5 V VDD - 15 V
MIN Tvpt MAX MIN Tvpt MAX
IIH High-level input current VI = VOO 10 10 p.A
IlL Low-level input current VI = 0 V -10 -10 p.A
Reference input impedance
8 11 15 8 11 15 kO
(Pin 15 to GNO)
OACA data latch loaded
OUTA with 00000000, 400 200
Output leakage VrefA = 10 V
II kg nA
current OACB data latch loaded
OUTB with 00000000, 400 200
VrefB = 10 V
Input resistance match
1% 1%
(REFA to REFB)
DC supply sensitivity,
~VOO = 10% 0.04 0.02 %1%
~ gain/~ VOO
OBO-OB7 at VIHmin or
100 Supply current (quiescent) 1 1 mA
VILmax
100 Supply current (standby) OBO-OB7 at 0 V or VOO 0.5 0.5 mA
OBO-OB7 10 10
Input
Ci WR, CS pF
capacitance 15 15
OACA/OACB
OAC data latches loaded
50 50
Output capacitance, with 00000000
Co pF
(OUTA,OUTB) OAC data latches loaded
120 120
with 11111111
o
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m
:-2
."
o
::D
S
::!
o
:2
2-254 TEXAS
INSTRUMENTS
-1!1
POST OFFlte BOX 655012 DALLAS. TEXAS 75265
ADVANCE TLC7528
INFORMATION Advanced LinCMOSTM DUAL 8BIT MULTIPLYING
operating characteristics over recommended operating freeair temperature range,

VrefA = VrefB = 10 V, VOA and VOB at 0 V (unless otherwise noted)
PARAMETER
Linearity error
Settling time (to 1/2 LSB)
TEST CONDITIONS
See Note 1
MIN
VDD - 5 V
TYP MAX
1/2
100
VDD - 15 V
MIN TYP MAX
1/2
100
UNIT
LSB
ns
II t/)
.....
Gain error See Note 2 2.5 2.5 LSB 'S
I REFA to OUTA
I REFB to OUTB See Note 3
-65 -65
dB
...
(,)
AC feedthrough -65 -65 C3

Temperature coefficient of gain See Note 4 0.007 0.0035 %FSR/OC t:
Propagation delay (from digital input o
See Note 5 80 80 ns '';:;
to 90% of final analog output current
I REFA to OUTB
'en
Channel-to- See Note 6 77 77
dB 'S
channel isolation I REFB to OUTA See Note 7 77 77 C"
(,)
Measured for code transition from
Digital-to-analog glitch impulse area 00000000 to 11111111. 160 440 nVs
<t
CO
TA = 25C .....
Measured for code transition from
CO
C
Digital crosstalk glitch impulse area 00000000 to 11111111, 30 60 nVs
TA = 25C
Vi = 6 V rms, f = 1 kHz,
Harmonic distortion -85 -85 dB
TA = 25C
NOTES: 1. OUTA, OUTB load = 100 0, Cext = 13 pF; WR and CS at 0 V; DBO-DB7 at 0 V to VDD or VDD to 0 V.
2. Gain error is measured using an internal feedback resistor. Nominal Full Scale Range (FSR) = Vref - 1 LSB.
3. Vref = 20 V peak-to-peak, 100-kHz sine wave; DAC data latches loaded with 00000000.
4. Temperature coefficient of gain measured from 0 DC to 25C or from 25 C to 70C.
5. VrefA = VrefB = 10 V; OUTA/OUTB load = 1000, Cext = 13 pF; WR and CS atO V; DBO-DB7 atO Vto VDD or VDDto 0 V.
6. Both DAC latches loaded with 11111111; VrefA = 20 V peak-to-peak, 100-kHz sine wave; VrefB '" 0; T A = 25C.
7. Both DAC latches loaded with 11111111; VrefB '" 20 V peak-to-peak, 100-kHz sine wave; VrefA = 0; TA = 25C.
The TLC7528 contains two identical8-bit multiplying D/A converters, DACA and DACB. Each DAC consists
of an inverted R-2R ladder, analog switches, and input data latches.'Binary-weighted currents are switched
between DAC output and AGND, thus maintaining a constant current in each ladder leg independent of
the switch state. Most applications require only the addition of an external operational amplifier and voltage
reference. A simplified D/ A circuit for DACA with all digital inputs low is shown in Figure 1. z
Figure 2 shows the DACA equivalent circuit. A similar equivalent circuit can be drawn for DACB. Both o
DACs share the analog ground pin 1 (AGND). With all digital inputs high, the entire reference current flows i=
to OUT A. A small leakage current (llkg) flows across internal junctions, and as with most semiconductor
ac.

devices, doubles every 10 Co is due to the parallel combination of the NMOS switches and has a value
that depends on the number of switches connected to the output. The range of Co is 50 pF to 120 pF
~
a:
maximum. The equivalent output resistance ro varies with the input code from 0.8R to 3R where R is
the nominal value of the ladder resistor in the R-2R network. o
~
Interfacing the TLC7528 to a microprocessor is accomplished via the data bus, CS, WR, and DACA/DACB
control signals. When CS and WR are both low, the TLC7528 analog output, specified by the DACA/DACB
control line, responds to the activity on the DBO-DB7 data bus inputs. In this mode, the input latches are
-z
w
transparent and input data directly affects the analog output. When either the CS signal or WR signal (.)
goes high, the data on the DBO-DB7 inputs is latched until the CS and WR signals,go low again. When z
CS is high, the data inputs are disabled regardless of the state of the WR signal.
The digital inputs of the TLC7528 provide TTL compatibility when operated from a supply voltage of 5 V. >
c
The TLC7528 may be operated with any supply voltage in the range from 5 V to 15 V, however, input
logic levels are not TTL compatible above 5 V.
TEXAS 2-255
INSTRUMENlS
TLC7528 ADVANCE
II
c
C
R
..-'I..1Vv--RFBA
r+ ~-+-- __-+--~~-4~~~-r--~~~---OUTA
C
~----~----__{}-----~--__--------AGND

(')
.c
c
Cii"
;::;."
0" FIGURE 1. SIMPLIFIED FUNCTIONAL CIRCUIT FOR DACA
::::J
o
::;"
RFBA
(')
c R
VREFA-""",~--.......- - - - - -.......- - - -___ ---e--- OUTA
;::;."
UI
-L
256
FIGURE 2. TLC7528 EQUIVALENT CIRCUIT, DACA LATCH LOADED WITH_11111111.
MODE SELECTION TABLE
DACAl
CS WR DACA DACB
DACB
L L L WRITE HOLD
H L L HOLD WRITE
X H X HOLD HOLD
X X H HOLD HOLD
L = low level, H = high level, X = don't care

c
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m
-2
"T1
o::g
S

o-
-I
2-256 TEXAS
INSTRUMENTS
ADVANCE TLC7528
fI
The TLC7528 is capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations
for 2-quadrant and 4-quadrant multiplication are shown in Figures 3 and 4. Input coding for unipolar and
bipolar operation are summarized in Tables 1,and 2, respectively.
vilA)
10 v
...
'S
en
...
(J
C3
VDD~-
(14) DBO
--- --- c
o
'';:;

(7) DB7
INPUT
BUFFER
'0
'S
C"
(J

(6)
I DACAl
DACB ...
CO
CO
(15) CS CONTROL C
(16) WR lOGIC
>-----4t- VOB
RECOMMENDED TRIM
RESISTOR VALUES
R1, R3 500 n Vi/B)
10 V
R2. R4 150 fI
NOTES: 1. R1. R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Make gain adjustment
with digital input of 255.
2. C1 and C2 phase compensation capacitors (10 pF to 15 pF) are required when using high-speed amplifiers to prevent ringing
or oscillation.
FIGURE 3. UNIPOLAR OPERATION (2QUADRANT MULTIPLICATION)
z
o
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TEXAS ~ 2-257
INSTRUMENTS
TLC7528 ADVANCE
Advanced LinCMOSTM DUAL 8BIT MULTIPLYING INFORMATION
DIGlTALTOANALOG CONVERTER

VilA)
10 V R6 (See Note 2)
20 kO
c
S
Q)
VDD~-----------
(14)1 DBO
(') I :
INPUT
BUFFER
.c (7) VOA
c
Ci)'
;::;.'
(6)
0'
::::s (15)
n
::;'
(16)
(')
C VOB
;::;.'
en (See Note 2)
R10
20 kO
NOTES: 1. Rl. R2. R3. and R4 are used only if gain adjustment is required. See table in Figure 5 for recommended values. Adjust Rl
for VOA = 0 V with code 10000000 in DACA latch. Adjust R3 for Vas = 0 V with 10000000 in DACS latch.
2. Matching and tracking are essential for resistor pairs R6. R7. R9. and Rl0.
3. Cl and C2 phase compensation capacitors (10 pF to 15 pF) may be required if Al and A3 are high-speed amplifiers.
FIGURE 4. BIPOLAR OPERATION (4QUADRANT OPERATION)
TABLE 1. UNIPOLAR BINARY CODE TABLE 2. BIPOLAR (OFFSET BINARY) CODE

DAC LATCH CONTENTS DAC LATCH CONTENTS
ANALOG OUTPUT ANALOG OUTPUT
MSB LSBt MSB LSB*
11111111 - Vi (255/256) 11111111 Vi (127/128)
10000001 -Vi (129/256) 10000001 Vi (1/128)
10000000 -Vi (128/256) = -Vi/2 10000000 OV
c
01111111
00000001
-Vi (127/256)
-Vi (1/256)
01111111
00000001
-Vi (1/128)
-Vi (127/128)
<
00000000 - Vi (0/256) = 0 00000000 -Vi (128/128)
2
(")
-m
2
"
o
:c
S
::!
o
2
2-258 TEXAS . .
INSTRUMENTS
ADVANCE TLC7528
INFORMATION Advanced LinCMOS DUAL 8BIT MULTIPLYING
II
microprocessor interface information
A8-A15 ADDRESS BUS ...

rn
ADDRESS A
.------+-----1 DACA/DACB .
'S
U
CJ
CPU
8051
DECODE c
LOGIC o
'';:::;
'Ci)
WRt------i
'S
C'
CJ

ALE
...coco
C
ADO-AD7 DATA BUS
~-------------~~-----~
NOTE: A = decoded address for TLC7528 DACA.

A+ 1 = decoded address for TLC7528 DACB.
FIGURE 5. TLC7528 - INTEL 8051 INTERFACE
A8-A15 ADDRESS BUS

I---~
A
r-----.----t DACA/DACB
ADDRESS
VMA DECODE
LOGIC
CPU
6800
z
o
i=
cd:
~
DO-D7 DATA BUS a:
oL1.
NOTE: A = decoded address for TLC7528 DACA.
A+ 1 = decoded address for TLC7528 DACB.
FIGURE 6. TLC7528 - 6800 INTERFACE

-w
Z
U
Z
cd:
>
c
cd:
TEXAS ~ 2-259
INSTRUMENTS
TLC7528 ADVANCE
Advanced LinCMOSTM DUAL 8-BIT MULTIPLYING INFORMATION
DlGlTAL-TO-ANALOG CONVERTER
II
C
m
A8-A15
t---~
ADDRESS BUS
,-----+----fDACA/DACB
r+
m

(')
CS
TLC7528
J:l CPU
r::: Z80-A
iii'
;;'
ci" WRt---L_~
~
o
::;.
(')
r::: 00-07 DATA BUS
;:::;.' ~--------------~------~
(J)
NOTE: A ~ decoded address for TLC7528 DACA.

A + 1 ~ decoded address for TLC7528 DACB.
FIGURE 7. TLC7528 TO Z80-AINTERFACE
programmable window detector

The programmable window comparator shown in Figure 8 will determine if voltage applied to the DAC
feedback resistors are within the limits programmed into the TLC7528 data latches. Input signal range
depends on the reference and polarity, that is, the test input range is 0 to - Vref. The DACA and DACB
data latches are programmed with the upper and lower test limits. A signal within the programmed limits
will drive the output high.
TEST
Voo Vee
INPUT----------,
o TO -Vref 1 krl
l>
o
<
l>
OAT A ,----'--'-~_t
INPUTS '----r--..,.....".'--I
:2 171 DB7 111
PASS/FAIL
('") _-+~~11~5~1 CS AGNOe-~~~__, OUTPUT
m _-4-~..:..11:..::6:.:.f1 WR TLC7528
:-2
_-+......_1.;...6,1 OACA/DACB
"T1 + Vref _-+-....:.1..;.;18;;.:.I~R~E:;.;..F;;;;.B---t
o
::J:J 151 DGND
s:
-l>
RFBB
1191
:::!
o FIGURE 8. DIGITALLY PROGRAMMABLE WINDOW COMPARATOR (UPPER- AND LOWER-LIMIT TESTER)
:2
2-260 TEXAS
INSTRUMENTS
ADVANCE TLC7528

digitally controlled signal attenuator
Figure 9 shows the TLC7528 configured as a two-channel programmable attenuator. Applications include
stereo audio and telephone signal level control. Table 3 shows input codes vs attenuation for a 0 to 15.5 dB
range.
II ..,en
= - 20 = digital
"5
Attentuation db log 10 0/256, 0 input code
...CJ
(3) C3
RFBA (2) c
OUTA o
OUTPUT "';:;
"0
"5
C'"
D~O t---r----, CJ
TLC7528
DB7
CS (15) ..,CO
WR (16)
CO
C
DACA/DACB 1-l-(6;:.:)_ _ _ _ __
(18)
VOB REFB
AGND (1)
DGND (5)
FIGURE 9. DIGITALLY CONTROLLED DUAL TELEPHONE ATTENUATOR
TABLE 3. ATTENUATION vs DACA, DACB CODE

CODE IN CODE IN
ATTN(dB) DAC INPUT CODE ATTN(dB) DAC INPUT CODE
DECIMAL DECIMAL
0 11111111 255 8.0 01100110 102
0.5 11110010 242 8.5 01100000 96
1.0 11100100 228 9.0 01011011 91
1.5 11010111 215 9.5 01010110 86 2
2.0 11001011 203 10.0 01010001 81 o
2.5 11000000 192 10.5 01001100 76
i=
3.0
3.5
10110101
10101011
181
171
11.0
11".5
01001000
01000100
72
68

4.0 10100010 162 12.0 01000000 64 ~
4.5 10011000 152 12.5 00111101 61 a:
5.0 10010000 144 13.0 00111001 57 oLL
5.5 10001000 136 13.5 00110110 54
6.0 10000000 128 14.0 00110011 51 2
6.5 01111001 121 14.5 00110000 48
7.0 01110010 114 15.0 00101110 46 w
7.5 01101100 108 15.5 00101011 43
(.)
2

>
c

TEXAS ~ 2-261
INSTRUMENTS
TLC7528 ADVANCE
Advanced LinCMOSTM DUAL 8BIT MULTIPLYING INFORMATION

programmable state-variable filter
II This programmable state-variable or universal filter configuration provides low-pass, high-pass, and band-
pass outputs, and is suitable for applications in which microprocessor control of filter parameters is required.
As shown in Figure 10, DACA 1 and DACB1 control the gain ami Q of the filter while DACA2 and DACB2
control the cutoff frequency. Both halves of the DACA2 and DACB2 must track accurately in order for
the cutoff-frequency equation to be true. With the TLC7528, this is easily achieved.
1
fc = 2rc R1 C1
The programmable range for the cutoff or center frequency is 0 to 15 kHz with a Q ranging from 0.3 to
4.5. This defines the limits of the component values.
C3
VI_....;.14....;.)~R;.;,;EF~A=---~
DATA
IN __--+-HIGH PASS
OUT
RFBBt"I_19..;..)_ _ _ _ _~
(18)
BANDPASS
OUT
c
DATA
IN
<
lOW PASS
OUT
2
om
CIRCUIT EQUATIONS:
-2 DACA2 AND DACB2

C1 - C2. R1 R2. R4 R5
R3 RF
'TI Q.
o:a R4 Rfb(DACB1)
_ RF
S Ao - RS
NOTES: A. Op-amps A 1. A2, A3, and A4 are TL287.

B. C3 compensates for the op-amp gain-bandwidth limitations.
::! C. DAC equivalent resistance equals

256 x (DAC ladder resistance)
o DAC digital code
2 FIGURE 10. DIGITALLY CONTROLLED STATE-VARIABLE FILTER
2-262 TEXAS . .
INSTRUMENlS
PRODUCT TLC75331, TLC7533C
PREVIEW Advanced LinCMOS 1081T MULTIPLYING
DlGITALTOANALOG CONVERTERS
02166, OCTOBER 1986
ADVANCED LinCMOSTM Silicon-Gate N DUAL-IN-L1NE PACKAGE


Fast Settling Time
CMOS/TTL Compatible (MSB) BIT
OUT1
OUT2
GND
1
RFB
REF
VDD
BIT 10 (LSB)
BII
....
(I)
BIT 2 BIT 9 ':5

FourQuadrant Multiplication
BIT 3 BIT 8 ...
(.)
Designed to be Interchangeable with Analog BIT 4 BIT 7 U

Devices AD7533. AD7520. and PMI BIT 5 BIT 6 c:
PM-7533 0
'';:::;
'Ci)
KEY PERFORMANCE
':5
SPECIFICATIONS C"
Resolution (.)
10 Bits
Linearity Error 1/2 LSB <C
Power Dissipation 30mW ....COCO
Settling Time 150 ns
C
description
The TLC7533 is an ADVANCED LinCMOSTM 10-bit digital-to-analog converter featuring two- and four-
quadrant multiplication.
The TLC7533 is pin and functionally equivalent to the AD7520 and AD7533. Texas Instruments advanced
thin-film-on-monolithic-CMOS fabrication process provides 10-bit linearity without laser trimming.
The TLC7533 features TTL or CMOS compatibility with low input leakage currents from 5-V to 15-V power
supplies. Output scaling is provided by an internal feedback resistor and an external operational amplifier.
Both positive and negative reference voltages can be utilized.
The TLC75331 is characterized for operation from - 25C to 85 C. The TLC7533C is characterized for
operation from OOC to 70 o C.
~
w
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ex:
c..
I-
(.)
::::l
C
oex:
ADVANCED LinCMOS is a trademark of Texas Instruments Incorporated c..
on products in the formative or design Jlhase of
development_ Characteristic data anil other
specifications are design goals. Talas Instruments
-1!1
TEXAS
INSTRUMENTS
2-263
TLC75331, TLC7533C PRODUCT
Advanced LinCMOSTM 1081T MULTlPLVING PREVIEW
DIGIT ALTOANALOG CONVERTERS
Supply voltage, VDD (see Note 1) ....................... -............. -0.3 V to 16.5 V
II
c
D)
Digital input voltage, VI ........................................ , - 0.3 to VDD + 0.3 V
Reference voltage, Vref .................................................. "
Operating free-air temperature range: TLC75331 .......................... - 25C to 85 C
TLC7533C ............................ OOC to 70C
25 V
r+
D)
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . .. . . . . . . . . . . . . . . . .. 260C

(')
NOTE 1: All voltage values are with respect to the network ground terminal.
.c
c
;" recommended operating conditions
;:;'"
ci"
::l
MIN NOM MAX UNIT
Supply voltage, VDD 5 16.5 V
o
::;"
Reference voltage, Vref 10 V
(') High-level input voltage, VIH 2.4 V
c Low-level input voltage, VIL 0.8 V
;:;: .. I TLC75331 -25 85
en Operatmg free-air temperature, TA I TLC7533C C
0 70
electrical characteristics over recommended operating temperature range, Voo .. 15 V,

Vref ... 10 V, OUT1 and OUT2 at 0 V (unless otherwise noted)
II Input leakage current, digital input VI =0 or VDD 1 p.A
q Input resistance (pin 15) (see Note 2) 5 20 kO
Output leakage current

oun Digital inputs at VIL 200
nA
II kg
OUT2 Digital inputs at VIH 200
Supply voltage sensitivity VDD = 14 V to 16.5 V,
k svs 0.008 %1%
(AAv/AVDD) (see Note 3) Digital inputs at VIH
100 Supply current 2 mA
Ci Input capacitance, digital input VI = VIL 10 pF
oun Digital inputs at VIH
100
OUT2 35
Co Output capacitance pF
oun Digital inputs at VIL
35
OUT2 100
NOTES: 2. Temperature coefficient is approximately - 300 ppm/oC.

3. AV is the ratio of the DAC's external operational amplifier output voltage to the REF input voltage when using the internal
feedback resistor.
""C
::c operating characteristics over recommended operating free-:air temperature range, VOO 15 V,
o Vref'" 10 V, OUT1 and OUT2 at 0 V (unless otherwise noted)
c
c:
('")
PARAMETER
Relative accuracy
TEST CONDITIONS
See Note 4
MIN MAX
0.05
UNIT
%FSR
Gain error Digital inputs at VIH, See Notes 4 and 5 1.5 %FS
-I To 0.05% FSR, RL = 1000,
Output current settling time 150 ns
""C Digital inputs changing from VIH to VIL, or VIL to VIH
::c Digital inputs at VIL,
m Feedthrough error
V.p.f = 10 V sine wave at 100 kHz
0.1 %FSR
S
m NOTES: 4. Practical Full Scale Range (FSR) = Vref - 1 LSB.
5. Gain error is measured using the internal feedback resistor. Full-Scale (FS) = -Vref (1023/1024). Maximum gain change
=E from T A = 25C to minimum or maximum temperature is 0.1 % FSR.
2-264 TEXAS ~
INSTRUMENlS
PREVIEW Advanced LinCMOSTM 1UBIT MULTIPLYING
DIGITALTOANALOG CONVERTERS
The TLC7533 is a 10-bit multiplying D/A converter consisting of an inverted R-2R ladder and analog
switches. Binary-weighted currents are switched between the OUT1 and OUT2 bus lines by NMOS current
switches. The on-state resistances of these switches are binarily scaled so that the voltage drop across
every switch is the same. The OUT1 and OUT2 bus lines should be maintained at the same potential so
that the current in each ladder leg remains constant and is independent of the switch state. Most applications
II en
.....
require only the addition of an external operational amplifier and a voltage reference.
The equivalent circuit for all digital inputs low is shown in Figure 1. With all of the digital inputs low, the u
.
"S
(,)
entire reference current, Iref, is switched to OUT2 as shown in Figure 2. The current source Iref/1024 c
represents the constant current flowing through the termination resistor of the R-2R ladder; while the current o
"';;
source Ilkg represents leakage currents to the substrate. The output capacitances, Co (1) and Co (2), are "Ci)
due to the capacitance of the NMOS current switches and vary with the switch state. With all digital inputs 'S
low, all of the current switches and the entire resistor ladder are switched to the OUT2 bus line. The C"
(,)
capacitance appearing at OUT2 is a maximum of1 00 pF; at OUT1 there is a maximum of 35 pF. With
all digital inputs high, all of the current switches are switched to OUT1, and 100 pF maximum appears
at OUT1. A maximum of 35 pF appears at
OUT2 as shown in Figure 3. co
.....
co
R R R C
2R
~--~-.~--~e-~-r~f~~~~---------OUT2
~--~__----~~'r--~~~'-~R~--OUT1
L...-J\N\r-- RFB
FIGURE 1. SIMPLIFIED DAC CIRCUIT - ALL DIGITAL INPUTS LOW
rr,
R R
RFB 'ref
-+
OUT1
R
Ilk,j = 135" 'ref/1024~
Vref-'\""'-....------~.-----...-----OUT2
A-r--
0UT2
sw
IIk,t~ 135 " :>w
FIGURE 2. DAC EQUIVALENT CIRCUIT - FIGURE 3 .. DAC EQUIVALENT CIRCUIT -
a:
0-
ALL DIGITAL INPUTS LOW ALL DIGITAL INPUTS HIGH
....
(.)
::l
C
oa:
0-
TEXAS ~ 2-265
INSTRUMENTS
Advanced LinCMOSTM 10BIT MULTIPLVING PREVIEW
DlGlTALTOANALOG CONVERTERS
II
c
Q)
The TLC7533 is capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations
for 2-quadrant or 4-quadrant multiplication are shown in Figures 4 and 5. Input coding for unipolar and
bipolar operation are summarized in Tables 1 and 2, respectively.
15 V VI
r+
Q) RA - 2 kfl
(see Note 6)
l>
(')
RB (see Note 6)
.c
c
iii" VDD'
::;." BIT1
DIGITAL
S"
::I INPUT ~-.....-Vo
(D)
o:::;"
(')
c
::;."
til
FIGURE 4. UNIPOLAR OPERATION (2-QUADRANT MULTIPLICATION)

15 V VI
RA - 2 kfl
(see Note 6) 20 kfl 20 kfl
RB (see Note 6)
VDD REF
Vo
INPUT
.
DIGITAl.--.........--t BIT1

(D) BI;10
FIGURE 5. BIPOLAR OPERATION (4-QUADRANT OPERATION)

NOTES: 6. RA and RB are used only if gain adjustment is required.
""C 7. C1 (10-33 pF) may be required for phase compensation when using high-speed op-amps_
::tJ
o TABLE 1. UNIPOLAR BlNARy'CODE TABLE 2. BIPOLAR (OFFSET BINARY) CODE
C DAC DIGITAL INPUT
ANALOG OUTPUT
DAC DIGITAL INPUT
ANALOG OUTPUT
C MSB LSBt MSB LSB:t
(') 1111111111 -VI (1023/1024) 1111111111 +VI (511/512)
-I 1000000001 -VI (513/1024) 1000000001 +VI (1/512)
1000000000 -VI (512/1024) = -Vref/2 1000000000 0
""C 0111111111 -VI (511/1024) 0111111111 -VI (1/512)
::tJ
m 0000000001 -VI (111024) 0000000001 -VI (511/512)
<
m
0000000000
t1 LSB = (2- 10) VI

- VI (0/1024) = 0 0000000000 -VI (512/512) = -VI
~
:t 1 LSB = (2 - 9) VI
2-266 TEXAS
INSTRUMENTS
-111
PREVIEW Advanced LinCMOSTM 1OBIT MULTIPLYING
DlGITALTOANALOG CONVERTERS
The TLC7533 may be used in voltage output operation as shown in Figure 6. In this configuration, the
input voltage is applied to the OUT1 terminal and the output voltage is taken from the REF terminal. The
output voltage varies with the digital input code according to the equation shown. The output should be
buffered to prevent loading errors due to the high output resistance of this circuit (typically 10 kilohms).
The input voltage should not exceed 1.5 volts to ensure nonlinearity errors less than 1 LSB.
....en
'S
...CJ
15 V
C3
c
o
'';:;
'm
DIGITALr-~--t BI:1 ~-_VI s1.5V 'S
C"
INPUT CJ
(D) ~
....caca
C
FIGURE 6. VOLTAGE OUTPUT OPERATION
By connecting the DAC in the feedback of an op-amp as shown in Figure 7, the circuit behaves as a
programmable gain amplifier with the transfer function: .
Vo = -VI CO~4)
where D Digital Input Code (expressed as a decimal number)
15 V
GAIN TABLE
D VONI
1023 -1.00097
512 -2
DIGITAL
256 -4
INPUT Vo
(D) 128 -8
2 -512
1 -1024
0 open loop
FIGURE 7. PROGRAMMABLE GAIN AMPLIFIER
TEXAS . . 2-267
INSTRUMENTS
Advanced LinCMOSTM 1OBIT MULTIPLYING PREVIEW
DlGlTALTOANALOG CONVERTERS
III
c
Q)
The programmable function generator shown in Figure 8 produces both square and triangular wave output
at a frequency determined by the digital input code. The digital input of the digitally programmable limit
detector shown in Figure 9 determines the trip point of the PASS/FAIL output. For a digital input of
00000 00000, the threshold is a v,
for 11111 11111, the threshold is - Vref.
r+
Q)

(")
-.:R:S--
SQUARE WAVE ....---411~:"":":1~Nv-<
.c
c
C;;" 15 V
;:;"
0"
::J
o
~" VDD REF
(")
c
;:;" DIGITAL BIT1
>-____- TRIANGLE
--A/--
en INPUT
(D) WAVE
f - 1 0~4 (8 R~ ex)
Rx == 10 kfl
FIGURE 8. PROGRAMMABLE FUNCTION GENERATOR
15 V Vref
DIGITAL
INPUT PASS/FAIL OUTPUT
(D)
THRESHOLD - - Vref(..E....)
1024
"'C FIGURE 9. PROGRAMMABLE LIMIT DETECTOR

::a
o
c
c
n
-I
"'C
::a
m
<
m
=e
2-268 TEXAS
INSTRUMENTS
-111
PREVIEW Advanced LinCMOS 1O-BIT MULTIPLYING
DlGlTAL-TO-ANALOG CONVERTERS
II
15 V Vref
R1
Va ... t/)
DIGITAL
BIT1
REF
R2
.
-S
U
CJ
INPUT c
(D) o
BIT10 + '';:;
'(j)
V o - V ref [~R2
Rl+R2)_ -E- ( R1+R2
1024 Rl )] 'S
C'
CJ
-= where: 0:5 0 :5 1023
<2:
FIGURE 10. MODIFIED SCALE-FACTOR AND OFFSET
... CO
CO
15 V Vref C
10 k!1 10 k!1
r--~--I BITl
MAGNITUDE
Va
BITS :
L.....,r---iBIT10
SIGN B I T - - - - _ ' - - - - - - - - - - - - - - - . . . J
FIGURE 11. 10-BIT AND SIGN MULTIPLYING DAC
~
w
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w
a:
Q.
....
(.)
:J
C
oa:
Q.
TEXAS . . 2-269
INSTRUMENTS
II
C
...
Dl
Dl

(")
.c
c
(ji"
;:+"
C)"
::l
o
::;"
(")
C
;:+"
C/I
2-270
PRODUCT TLC32040M, TLC320401
PREVIEW ANALOG INTERFACE CIRCUIT
02964. FEBRUARY 1987
ADVANCED LinCMOSTM Silicon Gate Process J OR N PACKAGE


14-Bit Dynamic Range ADC and DAC
10-Bit ADC and DAC Linearity Over Any
10-Bit Range
NU
RESET
EODR
FSR
NU
NU
IN+
IN-
II
en
.....

Variable ADC and DAC Sampling Rate Up to
19,200 Samples per Second
Switched-Capacitor Antialiasing Input Filter
DR
MSTR ClK
VDD
AUX IN+
AUX IN-
OUT+
.
"5
~
CJ
REF OUT-
and Output-Reconstruction Filter C
DGTl GND VCC+ o
"~
Serial Port for Direct Interface to SHIFT ClK VCC-
TMS32011, TMS32020, and TMS32025 EODX ANlG GND "en
Digital Processors DX ANlG GND
"5
0"
WORD/BYTE NU CJ
Synchronous or Asynchronous ADC and
DAC Conversion Rates with Programmable
FSX NU
CO
Incremental ADC and DAC Conversion NU - Nonusable; no external connection
.....
CO
Timing Adjustments should be made to these pins C
Serial Port Interface to SN54299 or
SN74299 Serial-to-Parallel Shift Registers
for Parallel Interface to TMS32010 or Other
Digital Processors
description
The TLC32040 is a complete analog-to-digital and digital-to-analog input/output system on a single
monolithic CMOS chip. This device integrates a bandpass switched-capacitor antialiasing input filter, a
14-bit resolution A/D converter, four microprocessor-compatible serial port modes, a 14-bit resolution D/ A
converter, and a low-pass switched-capacitor output-reconstruction filter. The device offers numerous
combinations of Master Clock input frequencies and conversion/sampling rates, which can be changed
via digital processor control.
Typical applications for this IC include modems (7.2-, 8-, 9.6-, 14.4-, and 19.2-kHz sampling rate), analog
interface for digital signal processors, speech recognition/storage systems, industrial process control,
biomedical instrumentation, acoustical signal processing, spectral analysis, data acquisition, and
instrumentation recorders. Four serial modes, which allow direct interface to the TMS32011, TMS32020,
and TMS32025 digital signal processors, are provided. Also, when the transmit and receive sections of
the Analog Interface Circuit (AIC) are operating synchronously, it will interface to two SN54299 or SN74299
serial-to-parallel shift registers. These serial-to-parallel shift registers can then interface in parallel to the
TMS32010, other digital signal processors, or external FIFO circuitry. Output data pulses are emitted to ~
inform the processor that data transmission is complete, or to allow the DSP to differentiate between two w
transmitted bytes. A flexible control scheme is provided so that the functions of the IC can be selected
and adjusted coincidentally with signal processing via software control. :>w
The antialiasing input filter comprises seventh-order and fourth-order CC-type (Chebyshev/elliptic a:
transitional) low-pass and high-pass filters, respectively, and a fourth-order equalizer. The input filter is c..
implemented in switched-capacitor technology and is preceded by a continuous time filter to eliminate
I-
any possibility of aliasing caused by sampled data filtering. When no filtering is desired, the entire composite
filter can be switched out of the signal path. A selectable, auxiliary, differential analog input is provided
o
for applications where more than one analog input is required.
::l
C
o
a:
ADVANCED LinCMOS'" is a trademark of Texas Instruments Incorporated c..
reserves the right to chanu. or discontinue thase
-1!1
TEXAS
INSTRUMENTS
2-271
products without notice. POST OFFICe BOX 655012 t>ALlAs. TeXAS 75265
TLC32040M, TLC320401 PRODUCT
ANALOG INTERFACE CIRCUIT PREVIEW
The A/D and D/A converters each have 14 bits of resolution with 10 bits of integral linearity guaranteed
II
'0
Q)
over any 1O-bit range. The A/D and D/A architectures guarantee no missing codes and monotonic operation.
An internal voltage reference is provided to ease the design task and to provide complete control over
the performance of the IC. The internal voltage is brought out to a pin and is available to the designer.
Separate analog and digital voltage supplies and grounds are provided to minimize noise and ensure a wide
dynamic range. Also, the analog circuit path contains only differential circuitry to keep noise to an absolute
r+
Q)
minimum. The only exception is the DAC sample-and-hold, which utilizes pseudo-differential circuitry.
l> The output-reconstruction filter is a seventh-order CC-type (Chebyshev/elliptic transitional low-pass filter
n
.c with a fourth-order equalizer) and is implemented in switched-capacitor technology. This filter is followed
c
(ii' by a continuous-time filte~ to eliminate images of the digitally encoded signal.
;:;.'
The TLC32040M is characterized for operation over the full military temperature range of - 55C to 125C,
0'
::l and the TLC320401 is characterized for operation from - 40C to 85 C.
(')
::;' functional block diagram
n
c
;:;.' FilTER
f/)
SERIAL
PORT
IN-
AUX IN+
.-
I
MSTR ClK
AUX IN-
__ R~EI~ S'::TI~ _ _ _ _ J SHIFT ClK
I WORD/BYTE
L:-_......,r-----'
OX
FilTER
OUT + 4 - + - - - - - - 1
OUT - + - 1 - - - - - 1
1f
TRANSMIT SECTION
vcc+ vcc- ANlG DTGl VDD

." GND GND (DIG)
::Jl
o
C
c
(")
"""I
."
::Jl
m
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m
~
2-272 TEXAS
INSTRUMENTS
analog input
Two sets of analog inputs, IN +, IN -, and AUX IN +, AUX IN -, are provided. Each input set can be operated
in either differential or single-ended modes, since sufficient common-mode range and rejection are provided.
Normally, the IN + and IN - inputs are used; however, the auxiliary inputs, AUX IN + and AUX IN -, can
II
...
en
be used if a second input is required. The gain for the IN +, IN -, and auxiliary AUX IN + and AUX IN- 'S
inputs can be programmed to either 1, 2, or 4 (see the Gain Control Table). Either input circuit can be ...
(,)
selected via software control. It is important to note that a wide dynamic range is assured by the differential U
internal analog architecture and by the separate analog and digital voltage supplies and grounds. c
o
'';::;
AID bandpass filter, AID bandpass filter clocking, and AID conversion rate timing '(ji
The AID bandpass filter can be selected or bypassed via software control. The frequency response of this 'S
C"
filter is presented in the following pages. This response results when the switched-capacitor filter clock (,)
frequency is 288 kHz. Several possible options can be used to attain a 288-kHz switched-capacitor filter <t
clock. When the filter clock frequency is not 288 kHz, the filter transfer function is frequency-scaled by
the ratio of the actual clock frequency to 288 kHz. The low-frequency roll-off of the high-pass section
...
CO
CO
is 300 kHz. However, the high-pass section low-frequency roll-off can be changed to 200 kHz with a metal C
mask option.
The Internal Timing Configuration and AIC DX Data Word Format sections of this data sheet indicate the
many options for attaining a 288-kHz bandpass switched-capacitor filter clock. These sections indicate
that the RX Counter A can be programmed to give a 288-kHz bandpass-switched capacitor filter clock
for several Master Clock input frequencies.
The AID conversion rate is then attained by frequency-dividing the 288-kHz bandpass switched-capacitor
filter clock with the RX Counter B. Thus, unwanted aliasing is prevented because the AID conversion rate
is an integral submultiple of the bandpass switched-capacitor filter sampling rate, and the two rates are
synchronously locked.
AID converter performance specifications

Fundamental performance specifications for the AID converter circuitry are presented in the AID converter
operating characteristics section of this data sheet. The realization of the AID converter circuitry with
switched-capacitor techniques provides an inherent sample-and-hold. .
analog output
The analog output circuitry is an analog output power amplifier. Both noninverting and inverting amplifier
outputs are brought out of the IC. This amplifier can drive transformer hybrids or low-impedance loads
directly in either a differential or single-ended configuration.
sw
DIA low-pass filter, DIA low-pass filter clocking, and DIA conversion rate timing
The frequency response of this filter is presented in the following pages. This response results when the
:>w
low-pass switched-capacitor filter clock frequency is 288 kHz. Like the AID filter, the transfer function a:
of this filter is frequency-scaled when the clock frequency is not 288 kHz. A continuous-time filter is provided a..
on the output of the D/A low-pass filter to greatly attenuate any switched-capacitor clock feedthrough.
I-
The D/A conversion rate is then attained by frequency-dividing the 288-kHz switched-capacitor filter clock
with TX Counter B. Thus, unwanted aliasing is prevented because the D/A conversion rate is an integral
o::)
submultiple of the switched-capacitor low-pass filter sampling rate, and the two rates are synchronously c
locked. o
a:
a..
TEXAS ~ 2-273
INSTRUMENTS
PRINCIPLES OF OPERATION (continued)
asynchronous versus synchronous operation

If the transmit section of the AIC (low-pass filter and DAC) and receive section (bandpass filter and ADC)
are operated asynchronously, the low-pass and band-pass filter clocks are independently generated from
C the Master Clock signal. Also, the D/A and A/D conversion rates are independently determined. If the
....DIDI transmit and receive sections are operated synchronously, the low-pass filter clock drives both low-pass
and band-pass filters. In synchronous operation, the A/D conversion timing is derived from, and is equal
l>
(')
to, the D/A conversion rate timing. (See description of the WORD/BYTE pin in the Pin Functional Description
.c Section.)
c
(ii"
;:::;'" D/A converter performance specifications
0" Fundamental performance specifications for the D/A converter circuitry are presented in the D/A converter
:::J
operating characteristics section of the data sheet. The D/A converter has a sample-and-hold that is realized
o
:::;" with a switched-capacitor ladder.
(')
c system frequency response correction
;:::;'"
C/I Sin x/x correction circuitry is performed in digital signal processor software. The system frequency response
can be corrected via DSP software to 0.1 dB accuracy to a band-edge of 3000 Hz for all sampling rates.
This correction is accomplished with a first-order digital correction filter, which requires only seven TMS320
instruction cycles. With a 200-ns instruction cycle, seven instructions represent an overhead factor of
only 1.1 % and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the sin x/x Correction Section
for more details).
serial port
The serial port has four possible modes that are described in detail in the pin description section. These
modes are briefly described below.
1. The transmit and receive sections of the AIC are operated asynchronously, and the AIC serial
port interfaces directly with the TMS32011.
2. The transmit and receive sections of the AIC are operated asynchronously, and the AIC serial
port interfaces directly with the TMS32020 and the TMS32025.
3. The transmit and receive sections of the AIC are operated synchronously, and the AIC serial port
interfaces directly with the TMS32011 .
4. The transmit and receive sections of the AIC are operated synchronously, and the AIC serial port
interfaces directly with the TMS32020, TMS32025, or two SN54299 or SN74299 serial-to-
'"tJ parallel shift registers, which can then interface in parallel to the TMS3201 0, to any other digital
jJ signal processor, or to external FIFO circuitry.
o
c testing
c
(')
An addendum accompanying this data sheet fully describes the test capabilities of the IC, provided by
the design.
-I
internal. voltage reference
'"tJ
jJ The internal reference eliminates the need for an external voltage reference, and thus provides overall circuit
m cost reduction. Additionally, the internal reference makes the performance of the IC less susceptible to
S
m
noise. Thus, the internal reference eases the design task and provides complete control over the performance
of the IC. The internal reference is brought out to a pin and is available to the designer. To keep the amount
~ of noise on the reference signal to a minimum, an external capacitor may be connected between REF and
ANLG GND.
2-274 TEXAS . .
INSTRUMENTS
PRODUCT TLC32040M. TLC320401
PRINCIPLES OF OPERATION (continued)
fI
reset
A reset function is provided to initiate serial communications between the AIC and DSP and to allow fast,
cost-effective testing during manufacturing. The reset function will initialize all AIC registers, including
the control register. The reset pin has an internal pull-up resistor. After a negative-going pulse on the RESET ....CI)
pin, the AIC will be initialized. This initialization allows normal serial port communications activity to occur
between AIC and DSP (see AIC DX Data Word Format section). .
'S
U
CJ
loop back c
o
This feature allows the user to test the circuit remotely. In loopback, the OUT + and OUT - pins are internally '~
connected to the IN + and IN - pins. Thus, the DAC bits (d15 to d2), which are transmitted to the DX 'Ci)
pin, can be compared with the ADC bits (d 15 to d2), which are received from the DR pin. An ideal comparison 'S
would be that the bits on the DR pin e'qual the bits on the DX pin. However, in practice there will be some C-
CJ
difference in these bits due to the ADC and DAC output offsets.
The loopback feature is implemented with digital signal processor control by transmitting the appropriate ....COCO
serial port bit to the control register (see AIC Data Word Format section).
C
PIN
DESCRIPTION
NAME NO. 110
ANlG GND 17,18 Analog ground return for all internal analog circuits. Not internally connected to DGTl GND.
AUX IN+ 24 I Noninverting auxiliary analog input stage. This input can be switched into the bandpass filter and A/D converter
path via software control. If the appropriate bit in the Control register is a 1, the auxiliary inputs will replace
the IN + and IN - inputs. If the bit is a 0, the IN + and IN - inputs will be used (see the AIC OX Data Word
Format section).
AUX IN- 23 I Inverting auxiliary analog input (see the above AUX IN + pin description).
DGTL GND 9 Digital ground for all internal logic circuits. Not internally connected to ANlG GND.
DR 5 0 This pin is used to transmit the ADC output bits from the AIC to the TMS320 serial port. This transmission
of bits from the AIC to the TMS320 serial port is synchronized with the SHIFT ClK signal.
DX 12 I This pin is used to receive the DAC input bits and timing and control information from the TMS320. This serial
transmission from the TMS320 serial port to the AIC is synchronized with the SHIFT ClK signal.
EODR 2 0 (See the WORD/BYTE pin description and the Serial Port Timing Diagram.) During the word-mode
timing, this signal is a low-going pulse that occurs immediately after the 16 bits of A/D information have been
transmitted from the AIC to the TMS320 serial port. This signal can be used to interrupt a microprocessor
upon completion of serial communications. Also, this signal can be used to strobe and enable external serial-
to-parallel shift registers, latches, or external FIFO RAM, and to facilitate parallel data bus communications
between the AIC and the serial-to-parallel shift registers. During the byte-mode timing, this signal goes low
after the first byte has been transmitted from the AIC to the TMS320 serial port and is kept low until the
3:
second byte has been transmitted. The TMS32011 can use this low-going signal to differentiate between
the two bytes as to which is first and which is second. -
w
>
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a:
0..
l-
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::J
C
o
a:
0..
TEXAS ~ 2-275
INSTRUMENTS
PIN
DESCRIPTION
NAME NO. I/O
II
c
EODX 11 0 (See the WORD/BYTE pin description and the Serial Port Timing Diagram.) During the word-mode
timing, this signal is a low-going pulse that occurs immediately after the 16 bits of D/A converter and control
or register information have been transmitted from the TMS320 serial port to the AIC. This signal can be used
...
Q)
Q)
to interrupt a microprocessor upon the completion of serial communications. Also, this signal can be used
to strobe and enable external serial-to-parallel shift registers, latches, or an external FIFO RAM, and to facilitate
parallel, data-bus communications between the AIC and the serial-to-parallel shift registers. During the byte-
:t> mode timing, this signal goes low after the first byte has been transmitted from the TMS320 serial port to
n
.c the AIC and is kept low until the liecond byte has been transmitted. The TMS32011 can use this low-going
c signal to differentiate between the two bytes as to which is first and which is second.
(ii'
::+' FSR 4 0 In the serial transmission modes, which are described in the WORD/BYTE pin description, the FSR pin is held
0' low during bit transmission. When the FSR pin goes low, the TMS320 serial port will begin receiving bits from
:::J the AIC via the DR pin of the AIC. The most significant DR bit will be present on the DR pin before FSR goes
(") low. (See Serial Port Timing and Internal Timing Configuration Diagrams.)
:::;'
n FSX 14 0 When this pin goes low, the TMS320 serial port will begin transmitting bits to the AIC via the
c OX pin AIC. In all serial transmission modes, which are described in the WORD/BYTE pin description, the FSX
::+'
en pin is held low during bit transmission (see Serial Port Timing and Internal Timing Configuration Diagrams).
IN+ 26 I Noninverting input to analog input amplifier stage
IN- 25 I Inverting input to analog input amplifier stage
MSTR ClK 6 I The Master Clock signal is used to derive all the key logic signals of the AIC, such as the Shift Clock, the
switched-capacitor filter clocks, and the A/D and D/A timing signals. The Internal Timing Configuration diagram
shows how these key signals are derived. The frequencies of these key signals are synchronous submultiples
of the Master Clock f,requency to eliminate unwanted aliasing when the sampled analog signals are transferred
between the switched-capacitor filters and the AID and D/A converters (see the Internal Timing Configuration).
OUT+ 22 0 Noninverting output of analog output power amplifier. Can drive transformer hybrids or high-impedance loads
directly in either a differential or a single-ended configuration.
OUT- 21 0 Inverting output of analog output power amplifier; functionally identical with and complementary to OUT + .
REF 8 The internal voltage reference is brought out to this pin.
RESET 2 I A reset function is provided to initialize the TA, TA', TB, RA, R~', RB, and control registers. This
reset function initiates serial communications between the AIC and DSP. The reset function will initialize all
AIC registers including the control register. After a negative-going pulse on the RESET
pin, the AIC registers will be initialized to provide an 8-kHz data conversion rate for a 5.184-MHz master clock
input signal. The conversion rate adjust registe~s, TA' and RA', will be reset to 1. The CONTROL register bits
will be reset as follows (see AIC OX Data Word Format section).
d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1
This initialization allows normal serial-port communication to occur between AIC and DSP. This pin has an
." internal pull-up resistor and is set to a high logic level unless it is pulled to ground.
:lJ SHIFT ClK 10 0 The Shift Clock signal is obtained by dividing the Master Clock signal frequency by four. This signal is used
o to clock the serial data transfers of the AIC, described in the WORD/BYTE pin description
C below (see the Serial Port Timing and Internal Timing Configuration diagram).
7 Digital supply voltage, 5 V 5%
C VDD
n VCC+ 20
19
Positive analog supply voltage, 5 V 5%
Negative analog supply voltage - 5 V 5%
-I VCC-
."
:lJ
m
:S
m
~
2-276 TEXAS . .
INSTRUMENTS
PRODUCT TLC32040M, TLC3204D1
PRE~IEW ANALOG INTERFACE CIRCUIT
PIN
DESCRIPTION
NAME NO. 110
WORDIBYTE 13 I This pin, in conjunction with a bit in the CONTROL register, is used to establish one of four serial
modes. These four serial modes are described below. This pin has an internal pull-up resistor and is set to
a logic high unless it is pulled to ground.,
AIC transmit and receive sections are operated asynchronously.
fI ....en
The following description applies when the AIC is configured to have asynchronous transmit and receive sections.
If the appropriate data bit in the Control register is a 0 (see the AIC OX Data Word Format), the transmit and
receive sections will be asynchronous.
.
U
':;
CJ
L Serial port will directly interface with the serial port of the TMS32011 and communicates in two
t:
a-bit bytes. The operation sequence is as follows (see Serial Port Timing diagrams). o
'';:
1. The FSX or FSR pin is brought low.
2. One 8-bit byte is transmitted or one 8-bit byte is received. 'w
':;
3. The EO OX or EODR pin is brought low.
C'
4. The FSX or FSR pin emits a positive frame-sync pulse that is CJ
four Shift Clock cycles wide. ~
5. One a-bit byte is transmitted or one a-bit byte is received.
6. The EODX or EODR pin is brought high.
....COCO
7. The FSX or FSR pin is brought high. C
H Serial port will directly interface with the serial port of the TMS32020 and communicates in one
16-bit word. The operation sequence is as follows (see Serial Port Timing diagrams):
1. The FSX or FSR pin is brought low.
2. One 16-bit word is transmitted or one 16-bit word is received.
3. The ~ or ~ pin is brought high.
4. The EO OX or EODR pin emits a low-going pulse.
AIC transmit and receive sections are operated synchronously.
If the appropriate data bit in the Control register is a 1, the transmit and receive sections will be configured
to be synchronous. In this case, the bandpass switched-capacitor filter and the AID conversion timing will
be derived from the TX Counter A, TX Counter a, and T A, T A', and TB registers, rather than the RX Counter
A, RX Counter B, and RA, RA', and RB registers. In this case, the AIC FSX and FSR timing will be identical,
as will the EODX and EODR timing. The synchronous operation sequences are as follows (see .serial Port Timing
diagrams).
L Serial port will directly interface with the serial port of the TMS32011 and communicates in two
8-bit bytes. The operation sequence is as follo~s (see Serial Port Timing diagrams):
1. The FSX and FSR pins are brought low.
2. One a-bit byte is transmitted and one 8-bit byte is received.
3. The EODX and EOD~ pins are brought low.
4. The FSX and FSR pins emit positive frame-sync pulses that are
four Shift Clock cycles wide.
5. One 8-bit byte is transmitted and one a-bit byte is received.
~
6. The EODX and EODR pins are brought high. w
H
7. The FSX and FSR pins are brought high.
Serial port will directly interface with the serial port of the TMS32020 and communicates in one
:>w
16-bit word. The ope~ation sequence is as follows (see Serial Port Timing diagrams):
1. The FSX and FSR pins are brought low.
a:
Il.
2. One 16-bit word is transmitted and one 16-bit word is received.
3. The FSX and FSR pins are brought high. ....
(.)
4. The EODX or EODR pins emit low-going pulses.
Since the transmit and receive sections of the AIC are now synchronous, the AIC serial port, with additional :::::>
NOR and AND gates, will interface to two SN54299 or SN74299 serial-to-parallel shift registers. Interfacing c
the AIC to the SN54299 or SN74299 shift register allows the AIC to interface to an external FIFO RAM and
facilitates parallel, data bus communications between the AIC and the digital signal processor. The operation
o
a:
sequence is the same as the above sequence (see Serial Port Timing diagrams). Il.
TEXAS ~ 2-277
INSTRUMENTS
TLC32040M. TLC320401 PRODUCT
INTERNAL TIMING CONFIGURATION
MASTER CLOCKr - - - - - - - - - - -, SHIFT CLOCK

5.184 MHz (1)1 DIVIDE BY 4 1 - - - - - - - + - - - - + 1 . 2 9 6 MHz (1)
10.368 MHz (2) _ _ _ _ _ _ _ _ _ _ _ _ .J 2.592 MHz (2)
...c
Q)
Q)
-------,
(") LOWPASS
.c SWITCHED
c OPTIONAL EXTERNAL CIRCUITRY DIVIDER CIRCUITRY CAP FILTER
(ii' FOR FULL DUPLEX MODEMS CLK - 288 kHz
;::;' - - ~s3.6kHz- - - --, SQUARE WAVE
0' DIVIDE CLOCK (1) COMMERCIAL I
:::s
BY 135 EXTERNAL I
n
:::;'
FRONT-END I
FULL-DUPLEX
(")
C
I SPLIT-BAND I
FILTERSt I
;::+'
en L __________ :.J TX COUNTER B
TB-40; 7.2 kHz DIA
TB - 36; 8.0 kHz CONVERSION
TB-30; 9.6kHz FREQUENCY
TB-20; 14.4 kHz
TB-15; 19.2 kHz
8ANDPASS
SWITCHED
DIVIDER CIRCUITRY CAP FILTER
CLK - 288 kHz
SQUARE WAVE
RB-40; 7.2kHz
AID
RB - 36; 8.0 kHz
CONVERSION
RB - 30; 9.6 kHz
FREQUENCY
RB-20; 14.4 kHz
L ____ _
RB-15; 19.2 kHz
__ ~_J
."
:lJ NOTE: Frequency 1, 20.736 MHz, is used to show how 153.6 kHz (for a commercially available modem splitband filter clock), popular
o speech and modem sampling signal frequencies, and an internal 288kHz switched-capacitor filter clock can be derived synchronously
and as submultiples of the crystal oscillator frequency. Since these derived frequencies are synchronous submultiples of the crystal
C frequency, aliasing does not occur as the sampled analog signal passes between the analog converter and switched-capacitor filter
C stages. Frequency 2, 4 i .472 MHz, is used to show that the AIC can work with high-frequency signals, which are used by high-
(") speed digital signal processors.
-I tSplit-band filtering can alternatively be performed after the analog input function via software in the TMS320.
tThese control bits are described in the AIC DX Data Word Format section .
."
:lJ
m
~
m
~
2-278 TEXAS . "

INSTRUMENTS
pest OFFICE BOx 655012 DALLAs. TXAS 11i2liS
explanation of internal timing configuration

All of the internal timing of the AIC is derived from the high-frequency clock signal that drives the Master
Clock input pin. The Shift Clock signal, which strobes the serial port data between the AIC and DSP, is
derived by dividing the Master Clock input signal frequency by four.
TX Counter A and TX Counter B, which are driven by the Master Clock signal, determine the DJA conversion
period timing. Similarly, RX Counter A and RX Counter B determine the A/D conversion period timing. In
II
...
en
order for the switched-capacitor low-pass and band-pass filters to meet their transfer function specifications, '5
the frequency of the clock inputs of the switched-capacitor filter must be 288 kHz. If the frequencies of ...
(J
the clock inputs are not 288 kHz, the filter transfer function frequencies are scaled by the ratios of the C3
clock frequencies to 288 kHz. Thus, to obtain the specified filter responses, the combination of Master c
Clock frequency and TX Counter A and RX Counter A values must yield 288-kHz switched~capacitor clock
o
'';:'
signals. These 288-kHz clock signals can then be divided by the TX Counter Band RX Counter B to establish 'Ci)
the DJA and A/D conversion period timings. '5
C"
TX Counter A and TX Counter B are reloaded every D/A conversion period, while RX Counter A and RX (J
Counter B are reloaded every AJD conversion period. The TX Counter Band RX Counter B are loaded with
the values in the TB and RB Registers respectively. Via software control, the TX Counter A can be loaded
with either the TA Register, the TA Register less the TA' Register, or the TA Register plus the TA' Register.
...
CO
CO
By selecting the T A Register less the T A' Register option, the upcoming conversion period timing will occur C
earlier by an amount of time that equals T A' times the signal period of the Master Clock. By selecting
the T A Register plus the T t .. Register option, the upcoming conversion period timing will occur later by
an amount of time that equals T A' times the signal period of the Master Clock. Thus, the DJ A conversion
timing can be advanced or retarded. An identical ability to alter the AID conversion timing is provided.
In this case, however, the RX Counter A can be programmed via software control with the RA Register,
the RA Register less the RA ' Register, or the RA Register plus the RA' Register.
The above feature is particularly useful for modem applications. This feature allows controlled changes
in the AJD and DJA conversion timing. This feature can be used to enhance signal-to-noise performance,
to perform frequency-tracking functions, and to generate nonstandard modem frequencies.
If the transmit and receive sections are configured to be synchronous (see WORD/BYTE pin description),
then both the low-pass and bandpass switched-capacitor filter clocks are derived from TX Counter A. Also,
both the D/A and A/D conversion timing are derived from the TX Counter A and TX Counter B. When the
transmit and receive sections are configured to be synchronous, the RX Counter A, RX Counter B, RA
Register, RA' Register, and RB Registers are not used.
.~
w
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ex:
0.
I-
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c
o
ex:
c..
TEXAS ~ 2-279
INSTRUMENTS
POST OFFICE 80)( 6Sso12 DALLAS. tEXAS 75265
AIC OR or OX word bit pattern

A/O or 01 A MSB
1st bit sent 1st bit sent of 2nd byte AID or O/A LSB
~ ~ ~
c 1015101410131012101110101 091 osl 07 06 05 04 03 02 01 DO
...
Q)
Q) AIC OX data word format section
l>
n d151d141d131d121d111d10ld91dSld71dSld51d41d21d11dO COMMENTS
.c primary DX serial communication protocol
c _ d15 (MSB) through d2 go to the D/A .... 1 0 0 The TX and RX Counter A's are loaded with the TA and RA register
iii'
;:;.' converter register values. The TX and RX Counter B's are loaded with TB and RB
0' register values.
~ _ d15 (MSB) through d2 go to the O/A The TX and RX Counter A's are loaded with the TA + TA' and
.... 1 0 1
o converter register RA+RA' register values. The TX and RX Counter B's are loaded
:::;' with the TB and RB register values. NOTE: d 1 =0, dO = 1 will cause
n
c the next O/A and AID conversion periods to be changed by the
;:;.' addition of TA' and RA' Master Clock cycles, in which TA' and
en
RA' can be positive or negative or zero. Please refer to the
Conversion Period A":;ustment Error Detection Table .
_ d15 (MSB) through d2 go to the O/A .... 1 1 0 The TX and RX Counter A's are loaded with the T A - T A' and
converter register RA-RA' register values. The TX and RX Coun~er B's are loaded
with the TB and RB register values. NOTE: d 1 =1, dO =0 will cause
the next O/A and AID conversion periods to be changed by the
subtraction of T A' and RA' Master Clock cycles, in which T A' and
RA' can be positive or negative or zero. Please refer to the
Conversion Period Adjustment Error Detection Table .
_ d15 (MSB) through d2 go to the O/A .... 1 1 1 The TX and RX Counter A's are loaded with the TA and RA register
converter register values. The TX and RX Counter B's are loaded with the TB and
RB register values. After a delay of four Shift Clock cycles, a
secondary transmission will immediately follow to program the AIC
to operate in the desired configuration.
NOTE: Setting the two least significant bits to 1 in the normal transmission of OAC information (Primary Communications) to the AIC
will initiate Secondary Communications upon completion of the Primary Communications.
Upon completion of the Primary Communication, m will remain high for four SHIFT CLOCK cycles and will then go low and initiate
the Secondary Communication. The timing specifications for the Primary and Secondary Communications are identical. In this manner,
the Secondary Communication, if initiated, is interleaved between successive Primary Communications. This interleaving prevents
the Secondary Communication from interfering with the Primary Communications and OAC timing, thus preventing the AIC from
"'0 skipping a DAC output. .'
:D
o
C
C
(')
-I
"'0
:D
m
~
m
=E
2-280
INSTRUMENTS
TEXAS -111
secondary OX serial communication protocol

x x I~ to TA register -+Ix x I~ to RA register -+ 1 0 0 d 13 and d6 are MSBs
x 1'- to TA' register
x 1'- to TB register
x x x x x x
-+Ix
-+Ix
x x
1'-
1'-
to RA' register -+1
to RB register -+1
d7 d6 d5 d4 d3 d2
~ CONTROL -+I
0
1 0
1 1
1 d14 and d7 are 2's complement sign bits
d14 and d7 are MSBs
d2 = 0/1 deleteslinserts the bandpass filter

II
... en
REGISTER d3 = 0/1 disables/enables the loopback function S
d4 = 0/1 disables/enables the AUX IN + and AUX IN - pins ...u
d5 = 0/1 asynchronous/synchronous transmit and receive sections U
d6 = 0/1 gain control bits (see Gain Control Section)
c
d7 = 0/1 gain control bits (see Gain Control Section)
.~
o
'Ci)
reset function
S
A reset function is provided to initiate serial communications between the AIC and DSP. The reset function C"
u
will initialize all AIC registers, including the control register. After a negative-going pulse on the RESET <t
pin, the AIC registers will be initialized to provide an 8-kHz AID and D/A conversion rate for a 5.184 MHz
master clock input signal. The AIC, excepting the CONTROL register, will be initialized as follows (see ...
m
m
AIC DX Data Word Format section): C
INITIALIZED
REGISTER
REGISTER VALUE (HEX)
TA 9
TA' 1
TB 24
RA 9
RA' 1
RB 24
The CONTROL register bits will be reset as follows (see AIC DX Data Word Format section):
d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1
This initialization allows normal serial port communications to occur between AIC and DSP. If the transmit
and receive sections are configured to operate synchronously and the user wishes to program different
conversion rates, only the TA, T A', andTB register need to be programmed, since both transmit and receive
timing are synchronously derived from these registers (see the pin descriptions and AIC DX Word Format
sections).
~
->w
W
a:
c..
I-
o
::J
C
oa:
c..
TEXAS
INSTRUMENTS
-1!1 2-281
AIC responses to improper conditions

The Ale has provisions for responding to improper conditions. These improper conditions and the response
II
c
of the Ale to these conditions are presented in Table 1 below:
AIC register constraints

The following constraints are placed on the contents of the Ale registers:
Ol
....
Ol 1 . T A register must be > 1.
:t> 2. T A' register can be either positive, negative, or zero.
(') 3. RA register must be > 1 .
.c
c 4. RA' register can be either positive, negative, or zero.
(ii' 5. (TA register TA' register) must be > 1.
;=;" 6. (RA register RA' register) must be > 1.
0' 7. TB register must be > 1.
::l
(')
::;' TABLE 1. AIC RESPONSES TO IMPROPER CONDITIONS
(')
C IMPROPER CONDITION Ale RESPONSE
;=;" T A register + T A' register = 0 or 1 Reprogram TX Counter A with TA register value
(/I
TA register - TA' register = 0 or 1
TA register + TA' regi'ster < 0 MOD 64 arithmetic is used to ensure that a positive value is loaded into the TX Counter A,
i.e., TA register + TA' register + 40 HEX is loaded into TX Counter A
RA register + RA' register = 0 or 1 Reprogram RX Counter A with RA register value
RA register - RA' register = 0 or 1
RA register + RA' register = 0 or 1 MOD 64 arithmetic is used to ensure that a positive value is loaded into RX Counter A, i.e.,
RA register + RA' register + 40 HEX is loaded into RX Counter A
T A register = 0 or 1 AIC is shut down
RA register = 0 or 1
TB register = 0 or 1 Reprogram TB register with 24 HEX
RB register = 0 or 1 Reprogram RB register with 24 HEX
AIC and DSP cannot communicate Hold last DAC output
improper operation due to conversion times being too close together

If the difference between two successive D/A conversion frame syncs is less that 1/19.2 kHz, the Ale
operates improperly. In this situation, the second D/A conversion frame sync occurs too quickly and there
is not enough time for the ongoing conversion to be completed. This situation can occur if the A and B
registers are improperly programmed or if the A + A' register or A - A' register result is too small. When
incrementally adjusting the conversion period via the A + A' register options, the designer should be very
careful not to violate this requirement -'see diagram below).
"'U
:::JJ
o ~~~~E~~
C
C FSX 'I I
(") ~:R - i4-0NGOING CONVERSION-+!
-I t2 - t1 ~ 1/19.2 kHz
"'U
:::JJ
m
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m
~
2-282 TEXAS . .
INSTRUMENTS
POST OFFICE B'Ox 655012 DALLAS. TEXAS 75265
asynchronous operation - more than one receive frame sync occurring between two transmit frame
syncs
When incrementally adjusting the conversion period via the A + A' or A :.... A' register options, a specific
protocol is followed. The command to use the incremental conversion period adjust option is sent to the
AIC during a FSX frame sync. The ongoing conversion period is then adjusted. However, either Receive
Conversion Period A or B may be adjusted. For both transmit and receive conversion periods, the incremental
FJ
...
tn
conversion period adjustment is performed near the end of the conversion period. Therefore, if there is
sufficient time between t1 and t2, the receive conversion period adjustment will be performed during Receive
Conversion Period A. Otherwise, the adjustment will be performed during Receive Conversion Period B.
.
'5
CJ
C3
The adjustment command only adjusts one transmit conversion period and one receive conversion period.
c
To adjust another pair of transmit and receive conversion periods, another command must be issued during o
a subsequent FSX frame (see figure below). ' '~
'en
'5
u
I"
111114~-----TRANSMIT CONVERSION PERIOD------~~I
U
I

C'
CJ
...CO
CO
C
1 I 1
14--- RECEIVE CON V . _ _ _ RECEIVE CONV.-ti
PERIOD A PERIOD B
asynchronous operation - more than one transmit frame sync occurring between two receive frame
syncs
When incrementally adjusting the conversion period via the A + A 'or A - A' register options, a specific
protocol is followed. For both transmit and receive conversion periods, the incremental conversion period
adjustment is performed near the end of the conversion period. The command to use the incremental
conversion period adjust options is sent to the AIC during a FSX frame sync. The ongoing transmit conversion
period is then adjusted. However, three possibilities exist for the receive conversion period adjustment
in the diagram as shown in the figure below. If the adjustment command is issued during Transmit
Conversion Period A, Receive Conversion Period A will be adjusted if there is sufficient time between t1
and"t2. Or, if there is not sufficient time between t1 and t2, Receive Conversion Period B will be adjusted.
Or, the receive portion of an adjustment command may be ignored if the adjustment command is sent
during a receive conversion period, which is already being or will be adjusted due to a prior adjustment
command. For example, if adjustment commands are issued during Transmit Conversion Periods A, B,
and C, the first two commands may cause Receive Conversion Periods A and B to be adjusted, while the
~
third receive adjustment command is ignored. The third adjustment command is ignored since it was issued
during Receive Conversion Period B, which already will be adjusted via the Transmit Conversion Period B
adjustment command.
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I I 1 1
I4-TRANSMIT CONV.~TRANSMIT CONV.~TRANSMIT CONV .... I-
PERIOD A PERIOD B PERIOD C o
t2 :::l
FSRU1
U
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Lr
I
C
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a:
!4-----RECEIVE CONVERSION PERIOD A ~ RECEIVE CONVERSION PERIOD B---"".~I Q.
TEXAS ~ 2-283
INstRUMENTS
asynchronous operation - more than one set of primary and secondary DX serial communication
occurring between two receive frame sync (see Ale DX Data Word Format section)
lEI
c
D,)
The TA, TA', TB, and control register information that is transmitted in the secondary communications
is always accepted and is applied during the ongoing transmit conversion period. If there is sufficient time
between t1 and t2, the TA, RA', and RB register information, which is sent during Transmit Conversion
Period A, will be applied to' Receive Conversion Period A. Otherwise, this information will be applied during
r+ Receive Conversion Period B. If RA, RA', and RB register information has already been received and is
D,)
being applied during an ongoing conversion period, any subsequent RA, RA', or RB information that is

(')
received during this receive conversion period will be disregarded (see diagram below).
.c t1
c PRIMARY SECONDARY PRIMARY SECONDARY PRIMARY SECONDARY
(ii'
;:;:
0'
::s
(") TRANSMIT I TRANSMIT I TRANSMIT I
:;' ....---CONVERSION---~~t-Ilf----CONVERSION-----1~~Iff----CONVERSION---~~~I
(')
PERIOD A PERIOD B PERIOD C
c
;:;:
u
tn
+- RECEIVE CONVERSION_~If-_____
PERIOD A ~14 RECEIVE CONVERSION PERIOD B-----~~I
I
u
absolute maximum ratings over ~perating free-air temperature range (unless otherwise noted)
Supply voltage, VCC + (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 15 V
Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 15 V
Output voltage, Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 15 V
Input voltage, VI .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .- 0.3 V to 15 V
Digital ground voltage .............................................. - 0.3 V to 15 V
Operating free-air temperature range: TLC32040M ....................... - 55 DC to 125 DC
TLC320401 ......................... - 40 DC to 85 DC
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300 DC
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ............ 260 DC
NOTE 1: Voltage values for maximum ratings are with respect to vee - .
."
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C
('")
-I
."
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m
~
m
~
2-284 TEXAS
INSTRUMENTS

PARAMETER MIN NOM MAX UNIT
Supply voltage, Vcc + (see Note 2)
Supply voltage, Vcc _ (see Note 2)
Digital supply voltage, VDD (see Note 2)
Digital ground voltage with respect to ANLG GND, DGTL GND
4.75
-4.75
4.75
-5
5
5
0
5.25
-5.25
5.25
V
V
V
V
II
...en
Low-level input voltage, VIL (see Note 3)
Load resistance at OUT + and/or OUT -, RL
-0.3
2
300
VOO+O.3
0.8
V
V
n
"5
C3
..
CJ
Load capacitance at OUT + and/or OUT -, CL 100 pF c

MSTR ClK frequency (see Note 4) 0.075 5 10.368 MHz o
"~
Analog input amplifier common mode input voltage (see Note 5) 1.5 V "Ci)
A/D or D/A conversion rate 19.2 kHz
"5
I TLC32040M -55 125
e
C'
I TLC320401 CJ
-40 85

NOTES: 2. Voltages at analog inputs and outputs, Vec +, and Vce _, are with respect to the ANLG GND terminal. Voltages at digital
inputs and outputs and Vce + (DIG) are with respect to the DGTL GND terminal.
...
CO
CO
3. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet C
for logic voltage levels and temperature only.
4. The bandpass and low-pass switched-capacitor filter responses are only guaranteed when the switched-capacitor clock frequency
is 288 kHz. For switched-capacitor filter clocks at frequencies other than 288 kHz, the filter response is shifted by the ratio
of switched-capacitor filter clock frequency to 288 kHz.
5. This range applies when (IN + - IN -) or (AUX + - AUX -) equals 6 V.
~
->w
W
a:
c..
l-
e.,)
::J
C
oa:
c..
TEXAS
INSTRUMENTS
-1!1 2-285
TLC32040M, TLC3204D1 PRODUCT
ANALOG INTERFACE CIRCUIT . PREVIEW
electrical characteristics over recommended operating free-air temperature range. Vcc+ = 5 V.

VCC- ... -5 V. VOO = 5 V (unless otherwise noted)
total device. MSTR elK frequency - 5.184 MHz. outputs not loaded
VOH High-level output voltage VDD = 4.75 V. IOH = -300 p.A 2.4 V
c
D) VOL low-level output voltage VDD = 4.75 V. IOl = 2 mA - 0.4 V
r+ Supply current from VCC + 25 mA
D) ICC+ '
ICC- Supply current from VCC- -25 mA
J>
(') Standby current (MSTR ClK, SHIFT ClK.
ICC(stdby) 5 mA
.c or FSR SYNC in static state)
c
(ii'
;:;: receive amplifier input
o::::J PARAMETER TEST CONDITIONS MIN Typt MAX UNIT
AID converter offset error (filters bypassed) 5 20 mV
(')
~. AID converter offset error (filters in) 50 140 mV
(') Common-mode rejection ratio at IN +. IN -
c CMRR See Note 6 55
;:;: or AUX+. AUX-
en Input resistance at IN +. IN-
q 100 kD
or AUX IN+. AUX IN-
transmit filter output

Output offset voltage at OUT + or OUT-
VOO 50 mV
(single-ended relative to ANlG GND)
Maximum peak output voltage swing across Rl <: 300 D.
YOM 3 V
Rl at OUT + or OUT - (single-ended) Offset voltage = 0
Maximum peak output voltage swing between
YOM Rl <: 6000 6 V
OUT + and OUT - (differential output)

NOTE 6: The test condition is a 0 dBm. 1-kHz input signal with an 8-kHz conversion rate .
."
:lJ
o
C
C
('")
-f
."
:lJ
m
~
m
~
2-286 TEXAS ~
INSTRUMENTS
!'OST bFFICE BOX eSS01:! DAllAS. TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, Vee + = 5 V,

vee- -= -5 V, Voo "" 5 V (unless otherwise noted)
specific modem specifications, SCF clock frequency .. 288 kHz
PARAMETER
Attenuation of second harmonic of
transmitted analog signal
single-ended
differential
TEST CONDITIONS
See Note 7
MIN
60
60
Typt
65
65
MAX UNIT
dB
II....en
"S
Attenuation of third and higher
harmonics of transmitted analog signal
single-ended
differential
See Note 7
60
60
65
65
dB ...CJ
U
gain and dynamic range c:
o
"';:
Absolute transmit gain tracking error while transmitting
"Cii
into 600 n (see Note 8)
- 50 to 0 dBm signal range 1.0 dB "S
C-
Absolute receive gain tracking error (see Note 8) - 50 to 0 dBm signal range 1.0 dB CJ

power supply rejection and crosstalk attenuation ....ctSctS
PARAMETER TEST CONDITIONS MIN Typt MAX UNIT C
Idle channel, supply signal 30
VCC + or VCC _ supply voltage f = 0 to 30 kHz
at 200 mV POp measured dB
rejection ratio, receive channel f = 30 kHz to 50 kHz 45
at DR (ADC output)
VCC + or VCC _ supply voltage Idle channel, supply signal 30
f = 0 to 30 kHz
rejection ratio, transmit channel at 200 mV Pop measured dB
f = 30 kHz to 50 kHz 45
(single-ended) at OUT+
Crosstalk attenuation, transmit-to-receive (Single-ended) 80 dB

NOTES: 7. The test condition is a 0 dBm, 1-kHz input signal into 600 n with an 8-kHz conversion rate.
8. Gain tracking is relative to the absolute gain at 1-kHz.
~
w
:>w
ex:
c.
....
(.)
:::)
C
o
ex:
c.
TEXAS ~ 2-287
INSTRUMENTS
delay distortion, SCF clock frequency .. 288 kHz, input (IN + - IN -) is 3-V sinewave
Please refer to filter response graphs for delay distortion specifications.
IJ
c
Q)
bandpass filter transfer function with 300-Hz high-pass roll-off (see curves), SCF clock
frequency - 288 kHz, input (IN + - IN -) is a 3-V sinewave (see Note 9)
r+ f = 100 Hz -45
Q)
= 150 Hz

(") Gain relative to gain at 1 kHz Input signal reference is 0 dB
f
300 Hz s f s 3.4 kHz -0.5
-33
0.5 dB
.c f =4 kHz -16
c f ~ 4.6 kHz -60
tn
;:;'0
0 bandpass filter transfer function with 200-Hz high-pass roll-off (see curves), SCF clock
:s frequency - 288 kHz, input (IN + - IN -) is a 3-V sinewave (see Note 9)
o
:::;0 PARAMETER TEST CONDITIONS MIN MAX UNIT
(")
C
f = 100 Hz -37
;:;.' f = 150 Hz -12
tn Gain relative to gain at 1 kHz Input signal reference is 0 dB 300 Hz s f s 3.4 kHz -0.5 0.5 dB
f =4 kHz -16
f ~ 4.6 kHz -60
low-pass filter transfer function, SCF clock frequency o:::z 288 kHz (see Note 9)
f s 3.4 kHz -0.5 0.5
f = 3.6 kHz -6
Gain relative to gain at 1 kHz Output signal reference is 0 dB dB
f = 4 kHz -30
f ~ 4.4 kHz -60
serial port
VOH High-level output voltage 10H = -300 p.A 2.4 V
VOL Low-level output voltage 10L = 2 rnA 0.4 V
II Input current .10 p.A
CI Input capacitance 15 pF
Co Output capacitance. 15 pF

"0 NOTE 9: The above filter specifications are guaranteed for a switched-capacitor filter clock range of 288 kHz. For switched-capacitor filter
::c clocks at frequencies other than 288 kHz, the filter response is shifted by the ratio of switched-capacitor filter clock frequency
o to 288 kHz.
c
c
(")
-t
"0
::c
m
S
m
~
2-288 TEXAS
INSTRUMENTS
-III
operating characteristics over recommended operating free-air temperature range, Vcc+ = 5 V,

vee - = - 5 V, voo = 5 V
AID converter (2's complement output, 14-bit resolution)
Integral linearity, f =
PARAMETER
4.5 kHz to 19.2 kHz

bit 1 thru bit 10
bit 2 thru bit 11
TEST CONDITIONS
Sixteenth full scale
Eighth full scale
MIN Typt
%
%
MAX UNIT
bit 1
bit 2
II
... fI)
oS
bit 3 thru bit 1 2 Quarter full scale % bit 3
(See Note 10)
bit 4 thru bit 13 Half full scale % bit 4 ...CJ
bit 5 thru bit 14 Full scale % bit 5 U
Conversion rate 1 20 kHz c
Signal-to-quantization distortion ratio (for input signals > - 15 dBm o
0';:;
60 dB
in the 300 Hz to 3400 Hz band) 0Cij
Equivalent input noise (relative to 600 {l) at the ADC input Inputs grounded 75 p.V rms oS
C"
CJ
DIA converter (2's complement input, 14-bit resolution)
PARAMETER TEST CONDITIONS MIN Typt MAX UNIT ...
CO
CO
bit 1 thru bit 10 Sixteenth full scale % bit 1 C
bit 2 thru bit 11 Eighth full scale Y2 bit 2
Integrallinearity,.f = 4.5 kHz to 19.2 kHz
bit 3 thru bit 12 Quarter full scale % bit 3
(See Note 10)
bit 4 thru bit 13 Half full scale Y2 bit 4
bit 5 thru bit 14 Full scale Ya bit 5
Settling time 10 p's
Conversion time 1 20 kHz
noise (measurement includes low-pass and bandpass switched-capacitor filters)

PARAMETER TEST CONDITIONS TYP MAX UNIT
Transmit noises
I single-ended DX input = 00000000000000, constant input code
125
p.Vrms
I differential 250
Receive noise (see Note 11) Inputs grounded, gain = 1 150 p.Vrms
timing requirements
serial port - Ale input signals
PARAMETER MIN MAX UNIT
tc(MCLK) Master clock cycle time 95 ns
tr(MCLKI Master clock rise time 10 ns
tf(MCLK) Master clock fall time 10 ns
Master clock duty cycle 42% 58% ~
tsu(DX) DX setup time before SCLK! 20 ns w
th(DXI DX hold time after SCLK!

t c(SCLKI/2 ns
:>W
NOTES: 10. Integral linearity for the AID and D/A converters is guaranteed over the conversion frequency range of 4.5 kHz to 19.2 kHz. X:
Over this range the slew rates of the AID and D/A converters' sample-and-hold circuits are adequate to guarantee the above c..
integral linearity specifications.
11. This noise is referred to the input with a buffer gain of one. If the buffer gain is two or four, the noise figure will be correspondingly ....
reduced. The noise is computed by statistically evaluating the digital output-of the AID converter. U
::J
C
o
a:
c..
TEXAS ~ 2-289
INSTRUMENTS
operating characteristics over recommended operating free-air temperature range, Vee + == 5 V,

Vee- == -5 V, VDD == 5 V (continued)
IJ
c
Q)
serial port - AIC output signals
tc(SCLKl
tf(SCLK)
Shift clock (SCLK) cycle time
Shift clock (SCLK) fall time
PARAMETER MIN
38
MAX
50
UNIT
ns
ns
r+ Shift clock (SCLK) rise time
Q) tr(SCLK) 50 ns
n td(CH-FL}
Shift clock (SCLK) duty cycle
Delay from SCLKi to FSR/FSX!
45 55
90
%
ns
.c td(CH-FH) Delay from SCLKi to FSR/FSK)i 90 ns
s:::::
(ii' td(CH-DR} DR valid after SCLKi 90 ns
;:::; tdw(CH-EL) Delay from SCLKi to EODX/EODR! in word mode 90 ns
0' tdw(CH-EH) Delay from SCLKi to EODX/EODRi in word mode 90 ns
::::s tf(EODX) EODX fall time 15 ns
n tf(EODR} EODR fall time 15 ns
::;' Delay from SCLKi to EODX/EODR! in byte mode 100 ns
n tdb(CH-EU
s::::: tdb(CH-EH) Delay from SCLKi to EODX/EODRi in byte mode 100 ns
;:::;"
en
analog input signal required for full-scale AID conversion
CONTROL REGISTER BITS AID CONVERSION
INPUT CONFIGURATIONS ANALOG INPUT
d6 d7 RESULT
Differential configuration 1 1 6 V full-scale
Analog input = IN + - IN- a a
= AUX+ - AUX- 1 0 +3 V full-scale
a 1 1.5 V full-scale
Single-ended configuration 1 1 3 V half-scale
Analog input = IN + - ANLG GND a a
= AUX + - ANLG GND 1 0 3 V full-scale
0 1 1.5 V full-scale
Rfb
R
IN+-W~t--f
R
IN--""'~ __-t
."
::D Rfb
o Rfb - R for d6 - 1. d7 - 1
C d6 - O. d7 - 0
Rfb - 2R for d6 -.1. d7 - 0
C Rfb - 4R for d6 - O. d7 m 1
(")
-4 FIGURE 1. IN + AND IN - GAIN CONTROL CIRCUITRY
."
::D
m
<
m
~
2-290 TEXAS ~
INSTRUMENTS
PRODUCT TLC32040M, TLC3204D1
PREVIEW' ANALOG INTERFACE CIRCUIT
Rfb
AUX IN -
R
AUX IN + - " I M.......>--f
R
-'VVIr1I>--f
II
...
en
'S
...CJ
Rfb U
Rfb - R for d6 - 1. d7 - 1 s::::
d6 - O. d7 - 0 o
Rfb - 2R for d6 ~ 1. d7 - 0 '';:::;
Rfb - 4R for d6 - O. d7 - 1
'Ci)
'S
FIGURE 2. AUXILIARY INPUT CIRCUITRY C-
CJ
sin xix correction section

The AIC does not have sin x/x correction circuitry after the digital-to-analog converter. Sin x/x correction
...
CO
CO
can be accomplished easily and efficiently in digital signal processor (DSP) software. Excellent correction C
accuracy can be achieved to a band edge of 3000 Hz by using a first-order digital correction filter. The
results, which are shown below, are typical of the numerical correction accuracy that can be achieved
for sample rates of interest. The filter requires only seven instruction cycles per sample on the
TMS320 DSPs. With a 200-ns instruction cycle, nine instructions per sample represents an overhead factor
of 1.4% and 1.7% for sampling rates of 8000 Hz and 9600 Hz, respectively. This correction will add a
slight amount of group delay at the upper edge of the 300-3000-Hz band.
sin xix roll-off for a zero-order hold function

The sin x/x roll-off for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz for
the various sampling rates is shown in the table below.
TABLE 2. sin x/x ROLL-OFF

sin 'lr fIts
20 log - - -
'lr tIts
t s (Hz)
(f - 3000 Hz)
(dB)
7200 -2.64
8000 -2.11
9600 -1.44
14400 -0.63
~
19200 -0.35 w
Note that the actual AIC sin x/x roll-off will be slightly less than the above figures, because the AIC has :>w
less than a 100 percent duty cycle hold interval.
a:
c..
....
o
::J
C
oa:
c..
TEXAS 2-291
INSTRUMENTS
correction filter
To compensate for the sin xix roll-off of the Ale, the first-order correction filter, which is shown below,
II
c
Q)
is recommended.
U(i+ 1) 1 - - - - - - - - - - - 1 . . - - - . . Y ( i + 1)
r+
Q)

n
.c
c
(ii'
;:::j.'
p1
'0'
::::J
The difference equation for this correction filter is:
(')
:::;'
n Yi+1 = p2(1-p1) (Ui+1)+p1 y1
c
;:::j.'
(I) where the constant p1 determines the pole locations.
The resulting squared magnitude transfer function is:
IH(f)12 = p22 (1 - p1 )2
1 - 2p1 cos(2 7r flfs) + p1 2
'"tJ
::c
o
c
c(')
-I
"C
II
m
<
m
~
2-292 TEXAS
INSTRUMENTS
correction results
Table 3 below shows the optimum p values and the corresponding correction results for 8000 Hz and
9600 Hz sampling rates.
TABLE 3
ERROR (dB) ERROR (dB)
II ....
(I)
"S
f (Hz)
fs - 8000 Hz
p1 - -0.14813
fs - 9600 Hz
p1 - -0.1307 ...CJ
p2 - 0.9888 p2 ~ 0.9951 (3
300 -0.099 -0.043 C
600 -0.089 -0.043 o
".;:=
900 -0.054 0 "0
1200 -0.002 0 S
1500 0.041 0 tr
CJ
1800 0.079 0.043
ct
2100 0.100 0.043
2400 0.091 0.043 ....caca
2700 -0.043 0 o
3000 -0.102 -0.043
TMS320 software requirements

The digital correction filter equation can be written in state variable form as follows:
Y = k1Y +k2U
where Y is the filter state and U is the next I/O sample. With the assumption that TMS processor page
pointer and memory configuration are properly initialized, the equation can be executed in seven instructions
or seven cycles with the following program:
ZAC
LT K2
MPY U
LTD K1
MPYY
APAC
SACH (dmal
~
w
:>w
a:
D.
~
(.)
::J
C
oa:
D.
TEXAS ~ 2-293
INSTRUMENTS
byte-mode timing
IFJ
C
SHIFT CLK
_
41,..tflSCLKI
tdiCH-FlI-+l14-
---.L~ . : :
2 v
I
~\;"--V--------l
:
I
~r--trlSCLKI
0.8 v I
-+lk-tdiCH-FHI
:
~ ~tdiCH-FLI
~tclSCLKI
2
:
v
tdiCH-FHI-+I If-
I-h-v-
...
Dl
Dl
FSR.FSX ~f-'----4f I I
0.8V\
~----jJ J
J..-_ _ _ _ _.....!J1/
I
2V
l> I ..., ~ ~dlCH-ORI I
~~L...--:-I- - -08- - - - -'GITJ/;r-oUL...-_

(')
.c DR 015 ~ 01 _ DO:
.-:.._ __
c I
tij" tsulOXI~ 14-- I I
;:::;'"
ci" ~ I, ___O~OQ!N~'!T.C~A~R~E_ _Ir;-:;-y-;-;t.~
::l OX ~'iJ,-_0_9-1,-_0_8...11)... 07 06 ~
0/ -+I It-thiOXI 4\ I
f4-tdbiCH-ELI
tdbiCH-EH~
I
It-
:::;"
(') -------------~;~f------_~ ~
EOOR.EOOX ~~0~8~V_ _ _ _ _ _ _ _ _ _ _ _ _ _ _~:,f-'_ _ _ _ _ _ _ _ _~!
c
;:::;'"
til
word-mode timing
2V
SHIFT CLK
I I
I 0.8 VI 0.8 V 0.8 V I I
~ r-tdiCH-FlI : tdiCH-FHr+l If- :
~I I ~_______~,'1~2~V~',-----
FSX. FSR 0.8 V\- I I '}- ..
I Ii I I
: -+\ r-tdiCH-ORI , I I
~
OR _ _.;;.0_15_ _ 014 013 012 ~ 01
01}J.D2l DIo l lI
I I
14-
tSUIOXI"4 I I
OX------~0~155lrrO~1~4lf~0~13~D1:iY[0~1~
I I I I
-~ j4-thiOXI tdwiCH-EL~ ~ -+I j4-tdwiCH-EHI
------------------~:~:---------LJI
EOOX. EOOR 0.8 V 2 V
FIGURE 3. SERIAL PORT TIMING .
o"
:a
c
c:
('")
-I
"m
:a
!5
m
~
2-294
INSTRUMENTS
TEXAS -111

TMS32010 FSX
SN74LS299
~ S1 H' OA
DEN G2
YO
Y1 t - - 08-015
\ \
SO
CIT
< t---
7 TLC32040
....rA
s
AO/PAO - A (J
A1/PA1 f--B \ A-H SA t-- a-
\ I
U
~
A2/PA2 f--C Y6~
Vi ~ SN74LS299
SHIFT CLK t:
o
SN74LS138 ~
S1 t-- o~
H'
' - - 02
om
SO
s
C"
' - - - - - 01 (J
00,015
I ,,00-015
\
00-07
\.
\
A-H SA

\ I
OX
....coco
C
WE
CLK OUT
INT
rU MSTR CLK
EOOX
FIGURE 4. TLC32010- TLC32040 INTERFACE CIRCUIT
in instruction timing
CLK OUT
---- ,
~---+I"'.
'I~------------------------------
I
so. G1 I
I
00-015 ------------C( VALID )~------------------
out instruction timing
CLKOUT _ _~
~
w
5=
w
SN74LS138 Y1 ex:
Q.
SN74LS299 elK
I-
00-015
U
( VALID )
::l
FIGURE 5. TMS32010-TMS32040 INTERFACE TIMING C
o
ex:
Q.
TEXAS ~ 2295
INSTRUMENTS
AIC TRANSMIT CHANNEL FILTER

10 0.3
Magnltud~
lEI
C
m
0
-10
-20
\
0.25
0.2
0.15
en
E
1
r+
m
III
~
-30
Group Delay ~ 0.1
>-
III
Cii

(')
~
1
II)
E -40
See Note B"'\. J \ 0.05
c
Q.
::J
.c
c
'2
Cl
-50
(1\ f<f' / \ 0
0
~
i\li 11 \...V
III
(ii'
IJ
II)
~
0.05 .~
V- _....
;:j.'
-60 III
0' I'---
r--_ I-See Note A 1\-
Cii
a:
::s -70 0.1
o
::;' -80
f-f--See Note C rv 0.15
(')
C -90 0.2
;:j.'
til
o 2 3 4 5
Frequency - kHz
NOTES: A. Maximum relative delay ( 0 Hz to 600 Hz) = 125 p.s.
B. Maximum relative delay (600 Hz to 3000 Hz) = 50 p.s.
C. Absolute delay (600 Hz to 3000 Hz) = 700 p.s.
D. VCC+ = 5 V. VCC- = -5 V. SCF clock f = 288 kHz. input = 3-V sinewave. TA = 25C.
FIGURE 6
AIC RECEIVE CHANNEL FILTER (300 Hz)

10 0.35
f- -See Note A
Magnitu~e 0.3
0
-10 0.25 en
-20
1\ 0.2
E
I
III
~
'/ \ >-
III
,,-
-30 0.15 Cii
1
II)
c
~ Q.
E -40 0.1 ::J

'2
Cl
III -50
Group Delay ['\ 0.05
~
0
JU71\ /\
II)
~ .~
-60 0 III
"tJ
:::a -70 UL7W V 0.05
Cii
a:
o -80
L~ee r 1\ Note
y
0.1
c \
See No~e C-
c(") -90
0 2 3 4 5
0.15
Frequency - kHz
-I
"tJ NOTES: A. Maximum relative delay (200 Hz to 600 Hz) = 3350 p.S.
:::a B. Maximum relative delay (600 Hz to 3000 Hz) = 50 p.s:
m C. Absolute delay (600 Hz to 3000 Hz) = 1230 p.s.
< D. VCC+ = -5 V. VCC- = -5 V. SCF clock f = 288 kHz. input = 3-V sinewave. TA = 25C.
m FIGURE 7
:e
2-296 TEXAS
INSTRUMENTS
-III
PRODUCT TLC32040M. TLC320401
AIR RECEIVE CHANNEL FILTER (200 Hz)

10 0.3
Ma~nitude
0 TTl 0.25
f-See Note A
-10 0.2 en
-20 f\ 0.15
E
I
t/)
+J
co
"C
I -30 \ 0.1
>-
(Q
Qj
c
'5
...CJ
Q)
"C
-40 Group Delay
1\ 0.05
Co
:I U
E
2
Cl -50 1\ ...., I \ 0
0
c.; c
o
(Q
~ '"' -=l T 'J \

III
.~
'';::;
-60 f--
f-See Nre B, 0.05 ; 'en
~\ 0.1 '5
Qj
a:
-70 I I
C'
r CJ
See Note C
-80 0.15 <C
CO
-90 +J
0.2 CO
o 2 3 4 5
C
Frequency - kHz
NOTES: A. Maximum relative delay (200 Hz to 600 Hz) = 3350 JlS.
B. Maximum relative delay (600 Hz to 3000 Hz) = 50 Jls.
C. Absolute delay (600 Hz to 3000 Hz) = 1080 JlS.
D. VCC+ = -5 V, VCC- = -5 V, SCF clock f = 288 kHz, input = 3-V sinewave, TA = 25C.
FIGURE 8.
~
w
:>w
a:
c..
....
o
::J
C
oa:
c..
TEXAS 2-297
INSTRUMENTS
c
...
D)
D)
l>
n
.c
c
en
~O
0
::::s
(")
::;0
n
c
~O
(I)
2-298
____G_e_"_e_ra_I_I"_f_O_rm_a_t_iO_"_____
Alphanumeric Index
----i1i
Selection Guide
Data Acquisitio" Circuits

Data Sheets
Display Drivers
Data Sheets
I. ._' _l_i"_e_D_r_iv_e_r_S_a_"_d__R_e_c_e_i_v_e_rs______
1I
Data Sheets
Peripheral Drivers} Actuators

Data Sheets
Memoryl"terface CirctJits
- ---
Data Sheets
Data Sheets
~ ".~~ .. "',."
Spe~ch. SYIl~hesis, Cir~uits

""~.' .
Appendi~A Povver Derating Curves
Appendix B
Explanation of
Logic Symbols
3-1
II
c
Ci)'
"C
Dr
<
...C
<'
...
CD
til
3-2
SN55426B, SN55427B
AC PLASMA DISPLAY DRIVERS
D2520, MARCH 1979-REVISED OCT08ER 1986
90-V Output Swing SN55426B .. J

CMOS-Compatible Inputs (TOP VIEW)
Quad Drivers with Independent Addressing lA 3A
of Each Gate for Serial or Parallel 2A 4A
Applications M VCCl
High Data Input Impedance .. 1 MO Typ S GND

NC VCC2
30-rnA Clamp Diodes on Output 2Y 4Y
lY 3Y
des~ription
The SN554268 and SN554278 are monolithic SN55427B . J

DUAL-IN-LINE PACKAGE
...
(I)
Q)
integrated-circuit plasma display drivers. The
logic of the two drivers is complementary to (TOP VIEW) >
'i:
permit controlled writing or erasing at a specified lA 3A C
point on the display. The '4268 noninverting 2A 4A >
CO
pulser is normally near ground potential and is M VCCl
pulsed near VCC2; the '4278 inverting pulser is
C.
S GND (I)
normally near VCC2 potential and is pulsed near NC VCC2 C
ground potential. The devices are designed to 2Y 4Y
accept CMOS logic input signals and drive one lY 3Y
display line per output.
, There are four gates per package with individual
data inputs. Additionally, each device has a
FUNCTION TABLE
strobe and a multiplex input controlling all four
gates. The devices require two power supplies: INPUTS OUTPUTS
the logic section power supply VCC1, and the A M S '426B '427B
high-voltage bias supply VCC2. VCC2 controls L X X L H
the magnitude of the output swing. X L X L H
X X L L H
Each output is designed to sustain
H H H H L
20-milliampere switching transients on the
output. Each output is also protected by source H = high level, L = low level,
and sink clamp diodes with 30-milliampere X = irrelevant
current capability, Each device is designed to be
operated at 50 kilohertz but may be operated as
high as 85 kilohertz.
The multiplex and strobe inputs (inputs M and
S, respectively) act on all four gates
simultaneously and aid in plasma panel design.
The SN554268 and SN554278 are
characterized for operation over the full military
temperature range of - 55 C to 125 C.
~~~~~:~~i~ai~~1~1~ ~!:~~~ti~r :1~o::~:~:t:~~S not
TEXAS -I./} 3-3
INSTRUMENTS
SN554268, SN554278
logic symbols t
'426B '427B
CMOS/PLASMA CMOS/PLASMA
DISP DISP
M (3)
M
S (4)
S
III
1A (1) 1A (1)
2A (2) 2A (2)
3A (14) 3A (14)
4A (13) 4A (13)
c(ii"
t These symbols are in accordance with ANSI/IEEE Std 91-1984
'C and lEe Publication 617-12.
iir
'<
logic diagrams (positive logic)
..,C
<"
..,CD M (3)
'426B
M (3)
'427B
(/I S (4) S (4)

1A (1) 1A (1)
2Y
2A (2) 2A (2)
3Y
3A (14) 3A (14)
4Y
4A (13) 4A (13)
POSITIVE LOGIC: Y =AMS POSITIVE LOGIC: Y = AMS
EQUIVALENT OF EACH A, M,OR S INPUT TYPICAL OF ALL OUTPUTS
VCC2
VCC1J~~~
INPUT-q ~--~~-4_ OUTPUT
3-4 TEXAS
INSTRUMENTS
SN554268. SN554278
Supply voltage, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Supply voltage, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 95 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Continuous output current, 10 ................ ;............................... 20 rnA
Continuous total dissipation at (or below) 25 DC free-air temperature (see Note 2) . . . . . . .. 800 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. - 55 DC to 125 DC
NOTES:
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds. . . . . . . . . . . . . . . . . .. . .. 300 DC
1. All voltage values are with respect to network ground terminal.

2. For operation above 25C free-air temperature, refer to,Dissipation Derating Curves in Appendix A. In the J package, SN55426B
and SN55427B chips are alloy mounted.
II ...
en
CD
recommended operating conditions >
'':::;
C
MIN NOM MAX UNIT
Supply voltage for logic section, VCCl 10 12 14 V >
CO
Supply voltage for output section, VCC2 40 70 90 V Q.
High-level input voltage, VIH 7 V en
Low-level input voltage, VIL 3 V C
Strobe frequency 0 85 kHz
Data input frequency 0 50 85 kHz
Duration of strobe pulse 1.5 5 p's
Operating free-air temperature, T A -55 125 C
electrical characteristics, VCC1 12V,VCC2 = 70 V, TA = -55Cto125C(unlessotherwise

noted)
VIH = 7 V, 10 = -1 mA VCC2- 4 VCC2 -1
VIL = 3 V 10 = -15 mA VCC2- 8 VCC2- 1.8
VIH = 7 V, 10 = 1 mA 2 4
VOL low-level output voltage V
VIL = 3 V 10 = 15 mA 3.5 8
Output high, 10 = 30 mA VCC2 +0.8 VCC2+2
VOK Output clamp voltage V
Output low, 10 = -30mA -0.9 -2
IA 12 60
IIH High-level input current VIH = 12 V p.A
1M, S 50 200
ICCl Supply current, logic section VCCl = 12 V, All inputs at 12 V 10 15 mA
VCC2 = 90 V, All outputs high 1.1 1.9
ICC2 Supply current, output section mA
No load All outputs low 0.1 0.6
ICCl (av) Average supply current, logic section tw = 5 p's, f = .50 kHz, 10 mA
ICC2(av) Average supply current, output section No load 1.3 mA
t All typical values are at 25C.
switching characteristics, VCC1 ... 12 V, VCC2 == 70 V, TA = 25C

tpLH Propagation delay time, low-to-high-Ievel output CL = 20 pF, RL = 100 k!l, 0.7 1.2
tpHL Propagation delay time, high-to-Iow-Ievel output See Figure 1 0.3 0.8
TEXAS 3-5
INSTRUMENTS
POST oFFice BOX 655012 ' DALLAS. TexAs 75265
SN55426B, SN55427B
C;;10ns~ 1+-*-C;;10ns
I 1 1 1
j,.,.g-o-%-----g-o-%N 11- - - - - -10 V
1-+-.....----11... OUTPUT
CL = 20 pF
(See Note BI
INPUT
J,:
1
I
10%
,
1
1
10%
OV
~tPLH-tot Ie-tPHL-tot
I I 1 1
: - 1- - - -- VOH
c '426B OUTPUT I 1
fir VCC1 VCC2
VOL
'tS
or
'<
CL = 20 pF
(see Note BI '427B OUTPUT
VOH
..<.
C ~+- ......----..- OUTPUT
.
CD
en
% SN55427B
TEST CIRCUITS VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zo = 50 0, PRR s 50 kHz, tw = 5 p.s.
B. CL includes probe and jig capacitance.
FIGURE 1. SWITCHING TIMES
3-6 . TEXAS ~
INSTRUMENTS
SN75491, SN75491A, SN75492, SN75492A
MOSTOLED DRIVERS
02355, OCTOBER 1972-REVISED SEPTEMBER 19B6
QUAD SEGMENT DRIVER AND HEX DIGIT DRIVER FOR INTERFACING

BETWEEN MOS AND LlGHTEMITTINGDIODE (LED) DISPLAYS
o 50-rnA Source or Sink Capability SN75491.SN75491A

('491, '491A) N DUAL-INLlNE PACKAGE
(TOP VIEW)
250-rnA Sink Capability ('492, ,492A)
1A 4A
Rated for 10-V Operation ('491, '492) 1E 4E

Rated for 20-V Operation ('491A, '492A)
Low Input Current for MOS Cornpatability
Low Standby Power
1C
GND
2C
2E 3E
2A --"'_ _...r- 3A
4C
VSS
3C II ...en
Q)
High-Gain Darlington Circuits
'i:
>
description
SN75492.SN75492A C
N DUAL-IN-LlNE PACKAGE
(TOP VIEW)
>
co
The SN75491, SN75491A, SN75492, and
SN75492A are monolithic integrated circuits 1Y 1A C.
en
designed to be used together with MOS 6Y
integrated circuits and common-cathode LED's
2Y C
2A 6A
in serially addressed mUlti-digit displays. This GND VSS
time-multiplexed system, which uses a segment- 3A 5A
address-and-digit-scan method of LED drive, 3Y 5Y
minimizes the number of drivers required. 4Y ....._ _...r-
The SN75491 and SN75491A are quadruple
segment drivers. The SN75492 and SN75492A logic symbols t
are hex digit drivers. The SN75491 and
SN75491,SN75491A
SN75492 are characterized for operation to
10 volts. The SN75491A and SN75492A are (1) MaS/LED ~
characterized for operation to 20 volts. 1A
~
The SN75491, SN75491A. SN75492, and 2A (7)
SN75492A are characterized for operation from
ooe to 70 oe.
(8)
3A
logic diagram (each driver)
(14)
SN75491. SN75491A 4A
SN75492, SN75492A
'NPUT A - r > t = :
1A (14)
2A (31
SN75492. SN75492A 3A (5)
,NPUT A ----[:>r--- OUTPUT Y

4A
SA
6A
(8)
(10)
(12)
t These symbols are in accordance with ANSIIIEEE

Std 911984 and lEG Publication 61712.
~~~~~:~~i~ai~:I~lJe ~~~~~~ti~r :1\o::~:~~t~:S~s not INSTRUMENTS
SN75491. SN75491A. SN75492. SN75492A
MOSTOLED DRIVERS
schematics
SN75491, SN75491A (each driver! SN75492, SN75492A (each driver!
V
__- - - _ ( 1 , 2 , 6 , 7,9,131
(1,7,8,141 (14,3,5,8,10,121
A ---~-~~-~.-~ A-. .-.JVI/v--il......-i
lEI
C
Vss ~(1_1=41.-...._ _ _- - -...4 ....--.....;..(4-1 GND VSS_(1_1~1.-.~__~. .____~__~___..._(4_1 GND
iii'
"C
Dr
<
...C
<' SN75491 SN75491A SN75492 SN75492A UNIT
...
CD
en
Input voltage range (see Notes 1 and 21
Collector (output) voltage, Vc
-5 V to Vss -5VtoVsS -5 V to Vss - 5 V to VSS
10 20 10 20 V
Collector (output)-to-input voltage 10 20 10 20 V
Emitter-to-ground voltage (VI 2: 5 V) 10 20 V
Emitter-to-input voltage 5 5 V
Voltage at VSS terminal with respect to any other device terminal 10 20 10 20 V
I
Collector (outputl current, IC Each collector (output) 50 50 250 250
mA
,I
All collectors (outputs) 200 200 600 600
Continuous total dissipation at (or below) 25C
875 875 875 875 mW
free-air temperature (see Note 31
Operating free-air temperature range o to 70 o to 70 o to 70 o to 70 C
Storage temperature range -65 to 150 -65 to 150 -65 to 150 -65 to 150 C
Lead temperature 1,6 mm (1/16 inch)
260 260 260 260 C
from case for 10 seconds
NOTES: 1. All voltage values are with respect to network ground terminal.
2. The input is the only device terminal that may be negative with respect to ground.
3. For operation at 25C free-air temperature, refer to Dissipation Derating Curves in Appendix A. For these devices in the N
package, use the 7-mW/oC curve.
'491, '491A electrical characteristics, VSS 10 V for SN75491, VSS ... 20V for SN75491A,
T A ... OOC to 70C (unless otherwise noted)
PARAMETER TEST, CONDITIONS MIN Tvpt MAX UNIT
Input = 8.5 V through 1 kfl, VE = 5 V,
0.9 1.2
IC = 50 mA, TA = 25C
VCE(on) On-State collector-emitter voltage V
Input = 8.5 V through 1 kfl, VE = 5 V,
1.5
IC= 50 mA
Off-state collector current
Vc = VSS, VE = 0, II = 4Ol'A 100
IC(oft) I'A
Vc = VSS, VE = 0, VI = 0.7 V 100
Input current at maximum input voltage

VI = VSS, VE = 0, 1'491 2.2 3.3
II mA
IC = 20 mA I '491A 4.7 6.5
IE Emitter reverse current VI = 0, VE = 5 V, IC = 0 100 I'A
ISS Current into VSS terminal 1 mA
3-8 TEXAS
INSTRUMENlS
SN75491, SN75491A, SN75492, SN75492A
MOSTOLED DRIVERS
'492, '492A electrical characteristics, VSS = 10 V for SN75492, VSS 20 V for SN75492A,
T A = OOC to 70C (unless otherwise noted)
Input = 6,5 V through 1 HI, IOL = 250 mA,
0,9 1.2
VOL Lo~-Ievel output voltage TA = 25C V
Input = 6.5 V through 1 kfl, IOL = 250 mA, 1,5
= VSS, =

VOH VI 40 p.A 200
IOH High-level output current p.A
VOH = VSS, VI = 0,5 V 200
1'492 2,2 3,3
II Input current at maximum input voltage VI = VSS, IOL = 20 mA mA
I '492A 4,7 6,5
ISS Current into VSS terminal 1 mA
t All typical values are at T A = 25C,

...en
Q)
>
'':;:
SN75491, SN75491A switching characteristics, VSS = 7.5 V, TA = 25C C
PARAMETER TEST CONDITIONS MIN TYP MAX >
CO
tpLH Propagation delay time, low-to-high-Ievel output (collector) VIH = 4,5 V, VE = 0, 1-_ _ _
1"..,,...--_-1_ _-1 C.
tpHL Propagation delay time, high-to-Iow-Ievel output (collector) RL = 200 fl, CL = 1 5 pF 20 en
is
SN75492, SN75492A switching characteristics, VSS = 7.5 V, TA = 25C
tpLH Propagation delay time, low-to-high-Ievel output VIH = 7.5 V, RL = 39 fl, 300
tpHL Propagation delay time, high-to-Iow-Ievel output CL = 15 pF 30

SN75491, SN75491A
75V
D-ooooo4H~-- OUTPUT
INPUT
1\",;,10,;,;%,;..._ _ _ _ 0 V
,----VOH
I
SN75492, SN75492A OUTPUT I
7.5V I I
I I
I '----i---'-I- - - - VOL
I I
tPHL~ I I
I4----*-tPLH
x~ ....- - - OUTPUT
TEST CIRCUITS VOLTAGE WAVEFORMS
NOTES: A, The pulse generator has the following characteristics: Zout = 50 fl, PRR ::5 100 kHz, tw = 1 p's,
B, CL includes probe and jig capacitance,
FIG,URE 1. P.ROPAGATION DELAY TIMES
INSTRUMENTS
TEXAS '1.!1 3-9
SN75491, SN75491A, SN75492, SN75492A
MOSTOLED DRIVERS
TYPICAL CHARACTERISITCS
SN75491,SN75491A
INPUT CURRENT COLLECTOR CURRENT
vs vs
INPUT VOLTAGE INPUT CURRENT
5 50
Vss = 10 V ('491, '492) V~S = 110 Vi
VSS = 20 V ('491A, '492A)
10 = 20 rnA /
/ 40 f-
Vc = 2.5 V
f-
VE =0
4
VE - 0 ('491, '491A) V <! TA = 25 C
<C E
C
en"
E
.!.c 3
TA = 25C
I I I /
/ .!.c
~ 30
"C ~ ! V :;
I-- f- '491, '492-
C)
'<
u
:;
... 1/ u
E
..
.<"
C
I
::J
Co
c
2
V
/ u
.!!!
(5
u
20
...
CD
t/)
// I
~
10
V /
o ./
/ o /
o 2 4 6 8 10 12 14 16 18 20 o 40 80 120 160 200
VI-Input Voltage-V 11-1 nput Current-IiA
FIGURE 2 FIGURE 3
SN75491,SN75491A SN75491,SN75491A
COLLECTOR CURRENT ONSTATE COLLECTOREMITTER VOLTAGE
vs vs
INPUT VOLTAGE COLLECTOR CURRENT
50 1 1.0
40 -
VSS = 10 V
-VC=2.5V
VE = 0
. ~
GJ
CI
(5
> 0.8
_--c- - --- t:::: f-- f - - - -
<C TA = 25 C
~V ~ -\ r-\
eLI;I=
GJ
E
I ,/'
~ 30 o 0.6
\ r\ '- TA = 70C
u
:; '0 \ \. TA = 25C
.!!!
(5 \... TA = OC
E
] 20 ~ 0.4
(5 ~
u ~
u
I c I
- 10 '[ 0.2 r- VSS = 10 V
C- VE =0
o
W f- Input = 3.5 V thru 1 kn
o ./ ~ 0 I I I I I
o 0.5 1.0 1.5 2.0 2.5 o 5 10 15 20 25 30 35 40 45 50
VI-Input Voltage-V Ie-Collector Current-rnA
FIGURE 4 FIGURE 5
3-10
TEXAS -I.!}
INSTRUMENTS
SN75491, SN75491A, SN75492, SN75492A
MOSTOLED DRIVERS
SN75492.SN75492A SN75492.SN75492A
OUTPUT CURRENT OUTPUT CURRENT
vs vs
INPUT CURRENT INPUT VOLTAGE
250 250
VSS = 10 V / V~S ='10 J I
<C
E
I
200
- Va = 2.5 V
TA = 25C
/
/
I
<C
E
.!.c
- VO=2.5V
200 _ TA = 25C
I
II
I
II
. rn
~ 150 ~ 150
Q)
>
:;
u
...
1 :;
(,J
...:s
''::
C
.s-:s:s 100 / S-
:s 100
I
ca
>
o
I
/ 0
I I Q.
rn
9
9
50 J 50
I C
/ L
o ~ o
)
o 50 100 150 200 250 300 o 0.5 1.0 1.5 2.0 2.5
II-Input Current-/lA VI-Input Voltage-V
FIGURE 6 FIGURE 7
SN75492.SN75492A
LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
-
1.0
!---
:::: :::: ::-
~
~ ! ---
>I
Ql
CI
:!
"0
0.8
~ ~ t...--
/~
~~
i""""
k- 1\f--
\
- '--!---
>...
:s 0.6 \ 1'-- T A = 70C
S-
:s \ \... TA = 25C
0
Q)
>
\.. r- TA = OC
Ql 0.4
..J
;:
0
..J
I
..J 0.2
0 VSS = 10 V
> I-Input = 6.5 V thru 1 kn
o I I I I I
o 50 100 150 200 250
la-Output Current-rnA
FIGURE 8
TEXAS 3-11
INSTRUMENTS
SN75491. SN75491A. SN75492. SN75492A
MOSTOLED DRIVERS
Figure 9 is an example of time multiplexing the individual digits in a display to minimize circuitry. Up to
twelve digits, each of which use a seven-segment display with decimal point, may be displayed using only
two SN75491 and two SN75492 drivers.
+v
RL
Vss --r----'~+-------------_+----------~----~
C A
l
I
II SN75491
I ~~~E~EGMENT
I (2 PACKAGES)
I
I
L ______ ~D
E_J
THISPOINT~ Ii C 0 E F G DP - -- -- - - --.- - I
IS CONNECTED
TOALL
("-
I TIL360
16-DIGIT
SEGMENTS OF I MONOLITHIC
ALL DIGITS. I ILED DISPLAY
I ___ _ I(2 PACKAGES)

L ___ ..J
r-- Vss -,
-i l I
I
2 of 12 I SN75492
DRIVERS SHOWN
(1 UNUSED)
I HEX DIGIT
I ~R~~~~AGES)
I
VDD _ _
_~ -.JI
L _____ ~ ______________ I ~
FIGURE 9. INTERFACING BETWEEN MOS CALCULATOR CIRCUIT

AND LED MULTI-DIGIT DISPLAY
3-12 TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 DALLAs, TEXAS 75265
SN75491, SN75491A, SN75492, SN75492A
MOSTOLED DRIVERS
SN75491, SN75491A, SN75491, SN75491A

SN75492, OR SN75492A SN75492, OR SN75492A
r------- r---------,
INPUTI INPUTI :
;"';"";"'1"""""....-1 ______---'
I I
I
I
1
1
L ___ _
:
I
1L _____ IL ___ JI
r--
I
~ II
... t/)
Q)
'492, '492A '492, '492A
>
.i:
FIGURE 11. QUAD OR HEX LAMP DRIVER
FIGURE 10. QUAD OR HEX RELAY DRIVER C
+V1
>
CO
+V2
-, r-------
SN75491, SN75491A
LOAD
C.
t/)
INPUT I I C
FROM-+"""IV\~--1
MOS
I I NPUT-f-"""IV\.......-l
I I I
I I 1
I I I
IL ___ _ I IL ___ _
.J OUTPUT
TO
TTl
FIGURE 12. MOS-TO-TTL LEVEL SHIFTER FIGURE 13. QUAD HIGH-CURRENT N-P-N
TRANSISTOR DRIVER
+V1
.-------...,
I
SN75941
I
+V2
LOAD
INPUT I
SN75491, SN75491A 1
SN75492, OR SN75492A
r-------- -1 LOAD
1
I ~-------------------------. I 1
I NPUT....:.I-'IN'......-t I IL _______ .JI
I I
I 1
I I
I -l
1
L ____ -lI ____ JI ,
'492, '492A INPUT I .--------. I
I I
NOTE A: This circuit may be used as a digit driver for common- I I
mode LED displays.
1
L ______ ..J1
FIGURE 14. QUAD OR HEX HIGH-CURRENT
P-N-P TRANSISTOR DRIVER
FIGURE 15. BASE/EMITTER SELECT N-P-N
TRANSISTOR DRIVER
TEXAS . . 3-13
INSTRUMENTS
SN75491. SN75491A. SN75492. SN75492A
MOSTOLED DRIVERS

+v
.------
SN75491 OR SN75491A
INPUT~11-W"""~ hNPUT2
>.AN"-'"I=
1 - -_ _ _ _ ......
I
lEI
c
C;;'
I
IL _____ _
SN75491, SN75491A,
I
_ _ _ _ _ ...1I
"C
iii" r-------
SN75492 OR SN75492A
.,
I
< STROBE I I
c INPUT -I-,....,.,.,.,.~ . . . . _ _. . .
.... I
<'
m
....
I
I
I
'491 '491A I
(I)
I r'---1
IL __ _ I ___ JI
'492, '492A
FIGURE 16. STROBED "NOR" DRIVER
5V--.-------------------.------.---------------.
2.7 kn .------
I
1/4 SN75491 OR SN75491A
-.....----r---.. OUTPUT
RL = 50 n
NONII~~~~TING -+-----1/4-S-N-75-4-91-0-R-S-N7-5-49-1A--+-------+--1-/4-S-N7-5-49-1-0-R-SN-7-54-91-A--'
r------ -------1
IN~~:J~NG --+-""'11,"""",~~
1 kn 1/4 SN75491 OR SN75491A

r-----
IN I
I
5kn I
L _____ _
-5V--~----------------------~
FIGURE 17 ~ SN75491/SN75491 A USED AS AN INTERFACE CIRCUIT BETWEEN THE
BALANCED 30MHz OUTPUT OF AN RF AMPLIFIER AND A COAXIAL CABLE
3-14 TEXAS . .
INSTRUMENTS
SN75494
HEX MOS-TO-LED DIGIT DRIVERS
D 1932. MARCH 1983 - REVISED JANUARY 1987
N
Low Input Current for MOS Compatibility
Low Voltage Operation ITOPVIEWI
Low Standby Power Vss Vee

1A 6A
Display Blanking Capability 1Y 6Y
250-mA Sink Capability 2Y 5Y
2A 5A
.

Low-Voltage Saturating Outputs
High-Gain Circuits
description
3Y
3A
Voo E
4Y
4A . II..
en
Q)
:>
The SN75494 is designed to be used as an interface between MOS integrated circuits 'and LEDs in serially -.:
addressed multidigit displays. This device is similar in operation to the SN75492. but has several advantages C
over the earlier circuit. The SN75494 can be operated at lower supply voltages therefore, reducing power >
CO
consumption. The enable (E) input is used as a blanking input. C.
en
C
logic symbol t schematic
Vee
~_ _... TO OTHER
DRIVERS
lA 121 1V
2A 151 2V
3A 171 3V
4A 1101 4V
SA 1121 Y
5V
6A 1151 6V
VSS---'"
IEC Publication 617-12.
Voo
NOTES: A. The VSS terminal must be connected to the most
positive voltage that is applied to the device.
B. Resistor values shown are nominal and in ohms.
~~~~~:~~i~a{:~I~~~ ~!~~~~ti:r :llo::~:~:t:ros~s not
TEXAS -1.!1 3-15
INSTRUMENTS
SN75494
HEX MOSTOLED DIGIT DRIVERS
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10 V
Supply voltage, VSS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10 V
Input voltage ............................................................. VSS
Off-state output voltage ........................... _ ........ '.... _ . . . . . . . . . . .. 10 V
Continuous output current (each driver) ....................................... 250 rnA
Continuous VOO current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 600 rnA
Continuous total dissipation at (or below) 25C free-air temperature (see Note 3) . . . . . . " 800 mW
Operating free-air temperature range ............ _ . . . . . . . . . . . . . . . . . . . . . . . .. ooC to 70C
Storage temperature range ................. _ ...................... _ - 65C to 150C
c recommended operating conditions
0"
"C
MIN MAX UNIT
Dr
-< Supply voltage. Vee 3.2 8.8 V
...c Supply voltage. VSS

Operating free-air temperature. T A
6.5
0
8.8 V
<"
...
CD
70 e
en electrical characteristics, Vee = 8.8 V, VSS = 8.8 V, TA = ooe to 70 0 e (unless otherwise noted)
II Input current
I A input A at 8.8 V.
Vee = 3.2 V.
Eat 8.8 V
A at 8.8 V. E to 8.8 V thru 100 kfl
2
1.8
3
2.5 mA
I E input Vee = 3.2 V. Eat 8.8 V 1.6 2.5
A to 8.8 V thru 100 kfl. Eat 0 V.
Off-state output 1 200
Y at 10 V
IO(oft) current (from p.A
Aat8.8V. E to 6.5 V thru 1 kfl.
Y to VOO) 1 100
Y at 10 V
On-state Vee = 3.2 V. VSS = 6.5 V. A to 6.5 V thru 1 kfl.
VO(on) 0.25 0.4 V
output voltage E to 8.8 V thru 100 kfl. IOL = 25.0 mA
One A input to 8.8 V thru 100 kfl, Eat 0 V.
10 500
All other A inputs at 0 V
p.A
Current into One A input at 8.8 V. E to 6.5 V thru 1 kO.
ICC 60 500
VCC terminal All other A inputs at 0 V
One A input at 8.8 V . Eat 0 V.
11 20 mA
All other A inputs at 0 V
Current into VSS
ISS
terminal
Vce = 3.2 V. Eat 0 V. All A inputs at 0 V 10 500 p.A

NOTES: 1. Voltage values are with respect to the most negative device terminal. VOO. unless otherwise noted.
2. No other terminal on the device may be more positive than VSS.
3. For operation above 25C free-air temperature. derate linearly from 800 mW at 63C to 736 mW at 70C at the rate of
9.2 mW/oC.
3-16 TEXAS
INSTRUMENTS
ADVANCE SN55500E
INFORMATION AC PLASMA DISPLAY DRIVEn
02471. DECEMBER 1984-REVISED NOVEMBER 1986
Controls 32 Electrodes JD PACKAGE

(TOP VIEW)
100-V Totem-Pole Outputs
Low Stand-by Power Consumption SO VCCl
DATA Sl
All Outputs Contain Sink and Source Clamp ClK STRB
Diodes 101 401
15 mA Steady-State Output Current 102 402
403
II
103
Rugged DMOS Outputs 104 404
CMOS Inputs 105 405
106 406
Dependable Texas Instruments Quality and
Reliability
107 407
408
...en
Q)
108
201 301
>
''::
Direct Replacement for SN55500D
202 302 C
description 203 303 >
ca
204 304
TheSN55500E is a monolithic BIDFETt 205 305 C.
en
integrated circuit designed to perform the line
select operation of a matrix-addressable display.
206 306 is
207 307
The device inputs are diode-clamped CMOS 208 308
inputs. GND VCC2
The outputs of the driver are normally low and
can be selectively switched high when the strobe FD PACKAGE
input is low. Selection of the outputs is achieved (TOP VIEW)
through the data, SO, and S 1 inputs. The 8-bit

data stored internally in the serial register is
inverted and sent to one of four output sections
by the 2-line to 4-line decoder. All other outputs 6 5 4 3 2 1 44434241 40
remain low. Internal circuits provide a high- 39
current pulse to the level-shifting circuit during 8 38
positive output transitions .. When the output 9 37
transition is complete, the low steady-state 10 36
current reduces the circuits stand-by power 11 35
consumption. All outputs contain clamp diodes 12 34 2
to the VCC2 and GND supply inputs. 13 33 o
The SN55500E is characterized for operation
14 32
i=
over the full military temperature range of
15
16
31
~
-55C to 125C. 17 29 :2E
1819202122 232425262728 a:
LOCDI'COOU
OOOOZZUOOOO
NCO I'CD LO oLL
NNNNC!) ~MMMM
2
w
U
2
~
C
t BIDFET -Bipolar, double-diffused. Nchannel and P-channel MOS
transistors on same chip - patented process.
ADVANCE INFORMATION documents contain Copyright 1984, Texas Instruments Incorporated
~~~~~~3~~~rono~h:::of~~~~f~p~e~~.8C~:~~~~r~st~~ TEXAS 3-17

lIata and other specifications are subject to change
SN55500E ADVANCE
AC PLASMA DISPLAY DRIVER INFORMATION
logic symbol t functional block diagram (positive logic)
CMOS/PLASMA DISP STRB - - - - - - . q . ; 1 > - - - - -.....-1 101
II
c
(ii'
Z2
Z3
B.ll
1.12
[>
[>
(41
101
(111 lOB
(1 21
201
SELECT
r
DATA
Sl
2-LlNE TO
4-LlNE
DECODER
lOB
201
20B
301
Rl
"C Z4 (191 20B
B.12 [> R2
Dr [> (291 301 CLK
R3
'< Z5
1.13
R4 30B
a-BIT
...
C Z6 (221 30B
SHIFT R5
<' B.13 [>

(371 401
REGISTER R6 401
...en
CD Z7
1.14 [> R7
RB
ZB [> (301 40B
B.14
40B
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and

lEG Publication 617-12_
Pin numbers shown arll for the JD package.
FUNCTION TABLE
INPUTS OUTPUTS
FUNCTION SELECT SHIFT REGISTER
DATA CLK STRB
S1 SO R1 R2 R3 . RS 101 ... 10S 201 ... 208 301 ... 30S 401 ... 40S
H t X X H L R1n R2n ... R7 n L ... L L ... L L ... L L ... L
LOAD
L t X X H H R1n R2n ... R7 n L ... L L ... L L ... L L ... L
X X X X H R1n R2n R3 n ... R8 n L ... L L ... L L ... L L ... L
X H L L L R1n R2n R3 n .. R8 n R1 ... R8 L ... L L ... L L ... L
c
STROBE X
X
X
H
H
H
L
H
H
H
L
H
L
L
L
R1n
R1n
R1n
R2n
R2n
R2n
R3 n ... RS n
R3 n ... RS n
R3 n ... RS n
L ... L
L ... L
L ... L
R1 ... R8
L ... L
L ... L
L ... L
R1 ... RS
L ... L
L ... L
L ... L
R1 ... RS
<
H = high level, L = low level, X = irrelevant, t = low-to-high transition.
R1 ... RS = levels currently at internal outputs of shift registers one through eight, respectively.
2 R 1n ... RS n = levels at outputs R1 through RS respectively, before the most recent t transition of the clock.
("')
m typical operating sequence
2
."
o
STRB --u
::D eLK
S
ANY OUTPUT IN rv:D1
L:!-.......---------------iH)-.......L:!-......---
rv:D1
o-
-I B SELECTED BY - -....
SO AND S1
3-18 TEXAS
INSTRUMENTS
-1!1
ADVANCE SN55500E
INFORMATION AC PLASMA DISPLAY DRIVER
EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS
VCC1--------~-----&~~
INPUT~.....JV\I"Ir_. . . . .
II t/)
r-
CD
>
'i:
GND ---'__- - - - - - - - - -.........-
C
co
>
Q.
t/)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) C
Supply voltage, VCC1 (see Note 1) ........................................... 13.8 V
Supply voltage, VCC2 .............................................. ~ . . . . . .. 100 V
Input voltage ...................................................... , VeC1 +0.3 V
Continuous total dissipation at (or below) 25C free-air temperature (see Note 2) . . . . . .. 1825 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55C to 125C
Case temperature for 60 seconds: FD package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260C
NOTES: 1. Voltage values are with respect to network ground terminal.

2. For operation above 25C free-air temperature, see Dissipation Derating Table.
POWER DERATING ABOVE

PACKAGE
RATING FACTOR TA
oz'
FD 1825 mW 14.6 mW/oC 25C
JD 1825 mW 22 mW/oC 67C
t=
<C
~
a:
oLL
-w
Z
(.)
z
<C
>
c
<C
TEXAS 3-19
INSTRUMENTS
SN55500E ADVANCE

MIN NOM MAX UNIT
Supply voltage, VCC1 10.8 12 13.2 V
Supply voltage, VCC2 0 100 V
High-level input voltage, VIH, as a percentage of VCC1 75%
Low-level input voltage, VIL, as a percentage of VCC1 25%
High-level output clamp current 20 mA
Low-level output clamp current -20 mA
II
c(ii'
Clock frequency, fclock (see Figure 2)
Duration of high or low clock pulse, tw
Setup time, tsu

Data inputs before clockt
Select inputs before strobe!
Data inputs after clockt (see Note 3)
0
62
20
50
50
8 MHz
ns
ns
"C Hold time, th Strobe input high after clockt 50 ns

Dr Select Inputs after strobet 50
< Operating free-air temperature, T A -55 DC
...c Operating case temperature, TC 125 DC
<'
~ NOTE 3: For operation above 25 DC junction temperature, refer to Figure 2.
en
electrical characteristics over recommended operating temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYpt MAX UNIT
VIK Input clamp voltage VCC1 = 12 V, II =
-12 mA -1 -1.5 V
10H = -1 mA 94 97.5
VCC1 = 13.2 V,
10H = -10 mA 92 94.5 V
VCC2 = 100 V
10H = -15 mA 90 93.5
10L = 1 mA 0.85 2
VCC1 = 13.2 V,
VOL Low-level output voltage 10L = 10 mA 2 4 V
VCC2 = 100 V
10L = 15 mA 2.75 5
10 = 20 mA 1 2.5
VOK Output clamp voltage VCC2 = 0 V
10 =-20 mA -1.2 -2.5
IIH High-level input current VCC1 = 13.2 V, VI = VIH min 1 p.A
IlL Low-level input current VCC1 = 13.2 V, VI = VIL max -1 p.A
ICC1 Supply current VCC1 = 13.2 V, VCC2 = 100 V 0.05 1 mA
c
ICC2 Supply current VCC2 = 100 V 1 5 mA
t All typical values are at VCC = 12 V, T A = 25 DC.

<
2
switching characteristics, VCC1 ... 12 V, VCC2 - 100 V, TA ... 25C
(")
m tDHL Delay time, high-to-Iow-Ievel output from strobe input 250 ns
-
2
-n
tDLH
tTHL
tTLH
Delay time, low-to-high-Ievel output from strobe input
Transition time, high-to-Iow-Ievel output
Transition time, low-to-high-Ievel output
CL = 30 pF,
See Figure 1
450
200
300
ns
ns
ns
o
:xJ
S
::!
o
2
3-20 TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 DALLAs, tEXAS 75265
ADVANCE SN55500E
INFORMATION AC PLASMA DISPLAY DRIVER
OUTPUT TEST
UNDER - - - - r - - - - - - P O I N T
l'
TEST
CL (see Note AI
CLK
--~
LOAD TEST CIRCUIT
, - - - - - - - - - /- - - - - - - - - ---------50%
VIH II
... U)
1 I--------------------VIL CD
:~ tw ~I "i:
>
t+-- tsu --+14-- th ~: C
DATA --IR-RE-L-EV-A-N-T-"""""')( : VALID 'f\~--I-RR-E-L-EV-A-N-T--- VIH >-
m
, . .....- - - - - - - - VIL C.
I--th~ U)
'\ I,-----VIH
C
ST~B
1~-----JI_th ~I - - VIL
14- tsu -'1 ~
1
~
SELECT
VOLTAGE WAVEFORMS
NOTE A. CL includes probe and jig capacitance.
FIGURE 1. SWITCHING CHARACTERISTICS

2:
o
i=

~
a::
oLL
-w
2:
()
2:

>
c

TEXAS
INSTRUMENTS
-1!1 3-21

SN55500E ADVANCE
MAXIMUM CLOCK FREQUENCY

vs
VIRTUAL JUNCTION TEMPERATURE
9
VCC1 - 12 V
VIH - 12 V
N
II --........
:J: 8 VIL - 0
::E (See Note 4)
>
u
I
~ ..........
cG) 7 -.....
~
j
C C'
I-----.
G)
(ji' LA:
'0 ~
6
u
iii' 0
< 0
...
C E
j
5
<' E
";(
...tn
(1) I
::E 4
3
25 45 65 85 105 125
TJ-Junction Temperature- C
NOTE 4: This curve assumes a symmetrical clock pulse.
FIGURE 2
THERMAL INFORMATION
junction temperature formula
TJ = TA + POROJA
c
TJ = TC + POROJC
< where
2 T J = virtual junction temperature

(") T A = free-air temperature
m Po = average device power dissipation
-2
'TI
RO = thermal resistance (junction-to-air, ROJA, or junction-to-case, ROJC)
o:J:J PACKAGE TYPE ROJA ROJC

FD 44'pin ceramic 68C/W 20 o C/W
S JD 40-pin ceramic 45C/W 12C/W
:::!
o
2
3-22 TEXAS ~
INSTRUMENTS
PRODUCT SN65500t IN75500E
PREVIEW AC PLASMA DISPLAY DRIVERS
Controls 32 Electrodes N PACKAGE

(TOP VIEW)
SO VCC1
Low Stand-by Power Consumption DATA S1
All Outputs Contain Sink and Source Clamp ClK STRB
Diodes 101 401
102 402
15 rnA Steady-State Output Current 103 403

Rugged DMOS Outputs
CMOS Inputs
Direct Replacement for SN75500A
104
105
106
1<;17
404
405
406
407
II
. en
(1)
108 408
description 201 301
>
''::::
202 302 C
The SN65500E and SN75500E are monolithic
BIDFETt integrated circuits designed to perform
203 303 >
CO
204 304 Q.
the line select operation of a matrix-addressable
205 305 en
display. The device inputs are diode-clamped
CMOS inputs.
206 306 C
207 307
The outputs of these drivers are normally low 208 308
and can be selectively switched high when the GND VCC2
strobe input is low. Selection of the outputs is
achieved through the data, SO, and S 1 inputs. FN PACKAGE
The 8-bit data stored internally in the serial (TOP VIEW)
register is inverted and sent to one of four output
sections by the 2-line to 4-line decoder. All other ~ ~ U
dU....JQU U..-t-Ud
~
outputs remain low .. Internal circuits provide a ZUO<llZ><Il<llZq-
high-current pulse to the level-shifting circuit
6 5 4 3 2 1 4443424140
during positive output transitions. When the
102 39 402
output transition is complete, the low steady-
103 8 38 403
state current reduces the circuit's standby power
104 9 37 404
consumption. All outputs contain clamp diodes
105 10 36 405
to the VCC2 and GND supply inputs.
106 11 35 406
The SN65500E is characterized for operation 107 12 34 407
from -40C to 85C. The SN75500E is 108 13 33 408
characterized for operation from OOC to 70C. 201 14 34 301
202 15 31 302
203 16 30 303
~
tBIDFET -Bipolar, double-diffused, N-channel and P-channel MOS 204 17
1819202122232425262728
29 304 w
transistors on same chip - patented process.
L!)(!)r--OOOU NOOr--(!)L!)
5:
w
ddddZZ Udddd
NNNN(!J :3:'(")(")(")(")
a:
Q.
t-
(.)
::J-
C
oa:
Q.
TEXAS -I!} 3-23
INSTRUMENTS
SN65500E, SN75500E PRODUCT
AC PLASMA DISPLAY DRIVERS PREVIEW
logicsymbol t functional block diagram (positive logic)
CMOS/PLASMA OISP STRB------q ; 1 - - - -......, 101
II
c
(4) 101
(11) 10B
(12) 201
.
SELECT
r
DATA
S1
10B
201
20B
301
(ii'
'C l4
or B.12 C>
(19) 208
(29) 301
CLK
< l5
1.13 C> 30B
...c l6 (22) 30B 401

<'CD B.13 C>
(37) 401
...
en
l7
1.14 C>
lB (30) 40B 40B

8.14 C>
tThis symbol is in accordance with ANSI/IEEE Std 91.-1984 and

lEe Publication 617-12.
Pin numbers shown are for the N package.
FUNCTION TABLE
INPUTS OUTPUTS
FUNCTION SELECT SHIFT REGISTER
DATA CLK STRB
S1 SO R1 R2 R3 .. R8 101 ... 108 201 .. 208 301 ... 308 401 .. 408
H f X X H L R1n R2n ... R7 n L ... L L ... L L ... L L ... L
LOAD
L f X X H H R1n R2n ... R7 n L ... L L ... L L ... L L ... L
X X X X H R1n R2n R3 n ... R8 n L ... L L ... L L ... L L ... L
X H L L L R1n R2n R3 n ... Ran Rl ... R8 L ... L L ... L L ... L
STROBE X H L H L R1n R2n R3 n ... Ran L ... L R1 ... R8 L ... L L ... L
X H H L L R1n R2n R3 n ... R8 n L .. L L ... L R1 ... R8 L ... L
X H H H L R1n R2n R3 n ... R8 n L ... L L ... L L ... L R1 ... R8
H = high level. L = low level. X = irrelevant. f = low-to-high transition.

R1 ... R8 = levels currently at internal outputs of shift registers one through eight, respectively.
"'C R1 n ... R8 n = levels at shift-register outputs R1 through R8, respectively, before the most recent f transition of the clock.
::c
o
c
c
o
-I
"'C
::c
m
S
m
~
3-24 TEXAS ~
INSTRUMENTS
PRODUCT SN65500E,SN75500E
PREVIEW AC PLASMA DISPLAV DRIVERS
STRB -U
ClK
ANY OUTPUT IN
II
RVALID RVALID
8 SELECTED BY
SO AND S1
---'--...L...------------4i )-S- - '_
- _""'-_ _

... (I)
Q)
EQUIVALENT OF EACH INPUT TYPICAL OF All OUTPUTS
'':
>
VCC1--------~----~--~
C
>
CO
C.
(I)
C
INPUT ----.-JV\;'v-.......
GND--__- - - - - - - - - -__-4~
Supply voltage, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 V
Input voltage ....................................................... VeC1 +0.3 V
FN package ....................... ~ ............ '. . . . . . . . . . . . . . . . . .. 1775 mW
N package ........................................................ 1275 mW
Operating free-air temperature range: SN65500E................. . . . . . . . .. - 40C to 85 C
SN75500E ............................ ooC to 70C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65 e to 150C ~
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ............ 260C w
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260C
5:
w
1. Voltage values are with respect to network ground terminal.
NOTES:
2. For operation above 25C free-air temperature, see Dissipation Derating Table. a:
a..
DISSIPATION DERATING TABLE t-
O
PACKAGE ::::)
RATING FACTOR TA
FN 1775 14.2 C
N 1275 10.2 o
a:
a..
TEXAS ~ 3-25
INSTRUMENTS
POST OFFice BOX 655012 , DALLAS. TeXAS 75265
SN65500E, SN75500E PRODUCT

SN65500E SN75500E
UNIT
Supply voltage, VCC1 10.8 12 13.2 10.8 12 13.2 V
Supply voltage, VCC2 0 100 0 100 V
High-level input voltage, VIH, as a percentage of VCC1 75% 75%
Low-level input voltage, VIL, as a percentage of VCC1 25% 25%
High-level output clamp current 20 20 mA
II
c
Low-level output clamp current
Setup time, tsu

Data inputs before clockl
0
62
20
-20
8 0
62
20
-20
8
rnA
MHz
ns
ns
0" Select inputs before strobe! 50 50
"C Data inputs after clockl (see Note 3) 50 50
Dr Hold time, th Strobe input high after clockl 50 50 ns
<
..c<" Select inputs after strobel
50
-40 85
50
0 70 C
..
CD
t/)
NOTE 3: . For operation above 25C junction temperature, refer to Figure 2 .
noted)
SN65500E SN75500E
VIK Input clamp voltage VCC1 = 12 V, II =
-12 mA -1 -1.5 -1 -1.5 V
10H = -1 mA 94 97.5 95 97.5
VCC1 = 13.2 V,
VOH High-level output voltage 10H = -10mA 92 94.5 93 94.5 V
VCC2 = 100 V
10H = -15 mA 90 93.5 91 93.5
IOL = 1 rnA 0.85 2 0.85 2
VCC1 = 13.2 V,
VOL Low-level output voltage IOL = 10 mA 2 4 2 4 V
VCC2 = 100 V
10L = 15 mA 2.75 5 2.75 5
10 = 20 mA 1 2.5 1 2.5
VOK Output clamp voltage VCC2 = 0 V
10 = -20 mA -1.2 -2.5 -1.2 -2.5
IIH High-level input current VCC1 = 13.2 V, VI = VIH min 1 1 p.A
IlL Low-level input current VCC1 = 13.2 V, VI = VIL max -1 -1 p.A
ICC1 Supply current VCC1 = 13.2 V, VCC2 = 100 V 0.05 1 0.05 1 rnA
ICC2 Supply current VCC2 = 100 V 1 5 1 3 mA
t All typical values are at VCC1 = 12 V, T A = 25C.

"'tJ
::JJ switching characteristics, VCC1 = 12 V, VCC2 = 100 V, TA = 25C
o
C PARAMETER TEST CONDITIONS MIN MAX UNIT
C tDHL Delay time, high-to-Iow-Ievel output from strobe input 250 ns

(") tDLH Delay time, low-to-high-Ievel output from strobe input CL = 30 pF, 450 ns
tTHL Transition time, high-to-Iow-Ievel output See Figure 1
-I 200 ns
tTLH Transition time, low-to-highlevel output 300 ns
"'tJ
::JJ
m
::;
m
~
3-26 TEXAS ~
INSTRUMENTS
PRODUCT SN65500E, SN75500E
PREVIEW AC PLASMA DISPLAY DRIVERS

OUTPUT TEST
UNOER ----I~--- POINT
l'
TEST
CL (see Note AI
II
LOAO TEST CIRCUIT
CLK
-----,.
\---------i --------- --
, , - - - - - - - - - - - - - - - - - - - - VIL
.
-------50%
VIH
...rn
l+-- tw ~I
~ - tsu ---+I~ th ----+: >
0t:
Cl)
C
DATA --I-RR-E-LE-V-A-NT----..)\ I VALID '1\,... . .-_-_-_
-_I-R_R=E=LE=V=A-N_T===== ~I: >-
CU
Q.
It---th ~ rn
STRB
'\ /,----VIH C
/4-tsu +, , " - - - - - - - - - ' '-th ~ I -
,~ ~
- VIL
SELECT
VOLTAGE WAVEFORMS
NOTE A. CL includes probe and jig capacitance.
~
w
5>
w
a:
a..
l-
t.)
::J
C
oa::
a..
TEXAS "'!} 3-27

INSTRUMENTS
SN65500E. SN75500E PRODUCT
MAXIMUM CLOCK FREQUENCY
vs
VIRTUAL JUNCTION TEMPERATURE
9
VCC1 ... 12 V
VIH - 12 V
N
J: 8 VIL'" 0
lEI
~
(See Note 4)
-------- ~ r--
I
>-
U
I:
al
7 .............
C
:3
c- ~
~
al
fi)' at 6
.:t!.
'C U
or 0
(3
< E 5
...
C :3
E
<'CD OJ(
(Q
...
C/l
~ 4
3
25 45 65 85 105 125
T J - Junction Temperature - C
NOTE 4: This curve assumes a symmetrical clock pulse ..
FIGURE 2
THERMAL INFORMATION
TJ = TA + PDROJA
TJ = TC + POROJC
where
T J = virtual junction temperature

"'tJ T A = free-air temperature
::a Po = average device power dissipation
o RO = thermal resistance (junction-to-air. ROJA. or junction-to-case. ROJC)
c
c
o PACKAGE TYPE
FN 44-pin plastic
ROJA
70 o C/W
ROJC
22C/W
-I
N 40-pin plastic 97C/W 27C/W
"'tJ
::a
m
-<
m
~
3-28 TEXAS
INSTRUMENTS
SN55501E
AC PLASMA DlSPLAV DRIVER
02472. APRIL 1986
Controls 32 Electrodes JD PACKAGE

(TOP VIEW)
CLOCK VCC1
Low Stand-by Power Consumption
SUSTAIN DATA IN
All Outputs Contain Sink and Source Clamp STROBE SERIAL OUT
Diodes Ql Q32
Q2 Q31

15 mA Steady-State Output Current
Q3 Q30
Rugged DMOS Outputs Q4 Q29
Q5 Q28
CMOS Inputs Q6 Q27
o Direct Replacement for SN55501 C, Q7 Q26 CI)
I-
SN55501D Q8 Q25 Q)
Q9 Q24 >
"a::
description Ql0 Q23 C
Qll Q22
The SN55501 E is a monolithic BIDFETt >
m
Q12 Q21
integrated circuit designed to provide the serial- C.
Q13 Q20 CI)
to-parallel conversion and level translation of
Q14 Q19
data in a matrix-addressable display. This device
Q15 Q18
C
has diode-clamped CMOS inputs.
Q16 Q17
The Q outputs of these drivers are normally high GND __________ Jr- VCC2
and can be switched either selectively or
together. Any output whose associated register
FD PACKAGE
bit (in the internal 32-bit serial register) contains
(TOP VIEW)
a low will switch low when the strobe input is
switched low if the sustain input is high. All other
outputs remain high. When the sustain input is
switched low, all outputs switch low
independently of the data or strobe inputs. This
feature can be used to generate a portion of the
sustain pulse required in the operation of an AC 6 5 432 1 4443424140
plasma display. The internal level-shift circuits Q2 7 39 Q31
provide additional drive during the times that the Q3 8 38 Q30
outputs switch high to facilitate fast rise times Q4 9 37 Q29
while maintaining low standby power Q5 10 36 Q28
consumption. All outputs contain clamp diodes Q6 11 35 Q27
to the VCC2 and GND supply inputs. Q7 12 34 Q26
Q8 13 33 Q25
The SN55501 E is characterized for operation 14 Q24
Q9 34
over the full military temperature range of 15
Ql0 31 Q23
-55C to 125C. 16
Ql1 30 Q22
Q12 17 ' 29 Q21
t BIDFET -Bipolar, double-diffused. N-channel and P-channel
1819202122232425262728
MaS transistors on same chip - patented process.
C"'l'<tlDC!)OU N,.....CXlOlO
aaaa~z~aaao
>
NC - No internal connection
specifications per the terms of Texas Instruments TEXAS "-!} 3-29
~~~~~:~~i~a{:~1~1e ~!~~~~ti~j fllo::~:~:t:ros~s not INSTRUMENTS
SN55501E
AC PLASMA DISPLAY DRIVER
logic symbol t functional block diagram (positive logic)
CMOSI SUSTAIN
PLASMA DISP
STROBE
EN3
CLOCK R1
Q1
CLOCK (11 DATA IN
141 Q1 R2
DATA IN (391 Q2
o
3
..
.(51 Q2
(19) Q16
R3
Q3
iii' 2 t> 3 32-BIT

(22) Q17
'C 2 t> 3 STATIC
SHIFT
ii) REGISTER
< (36) Q31 R30
...o
Q30
(37) Q32
c' (38) SERIAL OUT
...
(1)
en tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
R31
Q31
IEC Publication 617-12. R32

Q32
Pin numbers shown are for the JD package.
L-----r:>-- SERIAL OUT
FUNCTION TABLE
INPUTS OUTPUTS
FUNCTION SHIFT REGISTER SERIAL
DATA CLOCK STROBE SUSTAIN 01 02 03 .... 032
R1 R2 R3 ... R32 DATA
H t H H H R1n R2 n R31 n R32 n H H H .... H
LOAD
L t H H L R1n R2 n R31 n R32 n H H H .... H
X X H H R1n R2n R3 n R32 n R32 n H H H .... H
STROBE
X H L H R1n R2n R3 n R32 n R32 n R1 R2 R3 .... R32
SUSTAIN X X X L R1n R2n R3 n R32 n R32 n L L L .... L
H = high level, L = low level, X = irrelevant, t = low-to-high-Ievel transition.

R1 ... R32 = levels currently at internal outputs of shift registers one through thirty-two, respectively.
R1 n ... R32n = levels at shift-register outputs R1 through R32 respectively, before the most recent t transition at the Clock input.
3-30
TEXAS ~
INSTRUMENTS
SN55501E
SUSTAIN
STROBE U o-u-
UI ILfUlJ
CLOCK
ANY Q OUTPUT B I
L.. -.-
IRRElE----,VANT
r: B II ...
o
Q)
"i:
>
C
EQUIVALENT OF EACH INPUT TYPICAL OF ALL Q OUTPUTS TYPICAL SERIAL OUTPUT .
>
co
VCC1--------~----~~---- ------~~----~--~.--VCC2 -------4~------VCC1 C.
o
C
OUTPUT
INPUT--__~~~_e OUTPUT
-------4~~ __----~~GND
GND----------~~~~----
Supply voltage, VCC2 ...................................................... 100 V
Input voltage .............................. ; ........................ VeC1 +0.3 V
Continuous total dissipation at (or below) 25C free-air (see Note 2) . . . . . . . . . . . . . . .. 1825 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 e to 125C
Storage temperature range ......................................... - 65 e to 150C
Case temperature for 60 seconds: FD package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260C

PACKAGE
RATING FACTOR TA
FD 1825 mW 14.6 mW/oC 25C
JD 1825 mW 22 mW/oC 67C
TEXAS
INSTRUMENTS
'Ii1 3-31
SN55501E

MIN NOM MAX UNIT
Supply voltage, VCCl 10.8 12 13.2 V
High-level input voltage, VIH 0.75 VCe1
Low-level input voltage, VIL 0.25 Vee1
Peak high-level Q output current, IOH -20 mA
II
Peak low-level Q output current, IOL 20 mA
High-level Q output clamp current, IOKH 20 mA
Low-level Q output clamp current, IOKL -20 mA
Clock frequency, fclock, at or below, 25 DC junction temperature (see Note 3) 0 8 MHz
c Duration of high or low clock pulse, tw 62 ns
U;" Setup time, tsu Data inputs before clockf 20 ns
"C
or Data hold time after clockf 50
< Hold time, th Strobe high after clockf 150 ns
..<"
c Strobe high after sustainf
250
-55
..
CD
en
Operating case temperature, T C
NOTE 3: See Figure 3 for maximum clock frequency when devices are operated in cascade or for operation above T J = 25 DC.
125
DC
electrical characteristics over recommended operating temperature range

VIK Input clamp voltage VCCl = 12 V, II = 12 mA -1 -1.5 V
IIOH = -1 mA 94 97.5
VCCl = 13.2 V,
High-level Q outputs IIOH = -10mA 92 94.5
VOH VCC2 = 100 V V
output voltage IIOH = -15 mA 90 93.5
Serial out VCCl = 10.8 V, IOH = -100 p.A 9 10
IIOL = 1 mA 0.85 2
VCCl = 13.2 V,
Low-level Q outputs IIOL = 10 mA 2 4
VOL VCC2 = 100 V V
output voltage IIOL = 15 mA 2.75 5
Serial out VCC1 = 10.8 V, IOL = 100 p.A 0.1 1
Output clamp IIOK = 20 mA 1 2.5
VOK Q output VCC2 = 0 V
voltage IIOK = -20 mA -1.2 -2.5
High-level VCCl = 13.2 V, VIH = VIHmin,
1 p.A
IIH
input current VCC2 = 100 V
Low-level VCCl = 13.2 V, VIL = VILmax,
-1 p.A
IlL
ICCl Supply current from VCCl VCCl = 13.2 V, VCC2 = 100 V 0.05 1 mA
I Outputs low 0.1 1
ICC2 Supply current from VCC2 VCC2 = 100 V mA
I Outputs high 1 5
tTypical values are at VCCl
3-32
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 . DALLAS. TEXAS 75265
SN55501E
switching characteristics, VCC1 ... 12 V, VCC2 - 100 V, TA ... 25C

Delay time, Strobe to a outputs CL = 30 pF 250
tDHL high-to-Iow- Sustain to a outputs CL = 30 pF 250 ns
level outputs Clock to serial data output CL = 20 pF 147
tDLH low-to-high- Sustain to a outputs CL = 30 pF 450 ns
tTHL Transition time, high-to-Iow-Ievel a output CL = 30 pF 200 ns
tTLH Transition time, low-to-high-Ievel a output CL = 30 pF 300 ns
...
en
Q)
PARAMETER MEASUREMENT INFORMATION >
"a:
0
OUTPUT
UNDER
TEST
--1
....--- TEST
POINT
> co
''is.
~ CL (See Note A)
en
is
LOAD TEST CIRCUIT
VIH
DATA ______ R_R_E_LE_V_A_N_T____--J~~__~---V-A-L1-D--------J~~-----IR-R-E_LE_V_A_N_T______ VIL
tsu1~t--..~..
~---th--~~~1
CLOCK 1~5~0%~------------------------- VIH
VIL
~~ tDHL--+!
VOH
WAVEFORM 1 (See Note B) ,50%
SERIAL I I VOL
OUT jf-tDLH--.t ~_ _ _ _ _ _ _ _ __
VOH
WAVEFORM 2 (See Note C) I /50%
VOL
It---
th---+l
VIH
STROBE 'k,.50% /50%
I.--th--+l------ I VIL
I .I I
SUSTAIN 7 50 % I I
VIH
'-----tD-L"'HH tDHL~ tDLH-k---+!

VIL
On WAVEFORM 1-(S-e-e-N-o-te-D-)......9...0....
%-.L I I 90% VOH
10%,....----....;;!"" !~;.;,;;.---...;;111('"'10% VOL
____~~-.I~ ~ tTHL ~ \f-tTLH
VOH
an WAVEFORM 2 (See Note E) 90%"\;.!
10%~--- __ VOL
NOTES: A. CL includes probe and jig capacitance.
B. Serial out waveform for internal conditions such that a low is registered in R32.
C. Serial out waveform for internal conditions such that a high is registered in R32.
D. On output with a low stored in associated register Rn.
E. On output with a high stored in associated register Rn.
VOLTAGE WAVEFORMS
TEXAS 3-33
INSTRUMENTS
SN55501E
RECOMMENDED OPERATING CONDITIONS
MAXIMUM CLOCK FREQUENCY INPUT VOLTAGE LOGIC LEVEL LIMITS

vs vs
JUNCTION TEMPERATURE VCC1 SUPPLY VOLTAGE
10 10
N
VCC1 - 12 V V~
:I: VIH - VCC1
9 9
:l:
----
~\~(1\\(\
>
u
I
c:
CD
:J
8
7
- r-- ~J
VIL'" 0
(SYMMETRICAL CLOCK PULSE)
SINGLE
I
;;;;:-- >
8
7
~ V
-r--bL
C'
C
CD
U:: 6
I I DEVICE r-- r-- I
CD 6
Cl
;" ~
u f!
"C 0 5 CASCADED ~ "0 5
cr
-<
0
E 4
DEVICES r-- r-- >
...
:J 4
:J Co
E .E
.,C I - - -~
.
<".,CD
"xctI
:l:
I
3
2
3
2
- ~
\I\Lrna x
~
en u
0
::?
o o
25 50 75 100 125 10 11 12 13 14
TJ-Junction Temperature- C VCC1-Supply Voltage-V
FIGURE 2 FIGURE 3
THERMAL CHARACTERISTICS
junction temperature. formula
TJ = TA + PDRe
where
T A = free-air temperature
PD = average device power dissipation
Re = thermal resistance (junction-to-?lir, ReJA, or junction-to-case, RBJC)
PACKAGE RaJA RaJC

FD 68C/W 20 0 C/W
JD 45C/W 12C/W
3-34 TEXAS
INSTRUMENlS
SN65501E, SN75501E
AC PLASMA DlSPLAV DRIVERS
02472. MARCH 1983-REVISED DECEMBER 1985
Controls 32 Electrodes N PACKAGE

(TOP VIEW)
Low Stand-by Power Consumption CLOCK

SUSTAIN
VCC1
DATA IN
0 All Outputs Contain Sink and Source Clamp STROBE SERIAL OUT
Diodes 01 032
15 mA Steady-State Output Current 02 031
II
03 030
Rugged DMOS Outputs 04 029
CMOS Inputs
05
06
028
027
Direct Replacement for SN75501C 07
08
026
025
...en
Q)
description 09 024 'i:

>
The SN65501 E and SN75501 E are monolithic 010 023 C
BIDFETt integrated circuits designed to provide 011 022 >
CO
012 021
the serial-to-parallel conversion and level Q.
013 020 en
translation of data in a matrix-addressable
display. The device inputs are diode-clamped 014 019 C
015 018
CMOS inputs.
016 017
The Q outputs of these drivers are normally high GND ~_ _-.r- VCC2
and can be switched either selectively or
together. Any output whose associated register
bit (in the internal 32-bit serial register) contains FN PACKAGE
(TOP VIEW)
a low will switch low when the strobe input is
I-
switched low if the sustain input is high. All other :J
outputs remain high. When the sustain input is
switched low, all outputs switch low Ol-U
~~~ ...-~~
~~
a::UlO UI-Ci: N
independently of the data or strobe inputs. This ",-UI-:J...JU U~UJUC"l
OZUlUlUZ>OUlZO
feature can be used to generate a portion of the
sustain pulse required in the operation of an AC 6 5 432 1 4443424140
plasma display. The internal level-shift circuits 02 7 39 031
provide additional drive during the times that the 03 8 38 030
outputs switch high to facilitate fast rise times 04 9 37 029
while maintaining low standby power 05 10 36 028
consumption. All outputs contain clamp diodes 06 11 35 027
to the VCC2 and GND supply inputs. 07 12 34 026
08 13 33 025
The SN65501 E is characterized for operation
09 14 34 024
over the temperature range of - 40C to 85 DC.
010 15 31 023
The SN75501 E is characterized for operation
011 16 30 022
over the temperature range of OOC to 70C.
012 17 29 021
1819202122232425262728
t BIDFET - Bipolar. couble-diffused, N-channel and P-channel
MOS transistors on same chip - patented process. C"l"<tI!)(OOU Nt"- co 0')0
oooo[5Z U...- ...-...-N
uO 0 0 0
>
~~~~~:~~i~ai::I~1je ~~~:i~~ti~r :I~o::;:~:t:~~s not INSTRUMENTS
SN65501 E, SN75501 E
logic symbolt functional block diagram (positive logic)
CMOSI SUSTAIN
PLASMA DISP
STROBE
EN3
CLOCK
CLOCK (1) DATA IN
lEI
c
(ii'
DATA IN (39)
2
3
[> 3
(4) 01
.(5) 02
(19) 016
32-BIT
2 [> 3 (22) 017
"C STATIC
m SHIFT
-< REGISTER
..
c 2
2
[> 3
[> 3
(36) 031
(37) 032
..
<'
CD
en
(38) SERIAL OUT

1-------1>-- SERIAL OUT
FUNCTION TABLE
INPUTS OUTPUTS
FUNCTION SHIFT REGISTER SERIAL
DATA CLOCK STROBE SUSTAIN Q1 Q2 Q3 ... 032
R1 R2 R3 ... R32 DATA
H t H H H R1n R2 n .. R31 n R32 n H H H .... H
LOAD
L t H H L R1n R2 n .. R31 n R32 n H H H .... H
X X H H R1n R2n R3 n .. R32 n R32 n H H H .... H
STROBE
X H L H R1n R2n R3 n .. R32 n R32 n Rl R2 R3 .... R32
SUSTAIN X X X L R1n R2n R3 n .. R32 n R32 n L L L .... L

R1 ... R32 = levels currently at internal outputs of shift reQisters one through thirty-two, respectively.
R1 n ... R32n = levels at shift-register outputs R1 through R32 respectively, before the most recent t transition at the Clock input.
3-36 TEXAS -I!}

INSTRUMENTS
SN65501E, SN75501E
SUSTAIN
STROBEU
:~
UI'--- ILfUlJ
CLOCK
ANY Q OUTPUT B I
IRRELE----,VANT
r' B
II ...enCD
schematics of inputs and outputs >
"a::
C
EQUIVALENT OF EACH INPUT TYPICAL OF ALL Q OUTPUTS TYPICAL SERIAL OUTPUT
>
co
VCC1--------~-------4~ C.
en
C
INPUT--e-~~~-e
GND--__----------~~--
Supply voltage, Vee1 (see Note 1) ................ ; . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Supply voltage, Vee2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. VCC1 to 0.3 V
Continuous total dissipation at (or below) 25C free-air (see Note 2): FN package . . . . .. 1775 mW
N package . . . . . .. 1250 mW
Operating free-air temperature range: SN65501 E . . . . . . . . . . . . . . . . . . . . . . . . .. - 40 e to 85C
SN75501 E ............................ ooe to 70C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package .. . . . . . . . . .. 260C
Case temperature for 10 seconds: FN package ............................... ~ . .. 260C

PACKAGE
RATING FACTOR TA
FN 1775 mW 14.2 mW/oC 25C
N 1250 mW 10.0 mW/oC 25C
TEXAS . . 3-37
INSTRUMENTS
POST OFFICE BOX 65501 ~ " DALLAS, TEXAS 75265
SN65501E, SN75501E

MIN NOM MAX UNIT
Supply voltage, VCC1 10.8 12 13.2 V
High-level input voltage, VIH 0.75 VCC1
Low-level input voltage, VIL 0.25 VCC1
High-level Q output clamp current, 10KH 20 mA
Low-level Q output clamp current, 10KL -20 mA
II
c
Clock frequency, fclock, at or below, 25C junction temperature (see Note 3)
Setup time, tsu

Data inputs before clock!
Data inputs after clock!
62
20
0
50
8 MHz
ns
ns
en' Hold time, th

Strobe high after clock! 150
ns
'C Strobe high after sustain! 250
iii" I SN65501E -40 85
-< Operating free-air temperature, T A
I SN75501 E 0 70
C
...
C
:C:' NOTE 3: See Figure 3 for maximum clock frequency when devices are operated in cascade or for operation above T J = 25C.
CD
U; electrical characteristics over recommended operating free-air temperature range
SN65501E SN75501E
VIK Input clamp voltage VCC1 = 12 V, II = 12 mA -1 -1.5 -1 -1.5 V
I'OH = -1 mA 94 97.5 95 97.5
High-level Q outputs
VCC1 = 13.2 V'II
VOH VCC2 = 100 V 10H = -10 mA 92 94.5 93 94.5
V
output voltage !lOH = -15 mA 90 93.5 91 93.5
Serial out VCC1 = 10.8 V, 10H = -100 pA 9 10 9 10
I'OL = 1 mA 0.85 2 0.85 2
Low-level Q outputs
VCC1 = 13.2 V, II
2 4 2 4
VOL VCC2 = 100 ViOL = 10 mA V
output voltage IIOL = 15 mA 2.75 5 2.75 5
Serial out VCC1 = 10.8 V, 10L = 100 pA 0.1 1 0.1 1
Output clamp I'OK = 20 mA 1 2.5 1 2.5
VOK Q output VCC2 = 0 V
voltage !10K = -20 mA -1.2 -2.5 -1.2 -2.5
High-level VCC1 = 13.2 V, VIH = VIHmin,
IIH 1 1 pA
Low-level VCC1 = 13.2 V, VIL = VILmax,
IlL -1 -1 pA
VCC1 = 13.2 V,
ICC1 Supply current from VCC1 0.05 1 0.05 1 mA
VCC2 = 100 V
ICC2 Supply current from VCC2 VCC2 = 100 V 1 5 1 3 mA
tTypical values are at VCC1 = 12 V, TA = 25C.
3-38 TEXAS.
INSTRUMENTS
SN65501E. SN75501E
switching characteristics, V CC 1 12 V, VCC2

tDHL high-to-Iow- Sustain to a outputs CL = 30 pF 250 ns
tDLH low-to-high- Sustain to a outputs CL = 30 pF 450 ns

tTHL Transition time, high-to-Iow-Ievel a output CL = 30 pF 200 ns
tTLH Transition time, low-to-high-Ievel a output CL = 30 pF 300 ns

..
(I)
Q)
>
OUTPUT .~
UNDER
TEST
I TEST
POINT C
>
-:::r::- CL CO
':' (See Note A)
Q.
(I)
LOAD TEST CIRCUIT
C
DATA _ _ _IR_R_E_L_E_V_A_N_T_ _ ....JX VALID X:======I=R=R=EL=E=V=A=N=T====== ::~
tsu -iI~I-""'------..~;~:':':':':'-th-:"----- ---.....c~1
CLOCK
------""'"
, 1,50.%. - - - - - - - - - - - - - - - - - - - VIH
l4==-t-w--~~ tDHL~
VOH
WAVEFORM 1 (See Note B) ,,50%
SERIAL , 1. . . - - - - - - - - - - - VOL
OUT j4--tDLH--+/ _ - - - - - - - - - - - VOH
WAVEFORM 2 (See Note C) I /50%
jt-th ----+I
I ,I
~ ,.------
_ _ _ _ _/'50% VIH
STROBE
If---th---.t , VIL
,_-----+1-----.....11.....- - - - - VIH
SUSTAIN , - - - - - - ,7'50% I 1
tDHL~ tDLHH tDHL~ tDLH-k----.,j
On WAVEFORM 1 (See Note D)

""'k-------t-;f 4------~~VOH
:'lfr------iO% i~-------A'"10% 0 V
I I I ~If-t OL
-01 l+tTHL ~ 14-tTLH THL ~ k-tTLH V
--------~"1d--
On WAVEFORM 2 (See Note E)
-----t~90'*
'~ _____ -~10% 0
OH
VOL

B. Serial out waveform for internal conditions such that a low is registered in R32.
C. Serial out waveform for internal conditions such that a high is registered in R32.
D. On output with a low stored in associated register Rn.
E. On output with a high stored in associated register Rn.
VOLTAGE WAVEFORMS
TEXAS . . 3-39
INSTRUMENTS
SN65501E. SN75501E
MAXIMUM CLOCK FREQUENCY INPUT VOLTAGE LOGIC LEVEL LIMITS
VS VS
JUNCTION TEMPERATURE VCC1 SUPPLY VOLTAGE
--
10 10
N
VCC1 - 12 V l..--'-
l: VIH .' VCC1 9
-
9
~ ~"'~\(\
VILO l..--'
----
I
>-
(J
8 (SYMMEjRICAL CLOCK PULSE) 8
cQ)
:l
CT
Q)
7 t:::-:sr- iSiVicE ____
'IVG~E > 7
I
u: 6
---- ~ED~ 6
Q)
OJ
C .x
(J !9
iii" U
0 5 "0 5
"C
DEVICES~ >...
iii E 4 :l 4
--
:l
< E
C.
.E
'x!1l
C
~
C' ~
I
3
2
3
2
- VILma)!.
CD .x
(J
"'I
en 0
:;g
o o
25 50 75 100 125 10 11 12 13 14
TJ-Junction Temperature- C V CC 1 - Supply Voltage - V
FIGURE 2 FIGURE 3
THERMAL CHARACTERISTICS
TJ = TA + PORO
where
T A = free-air temperature
Po = average device power dissipation
RO = thermal resistance (junction-to-air, ROJA, or junction-to-case, ROJC)
PACKAGE RaJA RaJC

FN 22C/W
N 27C/W
3-40 TEXAS ~
INSTRUMENTS
ADVANCE SN6550B, SN75508
INFORMATION AC PLASMA DISPLAY DRIVERS
02924, DECEMBER 19B5- REVISED OCTOBER 1986
Controls 32 Electrodes FN PACKAGE

(TOP VIEW)
Very Low Steady-State Power Consumption
I-
::::>
Rugged DMOS Outputs o Zw
CMOS-Compatible Inputs ~ t;:;
..-~ ~
..-u ~ ffi ~ u tn;( ~ u ~
Dependable Texas Instruments Quality and dzucnCI:z>ocnzd
Reliability 6 5 4 3 2 1 44 43 42 41 40
description
The SN65508 and SN75508 are monolithic
81DFETt integrated circuits designed to provide
the serial-to-parallel conversion and level
02
03
7
8
9
10
11
39
38
37
36
35
031
030
029
028
027
II ...
(I)
Q)
translation of data in a matrix-addressable 12 34 026 >
'':
display. All inputs are CMOS compatible and all 13 33 025
C
outputs are totem-pole DMOS structures. 14 34 024
15 31 023 >
m
If the strobe input is at a high logic level, all 011 16 30 022 C.
outputs are high. When the strobe input goes 012 17 29 021 (I)
low, any output whose associated register bit 1819202122 232425262728 C

contains a low will go low. All outputs whose
associated register bit contains a high will remain
high. When the reset input is low, all register bits
are low. In this condition, all outputs will go low
when the strobe input goes low. The serial data
output from the shift register may be used to logic symbol t
cascade additional devices. This output is not
affected by the Strobe input.
CMOSI
The SN65508 is characterized for operation from PLASMA DISPLAY
- 40C to 85 DC. The SN75508 is characterized STROBE (42) V2
RESET
CLK--'-''!''''''-->
(6) Ql z
(7) Q2 o
. i=
2 !>
(21) Q16 <C
2 !> (25) Q17 :E
a:
ou.
-Zw
tThis symbol is in accordance with ANSI/IEEE Std 91-1094 and o
z
<C
>
c
tBIDFET -Bipolar, double-diffused, N-channel and P-channel MOS
transistors on same chip - patented process <C
~~~~~3~~~ro:~h~::of~:~:f~p~e~~8c~:~~~~rYst~~
~ata and other specifications are subject to change
without notice.
TEXAS
INSTRUMENTS
-111 3-41
SN65508, SN75508 ADVANCE
AC PLASMA DISPLAY DRIVERS INFORMATION
STRoBE-----------.
RESET----.....
01
CLOCK-----{>
DATA I N - - - - O I
c 32-BIT
(ii' STATIC
'C SHIFT
or REGISTER
.
<
...c
::-
...en
CD
P---SERIAL OUT
032
U
~---------------------------------------------------VIH
RESET
--------------------~
STROBE
u lj
- -
-------VIL
-VIH
c
CLOCK
32 _ _ _ _ _ _ VIL
V,H
<
2
(")
DATA
LJ-- ---- -:::

U
~------------------------------------~--------VOH
m
-2 OUTPUTS DATA
----VOL
'TI
o
:lJ
S
::j
o
2
3-42 TEXAS
INSTRUMENTS
"-!1
ADVANCE SN6550B, SN7550B
EQUIVALENT OF EACH INPUT TYPICAL OF ALL Q OUTPUTS TYPICAL OF SERIAL OUTPUT
VCC1--------e-----~~--- - - - - - - - -....- - - -...........- VCC1
INPUT ~D-J\N"Ir-o-" .....- - -__- OUTPUT II ...

U)
Q)
>
'':;:
C
GND~D-----------~~--- --------e-e--------GND >
C'CS
Q.
U)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) C
Supply voltage, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.3 V
High-level output voltage, VOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 95 V
High-level output current, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 3 rnA
Continuous total power dissipation at (or below)
25C free-air temperature (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1700 mW
Operating free-air temperature range: SN65508.......................... - 40C to .85 C
SN75508 ............................ ooc to 70C
Case temperature for 10 seconds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260C

2. For operation above 25 De free-air temperature, derate linearly to 1088 mW at 70 De at the rate of 13.6 mW/De.
2
o
i=
<C
~
a:
oLL
-2w
U
2
<C
>
c

TEXAS -Ii} 3-43
INSTRUMENTS
SN6550B, SN7550B ADVANCE
AC PLASMA DISPLAY DRIVERS INFORMATION

MIN MAX UNIT
Supply voltage. VCCl 7.65 9.35 V
Supply voltage. VCC2 Vee, 90 V
VCCl = 9.35 V 7 Vee,
High-level input voltage. VIH V
VCCl = 7.65 V 5.75 Veel
VCCl = 9.35 V 0 2.3
Low-level input voltage. VIL V
VCCl = 7.65 V 0 1.9
Output current. 10 (tw :5 1 /Ls) 80 mA
Clock frequency. fclock 4 MHz
Setup time. data before clock!, tsu 100 ns
Hold time. data after clock!. th 62 ns
Pulse duration. clock high or low. twCLK 125 ns
SN65508 -40 85
Operating free-air temperature. T A DC
SN75508 0 70
electrical characteristics over recommended operating free-air temperature range, VCC1 9.35 V,
VCC2 = 90 V (unless otherwise noted)
PARAMETER TEST. CONDITIONS MIN MAX UNIT
Q outputs VCCl = 7.65 V. 10H = -3 mA 83 87
Serial output VCCl = 7.65 V. 10H = -50/LA 6.8 7.65
Q outputs VCCl = 7.65 V. 10L = 10mA 1.4 2.4
VOL Low-level output voltage V
Serial output VCCl = 7.65 V. 10L = 50/LA 0 0.8
100 mAo tw :5 1 /LS 2.5
VOK Output clamp voltage VCC2 = 0110 = V
110 = -100 mAo tw :5 l/Ls -2.7
IIH High-level input current VI = 9.35 V 1 /LA
IlL Low-level input current VI = 0.4 V -1 /LA
lOS Short-circuit output current Vo = 0 -20 mA
ICCl Supply current from VCCl 500 /LA
Output high 500 /LA
ICC2 Supply current from VCC2
Output low 8.5 mA
switching characteristics, VCC1 7.65 V, TA

):>
C PARAMETER TEST CONDITIONS MIN MAX UNIT
<
):>
twRSTL
tdl
Pulse duration. reset low
Delay time. VCC2 to Q outputs (10%-10%) RL = 100 kn. CL = 100 pF
125
800
ns
ns
td2 Delay time. VCC2 to Q outputs (90%-90%) RL = 100 kn. CL = 100 pF 800 ns
:2
(")
):>
m
:-2
"T1
o
:JJ
S
):>
::!
o
:2
3-44 TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 DALLAS. TEXAs 75265
ADVANCE SN65508. SN75508
I14-4---twCLK--~~1
1 1
I 1
CLOCK ~\..O_% _ _ _ _ _..Jfo% 'i-%----::

I
14-14---twCLK~
1
j+-- tsu-~~14f--th---+t
1 6 V
II
...
CI)
DATAIN _ _ _ _ _ ...I~O% VALID ~\.,o_% _ _ _ _ _ _ _ oV

Q)
>
'i:
C
FIGURE 1. INPUT TIMING VOLTAGE WAVEFORMS >
ra
c..
CI)
STROBE~- - -- - - - -- - - - -- - - ----6V C
\10%
I OV
1
I
~---------90V
I 90%
14-14---10 ,.s---....~
VCC2 I
1 j+- t d2-.1
I I
I
------------'!I- - - - 10%
-1- - - - - - - -0 V
1 I~------VOH
I+-td1-+tll: 90%
ANY OUTPUT
z
o
-------------.......,j - - - - - - - --- 10%
VOL i=
~
FIGURE 2. VOLTAGE WAVEFORMS FOR OUTPUT DELAY TIMES
~
ex:
o
u.
-Zw
~
(.)
Z
~
>
C
~
TEXAS . . 3-45
INSTRUMENTS
'0
Cii"
'C.
or
<
o...
<"
...en
CD
3-46
SN65509, SN75509
02923, DECEMBER 19B5-REVISED OCTOBER 19B6
Controls 32 Electrodes FN PACKAGE

(TOP VIEW)
Very Low Steady-State Power Consumption
~
Rugged DMOS Outputs .--
dUUU~Ue~uu~
CMOS-Compatible Inputs .--ZZZUZ>ClZZv
Dependable Texas Instruments Quality and 6 5 4 3 2 1 44434241 40

Reliability 102 7 39
II
1~ 8 ~
description 104 9 37
105 10 36
The SN65509 and SN75509 are monolithic 106 11 35
BIDFETt integrated circuits designed to perform
the line-select operation of a matrix-addressable
107 12 34 ...tn
CI)
108 13 33
>
display. All inputs are CMOS compatible and all 201 14 34 308 'i:
outputs are totem-pole DMOS structures. 202 15 31 307 C
The 8-bit data stored internally in the serial 203 16 30 306 >
CO
204 17 29 305
register is transferred to one of four output
1819202122232425262728
C.
tn
sections selected by the last two bits entered
into the 10-bit shift register. All 24 unselected U'lc.or--COClU N..-NMV C
OOOOZzUOOOO
outputs will remain at the high level while the NNNNt!) ~MMMM
state of the eight selected outputs will be set by
the corresponding data in the shift register. NC-No internal connection
VCC2 can be used as an output strobe asshown
in typical operating sequence.
The SN65509 is characterized for operation from -40C to 85C. The SN75509 is characterized for
FUNCTION TABLE
INPUT BITS OUTPUTS

FIRST LAST
BYTE 4 BYTE 3 BYTE 2 BYTE 1
ENTERED ENTERED
08 07 06 05 04 03 02 01 51 SO 408-401 308-301 208-201 108-101
08-01
08-01
~
~
L
L
L
H
All H
All H
All H
All H
All H
08-01
08-01
All H
08-01 ~ H L All H 08-01 All H All H

4 08 01
H H 08 01 All H All H All H
t BIOFET - Bipolar, double-diffused, N-channel and P-channel MOS transistors on same chip - patented process
current as of publication date. Producu conform to
~~~~~:~~i~ar::1~78 ~!~~:~ti~r ~~o::~:~:t:~~s not INSTRUMENTS
SN65509, SN75509
logic symbol t
CMOS/PLASMA OISP
lEI
C
[S1]
[01]
o}
Z1
11
G14
1.11
8.11
1.12
iii' [02] Z2
'C
Dr [03] . Z3 8.12
-< 1.13
[04] Z4
...C
<' [OS] Z5
...
(I)
(I) [06] Z6
8.13
1.14
[07] Z7
[08] Z8 8.14

1Q1

1Q8
2Q1
DATA

2Q8
CLOCK
3Q1

10-81T
STATIC 3Q8
SHIFT
REGISTER 4Q1

08 4Q8
3-48 TEXAS "'.!}

INSTRUMENJS
SN65509, SN75509
ClK
DATA D8 D7 D6 D5 D4 D3 D2 D1 Sl SO
FIRST lAST SELECT
VCC2
BIT
ENTERED
----------------------------------------------~
DATA
BIT
ENTERED
BITS
II ...enCD
SELECTED
OUTPUTS QS-Q1
'i:
>
------------------------------------------------~---------------- C
>
m
UN SELECTED
OUTPUTS C.
en
C
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT TYPICAL OF All OUTPUTS
-------.------~--.--VCC2
OUTPUT
INPUT --.;..--A,N\t---<e-e
------~~~----~~GND
GND~.---------~~._-
TEXAS . . 3-49
INSTRUMENTS
SN65509, SN75509
Supply voltage, VCC2 ....................................................... 95 V
Input voltage, VI ........................................... - 0.3 V to VCC + 0.3 V
High-level output voltage, VOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 95 V
High-level output current, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 3 mA
Low-level output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25 mA
Continuous total power dissipation at (or below)
II
c
25C free-air temperature (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1700 mW
Operating free-air temperature range: SN65509 . . . . . . . . . . . . . . . . . . . . . . . . .. - 40C to 85 C
SN75509 ............................ ooC to 70C
C;;" Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260C
't:J
m
-<
2. For operation above 25C free-air temperature, derate linearly to 1088 mW at 70C at the rate of 13.6 mW/oC.
...c
<" recommended operating conditions
...en
CD
MIN MAX UNIT
Supply voltage, VCCl 8 11.4 V
Supply voltage, VCC2 VCCl 90 V
VCCl = 11.4 V 8.5 VCCl
VCCl = 8 V 6 VCCl
VCCl = 11.4 V 0 2.9
VCCl = 8 V 0 2
Output current, 10 (tw :5 1 I's) 80 mA
Clock frequency, fclock 3.1 MHz
Setup time, data before clock!. tsu 100 ns
Hold time, data after clock!. th 100 ns
Pulse duration, clock high or low, twCLK 161 ns
SN65509 -40 85
Operating free-air temperature, T A C
SN75509 0 70
electrical characteristics over recommended operating free-air temperature range, VCC1 11.4 V,
VOH High-level output voltage VCCl = 8 V, 10H = -3 mA 83 87 V
VOL Low-level output voltage VCCl = 8 V, 10L = 20 mA 1.4 2.4 V
100 mA, tw :5 1 I's 2.5
VOK Output clamp voltage VCC2 = 0 lio = V
lio = - 100 mA, tw :5 1 I's -2.7
IIH High-level input current VI = 11.4 V 1 I'A
IlL Low-level input current VI - 0.4 V -1 I'A
lOS Short-circuit output current Vo = 0 -20 mA
ICCl Supply current from VCCl 500 I'A
All outputs high 500 I'A
ICC2 Supply current from VCC2
Eight outputs low 5 mA
3-50 TEXAS -II}

INSTRUME:NTS
POST OFFICE BOX 65501 ~ bAllAS. 'tEXAS 75265
SN65509, SN75509
switching characteristics, VCC1 = 8 V, TA = 25C

I PARAMETER I TEST CONDITIONS I MIN MAX I UNIT I
I td1 Delay time. VCC2 to Q outputs (10% - 10%) I RL = 100 kn. CL = 100 pF I 800 I ns I
I td2 Delay time. VCC2 to Q outputs (90% - 90%) I RL = 100 kn. CL = 100 pF
I 800 I ns I

li'III4r---twCLK---"'~1
CLOCK ----t o
%
~14---twCLK--~~1
I
~'-~_%
I
______
I
...Il:'"-__
7V
0 V
...
CI)
CD
>
'i:
C
>
CO
14'- tsu-"'~"'14t---th-----+t C.
I I 7 V CI)
--'~O% ~,-o_'*_o
is
DATAIN _ _ _ _ _ _ VAUO _ _ _ _ _ _ _ oV
FIGURE 1. INPUT TIMING VOLTAGE WAVEFORMS
~----------90V
i-l-_______ --
J,90%
VCC2
____________
10_'*...1, -0 V
1Z
I I+-td241
I Ir--------VOH
90
II+- d1-+1
t
ANY OUTPUT %
I
I
10%
----------------' - - - - - - - - -VOL
FIGURE 2. VOLTAGE WAVEFORMS FOR OUTPUT DELAY
TEXAS -I.!} 3-51

INSTRUMENTS
POST OFFice BOX 655012 ' DALLAS. TeXAs 75265
II
c
(ii'
'C
or
-<
c...
<'
...
CD
fn
3-52
SN655128, SN755128
VACUUM FLUORESCENT DISPLAY DRIVERS
02654. DECEMBER 1985
Each Device Drives 12 Lines DW. N

DUAL-IN-L1NE PACKAGE
60-V Output Voltage Swing Capability (TOP VIEW)
25-mA Output Source Current Capability 011 010

o High-Speed Serially-Shifted Data Input 012 09
STROBE 08
TTL-Compatible Inputs SERIAL OUT 07
Latches on All Driver Outputs DATA IN VCC2
description
The SN65512B and SN75512B are monolithic
BIDFETt integrated circuits designed to drive a
VCC1
CLOCK
LA TCH ENABLE
01
02 '--_ _,-03
GND
06
05
04
II
... en
Q)
dot matrix or segmented vacuum fluorescent >
display. 0':::
logic symbol:t C
All device inputs are diode-clamped p-n-p inputs
>
CO
and will assume a high logic level when open- TTLIVAC
circuited. The nominal input threshold is 1.5 FLUOR DISP C.
en
volts. Outputs are totem-pole structures formed
by an n-p-n emitter follower and double-diffused
LATCH ENABLE (8)
STROBE (3 o
MaS (OM aS) transistors.
CLOCK (7)
The device consists of a 12-bit shift register, 12
latches, and 12 output AND gates. Serial data (9)
DATA IN (5) 2D t> 3 al
is entered into the shift register on the low-to- (10)
high transition of the Clock. When high, the 2D t> 3 a2
(11)
Latch Enable input transfers the shift register 2D t> 3 a3
(12)
contents to the outputs of the 12 latches. The 2D t> 3 a4
(13)
active-low strobe input enables all Q outputs. 2D t> 3 a5
Serial data output from the shift register may be (14)
2D t> 3 as
used to cascade shift registers. This output is not (17)
2D t> 3 a7
affected by the Latch Enable or Strobe inputs. (18)
2D t> 3 a8
(19)
The SN65512B is characterized for operation 2D t> 3 a9
from -40 DC to 85 DC. The SN75512B is 2D t> 3
(20)
al0
characterized for operation from 0 DC to 70 DC. (1)
2D t> 3 all
(2)
2D t> 3 a12
(4)
SERIAL OUT
t This symbol is in accordance with ANSI/IEEE Std 91-1984

and lEe Publication 617-12_
t BIDFET -Bipolar, double-diffused. N-channel and P-channel MOS transistors on same chip - patented process.
spacifications per the terms of Texas Instruments
TEXAS 3-53
:~:~:~~i~a{::1~1i ~!::i~~tj:; :I~::~::t:::s not INSTRUMENTS
SN655128, SN75512B
LATCH
ENABLE
STROBE
c
C;;'
"C
0;
<
C
CLOCK
R1
R2
12
.., 12-BIT
LATCHES
<' DATA STATIC

..,CD IN SHIFT R11
CJj
REGISTER
R12
>--------- SERIAL OUT
FUNCTION TABLE
CONTROL INPUTS
SHIFT REGISTER LATCHES OUTPUTS
FUNCTION LATCH
R1 THRU R12 LC1 THRU LC12 SERIAL 01 THRU 012
CLOCK ENABLE STROBE
t X X Load and shift t Determined by Latch Enablet R12 Determined by Strobe
LUAD
Not X X No change Determined by Latch Enablet R12 Determined by Strobe
X L X As determined above Stored data R12 Determined by Strobe
LATCH
X H X As determined above New data R12 Determined by Strobe
X X H As determined above Determined by Latch Enablet R12 All L
STROBE
X X L As determined above Determined by Latch Enable t R12 LC1 thru LC12, respectively

t R12 takes on the state of R11, R11 takes on the state of R10, ... R2 takes on the state of R1, and R1 takes on the state of the data input.
t New data enter the latches while Latch Enable is high. These data are stored while Latch Enable is low.
3-54 TEXAS ~
INSTRUMENTS
SN65512B, SN75512B
CLOCK
DATA
VALID IRRELEVANT
IN
II
SR
N_v_A_L1_D__________~___________V_A_L_ID____________
CoNTENTS ____________
LATCH
ENABLE
_________________________________ ~rl~ ________________________
... en
CD
PREVIOUSLY STORED DATA NEW DATA VALID
LATCH >
'i:
CONTENTS
STROBE --------------------------------~
C
>
co
Q OUTPUTS
Q.
VALID en
C

VCC1--------~-------- OUT
--------~------Vec2FOR
Q OUTPUTS
VeC1 FOR
SERIAL OUTPUT
._------OUTPUT
INPUT ---411~~
--~:rl
~GND
TEXAS 3-55
INSTRUMENTS
SN65512B, SN75512B
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. VCC1
Continuous total power dissipation at (or below) 25C free-air temperature (see Note 2)
OW package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1125 mW
N package ........................................................ 11 50 mW
Operating free-air temperature range: SN65512B.. . . . . . . . . . . . . . . . . . . . . . . .. - 40C to 85 C
11
C
NOTES:
SN75512B ............................ OOC to 70C

Cii"
"C 2. For operation above 25C free-air temperature, derate the DW package at the rate of 9.0 mW/oC and the N package at the
Dr rate of 9.2 mW/oC.
<
c... recommended operating conditions
<' SN65512B SN75512B
...en
CD
MIN MAX MIN MAX
UNIT

High-level input voltage, VIH 2 2 V
Low-level input voltage, VIL 0.8 0.8 V
High-level output current, IOH -25 -25 mA
Low-level output current, IOL VCC1 = 10 V 5 5 mA
VCC1 = 15 V, TA = 25C 0 4 0 4
Clock frequency, fclock MHz
VCC1 = 5 V, TA = 25C 0 1 0 1
VCC1 = 15 V, TA = 25C 100 100
Pulse duration, clock high or low, tw ns
VCC1 = 5 V, TA = 25C 500 500
Setup time, data before clocki, tsu VCC1 = 15 V, TA = 25C 100 100
ns
(see Figure 1) VCC1 = 5 V, TA = 25C 250 250
Hold time, data after clock i, th VCe1 = 15 V: TA = 25C 50 50
ns
(see Figure 1) VCC1 = 5 V, TA = 25C 250 250
Operating free-air temperature, T A -40 85 0 70 C
electrical characteristics over recommended operating free-air temperature range, VCC2 = 60 V (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TVpt MAX UNIT
VIK Input" clamp voltage II = -12 mA -1.5 V
High-level output Q outputs IOH = -25 mA 57.5 58
VOH V
voltage Serial output IOH = - 200 p.A, VCC1 = 10 V 9 9.5
Low-level output Q outputs IOL = 5 mA, VCC1 = 10 V 2.6 5
VOL V
voltage Serial output IOL = 200 p.A, VCC1 = 10 V 0.05 0.2
IIH High-level input current VCC1 = 15 V, VI = 5 V 0.01 1 p.A
IlL Low-level input current VCC1 = 15 V, VI = 0.8 V -25 -150 p.A
VI = 5 V 80 500 p.A
ICC1 Supply current from VCC1 VCC1 = 15 V
VI = 0.8 V 2 6 mA
All outputs high 10 100 p.A
ICC2 Supply current from VCC2 VCC1 = 15 V
Strobe at 2 V 0.8 3 mA
t All typical values are at VCC1 = 10 V, TA = 25C.
3-56 TEXAS
INSTRUMENTS
-1!1
SN65512B, SN75512B
switching characteristics, VCC1 10 V, VCC2 60 V, TA

tDHL Delay time, high-to-Iow-Ievel output 300 ns
tDLH Delay time, low-to-high-Ievel output CL = 30 pF, 300 ns
tTHL Transition time, high-to-Iow-Ievel output See Figure 2 500 ns
tTLH Transition time, low-to-high-Ievel output 500 ns
CLOCK
~--------tw------~~
'i:
C
...tVen
>
>-
CO
VIL Q.
en
14--------tw ------~
C
I4--tsu---.t.---th~
I ,
I
XX>OO : :
1
DATA IN <XX><>< VALID
~:S30ns t+---+t-:s 30 ns
I I 1 I
1 I , I
I I I ~1__- - - - - - - - - 3 V
1 90%
I
I 1
STROBE '.5 V
I
I 1 I
I "'1 1_
_______'__%__ I - - - - - - - 0 V
I
I 1
I4-tOLH~ J4- t OHL-+t
I I
1
I
.r--------~I"-90% ----VOH -
I
I I
Q OUTPUTS
I I
1 I
I
1 1 VOL
~tTHL
FIGURE 2. SWITCHING-TIME VOLTAGE WAVEFORMS
TEXAS . . 3-57
INSTRUMENTS
lEI
c
(ii'
"C
m
<
c...
<'
...
(1)
en
3-58
SN65513B, SN75513B
02721, MARCH 1983-REVISEO SEPTEM8ER 1986
Each Device Drives 12 Lines OW OR N PAC~A~E

(TOP VIEW)
60-V Output Voltage Swing Capability'
011 010
o High-Speed Serially-Shifted Data Input
STROBE 08
SERIAL OUT 07
TTL-Compatible Input DATA IN VCC2
Reset Input
VCC1 GND
description
The SN65513B and SN75513B are monolithic
BIOFETt integrated circuits designed to drive a
CLOCK
RESET
01
02
06
05
04
03
II
. (I)
CD
dot matrix or segmented vacuum fluorescent >
-.::,
display.
C
All device inputs are diode-clamped p-n-p inputs >
and will assume a high logic level when left open. CO
Q.
The nominal input threshold is 1.5 volts. Ou.,tputs (I)
are totem-pole structures formed by n-p-n is
emitter follower and double-diffused MOS
(OMOS) transistors.
The device consists of a 12-bit shift register and 12 output AND gates. Data is entered into the shift register
on the low-to-high transition of the Clock input. The active-low strobe input enables all Q outputs. The
Reset input sets the shift register contents to all lows. The serial data output from the shift register may
be used to cascade additional devices. This output is not affected by the strobe input.
The SN65513B is characterized for operation from -40C to 85C and the SN75513B is characterized
logic symbol:l:
TTLIVAC
FLUOR olSP
STROBE
RESET
CLOCK
191
DATA IN 01
1101
02
1111
C> 2 03
1121
C> 2 04
1131
C> 2 05
1141
C> 2 06
1171
C> 2 07
1181
C> 2 08
1191
C> 09
1201
C> 010
111
C> 2 all
121
C> 2 012
141
SERIAL OUT
t BIDFET -Bipolar, double-diffused, N-channel and P-channel MOS transistors on same chip-patented process.
i This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
PRODUCTION DATA documents contain Copyright 1983, Texas Instruments Incorporated

~fOd~~!~~onlfno:~ut~:~:~ifi;::~~~~ser~~~r~~~~ TEXAS . . 3-59
Production processing does not necessarJy INSTRUMENlS'
include testing of all parameters. POST OFFICE BOX 655012 DALLAS. TEXAS 75265
SN65513B, SN75513B
STROBE
RESET
EI
c
Ci)'
CLOCK
DATA IN - - - - - - + - - + - - - 1 1 0
....--~R
SHIFT
REGISTER
R1 01
'C
....-+---11> C1
iii'
-<
c...
...<'en
CD 10
R2 02
R
C1

R11 011
R
C1
10
012
R
L..-----l> C1
SERIAL OUT
FUNCTION TABLE
INPUTS OUTPUTS
FUNCTION SHIFT REGISTERS
RESET CLOCK STROBE SERIAL 01THRU 012
R1 THRU R12
LOAD H r x Load and Shift t R12t Determined by" strobe
H Nor H No Change R12 All L
STROBE
H Nor L No Change R12 R1 thru R12, respectively
RESET L H X All L L All L
H = high level, L = low level, X = irrelevant, r = low-to-high transition.

t R12 and the serial output take on the state of R11, R11 takes on the state of R10 ... R2 takes on the state of R1 , and
R1 takes on the state of the data input.
3-60 TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 ' DALLAS; TEXAS 75265
SN65513B, SN75513B
CLOCK
DATA IN VALID IRRELEVANT
SR CONTENTS
RESET
INVALID VALID
u
CLEARED
II
. (I)
Q)
>
''::
STROBE
C
Q OUTPUTS VALID >
CO
C.
(I)
schematics of inputs and outputs C

VCC1 --------~~-------- VCC2 FOR

Q OUTPUTS
VCC1 FOR
SERIAL OUTPUT
e-------- OUTPUT
INPUT - ....- - 4 ----.JSl

~GND
Supply voltage, VCC1 (see Note 1) ............................................ , 15 V
Supply voltage, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 70 V
.Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. V CC 1
Continuous total dissipation at (or below) 25 DC free-air temperature (see Note 2) . . . . . .. 1150 mW
Operating free-air temperature range: SN1355138. . . . . . . . . . . . . . . . . . . . . . . . .. - 40 DC to 85C
SN755138 ............................ ODC to 70C
NOTES: 1. Voltage values jlre with respect to network ground terminal.

TEXAS . . 3-61
INSTRUMENTS
SN65513B, SN75513B,
recommended operating conditions, T A ... - 40 C to 85C (unless otherwise noted)

MIN MAX UNIT
Supply voltage, VCC2 0 SO V
High-level input voltage, VIH 2 V
High-level output current, IOH 25 mA
Low-level output current, IOL VCC1 = 10 V 5 mA
VCC1 = 15 V, TA = 25C 0 4
Clock frequency, fclock MHz
VCC1 = 5 V, TA = 25C 0 1
VCC1 = 15 V, TA = 25C 100
Pulse duration, clock high, tw ns
VCC1 = 5 V, TA = 25C 500
VCC1 = 15 V, TA = 25C 100
Setup time, data before clockt (see Figure 1I, tsu ns
VCC1 = 5 V, TA = 25C 250
VCC1 = 15 V, TA = 25C 50
Hold time, data after clockt (see Figure 1I, th ns
VCC1 = 5 V, TA = 25C 250
SNS55138 -40 85
SN755138 0 70
electrical characteristics over recommended operating free-air temperature range, VCC1 - 10 V,

VCC2 .. 60 V (unless otherwise noted)
VIK Input clamp voltage 11= -12 mA -1.5 V
Q outputs IOH = -25 mA 57.5 58
Serial output IOH = -200/LA 9 9.5
Q outputs IOL = 5 mA 2.S 5
Serial output IOL = 200/LA 0.05 0.2
IIH High-,Ievel input current VCC1 = 15 V, VI = 15 V 0.01 1 /LA
IlL Low~level input current VCC1 = 15 V, VI = 0 V -25 -150 /LA
VCC1 = 15 V, All inputs at 5 V 0.08 0.5
ICC1 Supply current from VCC1 mA
VCC1 = 15 V, All inputs at 0.8 V 2 S
VCC1 = 15 V, All outputs high 0.01 0.1
ICC2 Supply current from VCC2 mA
VCC1 = 15 V, Strobe at 2 V 0.8 3
t All typical values are at VCC1 = 10 V, TA = 25C.
switching characteristics, VCC1 = 10 V, VCC2 = 60 V, TA ... 25C

tDHL Delay time, high-to-Iow-Ievel output 300 ns
tDLH Delay time, low-to-high-Ievel output CL = 30 pF, 300 ns
tTHL Transition time, high-to-Iow-Ievel output .See Figure 2 500 ns
3-62 TEXAS . .
INSTRUMENTS
SN655138, SN755138
14 tw ~I
CLOCK \1 \ . -_ _ _ _ _ _ _..J 1
I
t,.-------~'i~5~ VIH
L..:..- VIL
14 tw ~I
I
I4---tsu--t~*14--th~
DATAIN~
"><xxXXXXX><%I~~~~~~~
I
I I
VALID ~
#'1-----.. . . .-.. . . .-
\ll<XXXXXXXXXX
1 vlH
....
CI)
- \...-------~ ~~~~~~~IIo4VIL (1)

>
'i:
C
>
m
-+I 14-:s 30 ns
--+i j4-:S 30 ns I I 3 V Q.
CI)
~
STROBE
I
I 1.5 V
j{1 90% i5
~.
_ _ _ _ _ _...;1.;;.0';';;%.:I.1 _ _ _ _ _ _ OV
I
I4-tOLH~ I+-tOHL +i
90%~1
Q OUTPUTS
1:
~
_.
~ ~tTLH
II
I
I I
~ ~tTHL
10%
VOH
VOL
FIGURE 2. SWITCHING-TIME VOLTAGE WAVEFORMS
TEXAS ~ 3-63
INSTRUMENlS
C
Cii"
"C
Q)
-<
.<"
C
..
CD
o
3-64
ADVANCE SN75514
INFORMATION VACUUM FLUORESCENT DISPLAY DRIVER
D2732, APRIL 19B3-REVISED SEPTEMBER 19B6
Each Device Drives 12 Lines OW OR N PACKAGE

(TOP VIEW)
125-V Output Voltage Swing Capability
011 010
High-Speed Serially Shifted Data Input STROBE 08
SERIAL OUT 07
CMOS-Compatible Inputs DATA IN VCC3
Latches on All Driver Outputs VCC1 VCC2
CLOCK
01
02
03
GND
06
05
04
II
...
CI)
Q)
description >
'i:
The SN75514 is a monolithic BIDFETt integrated circuit designed to drive a dot matrix or segmented Vqcuum C
fluorescent display. All device inputs are diode-clamped CMOS compatible inputs. The outputs are totem- >
m
pole structures formed with double-diffused MaS (DMOS) transistors.
C.
CI)
The device consists of a 12-bit shift register, a 12-bit storage register, and 12 output AND gates. Serial
data is entered into the shift register on the low-to-high transition of the clock input. On the high-to-Iow C
transition of the strobe input, data is transferred from the shift registers to the latches. When Strobe goes
high, all Q outputs are enabled. Serial data output from the shift register may be used to cascade additional
devices. Serial Out is not affected by the Strobe input.
Supply voltage VCC2 and VCC3 are used to provide 25-milliampere output source current capability at
acceptable static device power dissipation. In this mode of operation VCC3 should be equal to
VCC2 + 10 volts. It is possible to operate this device with VCC3 = VCC2. However, the current capability
will be reduced.
The SN75514 is characterized for operation from OOC to 70C.
logic symbol * logic diagram (positive logic)
STROBE - - - - - - I
STROBE STORAGE
REGISTER
:2
CLOCK
DATA IN
CLOCK
C2
o
i=
DATA IN 01
02
<t
2D 03 :!E
(11)
04 a:
2D
2D t> 3
(12)
(13)
05 oLL
2D t> 3 06
2D
2D
2D
t>
t>
t>
3
3
3
(17)
(18)
(19)
07
08
09
-w
:2
(20) (.)
2D t> 3 010
2D t> 3
(1)
011 ~------SERIAL OUT
:2
2D t> 3
(2)
012 <t
c>
(4)
SERIAL OUT
t BIDFET -Bipolar, double-diffused, N-channel and P-channel MOS transistors on the same chip-patented process.
tThis symbol is in accordance with ANDI/IEEE Std 91-1984 lEG Publication 617-12. <t
information on new )Iroducts in the sampling or
preproduction phase of development. Charactenstic
without notice.
-IJ1
TEXAS
INSTRUMENTS
3-65.
SN75514 ADVANCE
VACUUM FLUORESCENT DISPLAY DRIVER INFORMATION
FUNCTION TABLE
CONTROL INPUTS SHIFT REGISTERS LATCHES OUTPUTS

FUNCTION
CLOCK STROBE R1 THRU R12 LC1 THRU LC12 SERIAL Q1 THRU Q12
t X Load and shift * Stored data R12 Determined by Strobe
LOAD
Not X No change Stored data R12 Determined by Strobe
X ~ As determined above New data R12 Determined by Strobe
LATCH
X No~ As determined above Stored data R12 Determined by Strobe
X H As determined above Stored data R12 LC 1 thru LC 12, respectively
II
c
STROBE
X L As determined above Stored data R12 All L
H = high level, L = Low level, X = irrelevant, I = low-to-high-Ievel transition, I = high-to-Iow-Ievel transition.

* R12 takes on the state of R11, R11 takes on the state of R10 ... R2 takes on the state of R1 , and R 1 takes on the state ofthe data input.
Cir typical operating sequence

"C
6)
< CLOCK
...C
<'
...
(t)
tJ)
SHIFT REGISTER INVALID VALID

CONTENTS ________________________________ ~ ________________________________ _
STROBE
STORAGECONTENTS
REGISTER __________________________________________
PREVIOUSLY STORED DATA ~
NEW DATA VALID
______________________ _
Q OUTPUTS VALID VALID

l>
c EQUIVALENT OF EACH INPUT TYPICAL OF ALL Q OUTPUTS TYPICAL OF SERIAL OUTPUTS
<
l> VCC1 --------__~----__~~--I
VCC3
------....t----- VCC1
:2
("')
l>
m
INPUT - -....JV\,..,......... ....----OUTPUT
:2 ...-tI.-4IHe--OUTPUT
."
o
:a
s:l> GND--__-.~--------__~---
--~TI' .
--------------~-4~~~-------GND
::!
o
:2
3-66
, TEXAS -Ij}
INSTRUMENTS
ADVANCE SN75514
Supply voltage, VCC1 (see Note 1) ........................................... . 15 V
Supply voltage, VCC2 ................................................... . 130 V
Supply voltage, VCC3 ................................................... . 140 V
Supply voltage difference, VCC3 - VCC2 ....................................... . 75 V
Input voltage ............................................................ . VCC1
DW package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1125 mW
N package ........................................................ 11 50 mW
Operating free-air temperature range ..................................... , OOC to 70C
Storage temperature range ......................................... - 65C to 1 50C
II (I)
I-
Q)
2. For operation above 25C freeair temperature, derate the OW package to 720 mW at 70C at the rate of 9.0 mW/oC, and >
0'::
the N package to 736 mW at 70C at the rate of 9.2 mW/oC.
C
recommended operating conditions ca
>
. NOM
Q.
MIN MAX UNIT (I)
Supply voltage, VCC1 5 15 V C
Supply voltage, VCC3 VCC2 VCC2+ 1O V
VCC1 =5V 4
High-level input voltage, VIH (see Figure 1) V
VCC1 = 15 V 11.25
VCC1 =5V 1
Low-level input voltage, VIL (see Figure 1) V
VCC1 = 15 V 3.75
High-level output current, IOH (T A = 25C) -25 mA
Low-level output current, IOL 2.5 mA
Clock frequency, fclock (see Figure 2) 0 7.5 MHz
Data setup time before clockt, tsu (see Figure 3) 150 ns
Data hold time after clockt, th (see Figure 3) 150 ns
VCC = 5 V 1200
Delay time, strobe low to clock high, td(SL-CH) ns
VCC = 15 V 500
2:
o
i=
<C
:?!
a:
o
U;.
2:
w
<C
'(.)
2:
Ie:(
>
c
<C
TEXAS 3-67
INSTRUMENTS
SN75514 ADVANCE
electrical characteristics over recommended operating free-air temperature ral"!ge, VCC1 = 10 V (unless
otherwise noted) .
VIK Input clamp voltage II = -1 mA -1.5 V
High-level output Q outputs VCC2 = 130 V, 10 = -25 mA 125 126
V
VOH
voltage Serial IOH = -200/loA 9 9.3
Low-level output Q outputs IOL = 2.5 mA 1.5 5
V
VOL
voltage Serial IOL = 200/loA 1
lEI
c
(ii'
IIH
IlL
ICCl
Supply Current from VCCl

VCCl
VCCl
VCCl
VCCl
VCCl
=
=
=
=
=
10 V,
10 V,
15 V
5 V
15V,
VI
VI
=
=
10 V
0 V
0.01
-5
1
5
5
/loA
p.A
mA
All outputs high -5

'C ICC2 Supply Current from VCC2 VCC2 = 130 V, mA
or VCC3 = 140 V
All outputs low 0.1
< VCCl = 15 V, All outputs high 5
c
~. ICC3 Supply Current from ICC3 VCC2 = 130 V, mA
Strobe atO V 0.1
:c:' VCC3 = 140 V
CD
C;; t All typical values are at T A = 25 cC.
switching characteristics, VCC1 =15 V, VCC2 = 130 V, TA

tDHL Delay time, high-to-Iow-Ievel output 0.8 p'S
tDLH Delay time, low-to-high-Ievel output CL = 30 pF, 0.8 /los

tTHL Transition time, high-to-Iow-Ievel output See Figure 4 1 P.s
tTLH Transition time, low-to-high-Ievel output 3 /los

c
<

2
n
m
-
2
'TI
o:D
S

:::!
o
2
3-68 TEXAS
INSTRUMENTS
ADVANCE SN75514
INPUT THRESHOLD MAXIMUM INPUT DATA RATE

vs vs
SUPPLY VOLTAGE VCC1 SUPPLY VOLTAGE
12 8
I0 I I 0 I 0
/V
0
=0 TA =0 C to 70 C
TA C to 70 C
7
/
II
N
10
V
J:
~ 6 /
>I ~~ ~ V
8 ~~ c
/
8. .~ ~
go
5
/ ...en
~
!! Q)
"0
>... 6 u:..:.: 4
"i:
>
::I
/~ V u
o
1/ C
~
Q.
C (3 3
'"j ~,\.. >
>
4
~
.(C\u(C\
E
::I
.5x 2 / Q.
CO
en
2 ~
ro /V C
/
o o
3 5 7 9 11 13 15 4. 6 8 10 12 14 16
Supply Voltage VCC1-V Supply Voltdge VCC1-V
FIGURE 1 FIGURE 2
2:
o
i=
<!
:a:c:
ou.
-w
Z
CJ
2:
<t
>
c
<t
TEXAS 3-69
INSTRUMENTS
POST OFFICE BOX 855012 OALLAs, TEXAS 1liaB5
SN75514 ADVANCE
1 4 - - - tw ---+I
I
, - - - - - - - ' \ - : - - - - - VIH
I
CLOCK
~tsu~th--+t
I I
o
C;;'
"0
iii'
-<
DATA IN <><XXX' :
VALID XXX><>
: VIH
V,L
..<'o FIGURE 3. INPUT TIMING VOLTAGE WAVEFORMS
..
CD
k-*- ';;;;30 ns
'
(I) 1+-+1-- QO ns
I I I I
-1:- - ---- -%:-1~9~0'l(~o

N
- - - - - - VCCl
STROBE r------- I 50%
I I I
I ------- :.i1Q1'o---------- OV
I
I4-----*-tDHL~~-__t~.... tDLH
a OUTPUTS
~O,:%
I
~tTHL
I M------:::
I~ ~I
~tTLH
FIGURE 4. SWITCHINGTIME VOLTAGE WAVEFORMS
l>
C
<
l>
;2
(')
m
;-2
11
o
:J:J
S
l>
-I
o;2
3-70 TEXAS ~
INSTRUMENTS
SN65518, SN75518
02720. MARCH 1983-REVISED OCTOBER 1986
Each Device Drives 32 lines N DUAl-IN-L1NE PACKAGE

(TOP VIEW)
o 60-V Output Voltage Swing Capability
25-mA Output Source Current Capability VCC2 VCCl

SERIAL OUT DATA IN
High-Speed Serially Shifted Data Input Q32 Ql
Latches on All Driver Outputs Q31 Q2
Q30 Q3
Q29 Q4
II
description
Q28 Q5
The SN65518 and SN75518 are monolithic Q27 Q6
BIDFETt integrated circuits designed to drive a
dot matrix or segmented vacuum fluorescent
display.
Q26
Q25
Q24
Q7
Q8
Q9
. f/)
CD
>
The devices each consist of a 32-bit shift Q23 Ql0 ''::::
register, 32 latches, and 32 output AND gates. Q22 Qll C
Serial data is entered into the shift register on Q21 Q12 >
CO
the low-to-high transition of the clock input. Q20 Q13
Q19 Q14
C.
f/)
While the Latch Enable input is high, parallel data
is transferred to the output buffers through a Q18 Q15 C
32-bit latch. Data present in the latch during the Q17 Q16
high-to-Iow transition of Latch Enable is latched. STROBE LA TCH ENABLE
When the Strobe input is low, all Q outputs are GND CLOCK
enabled. When the Strobe input is high, all Q
outputs are low. FN PACKAGE
Serial data output from the shift register may be (TOP VIEW)
used to cascade additional devices. This output

is not affected by the Latch Enable or Strobe
inputs.
The SN65518 is characterized for operation from
- 40C to 85 C and the SN75518 is
characterized for operation from 0 C to 70C. 6 5 4 3 2 1 4443 42 41 40
39 Q4
38 Q5
37 Q6
36 Q7
35 Q8
34 Q9
33 Ql0
32 Qll
31 Q12
30 Q13
29 NC
1819202122232425262728
UCXlr--WCl~W)U)<tU
Z~~CXlZU-I~~~2
dd~t!)g~ddd
t; U~
:r:
U
I-

-I
tSIDFET -Bipolar. double-diffused. N-channel and P-channel MaS NC - No internal connection
transistors on same chip-patented process.
~~~~~~~~i~ar~~I~~e ~!~:i~~tigt" :llo::~:~:t:~s~s not
TEXAS
INSTRUMENTS
"'J1 3-71

SN65518, SN75518
logic symbol t
CMOSIVAC
FLUORDISP
CLOCK (21)
II
c
C;;"
DATA IN (39)
2D [> 3
(38) Q1
(37) Q2
(23) Q16
2D [> 3 (18) Q17
"C
Dr
<
.<"
C 2D [> 3
2D [> 3
(4) Q31
(3) Q32
..
CD
tn
(2) SERIAL
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
OUT
STROBE
LATCH - - - - - - - ,
ENABLE SHIFT
REGISTER LATCHES
DATA IN
CLOCK ----.---1>
3-72 TEXAS -II}

INSTRUMENTS
SN65518, SN75518
FUNCTION TABLE
CONTROL INPUTS
FUNCTION LATCH
R1 THRU R32 LC 1 THRU LC32 SERIAL 01 THRU 032
CLOCK ENABLE STROBE
I X X Load and shift' Determined by Latch Enable R32 Determined by Strobe
LOAD
Nol X X No change Determined by Latch Enable R32 Determined by Strobe
X L X As determined above Stored data R32 Oetermined by Strobe
LATCH

X H X As determined above New data R32 Determined by Strobe
X X H As determined above Determined by Latch Enable~ ~32 All L
STROBE
X X L As determined above Determined by Latch Enable R32 LC 1 thru LC32, respectively
H = high level, L = low level, X = irrelevant, I = low-to-high-Ievel transition.

* R32 and the serial output take on the state of R31, R31 takes on the state of R30, ... R2 takes on the state of R1, and R1 takes on
the state of the data input.
...
(I)
Q)
New data enter the latches while Latch Enable is high. These data are stored while Latch Enable is low. >
'i:
C
typical operating sequence >-
CO
Q.
(I)
CLOCK,nnnn nnnnni
U U U U L J U U U U U C
SRCONTENTS INVALID VALID
LATCH ENABLE ________________________________~r_1~ _______________________
LATCH
CONTENTS PREVIOUSLY STORED DATA
__________________________________-L______ NEW DATA VALID
________________ __ ~
STROBE
a OUTPUTS ________________________________________~_V_A_L_ID__L__ _ _ _ _ _ _ _ _ _ _ __ _
TEXAS "'./} 3-73

INSTRUMENTS
SN65518, SN75518

VCC1--------e-----~~--- - - - - - - - -......~--- VCC2 - - - - - -...----......H..- VCC1
INPUT--e-~~~-e e_----- OUTPUT e----~-OUTPUT
c
(ii'
'C
or
'< - - - - - - - -..............~- GND ----~~-----GND
GND~__----------~~---
...
C
<'
...en
CD absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VeC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Supply voltage, VeC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 70 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. VCe1
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . .. 1650 mW
FN packag'e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1700 mW
Operating free-air temperature range: SN65518..... . . . . . . . . . . . . . . . . . . . . .. - 40C to 85 e
SN75518 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ooe to 70C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,.......... - 65C to 150C
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260C
2. For operation above 25 DC free air temperature, derate the N package linearly at the rate of 13.2 mW / DC and the FN package
linearly at the rate of 13.6 mW/ DC.
3-74 TEXAS
INSTRUMENTS
SN65518, SN75518
recommended operating conditions, T A - 25C (unless otherwise noted)

MIN MAX UNIT
Supply voltage, VCCl 4.5 15 V
VCCl = 4.5 V 3.5
VCCl = 15 V 12
VCCl = 4.5 V 1
II
VCCl = 15 V 6
High-level output current, IOH -25 rnA
I
Low-level output current, IOL 2 rnA
VCel = 10 V to 15 V 0 5
VCCl = 4.5 V 0 1
MHz
... en
CD
VCCl =10Vto15V 100
Pulse duration, clock high, tw(CKH) ns >
VeCl = 4.5 V 500 ".::
VCCl = 10 V to 15 V 100 C
Pulse duration, clock low, tw(CKL) ns
VCCl = 4.5 V 500 >
CO
VCel = 10 V to 15 V 75
Q.
Setup time, data before c1ockf, tsu ns
VCCl = 4.5 V 150 en
Hold time, data after clockf, th
VCCl = 10 V to 15 V 75
ns is
VCCl = 4.5 V 150
SN65518 -40 85
SN75518 0 70
electrical characteristics over recommended ranges of operating free-air temperature and VeC1 (unless
otherwise noted), VCC2 .. 60 V
PARAMETER TEST CONDITIONS MIN TYpt MAX UNIT
VIK Input clamp voltage II = -12 rnA -1.5 V
Q outputs IOH = -25 rnA 57.5 58
Serial output VCCl = 5 V, IOH = -20 p.A 4.5 4.9 5
Q outputs IOL = 1 rnA 5
Serial output IOL = 20 p.A 0.06 0.8
IIH High-level input current VCCl = 15 V, VI = 15.V 0.1 1 p.A
IlL Low-level input current VCCl = 15 V, VI = 0 V -0.1 -1 p.A
VCCl = 4.5 V 1.8 4
ICCl Supply current rnA
VeCl = 15 V 2 5
SN65518 Outputs high, TA = -40C 12
ICC2 Supply current SN65518, Outputs high, TA = OOC to MAX 7 10 rnA
SN75518 Outputs low 0.01 0.5
TEXAS -Ii} 3-75

INSTRUMENTS
SN65518, SN75518
VAC~UM FLUORESCENT DISPLAY DRIVERS
switching characteristics, VCC2 c: 60 V, CL == 50 pF, TA 25C (unless otherwise noted)

VCCl = 4.5 V CL = 15 pF. 600
td Delay time. Clock to data output ns
VCCl = 15 V See Figure 4 150
from latch enable See Figure 5 1.5
VCCl = 4.9 V
tDHL Delay time. high-to-Iow-Ievel from strobe See Figure 6 1
p.s
Q output from latch enable See Figure 5 0.6
VCCl = 15 V
from strobe See Figure 6 0.5
II
C
tDLH Delay time. low-to-high-Ievel
Q output
from latch enable
from strobe
from latch enable
from strobe
VCel
VCCl
=
=
4.5 V
15 V
See Figure 5
See Figure 6
See Figure 5
See Figure 6
1.5
1
0.25
0.25
p's
ui' Transition time. high-to-Iow-Ievel VCC1 = 4.5 V

See Figure 6
3
p's
'C tTHL
Q output = 15 V 1.5
VCCl
6r = 4.5 V 2.5
-< tTLH
Transition time. low-to-high-Ievel VCCl
See Figure 6 p's
Q output VCCl = 15 V 0.75
...
C
<'
...
CD
en RECOMMENDED OPERATING CONDITIONS
INPUT VOLTAGE LOGIC-LEVEL LIMITS MAXIMUM INPUT DATA RATE

vs vs
SUPPLY VOLTAGE VCC1 SUPPLY VOLTAGE VCC1
12 I I 6
I I
10
T A .. Full Range
,,/ N
::t 5
T A .. Full Range
> ~~
/ ~
I
> /
I 8 u 4
CD ~~ c
CD
/
~
Cl
:l
~ C'
"0
>
... 6
CD
&t 3 I
:l
C.
c
"I 4
//' -J\\. /
/ .:.!
U
U
0
I
,~\)~ E 2
/
'>
2
"../
~
:l
E
'j(
~
CQ /
o o
3 5 7 9 11 13 15 4 6 8 10 12 14 16
Supply Voltage VCC1-V Supply Voltage VCC1-V
FIGURE 1 FIGURE 2
3-76 TEXAS ~
INSTRUMENTS
I>Os1 OFtlCi sOx 8&5012 DALLAS, TExAS 76266
SN65518, SN75518
VACUUM FLUORESCEr~T DISPLAY DRIVERS
f.t--tw(CKHI---.j
I
1,.-----"""'\
I
CLOCK
I
: : VIL
<><XXX.
~tW(CKLI---.l
f4--tsu-4f+-th~
I
*><XX>
I II
. en
DATA IN VALID V,H CD
~ _ _ _ _.J, VIL
>
'i:
C
FIGURE 3. INPUT TIMING VOLTAGE WAVEFORMS >-
CO
Q.
en
r---tW(CKHI4 C
I -1-- - --VIH
CLOCK 50%
-----VIL
I
/.-t -4 d
OATA OU_T_P_UT
_____ ..J}(. .'_OO_*'_ _ _ _ _ _ _ VOH
- VOL
FIGURE 4
f
~----------------3.5V
LATCH
50%
ENABLE
---I-----------OV
I- ., tOLH or tOHL
QOUTPU_T______ ~:~:~~~~:tx(~_________ ::~

FIGURE 5
NOTE: For testing purposes, all input pulses have maximum rise and fall times of 30 ns.
TEXAS . . 3-77
INSTRUMENTS
,"oaT OFFICI 80)( 66~()1 a bALLAS, TEXAI 7a286
SN65518. SN75518
\ 3.5 V
STROBE
r------ t~-~-----
~tOLH ft--------.!-tOHL
Ov
:if -
II
c
(ii"
a OUTPUTS
____-..J!t-L--------L~
I I
'....HTLH
~O%---
I,
J+-+t-tTHL
VOH
VOL
"0
Dr FIGURE 6. SWITCHING-TIME VOLTAGE WAVEFORMS
< NOTE: For testing purposes, all input pulses have maximum rise and fall times of 30 ns.
...C
<"
CD
CiJ
3-78 TEXAS
INSTRUMENTS
SN55551, SN55552
ELECTROLUMINESCENT ROW DRIVER
02743, APRIL 1986
Each Device Drives 32 Electrodes SN55551 , .. FD PACKAGE

(TOP VIEW)
High-Voltage Open-Drain DMOS Outputs
50-rnA Output Current Capability
NN----- ___ _
~OOlCO"""(OLO'<tC"')N~
00000000000
6 5 4 3 2 1 4443424140
CMOS-Compatible Inputs 39
e Very Low Steady-State Power Consumption 38
37
10 36
II
description 11 35
12 34 05
The SN55551 and SN55552 are monolithic 13 33 04
BIDFETt integrated circuits designed to drive the 14 32 03
row electrodes of an electroluminescent display.
All inputs are CMOS-compatible and all outputs
15
16
31
30
02
01
...
(I)
CD
are high-voltage open-drain DMOS transistors. 17 29 NC >
'I:
1819202122232425262728
The SN55552 output sequence has been C
reversed from the SN55551 for ease in printed >
circuit board layout. CO
C.
(I)
The devices consist of a 32-bit shift register, 32
AND gates, and 32 output OR gates. Typically, C
a composite row drive signal. is externally
generated by a high-voltage switching circuit and
applied to the Substrate Common terminal. Serial
data is entered into the shift register on the high-
to-low transition of the clock input. A high Enable SN55552 ... FO PACKAGE
input allows those outputs with a high in their (TOP VIEW)
associated register to be turned on causing the _ _ _ _ _ _ _ _ NNN
NC"')'<tLO(o,.....COOlO~N
corresponding row to be connected to the 00000000000

composite row drive signal. When the Strobe 6 5 4 3 2 1 4443424140
input is low, all output transistors are turned on. 011 39 023
The Serial Data output from the shift register 010 8 38 024
may be used to cascade additional devices. This 09 9 37 025
08 10 36 026
output is not affected by the Enable or Strobe 027
07 11 35
inputs. 06 12 34 028
13 33
The SN55551 and SN55552 are characterized 14 32
for operation over the full military temperature 15 31
range of - 55C to 125C. 02 16 30 032
01 17 29 NC
1819202122 2324 2526 27 28
t BIDFET - Bipolar, double-diffused, N-channel and P-channel MaS transistors on same chip - patented process.
~~aC~~:~~i~a[~:I~~~ ~!:ti~~tigr :I~o~:;:~:t:~s~s not INSTRUMENTS
SN55551, SN55552
logic symbols t
SN55551 SN55552
CMOS/EL DlSP CMOS/EL DISP
[0. SOURCE SUPPLYI [0. SOURCE SUPPLYI
II
c
C;;.
"C
Q)
-<
...C
<'
...
CD
(/)
t These symbols are in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12. The symbol Q here indicates an n-channel
open-drain output.

SUBSTRATE __________________________________________--,
COMMON
STROBE--------------------~
1----+--- 01
ENABLE-------------------,
DATA IN ---------t
CLOCK---.---<1>
1----+--- Q2
I---t--- 031
032
>---------- SERIAL OUT
3-80 _ TEXAS-I!1
INSTRUMENTS
SN55551, SN55552
FUNCTION TABLE
CONTROL INPUTS OUTPUTS

SHIFT REGISTERS
FUNCTION
Rl THRU R32
CLOCK ENABLE STROBE SERIAL Ql THRU Q32
t X X Load and Shift t R32 Determined by Enable and Strobe

LOAD
No. t X X No Change R32 Determined by Enable and Strobe
X L H As determined above R32 All Q outputs off
ENABLE
X H H As determined above R32 Determined by Rl through R32
STROBE X X L As determined above R32 All Q outputs on
H = high level, L = low level, X = irrelevant, t = high-to-Iow transition.

tRegister R32 takes on the state of R31, R31 takes on the state of R30, ... R2 takes on the state of Rl, and Rl takes on the state of
the data input. ...
CI)
Q)
typical operating sequence >
".:::
CLOCK u U_____________ _ VIH
C
>-
CO
DATA IN _ _ _ _ ...In---- ----- -------- -. SUBSTRATE COMMON
VIH
Q.
CI)
SN55551 ENABLE _---In'-----'n ---------- SUBSTRATE COMMON

VIH
C
SN55552 ENABLE ________ __...JIl------- ~n~

SUBSTRATE COMMON
VIH
SUBSTRATE COMMON
STROBE l . . ___~ I I
VIH
SUBSTRATE COMMON
COMPOSITE ROW +HV
DRIVE APPLIED TO
SUBSTRATE COMMON ... J [ OV
-HV
HV
01S~~;:~~ -"
n~~; Il+
~~ __ :=U~ F~O:T: ___o~
1
-HV ____
01S~~;:~~ II O,~TPUTFLOA~' U.__:=~ :O~: _~Il+

HV
______ HV
-+HV
02 OUTPUT II. U~ _____ o~II -HV

SN55551 OUTPUT FLOATS OUTPUT FLOATS
I' 01 ____
r-I 3 j__ +HV
SN55552 J I OUTPUT FLOATS ~ ___~

:: ~U:::T.o",g, _14___________.,_ _ _________ HV
NOTE: During operation Clock, Data In, Enable, and Strobe are referenced to the Composite Row Drive signal received at the Substrate
Common pin of the device.
TEXAS 3-81
INSTRUMENTS
SN55551, SN55552
EaUIVALENT OF EACH INPUT TYPICAL OF ALL a OUTPUTS TYPICAL OF SERIAL OUTPUT
VCC ------4.---.......- ....---....- OUTPUT - - - -...- - - - VCC
lEI
c
INPUT ~......"""......... --~ __----~-OUTPUT
en'
"C
SUBSTRATE
iii' COMMON - . .- - - -.............
_ _ _....~~_-4~SUBSTRATE _ _ _........~_......~ SUBSTRATE
COMMON
'< COMMON
.<'
C
..
CD
en
absolute maximum ratings over operating temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 18 V
Q off-state output voltage, VO(off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 225 V
Input voltage ...............................................' . . . . . . . .. V CC + 0.3 V
Substrate common terminal current (see Note 2) .................................. 1.5 A
Minimum operating free-air temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 t
Operating case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 125C
Case temperature for 60 seconds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260C
NOTES: 1. Voltage values are with respect to substrate common terminal.

2. Duty cycle is limited by package dissipation.
3. For operation above 25C freeair temperature, derate linearly at the rate of 14.6 mW/oC.

MIN NOM MAX UNIT
VCC Supply voltage 10.8 12 15 V
VO(off) Off state Q output voltage 0 200 V
VIH High-level input voltage 0.75VCC VCC+ 0.3 . V
VIL Low-level input voltage -0.3 0.25VCC V
VCC = 10.8 V,
50
VDD = 80 V, TC = 25C
IO(on) On-state Q output current mA
Duty cycle :$ 1 % VCC = 15 V,
80
TC = 25C
fclock Clock frequency, T A = 25C 6.25 MHz
tw Clock pulse duration, high or low, TA = 25C 80 ns
tsu Setup time, data valid before clockL T A = 25C 20 ns
th Hold time, data valid after clockL T A = 25C 110 ns
TA Operating free-air temperature -55 c
TC Operating case temperature 125 c
3-82
. TEXAS ~
INSTRUMENTS
SN55551, SN55552
electrical characteristics over recommended operating temperature range, Vee 12 V, substrate

common at 0 V .
VOH High-level output voltage I Serial outputs 10 = - lOO IlA 10 V

I Q outputs 10 = 50 mA 50
V
I Serial output 10 = lOOIlA 1.5
IIH High-level input current VI = 12 V 5 I'A
Low-level input current VI = 0 -5
II
IlL I'A
10(ofl) Off-state Q output current Va = 200 V 50 I'A
ICC Supply current 500 I'A
switching characteristics,
PARAMETER
Vee 12 V, Te
TEST CONDITIONS MIN MAX UNIT
.. rn
CD
>
Delay time, clock~ to serial~ CL =45 pF to common, 200 ns
'i:
tdLH
Delay time, clock~ to seriali See Figure 1
C
tdHL 200 ns
VDD =
100 V, RL = 2 kO, >
co
tdHL Delay time, enable to Q output~ CL = 45 pF to common, 500 ns C.
rn
See Figure 1
C
TEXAS
INSTRUMENTS
-1!1 3-83
SN55551. SN55552
VDD - ::0.V2k!l
II
. SERIAL OUT ---r. . ---TEST POINT Q OUTPUTS
+ICl - . TEST POINT
cti)'
ICl - 45,F 45,F
't:I
or
<
SERIAL OUTPUT LOAD CIRCUIT Q OUTPUT LOAD CIRCUIT
C
:::!,
< ~~--------tw--------~.I
...en
(1)
I ~I VIH
CLOCK 50% ..x-
" 50% 1~~. _ _ _ _ _ _ _ _ _ _ _J 50% T ___ VIL
1f14----tw _I.. th---~~

I+--tsu~ I
-----------------~~Ir--------------------~Ir--------------VIH
DATA IN _____________________
50_%..,,* : VALID *'--_____________ VIL
J4~----tdHL-----...1
-------------~------------~:t..
WAVEFORM 1 (see Note AI I
I
- -- - - --
:\. 90%
.
VOH
I VOL
SERIAL OUT
11f4----tdLH----!.~1
I VOH
__________________________
WAVEFORM 2 (see Note BI ......-t-,;...
:/10% _____ VOL
VIH
ENABLE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _5_0...,,%{ _ _ _ _ _ _ _ _ _ _ _ VIL
14-- td(onl----t-l
Q OUTPUTS :\g----VOH
(see Note CI ~O%
~----VOL
VOLTAGE WAVEFORMS
NOTES: A. Waveform 1 is for internal conditions such that a low is clocked into R32.
B. Waveform 2 is for internal conditions such that a high is clocked into R32.
C. To measure td(onl' a high is stored In the associated register.
3-84 TEXAS . .
INSTRUMENTS
posf OFFICE eOX ai501:i gA~LAS. tfxAS 7526B
SN55551, SN55552
MAXIMUM ON-STATE Q OUTPUT CURRENT

vs
SUPPLY VOLTAGE
<t 80
E
.!.c:
Duty Cycle :s 1 %
TA ... 25e
/
II
75
~::l V
(J
5 70
/
S-
::l
o
o 65
V ...
'(1)
(I)
:>
/
~
''::
ctI C
en
c 60
/ >
CO
o
I
E
E 55
/ Q.
C
(I)
x
:!E
ctI
50 L
/
10 11 12 13 14 15
vee-Supply Voltage-V
FIGURE 2
OUTPUT CHARACTERISTICS SHOWING
OUTPUT SATURATION CURRENT
SAFE OPERATION AREA (SOA)
vs
110
100
SO~ d Duty eycle :s 1 %
120
JUNCTION TEMPERATURE
<t ! ' '. \ T e .. 25e

E
90
Vee'" 15 V 'I. .............
.!.c I I t-....
/ v
100
:!! 80 Vee" 12 V
1'- ......... ~ Ve~ -= 15 v
:s ,,
(J
... 70
/ ---I <t
E
............. ~r--.
.!.c: 80
::I
S- /1/ - Vee = 10.8 V ~
\
e
~
I'- --.......
-----r--r--
::I 60
SOA~ :s
0
VI
,I
(J 60
0 ...
~
ctI
en
c
50
40 r ::I
S-
::I
0 40
Vee - 10.8 V- I--
0 30 I
I 9
C 20 20
I
0
10
o o
o 20 40 60 80 100 120 140 160 -75 -50 -25 0 25 50 75 100 125
VO-Output Voltage-V TJ-Junction Temperature- e
FIGURE 3 FIGURE 4
TEXAS 3-85
INSTRUMENTS
II
c
en'
"0
<
or
.<'
c
..
CD
en
3-86
SN65551, SN65552, SN75551, SN75552
D2743, MARCH 1983-REVISED SEPTEMBER 1986
Each Device Drives 32 Electrodes N

DUAL-IN-LlNE-PACKAGES
High-Voltage Open-Drain DMOS Outputs (TOP VIEW)
50-rnA Output Current Capability SN65551.SN75551
CMOS-Compatible Inputs 016 015

Very Low Steady-State Power Consumption 017 014
018 013

description 019 012
020 011
The SN65551, SN65552, SN75551, and 021 010
SN75552 are monolithic BIDFETt integrated 022 09
circuits designed to drive the row electrodes of
an electroluminescent display. All inputs are
023 08 ...CI)
Q)
024 07
CMOS-compatible and all outputs are high- 025 'i:
>
06
voltage open-drain DMOS transistors. The 026 05 C
SN75552 output sequence has been reversed 027 04 >
from the SN75551 for ease in printed circuit CO
028 03 Q.
board layout. 029 02 CI)
The devices consist of a 32-bit shift register, 32 030 01 C

AND gates, and 32 output OR gates. Typically, 031 NC
a composite row drive signal is externally 032 DATA IN
generated by a high-voltage switching circuit and SERIAL OUT STROBE
applied to the Substrate Common terminal. Serial ENABLE VCC
data is entered into the shift register on the high- CLOCK SUBSTRATE
to-low transition of the clock input. A high Enable COMMON
input allows those outputs with a high in their SN65552. SN75552
associated register to be turned on causing the
corresponding row to be connected to the 017 018
composite row drive signal. When the Strobe 016 019
input is low, all output transistors are turned on. 015 020
The Serial Data output from the shift register 014 021
may be used to cascade additional devices. This 013 022
output is not affected by the Enable or Strobe 012 023
inputs. 011 024
010 025
The SN65551 and SN65552 are characterized
09 026
for operation from -40C to 85C. The
08 027
SN75551 and SN75552 are characterized for
07 028
operation from OC to 70C.
06 029
05 030
04
03
02 NC
01 DATA IN
SERIAL OUT STROBE
ENABLE VCC
CLOCK SUBSTRATE
COMMON
t BIDFET - Bipolar, double-diffused, N-channel and P-chann~1 MaS transistors on same chip - patented. process.
~~~~~:~~i~ai::I~~~ ~~~ti~~ti:f ~~o~:~:~:t:~s~s not
TEXAS "!} 3-87
INSTRUMENTS
SN65551, SN65552, SN75551, SN75552
SN6555l, SN75551 ... FN PACKAGE SN65552, SN75552 ... FN PACKAGE

(TOP VIEW) (TOP VIEW)
N ocnCOr"'-<Ol!>.;tC"lN
N- _______ _ NC"l.;tl!><Or"'-COcno N
_ _ _ _ ..... .._ _ _ N N N
00000000000 00000000000
6 5 432 1 4443424140 6 5 4 3 2 1 4443424140
7 39 010 011 7 39 023
8 38 09 010 8 38 024
9 37 08 09 9 37 025
10 36 07 08 10 36 026
11 35 06 07 11 35 027
027 12 34 05 06 12 34 028
C 028 13 33 04 05 13 33 029
C;;" 029 14 34 03 04 14 34 030
"C 030 15 31 02 03 15 31 031
D) 032
031 16 30 01 02 16 30
< 032 17 29 NC 01 17 29 NC
...C 1819202122232425262728 1819202122232425262728
<" I-
~~~~~Q~
u W Z I - u u u u w::Z u w ~
...
(1)
en
:> ual -
<1:0:2: >0<1: 6 ZZZZ ...Juo ual
~0:2: >0 <1:

...J
<1: zd:2:
w.
0:1-
1-<1:
CJ)o
...J,
<1:
z...J:2:
wuo
0:
I-
CJ)
I-
<1:
0
~ U ~ U
w w
CJ) w CJ) w
l- I-
<1: <1:
0: 0:
l- I-
CJ) CJ)
al al
:> :>
CJ) CJ)
logic symbols t
SN65551, SN75551 SN65552, SN75552
CMOS/El DISP CMOS/El DISP

SUBSTRATE 1211 SUBSTRATE (211
I~ SOURCE SUPPlYI I~ SOURCE SUPPLY)
COMMON COMMON
STROBE 1231 STROBE 1231
2.3
2.3 [> 2.3 [>

2.3 [> 2.3 [>
2.3 [> 2.3 [>

2.3 [> 2.3 [>
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. The symbol ~ here indicates an n-channel
open-drain output.
Pin numbers shown are for N package.
3-88 TEXAS ~
INSTRUMENTS
SN65551, SN65552, SN75551, SN75552

SUBSTRATE __________________________________________ ~
COMMON
STROBE --------------------~
ENABLE ------------........,
DATA IN ---------i
CLOCK -~'--<D
II
..en
Q)
>
'i:
C
>
co
C.
en
C
FUNCTION TABLE

SHIFT REGISTERS
FUNCTION
R1 THRU R32
CLOCK ENABLE STROBE SERIAL Q1 THRU Q32
! X X Load and Shift t R32 Determined by Enable and Strobe

LOAD
No. ! X X No Change R32 Determined by Enable and Strobe
X L H As determined above R32 All Q outputs off
ENABLE
X H H As determined above R32 Determined by R1 through R32
H = high level, L = Low level; X = irrelevant, ! = high-to-Iow transition.

tRegister R32 takes on the state of R31, R31 takes on the state of R30, ... R2 takes on the state of R1, and R1 takes on the state of
the data input.
TEXAS -I.!} 3-89

INSTRUMENTS
SN65551, SN65552, SN75551, SN75552
CLOCK u U_____________ _
__In ------------------.
DATA IN _ _ _ _
SUBSTRATE COMMON
VIH
SN75551 ENABLE _---In''-----Jn ---------- SUBSTRATE COMMON

VIH
SUBSTRATE COMMON
SN75552 ENABLE ________ ____In------- ~n~

VIH
SUBSTRATE COMMON
cC;;" STROBE l"'___ J

VIH
SUBSTRATE COMMON
"C
or COMPOSITE ROW r - I - - +HV
'< DRIVE APPLIED TO
..<"
C
SUBSTRATE COMMON ... J L OV
..
CD
til SN75551
Q1 OUTPUT
SN75552
01 OUTPUT OUTPUT FLOATS
----- - - - -- - ---_-HV
r - I - - + HV
SN75551
J r-I
I ,..
U~~-U-~-P-~-T-~-L-~-A-: ~ ~
02 OUTPUT OUTPUT FLOATS _I
.... ___ -HV
Fl-,.---...,...--------,--~
UTPUT - - +HV
SN75552
OUTPUT FLOATS FLOATS
HV . hi9~::,::.UT _________ -HV
NOTE: During operation Clock, Data In, Enable, and Strobe are referenced to the Composite Row Drive signal received at the Substrate
Common pin of the device.
3-90 TEXAS . .
INSTRUMENTS
SN65551, SN65552, SN75551, SN75552
Vee - - - -....- -...............-- r - - - -....- OUTPUT - - - -....- - - - Vee
INPUT - ....A.N_.....
J--- --~ - - -.....- OUTPUT
II
>
~
Q)
C
C
- - -..........--41~ ~~~~~:TE
SUBSTRATE - ...- - - -.......-4.....
COMMON
>
ca
Q.
U)
is
Supply voltage, VCC (see Note 1) ............................................. , 18 V
Q off-state output voltage, VO(off) .......................................... " 225 V
Input voltage. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Vec + 0.3 V
Substrate common terminal current (see Note 2) .................................. 1.5 A
Continuous total dissipation at (or below) 25C tree-air temperature
(see Note 3): FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1700 mW
N package .............................................. 1250 mW
Operating free-air temperature range: SN65551, SN65552 .................. - 40C to 85 C
SN75551, SN75552 .................... ooe to 70C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260C

2. Duty cycle is limited by paCkage dissipation.
3. For operation above 25 DC free-air temperature. refer to Dissipation Derating Curves in Appendix A. In the N package, use
the 10.0-mW/DC curve for these devices.

MIN NOM MAX UNIT
Vee Supply voltage 10.8 12 15 V
Vee ;0 10.8 V 8.1 11.1
VIH High-level input voltage (see Figure 1) V
Vce ;0 15 V 11.25 15.3
Vee ;0 10.8 V -0.3 2.7
VIL Low-level input voltage (see Figure 1) V
Vee = 15 V -0.3 3.75
VO(off) Off-state Q output voltage 0 200 V
!:?n-state output current, duty cycle :5 1%, Vee ;0 10.8 V. TA ;0 25e 50
10(on) mA
(see Figures 2, 3, and 4) Vee;o 15 V, TA' ;0 25 0 e 80
10K Output clamp current -45 mA
fclock elock frequency 0 4 MHz
tw Pulse duration. clock high or low 125 ns
tsu Setup time, data before clock (see Figure 3) 50 ns
th Hold time. data after clock (see Figure 3) 100 ns
ISN65551. SN65552 -40 85
TA Operating free-air temperature De
I SN75551, SN75552 0 70
TEXAS . " 3-91

INSTRUMENTS
SN65551, SN65552, SN75551, SN75552
electrical characteristics over recommended operating free-air temperature range

10(ott) Off-state Q output current Vo = 200 V 10 ItA
VOH High-level output voltage I Serial outputs 10 = -100 p.A Vee- l .5 V
I Q outputs 10L = 50 mAo See Figure 3 30
I Serial output 10L = 100 p.A 1
IIH High-level input current VI @ Vee 1 ItA
111 =0
IlL Low-level input current VI -1 p.A
ICC Supply current from Vee 250 ItA
switching characteristics, V CC 12 V, TA
C
iii PARAMETER TEST CONDITIONS MIN MAX UNIT
"'C Propagation delay time. high-to-Iow
Dr tpHL
level serial output from clock
200 ns
-< Propagation delay time. low-to-high
eL = 20 pF to ground. See Figure 7
...c<. tpLH
200 ns
Turn-on delay time. Q outputs 10L = 50 mAo Strobe at Vee.

...en
m td(on)
from enable RL = 1.4 kD to 100 V. See Figure 7
500 ns
INPUT VOLTAGE LOGIC-LEVEL LIMITS MAXIMUM ON-STATE Q OUTPUT CURRENT

vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
12
10
TA = Full Range
y <I:
E
J.c
80
Duty Cycle
TA = 25e
~ 1%
/
---------
75
Minimum VIH ~ V
:;
>I 8 u
... 70 /
V
CII
CI :::I
!! So
:::I
'0 0
>
... 6
0 65
:::I
Q.
C
"T 4
- -
~
'"
(i)
C: 60
/
">
-~
r--
Ma'ximum VIL
I
0
E
:::I
/v
2 E 55
~J7
'x
'"
:i:
o 50
10 11 12 13 14 15 10 11 12 13 14 15
vee-Supply Voltage-V vee-Supply Voltage-V
FIGURE 1 FIGURE 2
3-92 TEXAS ~
INSTRUMENTS
SN65551, SN65552, SN75551, SN75552
ON-STATE Q OUTPUT CURRENT OUTPUT SATURATION CURRENT

vs vs
OUTPUT VOLTAGE FREE-AIR TEMPERATUREt
110 110
Duty Cycle";;; 1%
~ 100
SbA.-.h
~ 10Q
~
E
ve~ - 1~~' ...............
~
II
1-c 90 t'-..
". J 1 , ~
90
~ I'-..... ~ee=l ':JV
~
:; 80
/
Vee= 12 V , :; 80
(.) 1/ (.) ............... ~I'-
...
::I
70
1//
,.."
Vee = 10.8 V
,, .g
~
70 b-....
............... ...enCD
S-
,
ns
::I 60
a
0
0
~
50
~
SOA i~
ns
...
en
::I
60
50
Vee == 10.8 V ---- !'-
C
>
oil:
J3
en
40 e >
C 6 40 CO
0 30 I Q.
I j i 30 en
,I
C 20
0
:: 20
Q
10
Duty Cycle";;; 1%_
TA = 25C
10
-40 -20 0 20 40 60 80 100
00 20 40 60 80 100 120 140
Vo-Output Voltage-V TA-Free-Air Temperature-Oe
SOA = Safe Operating Area
FIGURE 3 FIGURE 4
tD ata for temperatures belowOC and above 70C apply only for SN65551 and SN65552.
i+---tw----+i
CLOCK
I
I
I
I4---tw .1
j+--tsu~th~
DATA IN
~ VALID ~r--"ll~-r--.-- VIH
- -VIL
TEXAS . . 3-93
INSTRUMENTS
SN65551, SN65552, SN75551, SN75552
~
f VIH
CLOCK 50",(, 50%i /
I -- --- --- -t'--'--------- VIL
-+I ~tpLH -.I /4- tPHL
SERIAL OUT J.;;-if - l - - - - - - - - - -
50% \50%
VOH
lEI
'-.- - - - - - VOL
FIGURE 6. VOLTAGE WAVEFORMS, SERIAL OUTPUT
c
(ii'
'C
ENABLE
_ _ _ _ _ _. J
-1=\----------
I
VIH
VIL
ar
-< :I 1\,900,(,---- 100V
c
...;:- a OUTPUT
I4-- t d(onl--+t VOL
c...
t/) FIGURE 7. VOLTAGE WAVEFORMS, Q OUTPUT
3-94 TEXAS
INSTRUMENTS
-111
SN55553, SN55554
ELECTROLUMINESCENT COLUMN DRIVERS
D2744. APRIL 1986
Each Device Drives 32 Electrodes SN55553 .. FD PACKAGE

(TOP VIEW)
60-V Output Voltage Swing Capability
C'\I('I)'<tL!)CDI'OOO)O .... C'\I
. . . - . - . - . - . - .......... . - N N N
1 5-mA Output Source and Sink Current 00000000000
Capability
6 5 4 3 2 1 44 43 42 41 40
High-Speed Serially-Shifted Data Input 7 39 023

8 38 024
Totem-Pole Outputs
9 37 025
Latches on All Driver Outputs 10 36 026
11 35 027
description 12 34 028
The SN55553 and SN55554 are monolithic 13 33 029 ...
(I)
Q)
BIDFETt integrated circuits designed to drive the 14 32 030 >
15 31 031 'i:
column electrodes of an electroluminescent
16 30 032 C
display. The SN55554 output sequence has
been reversed from the SN55553 for ease in
01 17 29 NC >
CO
1819202122232425262728
printed circuit board layout. 1i
(I)
I-UUU::'::O C'\I .... wZw
The devices consist of a 32-bit shift register, 32 :::lZZZUZUU-I--I
o O(!)UU~~
C
latches, and 32 output AND gates. Serial data -I d zl- z
is entered into the shift register on the low-to- w~W
high transition of the clock input. When high, the
a:W J:
U
I-
:::l
U) I- a..
Latch Enable input transfers the shift register -I I-
:::l
contents to the outputs of the 32 latches. When o
O'utput Enable is high, all Q outputs are enabled.
Serial data output from the shift register may be SN55554 ... FD PACKAGE
used to cascade shift registers. This output is not (TOP VIEW)
affected by the Latch Enable or Output Enable .... Oo)OOI'CDL!)'<t('l)C'\I ....
inputs. SSooooooooo
The SN55553 and SN55554 are characterized 6 5 4 3 2 1 4443424140
for operation over the full military temperature 022 7 39 010
range of - 55 C to 125 C. 023 8 38 09
024 9 37 08
025 10 36 07
026 11 35 06
027 12 34 05
028 13 33 04
029 14 32 03
030 15 31 02
031 16 30 01
032 17 29 NC
1819202122232425262728
I-UUU::'::
:::lZZZU
o 0
-I
-I
U
a:
W
U)
tBIDFET - Bipolar, double-diffused. N-channel and P-channel MOS transistors on same chip - patented process.
:~~~~:~~i~ai~:1~1i ~!:~:~tigr ~~o::~:~:t:~~s not INSTRUMENlS
SN55553. SN55554
. ELECTROLUMINESCENT COLUMN DRIVERS
logic symbols t
SN55553 SN55554
CMOS/EL OISP CMOS/EL OISP

OUTPUT ENABLE (28) EN3 OUTPUT ENABLE (28) EN3
LATCH ENABLE (26) C2 LATCH ENABLE(26) C2
lEI
c(j)' 20 C> 3 (44) 015
'C' 20 C> 3 .(1) 016
ar
-<
...c
<'
...
CD
en tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

OUTPUTENABLE--------------------------~
LATCH ENABLE-------------------,
A1
CLOCK Q1
A2 32
32BIT LATCHES
STATIC
Q2
SHIFT
REGISTER
DATA IN A31
Q31
A32
Q32
>------ SERIAL DATA OUT
3-96 TEXAS . .
INSTRUMENTS
SN55553. SN55554
FUNCTION TABLE
CONTROL INPUTS
FUNCTION LATCH OUTPUT
CLOCK ENABLE ENABLE
t X X Load and shift t Determined by R32 Determined by

LOAD
Not X X No change Latch Enable t R32 Output Enable
X L X As determined above Stored data R32 Determined by
II
LATCH
X H X As determined above New data R32 Output Enable
OUTPUT X X L As determined above Determined by R32 All L
ENABLE X X H As determined above Latch Enable t R32 LCl thru LC32, respectively
H = high level, L = low level, X = irrelevant, t = low-to-high-Ievel transition. ...en

Q)
tR32 and the serial output take on the state of R31, R31 takes on the state of R30, ... R2 takes on the state of Rl, and Rl takes
on the state of the data input. 'Ii:
>
tNew data enter the latches while Latch Enable is high. These data are stored while Latch Enable is low. C
>
m
typical operating sequence Q.
en
CLOCK Inn n n n nnnn I
u U u U L J U U U U U is
SR CONTENTS INVALID VALID
LATCH ENABLE __________________________________~r_l~ ________________________
LATCH CONTENTS PREVIOUSLY STORED DATA NEW DATA VALID
OUTPUT ENABLE
a OUTPUTS VALID
------------------------------~~----~-----------
EQUIVALENT OF EACH INPUT TYPICAL OF ALL a OUTPUTS TYPICAL OF SERIAL OUTPUT
VCC1--------....-----.~~-- - - - - - - - -....- -....~..-- VCC2 - - - - - - - - - - - - - - - - - - VCCl
INPUT --.--'ll\i'Y-." OUTPUT ....----~..-- OUTPUT
GND--e----------e-4~t_ --4~---- ..........-41..-- GND - - - - - -...._ _4I~-- __-GND
TEXAS lj} 3-97

INSTRUMENTS
SN55553, SN55554
absolute maximum ratings over operating temperature range (unless otherwise noted)
Supply voltage, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 V
Input voltage ..................................................... VCC1 + 0.3 V
Ground current ............................................ ; ............ , 700 mA
Minimum operating free-air temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55C
Operating case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 125C
II
c
C;;'
NOTES:
Case temperature for 60 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260C

2. For operation above 25C freeair temperature, derate linearly at the rate of 14.6 mW/oC.
"C
or
-<
...c VCC1 Supply voltage

MIN
10.8
NOM
12
MAX
13.2
UNIT
V
<' Supply voltage 0 60 V
...CD
en
VCC2
VIH High-level input voltage O. 75V CC VCC+O.3 V
VIL Low-level input voltage -0.3 0.25VCC
10H High-level output current -15 mA
10L Low-level output current 15 mA
10K Peak output clamp diode current 20 mA
fclock Clock frequency, T A = 25C 6.25 MHz
twICLK) Clock pulse duration, high or low, TA = 25C 80 ns
tw(LE) Latch enable pulse duration, T A = 25C 80
tsu Setup time, data valid before clockt, T A = 25C 20 ns
th Hold time, data valid after clock t, T A = 25C 110 ns
TA Operating free-air temperature - 55
TC Operating case temperature 125
electrical characteristics over recommended operating temperature range, VCC1 12 V,

VCC2 = 60 V

Q outputs 10 = -15 mA 55
V
VOH
Serial output 10 = -100 p.A 10

Q outputs 10 = 15 mA 10
V
VOL
Serial output 10 = 100 p.A 1.5
IIH High-level input current VI = 12 V 5 p.A
IlL Low-level input current VI =0 -5 p.A
ICC1 Supply current, VCC1 7 mA
Outputs high 20
ICC2 Supply current, VCC2 mA
Outputs low 2
3-98
TEXAS -II}
INSTRUMENTS
SN55553. SN55554
switching characteristics, VCC 1 12 V, VCC2 = 60 V, TC = 25C

tdLH Delay time. clockl to seriall CL = 45 pF to ground. 200 ns
tdHL Delay time. clockl to serialt See Figures 1 and 2 200 ns
tdLH Delay time. LE to Q outputl CL = 45 pF to ground. 1000 ns
tdHL Delay time. LE to Q outpuH See Figures 1 and 3 500 ns
OUTPUT ---1
....---
~ CL - 45 pF
TEST POINT II
.. tn
Q)
".:;
>
FIGURE 1. OUTPUT LOAD CIRCUIT
C
>
CO
~14----tW(CLKI-----1~~1 Q.
tn
CLOCK~ 50%1
is
~ tW(CLKI---"'~oH~f---th--4
I+-tsu~ I
~,----------",,'v~------ VIH
50% 7I\'--_ _ _~I-V-AL-I-D----..JA
OATAIN
VIL
I
j4---tdHL--~~1
SERIAL OUT WAVEFORM 1 I -X90%----- VOH

(see Note AI \..-----VOL
14------ t d L H - - - . j
SERIAL OUT WAVEFORM 2
(see Note BI - - - - - - - - - - - - - -_ _ _ _ _ _ _ _.JI 10%
- -
,I VOH
- - - - VOL
FIGURE 2. VOLTAGE WAVEFORMS FOR SERIAL OUTPUT
~---------------------VIH
OUTPUT ENABLE _ _ _ _ _ -J/ ____________________ VIL
LATCH ENABLE ~ ------VIH

----------------.-J 14
Htw(LEI VIL
k--tdLH~h VOH
Q OUTPUT (see Note CI
__________________I ~------J ----
10%
VOL
I
Q OUTPUT (see Note 01 _____-J / I
I+--tdHL--H
0\-_ - - - -VOH
:\,0%
VOL
FIGURE 3. VOLTAGE WAVEFORMS FOR Q OUTPUTS

NOTES: A. Waveform 1 is for internal conditions such that a low is clocked into R32.
B. Waveform 2 is for internal conditions such that a high is clocked into R32.
C. To measure tdLH. initially a low is stored in the latch and a high is stored in the shift register.
D. To measure tdHL. initially a high is stored in the latch and a low is stored in the shift register.
TEXAS ~ 3-99
INSTRUMENlS
II
c
;r
"C
Dr
'<
...
C
:c:-
...
CD
en
3-100
SN65553, SN65554, SN75553, SN75554
D2744, MARCH 1983-REVISED SEPTEMBER 1986
N
Each Device Drives 32 Electrodes
DUAL-IN-LiNE PLASTIC PACKAGE
SN65553. SN76553
1 5-mA Output Source and Sink Current
Capability 017 018
High-Speed Setially-Shifted Data Input 016 019
015 020
o Totem-Pole Outputs 014 021

description
Latches on All Driver Outputs
The SN65553, SN65554, SN75553, and

013
012
011
010
09
022
023
024
025
026
II
.. en
Q)
SN75554 are monolithic BIDFETt int(lgrated 08 027 >
".:;:
circuits designed to drive the column electrodes 07 028
of an electroluminescent display. The SN65554
C
06 029
and SN75554 output sequence has been 05 030
>
CO
reversed from the SN65553 and SN75553 for 04 03.1 Q.
ease in printed circuit board layout. en
03 032
The devices consist of a 32-bit shift register, 32 02 OUTPUT ENABLE
C
latches, and 32 output AND gates. Serial data 01 DATA IN
is entered into the shift register on the low-to- SERIAL OUT LA TCH ENABLE
high transition of the clock input. When high, the CLOCK VCC1
Latch Enable input transfers the shift register GND VCC2
contents to the outputs of the 32 latches. When
Output Enable is high, all Q outputs are enableq. FN PLASTIC CHIP CARRIER PACKAGE
Serial data output from the shift register may be (TOP VIEW)
used to cascade shift registers. This output is not SN65553. SN75553
affected by the Latch Enable or Output Enable NM.;tLOtO 1 ' ( 0 0 ) 0 . - ( ' . 1

........ .- ........ ....-.- .... NNN
inputs. OOOOOOpOOOO
6 5 432 1 4443424140
7 39 023
for operation from - 40C to 85 DC. The
SN75553 and SN75554 are characterized for 8 38 024
operation from OOC to 70C. 9 37 025
10 36 026
07 11 35 027
06 12 34 028
13 33 029
04 14 32 030
03 15 31 031
02 16 30 032
01 17 29 NC
1819202122232425262728
tBIDFET - Bipolar. double-diffused. N~channel and P-channel MOS transistors on same chip - patented process.
=~~~~:~~I~ai~:I~~~ ~!:~~~ti~r :lla~:;:~:t::I~s nat INSTRUMENlS
SN65553, SN65554, SN75553, SN75554
N FN PLASTIC CHIP CARRIER PACKAGE

DUAL-IN-LiNE PLASTIC PACKAGE (TOP VIEW)
(TOP VIEW) SN65554, SN75554
SN65554,SN75554 .-OcnCOI"<OLO'<tC")N.-
NN~.-.-.- ....................
016 015 ddddddddddd
017 014 6 543 2 1 4443424140
018 013 022 7 39 010
019 012 023 8 38 09
lEI
C
020
021
022
023
024
011
010
09
08
07
025
026
027
028
10
11
12
13
37
36
35
34
33
08
07
06
05
04
en"
"C 025 06 029 14 32 03
Dr 026 05 030 15 31 02
-< 027 04 031 16 30 01
...C<" 028 03 032 17
18 19 2021 22 2324 2526 27 28
29 NC
029 02
...
C1I
en
030 01 f-UUU~O N.-WWW
: : l Z Z Z U Z UU-J-J-J
031 OUTPUT ENABLE o Oc;JUU~~~
032 DATA)N <X: -J ZZZ
f- U WWW
SERIAL OUT LA TCH ENABLE <X: J:<X:f-
0 Uf-::l
CLOCK VCC1 f-<X:[l..
<{Of-
GND VCC2 -J ::l
0
NC-No internal connection.
logic symbols t
SN65553, SN75553 SN65554, SN75554

OUTPUT ENABLE (25) EN3 OUTPUT ENABLE (25) EN3
LATCH ENABLE (23) C2 LATCH ENABLE (23) C2
20 C> 3 "(1)017 20 C> 3 (40) 015

20 C> 3 (40) 018 20 C> 3 (1) 016
20 C> 3 (27) 031 20 [;> 3 (16) 031

20 C> 3 (26) 032 20 C> 3 (17) 032
(18) SERIAL OUT (18) SERIAL OUT
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for N packages.
3-102 TEXAS
INSTRUMENTS
SN65553, SN65554, SN75553, SN75554

OUTPUTENABLE-----------------------------.
LATCHENABLE----------------~
SHIFT
REGISTER
DATA IN
CLOCK ---.---{>
II
.. fI)
CD
>
'i:
C
>-
co
Q.
fI)
FUNCTION TABLE

SHIFT REGISTER LATCHES
CLOCK R1 THRU R32 LC1 THRU LC32 SERIAL 01 THRU 032
ENABLE ENABLE
LOAD
Not X X No change Latch Enable:!: R32 Output Enable
LATCH
X H X As determined above New data R32 Output Enable
OUTPUT X X L As determined above Determined by R32 All L
ENABLE X X H As determined above Latch Enable:!: R32 LCl thru LC32, respectively

tR32 and the serial output take on the state of R31, R31 takes on the state of R30, ... R2 takes on the state of Rl, and Rl takes
on the state of the data input.
:!:New data enter the latches while Latch Enable is high. These data are stored while Latch Enable is low.
TEXAS "-!} 3-103

INSTRUMENTS
SN65553, SN65554, SN75553, SN75554
CLOCK ---,
unununUnL JlJUlJUlJ
lEI SRCONTENTS INVALID
LATCH ENABLE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ --InL.___________

VALID
LATCH
CONTENTS _ _ _ _P_R_E_V_IO_U_S_LY_ST_O_R_E_D_D_A_T_A_ _ _ _~_ _ _ _N_E_W_D_A_T_A_V_A_L_ID______
OUTPUT
ENABLE
----------------------~
Q OUTPUTS VALID
VCC1----~~--e_e_- ----~~-e...._.._. VCC2 - - - - . - - - - - VCC1
I NPUT ----4It-'VI/'I,~..... OUTPUT _ - -....- OUTPUT
GND--e-------e-e-.... ---e---e-e~...._.._.GND
- - -.......-..--.....- GND
3-104 TEXAS
INSTRUMENTS
SN65553. SN65554. SN75553. SN75554
Supply voltage, VCC2 ...................................................... 70 V
Ground current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 700 rnA
Continuous total dissipation at (or below) 25C free-air temperature (see Note 2)
FN package ....................................................... 1700 mW
N package ........................................................ 1250 mW
Operating free-air temperature range: SN65553, SN65554 ... . . . . . . . . . . . . . .. -40C to 85C
SN75553, SN75554 . . . . . . . . . . . . . . . . . . . .. a C to 70C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package. . . . . . . . . . . .. 260C
II
... en
Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260C Q)
>
'i:
2. For operation above 25C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the N package, use C
the 10.0-mW/oC curve for these devices. >-
co
recommended operating conditions Q.
en
MIN NOM MAX UNIT is
Supply voltage, VCCl 10.8 12 15 V
High-level input voltage, VIH (see Figure 1)

VCCl = 10.8 V 8.1 11.1
V
VCCl = 15 V 11.25 15.3
VCCl = 10.8 V -0.3 2.7

low-level input voltage, Vll (see Figure 1) V
VCCl = 15 V -0.3 3.75
High-level output current, 10H -15 mA
low-level output current, 10l 15 mA
Output clamp current, 10K 20 mA
Clock frequency, fclock 0 6.25 MHz
Pulse duration, clock high or low, tw(ClK) (see Figure 2) 80 ns
Pulse duration, latch enable, tw(lE) (see Figure 4) 80 ns
Data setup time before clock t, tsu (see Figure 2) 20 ns
Data hold time after clock t, th (see Figure 2) 80 ns

I SN65553, SN65554 -40 85
C
I SN75553, SN75554 0 70
electrical characteristics over recommended ranges of V CC 1 and operating free-air temperature,

Q outputs 10 = -15 mA 57
Serial output 10 = -100 J.lA VCC1-l.5
Q outputs IOl = 15 mA 8
Serial output IOl = 100 J.lA 1
IIH High-level input current VI = VCCl 1 J.lA
III low-level input current VI = 0 -1 J.lA
ICCl Supply current from VCCl 5 mA
I
SN65553, SN65554 12
mA
ICC2 Supply current from VCC21 SN75553, SN75554 10
TEXAS ~ 3-105
INSTRUMENTS
SN65553, SN65554, SN75553, SN75554
switching characteristics, VCC1 = 12 V, VCC2 = 60 V, TA "" 25C

Propagation delay time, high-to-Iow-Ievel

tpHL 140 ns
Serial output from Clock CL = 20 pF to ground,
Propagation delay time, low-to-high-Ievel See Figure 3
tpLH 140 ns
Serial output from Clock
Delay time, high-to-Iow-Ievel CL = 20 pF to ground,
II tDHL 500 ns
Q output from Latch Enable See Figure 4
Delay time, low-to-high-Ievel CL = 20 pF to ground,
tDLH 1 I"s
Q output from Latch Enable See Figure 4
c
Ci)'
"C
Dr RECOMMENDED OPERATION CONDITIONS
-<
..<'
C
..
INPUT VOLTAGE LOGIC-LEVEL LIMITS
CD vs
(I) SUPPLY VOLTAGE VCC1
12
TA = F~II Range J
t'O \1\\"\ ___ ~
10
t/I~-
>
"0
~CI 8
!l
... -----
>... 6
::I
a.
c:
"T
->
4
-
Ma){imumV1L
-
2
o
10 11 12 13 14 15
FIGURE 1
3-106 TEXAS ~
INSTRUMENTS
SN65553, SN65554, SN75553, SN75554
CLOCK
OATAIN <XXXX
t+--tsu~th---+t
I
VAllO
I
*>Qoo : : II
. en
(I)
>
FIGURE 2. INPUT TIMING VOLTAGE WAVEFORMS 'a::::
C
>-
CO
C.
CLOCK
___--J{60% \ n ____ :::
en
C
I
I
I r--------- VOH
SERIAL OUTPUT
: 1'0%
----tP-LH--.!~..J ~ - - - - - - - - - - VOL
~ __
SERIAL OUTPUT
tPHL-+j
,0% - - _ _ _ _ _ VOH
......- - - - - - - - - - - - - - VOL
FIGURE 3. VOLTAGE WAVEFORMS FOR PROPAGATION DELAY

CLOCK TO SERIAL OUTPUT
LATCH ENABLE _ _ _ ..Jf.'O% 'WIL,,~5~ - - - - ~',:

I
'"f-tOLH
I ~I, . . - - - - - - - - - VOH
a OUTPUT I I
_ _ _ _+-1.JI ~o~ - - - - - - - - - VOL
I
i 1\'"' ---------
I
VOH
a OUTPUT
L_I VOL
~tOHL
FIGURE 4. VOLTAGE WAVEFORMS FOR DELAY TIMES,

LATCH ENABLE TO Q OUTPUTS
TEXAS . . 3-107
INSTRUMENTS
lEI
c
(ii'
'C
m
<
c...
<'
...
CD
tn
3-108
SN65555, SN65556, SN75555, SN75556
ELECTROLUMINESCENT COLUMN DRIVER
02744, APRIL 1985-REVISED SEPTEMBER 1986
Each Device Drives 32 Electrodes SN65555. SN75555

N DUAL-IN-L1NE PACKAGE
Using Ramped Supply
017 018
15-mA Output Source and Sink Current 016 019
Capability 015 020
High-Speed Serially-Shifted Data Input 014 021
013 022
Totem-Pole Outputs
Latches on All Driver Outputs
description
012
011
010
09
08
023
024
025
026
027
II
...
CI)
Q)
The SN65555, SN65556, and SN75556 are 07 028 >
0a:
monolithic BIDFETt integrated circuits desiglled 06
to drive the column electrodes of an electro-
029 0
05 030
luminescent display. The SN65556 and >
CO
Q4 031
SN75556 output sequence has been reversed 03 032
Q.
CI)
from the SN65555 and SN75555 for ease in OUTPUT ENABLE
printed circuit board layout.
02
01 OATAIN
C
The devices consist of a ~2-bit shift register, 32 SERIAL OUT LA TCH ENABLE
latches, and 32 output AND gates. Serial data CLOCK VCCl
is entered into the shift register on the low-to- GND VCC2
high transition of the clock input. When high, the
Latch Enable input transfers the shift register SN65555. SN75555
contents to the outputs of the 32 latches. When FN PLASTIC CHIP CARRIER PACKAGE
Output Enable is high, all Q outputs are enabled. (TOP VIEW)
Data must be loaded into the latches and Output NM'<tLn<O r--CXlcnO~N
Enable must be high before supply voltage VCC2 ~~"---'-..-_NNN
00000000000
is ramped up.
6 5 4 3 2 1 4443424140
Serial data output from the shift register may be 7 39
011
used to cascade shift registers. This output is not 8 38
010
affected by the Latch Enable or Output Enable 09 9 37
inputs. 10 36
08
The SN65555 and SN65556 are characterized 07 11 35 027
for operation from - 40 C to 85C. The 06 12 34 028
SN75555 and SN75556 are characterized for 05 13 33 029
operation from OOC to 70 o C. 04 14 32 030
03 15 31 031
02 16 30 032
01 17 29 NC
1819202122232425262728
f-UUU:,o:
:JZZZU
o 0
...J
...J
<{ U
ffi
(/)
tBIDFET - Bipolar. double-diffused. N-channel and P-channel MOS transistors on same chip - patented process.
TEXAS ~
. 3-109
SN65555, SN65556, SN75555, SN75556
SN65556. SN75556 SN65556. SN75556

N DUAL-IN-LiNE PACKAGE FN PLASTIC CHIP CARRIER PACKAGE
.-OOlCOl'COL!)q-C")N.-
016 015 NN~.-.-'-""''-'-'-'-
00000000000
017 014
018 013
019 012 022 7
020 011 023 8
II
C
U;'
021
022
023
024
025
010
09
08
07
06
027
9
10
11
12
13
'"C 14
026 05
Dr 027 04
15
<
..<'
C
028
029
03
02
031 16
17 29 NC
..
CD
0
030
031
032
01
OUTPUT ENABLE
DATA IN
1819202122232425262728
SERIAL OUT LATCH ENABLE

CLOCK VCC1
GND VCC2
logic symbols t
SN65555. SN75555 SN65556.SN75556
(17) 01
(16)02
20 I>

(40) 015
. 20 I> (1) 016

20 i271 031 20 (16) 031
I> I>
20 I> (26) 032 20 I> (17) 032
(18) SERIAL OUT (18) SERIAL OUT
Pin numbers shown are for N packages.
3-110 TEXAS
INSTRUMENTS
SN65555. SN65556. SN75555. SN75556
VCC2------------------------------------------------------,
OUTPUT ______________________________________-.
ENABLE
OUTPUT
LATCH BUFFERS
ENABLE
DATA IN --------I
CLOCK --_.----[> t--+----01

II.. en
Q)
>
"i:
t--+----02
C
>
C'O
28 STAGES Q.
(03 THRU Q30)
en
NOT SHOWN C
t--+----031
t----032
> - - - - - - - - - - - - - - - - S E R I A L OUT
FUNCTION TABLE

CLOCK ENABLE ENABLE
i X X Load and shift t Determined by Latch Enable t R32 Determined by Output Enable
LOAD
Noi X X No change Determined by Latch Enable t R32 Determined by Output Enable
X L X As determined above Stored data R32 Determined by Output Enable
LATCH
X H X As determined above New data R32 Determined by Output Enable
OUTPUT X X L As determined above Determined by Latch Enable t R32 All L
ENABLE X X H As determined above Determined by Latch Enable t R32 LC 1 thru LC32, respectively
H = high level, L = low level, X = irrelevant, I = low-to-high-Ievel transition.

tR32 and the serial output take on the state of R31, R31 takes on the state of R30, ... R2 takes on the state of Rl, and Rl takes on
the state of the data input.
tNew data enter the latches while Latch Enable is high. These data are stored while Latch Enable is low.
TEXAS . . 3-111
INSTRUMENTS
POST OFFice BOX 655012 OAllAS, TeXAS 75265
SN65555, SN65556, SN75555, SN75556
CLOCK - - ,
unununUnL Jl.fUlIlflJ
II
C
Ci)'
SR CONTENTS
LATCH ENABLE
INVALID
__________________________ ~r1~
VALID
___________________
'C
LATCH
Dr PREVIOUSL Y STORED DATA NEW DATA VALID
-< CONTENTS
..<'
C OUTPUT
..
CD
en
ENABLE
VCC2
-------------------------~/
QOUTPUTS ____________________________________-LI'_~V_A_L_ID "~_____________
___
'''''''----
VCC1------~~----e-e--- ---~I--'-""- VCC2 VCC1
INPUT_.....VV\....-4I~ OUTPUT e - - -......- OUTPUT
.....____....- GND
GND--e---------e-~~
-~~~
---~ ....-e-~~ GND
3-112 TEXAS . .
INSTRUMENTS
SN65555, SN65556, SN75555, SN75556
Ground current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 700 mA
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1250 mW
FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1700 mW
Operating free-air temperature range: SN65555, SN65556 .................. -40 o C to 85C
SN75555, SN75556 ..................... OOC to 70C
Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260C
II...U)
Q)
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package. . . . . . . . . . . .. 260C
:::-
"i:
C
2. These devices have been designed to be used in applications in which the highvoltage supply, VCC2, is switched to ground
before changing the state of the outputs. >
m
3. For operation above 25C freeair temperature, derate the N package at the rate of 10 mW/oC and the FN package at the
Q.
rate of 13.6 mW/oC. U)
recommended operating conditions is

MIN NOM MAX UNIT
VCC1 Supply voltage 10.S 12 15 V
VCC2 Supply voltage 0 SO V
VCC1 = 10.S V S.1 11.1
VIH Highlevel input voltage (see Figure 1) V
VCC1 = 15 V 11.25 15.3
VCC1 = 10.S V -0.3 t 2.7
VIL Lowlevel input voltage (see Figure 1) V
VCC1 = 15 V -0.3 t 3.75
IOH Highlevel output current -15 rnA
IOL Lowlevel output current 15 rnA
10K Output clamp current 20 rnA
fclock Clock frequency 0 6.25 MHz
tw(CLK) Pulse duration, clock high or low (see Figure 2) SO ns
tw(LE) Pulse duration, latch enable (see Figure 4) SO ns
Data before clock t (see Figure 2) 20
tsu Setup time ns
Output enable before Vcct (see Figure 4) 500
Data after clock t (see Figure 2) SO
th Hold time ns
Output enable after Vcct (see Figure 4) 100
dv/dt Rate of rise for VCC2 (see Figure 4) SO V/p.5
SN65555, SN65556 -40 S5
TA Operating free-air temperature C
SN75555, SN75556 0 70
tTh~ algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic
voltage levels.
TEXAS . . 3-113
INSTRUMENTS
SN65555. SN65556. SN75555. SN75556
electrical characteristics over recommended operating free-air temperature range, VCC1 -= 12 V,

VCC2 ... 80 V
Q outputs 10 = -15 rnA 77
Serial output 10 = -100 p.A 10.5
Q outputs 10l = 15 rnA 8
Serial output IOl = 100 p.A 1
IIH High-level input current VI = 12 V 1 p.A
III low-level input current VI = a -1 p.A
ICC1 Supply current from VCC1 2 rnA
ICC2 Supply current from VCC2 5 rnA
c
(ii' switching characteristics, VCC1 ... 12 V, TA == 25C
'C
iii' PARAMETER TEST CONDITIONS MIN MAX UNIT
-< Propagation delay time, high-to-Iow-Ievel
...c tPHl
Serial output from Clock Cl = 20 pF to ground, VCC2 = 0,
140 ns
<' Propagation delay time, low-to-high-Ievel See Figure 3
...
CD
(/)
tPlH
Serial output from Clock
dv/dt = 80 V/p.s,
140 ns
td Delay time, VCC2 to Q outputs 100 ns

See Figure 4
RECOMMENDED OPERATION CONDITIONS

vs
SUPPLY VOLTAGE VCC1
12
TA - L
Full RangeI I
I \'-J\~ ___ ~
10
tl\~~
>I 8
;~
II)
CI
:!
'0
>... 6
::I
C.
-
c
T 4 Maximum VlL
;>
-t--"
2
o
10 11 12 13 14 15
FIGURE 1
3-114 TEXAS ~
INSTRUMENTS
SN65555, SN65556, SN75555, SN75556

If---- tw(CLK)---+I
I J. ___ VIH
I I
CLOCK
1 ...... ----1I
If----tw(CLK)~
DATA IN \t'tf:)(
If- tsu--+l+--- th-.j
I
VALID 'KIX)
: VIH
vlL
II
... CI)
Q)
FIGURE 2. INPUT TIMING VOLTAGE WAVEFORMS "i:

>
C
CLOCK _ _ _ ..Jta. ca
Q.
>-
CI)
~ !+-tPLH C
SERIAL OUTPUT
1
I flI ,.-------- VOH
I 50"10
-----+I~ - - - - - - - - VOL
~ If-tPliL
SERIAL OUTPUT - - - -..... ~O%- - - - - - - VOH
,-,- - - - - - - - VOL
FIGURE 3. VOLTAGE WAVEFORMS FOR PROPAGATION DELAY
CLOCK TO SERIAL OUTPUT
OUTPUT
ENABLE _ _ _---'
t
.
I
, - -_ _ _ _ _ _---..
O'J
5 Yo
~<.
-!\O%
I
_ - _ _ VIH
VIL
I I
-It---.r - _1- - - - -
'w y,.. 1~~'h
80 V
OV
1
ld~ 14-
I ,..--"'" - - - - - - - VOH
QOUTPUT il VALID \
l1O% VOL
FIGURE 4. VOLTAGE WAVEFORMS FOR DELAY TIMES, LATCH ENABLE TO Q OUTPUTS
INSTRUMENTS
TEXAS -1!1 3-115

II
c
(ii'
"C
Q)
-<
...c
<'
...
CD
U)
3-116
SN65557, SN65558, SN75557, SN75558
ELECTROLUMINESCENT ROW DRIVERS
02999, DECEMBER 19B5
Each Device Drives 32 Electrodes SN65557, SN75557 .. FN PACKAGE

(TOP VIEW)
High-Voltage Open-Collector N-P-N Outputs ~OOlCOr-.CDl!l<tC"lN
Using Ramped Supply NN~~~~~~~~tJ
OOOOOOOOOOz
300-mA Output Current Capability 6 5 4 3 2 1 4443424140
NC 39 NC
CMOS-Compatible Inputs 022 38 011
Very Low Steady-State Power Consumption 37 010
II
024 10 36 09
description 025 11 35 08
026 12 34 07
These devices are monolithic BIDFETt integrated 027 13 33 06
028
029
14
15
34
31
05 ...
en
CD
CMOS-compatible and all outputs are h'igh- 16 30 >
'i:
031 17 29
voltage open-collector n-p-n transistors. The C
1819202122 232425262728
SN65558 and SN75558 output sequences have >
been reversed from the SN65557 and SN75557 NUI-W~ZUwZU~ CtI
C"lz=>...JUOuco-ZO
for ease in printed circuit board layout. o o~g~>~~ C.
en
The devices consist of a 32-bit shift register, 32
~r5U~ tii~ C
ffi U
AND gates, and 32 output OR gates. Typically, (/) ~
a composite row drive signal is externally <!
a:
l-
generated by a high-voltage switching circuit and (/)
co
applied to the Substrate Common terminal. Serial =>
(/)
data is entered into the shift register on the high-
.to-low transition of the clock input. A high Enable
SN65558. SN75558 ... FN PACKAGE
input allows those outputs with a high in their (TOP VIEW)
associated register to be turned on causing the
corresponding row to be connected to the
composite row drive signal. When the Strobe
--------NNU
NC"l<tl!lCDr-.COOlO~
OOOOOOOOOOz
6 543 2 1 4443424140
input is low, all output transistors are turned on.
NC 7 39 NC
The Serial outPl:It from the shift register may be 011 8 38 022
used to cascade additional devices. This output 010 9 37 023
is not affected by the Enable or Strobe inputs. 09 10 36 024
08 11 35 025
07 12 34 026
for operation from - 40 cC to 85 cC. The
06 13 33 027
05 14 34 028
operation from 0 cC to 70 cC. 04 15 31 029
03 16 30 030
02 17 29 031
1819202122232425262728
~UI-W~ZUWZUN
Oz=>...JUOUCO-zC"l
o~g~>~~ 0
~r5U~ tiii3
a: U
W
(/) W
I-
<!
a:
l-
(/)
co
=>
(/)
NC-Nc internal connection
t 8IDFET - Bipolar, double-diffused. N-channel and P-channel MOS transistors on same chip - patented process
PRODUCTIDN DATA documents contain information Copyright 1985, Texas Instruments Incorporated
~
. TEXAS 3-117
:~~~~~~~i~ar::I~~~ ~!~~~~ti~r ~lo::::~:t::s~S not INSTRUMENTS
SN65557, SN65558, SN75557, SN75558
logic symbols t
SN65557. SN75557 SN75558. SN75558

SUBSTRATE 123) SUBSTRATE 123)
[Q EMITTER SUPPL VI [Q EMITTER SUPPL VI
COMMON COMMON
STROBE 125) STROBE 125)
II
C
C;;'
2.3
"C 2.3 I> 2.3 I>

Di' 2.3 I> 2.3 I>
<
...C 2.3 I> 2.3 C>
<'
...
CD
tJ)
2.3 I> 2.3 I>
2.3 I> 2.3 C>

2.3 I> 2.3 I>
2.3 I> 2.3 I>

2.3 I> 2.3 C>
tThese svmbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
SUBSTRATE
COMMON--------------------------------------~
STROBE-------------------d
ENABLE--------------~
DATA IN -------f
CLOCK ---.---a;>
031
032
' - - - - - - - - - - - - - - - - - - - - - - - - - - - SERIAL OUT
3-118 TEXAS ~
INSTRUMENTS
SN65557, SN65558, SN75557, SN75558
FUNCTION TABLE

SHIFT REGISTERS
FUNCTION
R1 THRU R32
CLOCK ENABLE STROBE SERIAL 01 THRU 032
! X X Load and Shift t R32 Determined by Enable and Strobe

LOAD
No! X X No Change R32 Determined by Enable and Strobe
X L H As determined above R32 All 0 outputs off
ENABLE
II
X H H As determined above R32 Determined by Rl through R32
H = high level, L = low level, X = irrelevant, ! = high-to-Iow transition.

t Register R32 takes on the state of R31, R31 takes on the state of R30, ... R2 takes on the state of R 1, and R 1 takes
'i:
-
(/)
Q)
>
schematics of inputs and outputs C
>-
S
EQUIVALENT OF EACH INPUT TYPICAL OF All Q OUTPUTS TYPICAL OF SERIAL OUTPUT
C.
(/)
VCC--------.-----~~--- r----~-- OUTPUT --------e-----VCC C
INPUT_.--"""...........___ OUTPUT
SUBSTRATE~~______~~~~___
COMMON
TEXAS . . 3-119
INSTRUMENTS
SN65557, SN65558, SN75557, SN75558
CLOCK
----..Uro-----'"IU VIH
- - - - - - - - - - SUBSTRATE COMMON
DATA IN _ _ _ ..,jn - - - - --- ,. . - - ----- ~~BSTRATE COMMON

SN65557. SN75557 .. ..-- - - - - - VIH
ENABLE - - - - - . . . SUBSTRATE COMMON
SN65558. SN75558
ENABLE _ _ _ _ _ _ _ _ _ _...
SUBSTRATE COMMON
c RAMPED COMPOSITE ROW

C;;" DRIVE APPLIED TO
"C SUBSTRATE COMMON
iii'"
v _____________ ~:V
<
.<"
C SN65557. SN75557
..
CD
Q10UTPUT
en SN65558. SN75558
Q1 OUTPUT
V_ -________ ~:V
SN65557. SN75557
Q2 OUTPUT
V--- ---- ::V
~::V
SN65558. SN75558
Q2 OUTPUT
HV = High voltage
3-120 TEXAS . .
INSTRUMENTS
SN65557, SN65558, SN75557, SN75558
Supply voltage, Vee (see Note 1) ..................... '. . . . . . . . . . . . . . . . . . . . . . . .. 18 V
Off-state output voltage, Va (off) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 110 V
Input voltage ........................................................ Vee +0.3 V
Substrate common terminal current (see Note 3) ................................ 750 mA
Continuous total dissipation at (or below) 25e free-air temperature (see Note 4): . . . . .. 1700 mW
Operating free-air temperature range: SN65557, SN65558 .................. - 40 0 e to 85e
SN75557, SN75558 ..................... ooe to 70 0 e
Storage temperature range ......................................... -65e to 150 0 e
ease temperature for 10 seconds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260 0 e
II
2. Data must be clocked into the shift register and Q outputs enabled prior to ramping substrate common to - HV (see typical
operating sequence).
.
U)
(1)
>
3. Duty cycle is limited by package dissipation. 0ii:
4. For operation above 25C free-air temperature, derate linearly to 1088 mW at the rate of 13.6 mW/oC. C
>
CO
recommended operating conditions Q.
U)
Supply voltage, Vee

MIN NOM MAX UNIT
C
10.8 12 15 V
Vee = 10.8 V 8.1 11.1
Vee = 15 V 11.25 15.3
Vee = 10.8 V -0.3 2.7
Vee=15V -0.3 3.75
Off-state Q output voltage, Va (off) -0.3 100 V
On-state Q output current, 10(on), duty cycle :5 1%, Vee = 15 V 300 mA
Rate of rise for substrate common, dV/dt (see Figure 4) 100 V/p,s
Clock frequency, fclock 0 4 MHz
Pulse duration, clock high or low, tw 125 ns
Data before clock! (see Figure 3) 50
Setup time, tsu ns
Enable before substrate common! (see Figure 4) 500
Hold time, th, data after clock! (see Figure 3) 100 ns
SN65557, SN65558 -40 85
Operating free-air temperature, T A e
SN75557, SN75558 0 70
electrical characteristics over recommended operating free-air temperature range, Vee = 12 V (unless
otherwise noted)
SN65557 SN75557
TEST
PARAMETER SN65558 SN75558 UNIT
CONDITIONS
MIN MAX MIN MAX
10(off) Off-state Q output current Vo = 100 V 20 10 p.A
VOH High-level output voltage Serial outputs 10 = -100 p.A 10.5 10.5 V

IQ outputs 10L = 300 mA 20 10
V
VOL
I Serial output 10L = 100 p.A 1 1
IIH High-level input current VI = 12 V 1 1 p.A
IlL Low-level input current VI = a -1 -1 p.A
lec Supply current from Vee 250 250 p.A
TEXAS ~ 3-121
INSTRUMENTS
SN65557, SN65558, SN75557, SN75558
switching characteristics, VCC = 12 V, TA = 25C

Propagation delay time, high-to-Iow-
tpHL 200 ns
level serial output from clock CL = 20 pF to substrate common
Propagation delay time, low-to-high- (see Figure 4)
tpLH 200 ns
Turn-on delay time, Q outputs dVldt = 100 V/p.s, Strobe at VCC,
td(on) 500 ns
from enable RL = 2 Hl to 60 V (see Figure 4).
C RECOMMENDED OPERATING CONDITIONS

iii'
'C
or
<
vs
...c SUPPLY VOLTAGE
<' 12~----~----~----~-----r-----'
...en
(1)
10r-----r-----r-----t7~--r---~
>
I 8
(II
Cl
~
"0
>
... 6
::J
C.
.5
I 4
">
2
0
10 11 12 13 14 15
FIGURE 1
3-122 TEXAS . .
INSTRUMENTS
SN65557, SN65558, SN75557, SN75558
VIH
CLOCK
I
1
If--t w ....,
t+- tsu----M-- th~

I IVIH
II
..
~ ~VIl
o
DATA IN VALID Go)
>
'a::
FIGURE 2. INPUT TIMING VOLTAGE WAVEFORMS C
>
CLOCK
_-~ ..F-"--"'~:%- ---- VIH
ca
Q.
C
o
1 VIL
~--~~I~t_PL_H_ _ _~.... I. ~I
50X---
tpHL
!,( II
VDH
DATA OUT _ _ _ _--J T50 % fO
LVOL
FIGURE 3. VOLTAGE WAVEFORMS FOR PROPAGATION DELAY TIMES, CLOCK TO DATA OUT
SUBSTRATE
COMMON
Q OUTPUT
90%
t-----
\
OV
'-----VOL
FIGURE 4. VOLTAGE WAVEFORMS FOR TURN ON DELAY TIME,

SUBSTRATE COMMON TO a OUTPUT
TEXAS 3-123
INSTRUMENTS
SN65557, SN65558, SN75557, SN75558
ON-STATE Q OUTPUT CURRENT

vs
ON-STATE Q OUTPUT VOLTAGE
300
VCC co 12 V
TA "" 25C
1/
II
C
ct
E
.!.c:
l!!
:;
250 I- Duty Cycle ~ 1 %
200
/
fir
"C
gr
..
u
:l
c. 150 J
V
S
<
..
C
.r
0
d
100 /
.
(1)
0
!co
cii
c
0 50
/
o
o
/ 5 10 15 20 25
On-State Q Output Voltage-V
FIGURE 5
3-124 TEXAS ~
INSTRUMENTS
ADVANCE SN65559, SN65560, SN75559, SN75560
INFORMATION ELECTROLUMINESCENT DISPLAY COLUMN DRIVERS
D2947, APRIL 1986-REVISED OCTOBER 19B6
Controls 32 Electrodes SN65559,SN75559

80-V (Ramped VCC2) Totem-Pole Outputs (TOP VIEW)
Low CMOS Stand-By Power Consumption 017 018
Energy Recovery System Compatible 016 019
015 020
15-mA Source and Sink Compatibility 014 021
description
The SN65559, SN65560, SN75559, and
SN75560 are monolithic BIDFETt integrated
012
011
010
09
08
023
024
025
026
027
Ell
.en
CD
circuits designed to provide the serial-to-parallel
07 028 >
0i:
conversion and level translation of data in a
matrix-addressable electroluminescent display.
06 029 C
05 030 >
The device inputs are diode-clamped CMOS CO
04 031
inputs. The SN65560 and SN75560 output
03 032
Q.
sequences are reversed from the SN65559 and en
NC
SN75559 for ease in printed circuit board layout.
02
01 DATA IN
C
These column drivers consist of a 32-bit static SERIAL OUT LATCH ENABLE
shift register, 32 latches, and 32 high-voltage CLOCK VCC1
outputs. Serial data is entered into the shift GND VCC2
register on the low-to-high transition of the clock
signal. A logic high signal on the Latch Enable
SN65559, SN75559 ... FN PACKAGE
input transfers the data from the shift register
(TOP VIEW)
to the latches while the VCC2 bus is low. Once
NC"lq-L!)(oI'-COo)O.--N
stable in the latch circuits, the VCC2 rail is .- or- ...... .- .- .... ...... or-'. N N N
ramped up to allow the data to appear at the dddOddddddO
high-voltage outputs. By limiting VCC2 to a 6 5 432 1 4443424140
maximum of 60 volts, these devices may be 7 39 023
safely operated in a non-ramped VCC2 mode. 8 38 024
Drivers may be cascaded via the serial data 9 37 025
output of the static shift register. This output is 10 36 026
not affected by the Latch Enable input. 11 35 027
z
12
13
34
33
028
029
o
for operation from - 40C to 85 C. The 32 030 i=

14
15 31 031
16 30 032 ~
01 17 29 NC a:
1819202122 232425262728
oLL
Z
W
U
z

>
c
tBIDFET -Bipolar, double-diffused, N-channel and P-channel MOS transistors on the same chip-Patented Process
~~~~~3~~~nO:~h~~~ o~r3:vue~~~~~n\~ec~:~~:~~rst~~ TEXAS . .

data and other specifications ara subject to change 3-125
without notica. INSTRUMENTS
SN65559, SN65560, SN75559, SN75560 ADVANCE
ELECTROLUMINESCENT DISPLAY COLUMN DRIVERS INFORMATION
SN65560, SN75560 SN65560, SN75560 ... FN PACKAGE

N DUAL-IN-LiNE PACKAGE (TOP VIEW)
(TOP VIEW) ..-OC"lOOf-..COLClq-MN..-
NN ................ . - . - . - ........
016 015 ddddddddddd
017 014 6 5 4 3 2 1 44 43 42 41 40
018 013 7 39
019 012 8 38
020 011 9 37
lIB
C
(ii'
021
022
023
024
010
09
08
07
06
025 10
11
12
13
36
35
34
33
025 14 32 03
'C 15
026 05 31 02
iii"
< 027 04 031 16 30 01
.<'
C 028
029
03
02
032 17
1819202122232425262728
29 NC
.
m
en
030
031
032
01
NC
DATA IN
SERIAL OUT LA TCH ENABLE
CLOCK VCC1
GND VCC2
logic symbols t
SN65559, SN75559 SN65560, SN75560
CMOS/EL DISP CMOS/EL DISP

(21)
V CC2
LATCH (23) LATCH (23)

ENABLE ENABLE
c CLOCK .;-.(1_9~)--r:> (19)

CLOCK---L>
<
2: DATA IN (24) (17) 01 DATA IN (24) (26) 01
(16) 02 (27) 02
n
m
(1) 017
(40) 015
2D [> 2D [>
(40) 018 (1)
2D [> 2D [>
2: 016
-n
o 20 [>

(27) 031 2D [>

i16) 031
::a (26)
s: 20 [> 032
(18) SERIAL OUT
2D [> (17) 032
(18) SERIAL OUT

:::! tThese symbols are in accordance with ANSI/lEEE Std 91-1984 and IEC Publication 617-12.
o Pin numbers shown are for N packages.
2:
3-126 TEXAS -I.!;

INSTRUMENTS
ADVANCE SN65559. SN65560. SN75559. SN75560
FUNCTION TABLE
CONTROL INPUTS
SHIFT REGISTERS LATCHES OUTPUTS
FUNCTION LATCH
CLOCK R1 THRU R32 LC1 THRU LC32
ENABLEt SERIAL Q1 THRU Q32
r X Load and Shift R32 t
LOAD Determined by Latch Enable LC1 thru LC32 respectively
Nor X No change R32
X L Stored data R32
LATCH As determined above LC1 thru LC32 respectively
X H New data R32
H = high level; L = low level; X = irrelevant; r = low-to-high-Ievel transition

t New data enters the latches while Latch Enable is high. These data are stored while Latch Enable is low.
t R32 and the serial output take on the state of R31. R31-takes on the state of R30 ... R2 takes on the state of R1 and R1 takes
II tI)
~
Q)
logic diagram (positive logic) >

''::::
C
VCC2
>-
co
LATCH Q.
ENABLE tI)
SHIFT
REGISTER LATCHES
OUTPUT BUFFERS
I
o
OATAIN 10
R1
..-- C2
[>
LC1
CLOCK - C1 20 f- Q1
T
L 10
R2
..-- C2
LC2
[>
C1 20 f- Q2

28 STAGES

I
(Q3 THR U Q30)
L 10
R31
..-- C2
LC31
[>
NOT SHOWN
C1 20 f- Q31 2'
T o
L10
I
i=
R32
' - - - C2
[>

C1 2D f-
LC32
Q32 :2:
a:
I SE RIAL OUT
o
u.
2
w
c.J
2

c>

TEXAS ~ 3-127
INSTRUMENTS
unununUnL JUlJlJl..f1J
CLOCK - - - ,
II
C
iii
SR CONTENTS INVALID
LATCHENABLE ______________________________~r_1~
VALID
_____________________
'C
Dr LATCH PREVIOUSLY STORED DATA NEW DATA VALID
< CONTENTS __________~--------------------~------------------------
...C
:;:-
...
ell
VI
VCC2 ___________________________________ 1
,-----
QOUTPUTS __________________________________~I' ___ "~____________
V_A_L_ID___
VCC1------~~--~~~- -------4..---4~t__ VCC2 - - - - - - - . - - - - - - - - VCC1
INPUT_~VV'I.."""~ OUTPUT . - - - - -.....- OUTPUT
c
<
2 --__---e-4__ ~~GND
- - - - . -..........- -......- GND
C')
m
-2
'TI
o
:lJ
S
:::!
o
2
3-128 TEXAS
INSTRUMENTS
-III
Input voltage, Vi .................................................... VCC1 +0.3 V
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1250 mW
FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1700 mW

Operating free-air temperature range: SN65559, SN65560 .................. - 40C to 85C
SN75559, SN75560 .................... , OOC to 70C
, Storage temperature range .......................................... - 65C to 150C
Case temperature for 10 seconds: FN package. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . .. 260C ...
f/)
(1)
'i:
>
2. For operation above 25C free-air temperature. derate the N package linearly at the rate of 10 mW/oC and the FN package
at the rate of 13.6 mW/oC.
C
>
CO
recommended operating conditions C.
f/)
Supply voltage. VCCl

MIN
10.8
NOM
12
MAX
15
UNIT
V
C
Supply voltage. VCC2 0 80 V
VCCl = 10.8 V 8.1 11.1
High-level input voltage. VIH (see Figure 1) V
VCCl = 15 V 11.25 15.3
Low-level input voltage. VIL (see Figure 1)

VCCl = 10.8 V -0.3 2.7
V
VCel = 15 V -0.3 3.75
High-level Q output current. IOH -15 mA
Low-level Q output current. IOL 15 mA
Q output clamp current. 10K 20 mA
Clock frequency. fclock 0 8 MHz
Pulse duration. clock high. tw(CLK) 62 ns
Pulse duration. latch enable high. tw(LE) 62 ns
Setup time. data before clock f. tsu 20 ns
Hold time. data after clock f. th 50 ns
Rate of rise of VCC2. dv/dt (see Figure 4) 80 V/p.s 2
Operating free-air temperature. T A
SN65559. SN65560
SN75559. SN75560
-40
0
85
70
c o
i=
NOTE 3: VCC2 must be ramped only when data within the latches is stable, <C
electrical characteristics over recommended operating free-air temperature range, VCC1 12 V
:2:
a:
PARAMETER
Q outputs VCC2
TEST CONDITIONS
= 80 V. IOH = -15 mA
MIN
77
MAX UNIT oLL
Serial output IOH = 100 pA 10.5 2
Q outputs IOL = 15 mA 8
Serial output IOL = 100 pA 1
V
w
IIH High-level input current VIH - VCCl 1 pA <C
IlL Low-level input current VIL = GND -1 pA (.)
ICCl Supply current from VCCl VI = VCCl 500 pA 2
I Outputs low 3 <C
Supply current from VCC2 VCC2 = 80 V mA
ICC2
I Outputs high 0.5
>
c
<C
TEXAS 3-129
INSTRUMENTS
switching characteristics, VCC1 = 12 V, VCC2 = 0, T A = 25C

FROM TO
INPUT OUTPUT
Serial CL = 20 pF,
tpHL Propagation delay time, high-to-Iow level Clock 140 ns
Out See Figure 3
Serial CL = 20 pF,
tpLH . Propagation delay time, low-to-high level Clock 140 ns
Out See Figure 3
dv/dt = 80 V/p.s,
lEI
c
td Delay time, VCC2 to Q output VCC2 Q CL = 100 pF,
See Figure 4
100 ns
0" RECOMMENDED OPERATING CONDITIONS

"C
Dr INPUT VOLTAGE LOGIC-LEVEL LIMITS
<
vs
...C SUPPLY VOLTAGE VCC1
:c:"
...
CI)
f/)
12
I RangeI
T A - Full I ~
10 L t1''\J\\'\~
tJ\~~
>
I 8
... ~
CD
Cl
~
'0
> 6
Sc.
c
I
'>
4
-
Maximum VIL
-
2
C 0
10 11 12 13 14 15
<

VCC1-Supply Voltage-V
FIGURE 1
;2
n

m
-2
'TI
0
::D
3:

::::!
0
2
....
3-130 TEXAS '9I.!f
INSTRUMENTS
If-- twICLK)----.I
I ..l.---vIH
I I
CLOCK
1'-------'1
I
DATA IN ~
14-- twICLK)--+i
/+-tsu
I
--+k-- th-+l
VAUD
I
JfYXI)
VIH
V"
II
... (/)
(1)
'':
>
FIGURE 2. INPUT TIMING VOLTAGE WAVEFORMS C
>-
CO
Q.
\ ----V,H (/)
CLOCK _ _ _...,/0% i5
'-----VIL
-+I !+-tPLH
I I
I 1'1-------- VOH
SERIAL OUTPUT _ _ _ --+/-' ~O~ _ _ _ _ _ _ VOL
~
SERIAL OUTPUT ----"""~O:-
I4-tPHL
- ----- VaH
'-.- - - - - - - - VOL
FIGURE 3. VOLTAGE WAVEFORMS FOR PROPAGATION DELAY CLOCK TO SERIAL OUTPUT
2:
o
i=
cd:
~
If-- a:
Q OUTPUT ~~%-V-A-LlD-\ - - - - - - ::: oLL
FIGURE 4. VOLTAGE WAVEFORMS FOR DELAY TIMES, LATCH ENABLE TO Q OUTPUTS -2:w
cd:
(.)
2:
cd:
>
c
cd:
TEXAS 3-131
INSTRUMENTS
c
(ii'
'C
Dr
-<
...C
ct
CD
(iJ
3-132
ADVANCE SN65563. SN65564. SN75563. SN75564
INFORMATION ELECTROLUMINESCENT ROW DRIVERS
02945. MAY 1986 REVISED NOVEMBER 1986
Each Device Drives 34 Electrodes SN65563. SN75563 , . , FN PACKAGE

(TOP VIEW)
Selectable Open-Source or Open-Drain
Output N .- o c) 00 1'(.OU'l.;tMN
N N N . . - . - ................ ..-.- .....
00000000000
Outputs Rated at 225 V
6 5 432 1 4443424140
70-mA Output Current Capability 023 7 39 011
024 8 38 010
CMOS-Compatible Inputs
025 9 37 09
Very Low Steady-State Power Consum'ption
description
The SN65563, SN65564, SN75563, and
026
027
028
029
10
11
12
13
36
35
34
33
08
07
06
05
II
... en
030 14 32 04 CD
SN75564 are monolithic BIDFETt integrated >
031 15 31 03 'i:
032 16 30 02 C
033 17 29 01 >-
CMOS compatible. If the Positive Write input is CO
1819202122 232425262728
high, the Q outputs act like open-source outputs C.
and output data is not inverted with respect to .;tl-W:"::(/)(/),-WZNN
M::J~U(/)(/)UI--Uu
en
input data. If the Positive Write input is low, the O0<l:oua:<l:UU is
Q outputs act like open-drain outputs and output :trE G >~~
data is inverted with respect to input data. The a: ~Cl
W -
SN65564 and SN75564 output sequences have (/) t::
(/)
been reversed from the SN65563 and SN75563 0
c..
for ease in printed circuit board layout.
SN65564. SN75564 ... FN PACKAGE
Typically, composite VCC2 and ground signals (TOP VIEW)
are externally generated by a high-voltage
M.;tU'l('oI'OOc)O.-NM
switching circuit. Serial data is entered into the .-.- .......... ..- .......... NNNN
00000000000
shift register on the high-to-Iow transition of the
clock input. A high Enable input allows those 6 5 432 1 4443424140
outputs with a high in their associated register 012 39 024
to be turned on causing the corresponding row 011 8 38 025
to be connected to VCC2 when Positive Write 010 9 37 026
is high or to ground when Positive Write is low. 09 10 36 027
The Serial Output from the shift register may be 08 11 35 028
2
used to cascade additional devices. This output
is not affected by the Enable or Positive Write
07
06
12
13
34
33
029
030 o
inputs. 05 14 32 031 i=
04 15 31 032
for operation over the full automotive operating
03 16 30 033
~
temperature range of - 40C to 85 oCr The
02 17 29 034
a:
1819202122232425262728
.-I-W :,.:: (/) (/) .- W Z N N

oLL
operation from OOC to 70C. O::J-I U (/) (/) U I- - UU
0 00 o > >
..JZ G
U a: <l: u u
>~ I-
2
<l:w <l:
a:
W
W Cl
> w
(/) i=
ii5 CJ
0 2
c..

>
c
tBIDFET-Bipolar, double-diffused, N-channel and P-channel MOS transistors on the same chip - Patented Process <C
preproduction phase of development Characteristic
data and other specifications are subject to change TEXAS . . 3-133
without notica. INSTRUMENTS
POST OFFICE BOX 656012 CA~~AS. TEXAS 75265
ELECTROLUMINESCENT ROW DRIVERS INFORMATION
LOAD FUNCTION TABLE

SHIFT REGISTER
FUNCTION POSITIVE
CLOCK ENABLE R1 THRU R34 SERIAL 01 THRU 034
WRITE
l X X Load and Shift t _ R34 Determined by Enable and Positive Write
LOAD
Nol X X No Change- 'R34 Determined by Enable and Positive Write
t Register R34 takes on the state of R33, R33 takes on the state of R32, _ .. R2 takes on the state of R1, R1 takes on the state of the
lEI
data input.
OUTPUT CONTROL FUNCTION TABLE
c(ii' CONTROL INPUTS

SHIFT REGISTER
CONTENTS Rn FOR
OUTPUTS
FUNCTION POSITIVE
"C R1 THRU R34 SERIAL 01 THRU 034
m
-<
CLOCK ENABLE
WRITE (Determined Above)
.<'c OUTPUT
X
X
L
H
X
H
X
H
R34
R34
High-Impedance
H
..
CD
(I)
H =
CONTROL
high, L = low, X
X
X
=
H
X
irrelevant, l =
L
X
high-to-Iow transition
H
L
R34
R34
L
High-Impedance
logic symbols*
SN65563, SN75563 SN65564, SN75564
1271 CMOS/EL DISP (27) CMOS/EL DISP

VCC2
12B) ] [~ DRAIN SUPPLY]
VCC2
VCC2
(28) ] [~ DRAIN SUPPLY]
VCC2
(22) (22)
Vss (23)
VSS
(23)
] [Q SOURCE SUPPLY] ] [ Q SOURCE SUPPLY]
VSS VSS
(20) (20)
ENABLE EN3 [OUTPUT ENABLE] ENABLE EN3 [OUTPUT ENABLE]
POSITIVE (25) POSITIVE (25)
EN2 [OUTPUT SELECT] EN2[OUTPUT SELECT]
WRITE WRITE
SRG34 SRG34
., .......
.,
(21) r-.. (21)
CLOCK C1!- CLOCK Cl/-
r r
2.3U 2.3~
DATA IN
(26)
10 I> 2.3Q f::1 (29)
01
DATA IN
(26)
10 I>
2.3Q
::::l (18)
01

c
I>
2.3U
2.3Q
f::1 (30)
02
I>
2.3~
2.3Q
~ (17)
02
<

:2
I>
2.3U
2.3Q
t.l (44)
016
I>
2.3~
2.3Q
~ (1)
018
2.3~
(") I>
2.3U
t:l (1)
017
I> Q (44)
019
m 2.3Q 2.3Q
-:2
."

2.3~
o I>
2.3U
2.3Q
t.l (17)
033
I>
2.3Q
b (30)
033
::xl I>
2.3U
2.3Q f::1 (18)
034
I>
2.3U
2.3Q
b (29)
034
S (19) SERIAL (19) SERIAL
~These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
OUT OUT
:::!
o
:2
.1;;&
3-134 1iEXAS
"'V'
INSTRUMENTS

VCC2-------------------------------------------------.
POSITIVE ________________-*____________---,
WRITE
....__-+------ 01
ENABLE
OATA IN
CLOCK
----------i
II
. en
Q)
....__-+----02
>
".:;:
C
>-
co
Q.
en
C
.. .. 31 STAGES
(03 THRU 033)
NOT SHOWN
VSS~
:>---------------- SERIAL OUT
schematics of inputs and outputs 2:

o
EQUIVALENT OF EACH INPUT TYPICAL OF ALL Q OUTPUTS SERIAL OUTPUT ....

VCC1------~.---~.----- 1-----.~----~-----VCC2 ------~.---------VCC1 ~
a:
ou.
INPUT - 4.........""",......~
............... OUTPUT
._-------OUTPUT
-w
2:
(.)
2:
--~~
1-~_4~~------e--VSS -----J7..-..lJ~--------
. VSS
>
c

TEXAS ~ 3-135
INSTRUMENTS
SN65563. SN65564. SN75563. SN75564 ADVANCE
---... r-------..., VIH

CLOCK U U_ -- - -- - - -- -VSS
DATA IN -rI- -- -- - - - - - - - - -- - -- -- - -:~HS
-----VIH
ENABLE
.....-----VSS
POSITIVE WRITE CYCLE
c
(ii' PO~~II~~.J _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ -~~S
'C
Dr
-<
...C Vee2 / \ / \ -------::S::MGND
...<'
VSS-------------------------------SYSTEMGND
(I)
en
FIRST
OUTPUT
/ \ - - - - - - ______ u _ :Y:::M GND
----J
SECOND
OUTPUT
/
::S::MGND
-----
\ - - u __
NEGATIVE WRITE CYCLE
PO~~II~~I-- - - - -- - - - - - - - - - - - -----~~HS
VCC2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Vselect*
r-----..... SYSTEM GND
l>
C
VSS
\~/ \"------.1./
r------------------
-------HVt
SYSTEM GND
<
l>
FIRST
OUTPUT
\ ---~.
/- - - - - - - - - - - - - - - - -HVt
2
(j SECOND
m
--n
OUTPUT
2 tHV = high voltage
o
II
tVselect is a voltage level typically equal to VCC2 of the column driver.
:::t
o
2
3-136 TEXAS ~
INSTRUMENTS
Supply voltage, V CC 1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Supply voltage, VCC2 ........... ; .......................................... 230 V
Supply voltage, VSS .................................................. . .. - 230 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to VeC1 + 0.3 V
Continuous total power dissipation at (or below) 25C free-air temperature
(see Note 2) ........................................................ 1700 mW
Operating free-air temperature range: SN65563, SN65564 .. . . . . . . . . . . . . . . .. - 40C to 85 C
NOTES:
SN75563, SN75564 ..................... OC to 70C
1. Voltage values are with respect to VSS.

II
. en
Q)
2. For operation above 25C free-air temperature, derate to 1088 mW at 70C at the rate of 13.6 mW/ ce. >
'i:
recommended operating conditions (see Note 1, Figure 1, and Figure 2) C.
NOM UNIT
>
CU
MIN MAX
Supply voltage, VCCl 10.8 12 13.2 V C.
en
0 225 V
Supply voltage, VCC2
Supply voltage, VSS 0 -225 V
i5
High-level input voltage, VIH 0.75VCCl VCC1 +0.3 V
Low-level input voltage, VIL t -0.3 O.25VCCl V
High-level output current, IOH -70 mA
Low-level output current, IOL 70 mA
Output clamp current, 10K 70 mA
Clock frequency, fclock 4 MHz
Pulse duration, Clock high or low, twCLK 125 ns
Setup time, data high or low before clock!, tsul 100 ns
Setup time, Clock low before VCC21 or VSS!. tsu2 300 ns
Setup time, Enable high before VCC2i or VSS!, tsu3 300 ns
Setup time, Positive Write high or low before VCC21 or YSS!, t su 4 300 ns
Hold time, data high or low after clock!, thl 100 ns
Hold time, Clock high after VCC2! or VSSl. th2 500 ns
Hold time, Enable high after VCC2! or VSS1, th3 300 ns
Hold time, Positive Write after VCC2! or VSSl. th4 300 ns 2:
,Slew rate, VCC2 or VSS with one active output driving a 4.7-nF load
to VSS or VCC2, dv/dt
45 V/p.s o
~
Rest time, period between successive rampings of VCC2 or VSS
Operating free-air temperature, T A I SN65563, SN65564 -40

5
85
p's
C

I SN75563, SN75564 0 70 :2E
ex:
tThe algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for logic
voltage levels only. o
LL
-2:w
U
2:

>
c

TEXAS -Ij} 3-137
INSTRUMENTS
electrical characteristics over recommended operating ranges of VCC1and free-air temperature,

VCC2 = 225 V, VSS = 0 (unless otherwise noted)
Va = 225 V 20
10(0ft) Off-state Q output current ~A
Va = 0 -20
High-level Q outputs 10 = -70 rnA VCC2- 3O
VOH V
output voltage Serial Out 10 = -100/lA, VCC1 = 12 V 10.5
Low-level Q outputs 10 = 70 rnA 30
lEI
VOL V
output voltage Serial Out 10 = 100/lA 1
IIH High-level input current VIH = VCC1 1 /lA
IlL Low-level input current VIL = 0 -1 /lA
c ICC1 Supply current from VCC1 500 /lA

en' ICC2 Supply current from VCC2
One Q output high 5 rnA
'C All Q outputs low 200 ~A
Dr
'<
switching characteristics operating range of VCC1, TA = 25C
...
C
.::-
...
(1)
(f)
tpLH
Propagation delay time, low-to-high
level serial output from clock CL = 50 pF to VSS,
400 ns
Propagation delay time, high-to-Iow See Figures 3 and 5

tpHL 400 ns
Propagation delay time, low-to-high dv/dt = 45 V//ls,
tpLH 6 /ls
level Q output from VCC2 One output on with
Propagation delay time, high-to-Iow CL = 4.7 nF to VSS,
tpHL 6 ~s
level Q output from VCC2 See Figures 4 and 5
Propagation delay time, low-to-high dv/dt - 45 V//ls,
tPLH 6 ~s
level Q output from VSS One output on with
Propagation delay time, high-to-Iow CL = 4.7 nF to VCC2,
tpHL 6 ~s
level Q output from VSS See Figures 4 and 6

c
<

:2
(")
m
-:2
"TI
o
:lJ FIGURE 1. INPUT TIMING VOLTAGE WAVEFORMS
S

::j
o
:2
3-138 TEXAS.
INSTRUMENTS
----, I r - VIH
CLOCK L-JI L.J __ _
I 1 VIL
\4-- t su2 -----+t t+--- th2----.t
I
ENABLE
90%/:1
I
I I "K % -
90 - - - ---VIH
II
I 1 I VIL
I 1 1 I
j4- t su3-+\ ~th3
1 I I I
POSITIVE ----"""\\F 90% 90% V , - - - - - - - - VIH en
WRITE _ _ _ _-'I\:~.:.;:10:;..:;'*::...o_~----------:.1.;;.oo.:.::.*'~I\"-------- VIL ~
(1)
1 I I I >
I4- t su4-+1 ~ th4 'i:
I C
VCC2 t _ _ _ _ _ _ _ ---JY.% 1~- - -- - - - - -- - ::~EM GND a.

en
>-
CO
1 1 Q
1_---------
-------_1
\% '-.------1.
97 ------------HV
SYSTEM GND
tTiming waveforms are with respect to VCC2' or VSS. as appropriate.
FIGURE 2. CONTROL INPUT TIMING VOLTAGE WAVEFORMS
CLOCK
--....., 7f---""'\t-: ---- V'H
I
1 I . VIL
I+- tPLH--+I i+-tpHL-+I
I ,.----~:f
~VOH
DATA OUT _ _ _ _ _ )1.0% o
2
VOL
i=
FIGURE 3. VOLTAGE WAVEFORMS FOR PROPAGATION DELAY TIMES, CLOCK TO DATA OUT
:E
a:
oLL
-2w
(J
2

>
c

TEXAS . . 3-139
INSTRUMENTS
A'%
, . . - - - - - - - - -__ - - ---------+HV
-----'. I
~% I \"'.- - - - - - - S Y S T E M GND
~tPlH ~tPHl
. . DOUTPUT y.% ~%-------+HV

_ ------'. . SYSTEM GND
- - -........' , _ _ - - - - - - - SYSTEM GND
~ ....
"I<_O _ _ _ _ _ _ _ _ --'~:-u _u'__ -HV
~tpHl I4-+t-tPlH
_____ I I SYSTEM GND
Q OUTPUT
~% X':----___ HV
FIGURE 4. VOLTAGE WAVEFORMS FOR PROPAGATION DELAY TIMES. VCC2 (VSS) TO Q OUTPUT
OUTPUT
UNDER
TEST
-----1..------ TEST
POINT
Clt
VSS
T
l>
1
c FIGURE 5. LOAD CIRCUIT
<
l>
:2 VCC2~
C')
m Clt
:2
-n
OUTPUT
I
UNDER - - - - -.....- - - - -
TEST
TEST
POINT
o
:0 FIGURE 6. LOAD CIRCUIT
S tel includes probe and jig capacitance.
l>
:::!
o
:2
,I"a
3-140
TEXAS .}
INSTRUMENTS
Controls 32 Electrodes SN65567. SN75567 ... FN PACKAGE

(TOP VIEW)
60-V (Ramped VCC2) Totem-Pole Outputs
NM<tL!)COI'-CXlC'lO..-C\j
..-..-..-,..- ..... ..-.-.-NN~
Low CMOS Stand-By Power Consumption 00000000000
Energy Recovery System Compatible 6 5 4 3 2 1 4443 42 41 40
011 7 39
15-mA Source and Sink Compatibility
8 38
o High-Speed Serially-Shifted Da~a Input 37
II
9
10 36
description 11 35
-
12 34
The SN65567, SN65568, SN75567, and 13 33 en
SN75568 are monolithic BIDFETt integrated 14 32 Q)
circuits designed to provide the serial-to-parallel 15 31
>
'i:
conversion and. level translation of data in a 16 30 C
matrix-addressable electroluminescent display.
The device inputs are diode-clamped CMOS
01 17 29 >
CO
181920212223242526.2728
inputs. The SN65568 and SN75568 output C.
sequences are reversed from the SN65567 and N"-UU~ en
SN75567 for ease in printed circuit board layout.
ZZZZU
--
<l:<l:
0
...J
C.
f-f- U
These column drivers consist of two 16-bit static <l:<l:
00
shift registers, 32 latches, and 32 high-voltage
outputs. Typically, a 32-bit data string is split
into two 16-bit data strings externally and then
entered in parallel into the shift registers on the SN65568, SN75568 .. FN PACKAGE
low-to-high transition of the clock signal. The (TOP VIEW)
register associated with Data Input 1 loads the .-OC'lCXlI'-COL!)<tMN ....
odd bits while the shift register associated NN..-.-.-,..-.-.-.-.-..-
00000000000
with Data Input 2 loads the even bits of the
32 latches. This method of entering data 6 5 4 3 2 1 44434241 40
effectively doubles the clock frequency of a 39
32-bit shift register. A logic high signal on the 023 8 38
latch enable input transfers the data from the 024 9 37
shift register to the latches while the VCC2 bus 025 10 36 2:
is low. Once stable in the latch circuits, the 026
027
11
12
35
34
o
VCC2 rail is ramped up to allow the data to
i=
appear at the high-voltage outputs. By limiting
VCC2 to a maximum of 50 volts, these devices
028
Q29
13
14
33
32
may be safely operated in a non-ramped VCC2 030 15 31 ~
mode. Drivers may be cascaded via the serial 031 16 30 a:
data outputs of the static shift registers. These
outputs are not affected by the latch enable
032 17
1819202122232425262728
29 oLL
input.
N'-UU~
f-f-ZZU
::>::>
00
0
...J
-w2:
for operation from - 40C to 85 DC. The
...J...J
<l:<l:
a:w a:
w
U

CJ
operation from OC to 70C. (J)(J)
2:

>
c
tBIDFET -Bipolar. double-diffused. N-channel and P-channel MOS transistors on the same chip-Patented Process
~~~~r~:~~~rO:~h~::ofd:~~r~p~e~~.eC~:~~~~r~st~~
TEXAS ~ 3-141
logic symbols t
SN65567, SN75567 SN65568, SN75568

VCC2 ~ IPWR 01-0321 VCC2 ~ IPWR 01-0321
LATCH ENABLE ~ C42

CLOCK .llli.- >Z40
LATCH ENABLE
CLOCK
-.EL..
(26)
C42
>Z40
SRG16 ~ SRG16 ~
II
;0IC41/-) ~0(C41/-)
r r
DATA IN1 ..!.!.!!.l- 410 Zl 1 420 I> --.!!ZL 01 DATA INl ..!!!.L- 410 Zl 1 420 I> ~ 01
Z3 2 420 l> ~ 02 Z3 2 420 I> ...2!L 02
c 3 420
4 420
I>
l>
~ 03
...!2!L.. 04 4
3 420
420
l>
I>
-illL 03
...illL 04
(ii'
'C
Z17
Z19 Z15
Z17
<
or 16 420 I> .....EL 016
--!!L. 017 14 420 I> ~ 014
~ 015
.c<'
17 420 I> 15 420 I>
~
Z29 18 420 I> 018 Z29 16 420 I> ......!!L 016
Z31 19 420 l> 019 Z31 17 420 l> ~ 017
..
CD
en DATA IN2 ~430
SRG16
--j0(C43/-)
r
Z2 29 420

I> ~ 029
(32)
DATA IN2 E!L'~--
SRG16
40(C43/+]]) r
Z2 29 420

I> ...l!!L 029
Z4 30 420 I> 030 Z4 30 420 I> ~ 030

I3il 031 420 ...J.!;L 031
~ 032
31 420 I> 31 I>
32 420 I> 32 420 I> ~ 032
Z16 Z14
ZlB 31 1
- (27) SERIAL
Z16 31 1 ....!.22.L SERIAL
Z30 32 1
oun
.J!!!L.. SERIAL
Z30 32 1 ~ OUT2
SERIAL
oun
OUT2
Z32 Z32
t These symbols are in' accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
FUNCTION TABLE

SHIFT REGISTERS LATCHES
FUNCTION LATCH SERIAL PARALLEL
CLOCK Rl THRU R32 LC1 THRU LC32
c LOAD
t
Not
ENABLE
X
X
Load and Shift t
No change
Determined by Latch Enable i
SOl
R31
R31
S02
R32
R32
01 THRU 032
LC 1 thru LC32 respectively
<
LATCH
X
X
L
H
As determined above
Stored data
New data
R31
R31
R32
R32
LC 1 thru LC32 respectively
:2
n H = high level; L = low level; X = irrelevant; t = fow-to-high-Ievel transition
tEach even-nutnbered shift register stage takes on the state of the next-lower even-numbered stage and likewise each odd-numbered
m
-
:2
shift register stage takes on the state of the next-lower odd-numbered state; i.e., R32 takes on the state of R30, R30 takes on the state
of R28, ... R4 takes on the state of R2, R2 takes on the state of Data In 2, R31 takes on the state of R29, R29 takes on the state
of R2 7, ... R3 takes on the state of R1, and R1 takes on the state of Data In 1.
"o tNew data enters the latches while Latch Enable is high. These data are stored while Latch Enable is low.
::rl
S
::t
o
:2
~ ...tiI
3-142 tEXAS V
INSTRUMENTS

VCC2
LATCH
ENABLE
CLOCK SHIFT
REGISTER 1 LATCHES OUTPUT
BUFFERS
DATAIN1 >--+---I1D
II
R1
01
... o
CI)
02 >
'Ii:::
C
>-
CO
Q.
03
o
C
LC4
04

SHIFT
REGISTER 2
. DATA IN2 >--+--t1D

R2
C2
L-----+--I 20 029
z
o
C2
i=
~-+--------~~20 030 <t
~
a:
C2 o
u.
.....--------+--t 20 I--LC_3_1--1 t> 031
Z
C2
w
U
~,-----+-----------~20
LC32
032 z
<t
SERIAL OUT1
>
c
SERIAL OUT2
<t
TEXAS . . 3-143
INSTRUMENlS
POST OFFice BOX 655012 DALLAS. TEXAS 75265
CLOCK
u u unUnL fUU1J1JU
Inn
c LATCHENABLE ________________________________~r_l~ ______________________

en'
"C
Dr LATCH
CONTENTS ________________________________
PREVIOUSL Y STORED DATA ~ ________________________
NEW DATA VALID __
-<
...c
<'
...
CD
(J)
VCC2 __________________________________~I'
,-----
OOUTPUTS __________________________________~I' ____ VA_L_I_D__"~_____________
EQUIVALENT ()F EACH INPUT TYPICAL OF ALL Q OUTPUTS TYPICAL OF SERIAL OUTPUTS
VCC1-------4.----4~e--- ------~---.~t--VCC2 - - - - - - - - . -......- - - VCC1
OUTPUT
INPUT ---i.--..,.,.,. . . . ---e ...---.-....- OUTPUT
c
<
----~.-.-~--....-GND
:2
(")
m
-:2
"o
:lJ
S
:::j
o
:2
3-144
TEXAS ~./}
INSTRUMENlS
Supply voltage, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8 V
Input voltage, VI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. VCC1 +0.3 V
Operating free-air temperature range: SN65567, SN65568 .................. - 40C to 85 C
SN75567, SN75568 ..................... DoC to 70C
II
Case temperature for 10 seconds. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 260C

2. For operation above 25C free-air temperature, derate linearly at the rate of 13.6 mW/oC.
...en
Cl)
recommended operating conditions :>
0':;:
MIN NOM MAX UNIT C
Supply voltage, VCC1 4.5 5 5.5 V >
CO
= C.
Highlevel input voltage, VIH
VCC1 4.5 V 3.4 . 4.8
V en
VCC1 = 5.5 V 4.2 5.8 C
VCC1 = 4.5 V -0.3 1.1
VCC1 = 5.5 V -0.3 1.3
Highlevel Q output current, IOH -15 mA
Low-level Q output current, IOL 15 mA
Q output clamp current, 10K 20 mA
Clock frequency, fclock 0 5 MHz
Pulse duration, clock high, tw(CLKI 100 ns
Pulse duration, latch enable high, tw(LE) 100 ns
Setup time, data before clock t, tsu 50 ns
Hold time, data after clock t, th 50 ns
Rate of rise of VCC2, dv/dt (see Figure 3) 60 V/p.s
SN65567, SN65568 -40 85
SN75567, SN75568 0 70
NOTE 3: VCC2 must be ramped only when data within the latches is stable.
2:
electrical characteristics over recommended operating free-air temperature range, Vee1 5V o
i=
Q outputs VCC2 = 60 V, IOH = -15 mA 57 <C
Serial output IOH = 100 p.A 3.8
V
~
Q outputs IOL = 15 mA 8 I:
VOL
IIH

Serial output IOL = 100 p.A
VIH = VCC1
1
1
V
p.A
oLL
IlL
ICC1
Supply current from VCC1

VIL = 0
VI = VCC1
=
I Outputs low
-1
500
0.5
p.A
p.A
mA
-w
2:
ICC2 VCC2 60 V
I Outputs high 0.5 <C
u
2:
<C
>
c
<C
TEXAS ~ 3-145
INSTRUMENTS
switching characteristics, VCC1 = 5 V, VCC2 O,TA

FROM TO
INPUT OUTPUT
Serial CL = 20 pF,
tpHL Propagation delay time, high-to-Iow level Clock 140 ns
Out See Figure 2
Serial CL = 20 pF,
tPLH Propagation delay time, low-to-high level Clock 140 ns
Out See Figure 2
= 60 VII's,
II
dvldt
td Delay time, VCC2 to Q output VCC2 Q CL = 100 pF, 100 ns
See Figure 3
c
(j)'
"C PARAMETER MEASUREMENT INFORMATION
ar
-<
.
c k---tw(CLKI~
I .J. - - - VIH
.
<'
CD
en
CLOCK
I
I
I
I
I
14-- tw(CLKI---+I
I4-tsu~th-+l
I : VII-{
DATA IN ~ VALID "f.:IXI) V"
CLOCK _ _ _ --Jto% \ - - --::~

--+I I+- tpLH
c
I
I Jt.,...--------
I
VOH
:..J1_50: .
<
SERIAL OUTPUT _ _ _ _... _ _ _ _ _ _ VOL
:2 -.I i4- tPHL

n ----~~o:- - - - - - - VaH
m SERIAL OUTPUT
-
:2
"TI
'-.- - - - - - - - - VOL
FIGURE 2. VOLTAGE WAVEFORMS FOR PROPAGATION DELAY CLOCK TO SERIAL OUTPUT

o
:xJ
S
:::!
o
:2
__ .1'.1.
3-146 tEXAS
INSTRUMENTS
+
tr - 0.8 I's-+l 14-

VCC2 ____"""~~:~oOO--YO- - - \ - - - - - - :0:
I
-+t !.--
II
td
Q OUTPUT U~~/O-VA-l-ID-,\ - - - - ~ - :::

FIGURE 3. VOLTAGE WAVEFORMS FOR DELAY TIMES. LATCH ENABLE TO Q OUTPUTS
...
(I)
Q)
>
'':::
C
>
CO
C.
(I)
2
o
i=
<C
~
a:
oLL
-w
2
U
2
<C
>
c
<C
TEXAS 3-147
INSTRUMENTS
C
fii"
"C
Dr
<
...<"
C
...
CD
en
3-148
SN75581
GAS DISCHARGE DISPLAY DRIVER
02725, MARCH 1983
Each Device Drives 7 Lines J AND N

DUAL-IN-L1NE PACKAGES
TTL Compatible Inputs VCC+ 01

NC 02
Latches on All Driver Outputs OUTPUT ENABLE 03
High-Speed Serially Shifted Data Input CLOCK 04
LATCH ENABLE 05
Output Enable/Disable Function
II
DATA IN 06
Serial Data Output for Cascade Operation VCC- 07
GND -...;;_--,;..r- SERIAL OUT
Shift Register Has Synchronous Clear
Function NC-No internal connection ...en
Q)
description
>
'':::;
C
The SN75581 is a monolithic BIDFETt integrated circuit designed to drive a dot matrix or segmented display.
The output characteristics of this driver make it compatible to several display types including VF and DC >-
ctI
plasma displays. c..
en
All device inputs are diode-clamped p-n-p inputs and, when left open, assume a high-logic level. The nominal is
input threshold is 1.5 volts. Outputs are open-source DMOS transistors for excellent high-voltage
characteristics and reliability.
The device consists of a 7-bit shift register, seven latches, and seven output AND gates. Serial data is
entered into the shift register on the low-to-high transition of the Clock input. When the Latch Enable input
is high, data is transferred from the shift registers to the latch outputs. When Latch Enable makes a high-
to-low transition with the Clock input high, the shift register is cleared. Taking the Output Enable input
high enables all Q outputs simultaneously. The Serial Output is not affected by the Output Enable input.
The SN75581 is characterized for operation from OOC to 70 o C.
logic symbol:l: logic diagram (positive logic)
TTL/GAS DISCH OUTPUT ENABLE

DISPLAY
OUTPUT (3) LATCH ENABLE
E~::~~ 15)
ENABLE CLOCK
DATA IN------1f--+--I
(16) 01
3D (15) 02
3D (14) 03
3D (13) 04
3D (12) 05
3D (11) 06
3D (10) 07
(9) SERIAL
OUT
t BIDFET -Bipolar, double-diffused, N-channel and P-channel MOS transistors on same chip-patented process.
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

~fodf:!~~onlno:~ut~:~:;ifi;::~~~~ser!~~::~~~ TEXAS 3-149
Production processing does not necessarly
include testing of al/ parameters.
INSTRUMENTS
SN75581
CLOCK
UU1JUUU1J
DATA------------~------~-----------------
IRRELEVANT VALID IRRELEVANT
IN
SHIFT
REGISTER NEW DATA CLEARED
lEI
CONTENTS------------~--------------L----------
LATCH _______________________r--1
ENABLE , 1
.._________
c LATCH
(i)" CONTENTS. _____
PR_E_V_IO_U_SL_y_S_T_O_RE_D_D_A_T_A____L ____N_E_W_D_A_T_A_ _
"C
or
< OUTPUT~
..
c
:cr
ENABLE
.
CD
tn
Q
OUTPUTS - ---,
_____ ~ __ ~
PREVIOUS
_____ DATA
VA_L_ID______ ~
NEW DATA VALID _
____________

EQUIVALENT OF EACH INPUT TYPICAL OF ALL Q OUTPUTS TYPICAL SERIAL OUTPUT
VCC+-----4~---- - - - - -....- - VCC+ - - - - -....- - VCC+
INPUT OUTPUT
VCC-------.----- - ....- - -. .- - OUTPUT ------~___- - - GND
Supply voltage, Vee + (see Note 1) ................ . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Supply voltage, Vee - .................................................... - 15 V
Differential supply voltage, Vee + - Vee - .................................... 18.7 V
Output current (one output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 5.5 mA
Applied output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " Vee + - 145 V
Continuous total dissipation at (or below) 25e free-air temperature (see Note 2):
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150 mW
J package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : . . . . . . . . .. 1025 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 70 0 e
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 e to 150 e
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300 0 e
Lead temperature 1,6 mm (1/16 inch) from case.for 10 seconds: N package .......... " 260 0 e

2. For operation above 25C freeair temperature, derate the J package linearly to 656 mW at 70C at the rate of 8.2 mW/oC
and the N package to 736 mW at 70C at the rate of 9.2 mW/oC.
3-150 TEXAS ~
INSTRUMENTS
SN75581

MIN NOM MAX UNIT
Supply voltage, Vcc + 4.5 5 5.5 V
Supply voltage, VCC- -10.8 -12 -13.2 V
Pulse duration, clock high, tw(CKH) 140 ns
Pulse duration, clock low, tw(CKL)
Pulse duration, latch enable high, tw(LEH)
Pulse duration, output enable low, tw(OEL)
Setup time, tsu

Data before clockt
Clock high before latch enablet
320
250
3
70
75
ns
ns
p's
ns
II
.. tn
(1)
Data after clockt 70 "i:

>
Hold time, th ns
Clock high after latch enable~ 500 C
Operating free-air temperature, T A 0 70 c >
co
electrical characteristics over recommended operating free-air temperature range, Q.
tn
VCC + = 4.5 V to 5.5 V (unless otherwise noted)
is
VOH High-level output voltage, serial output IOH = -500 p.A 2.4 4.7 V
VOL Low-level output voltage, serial output VCC+ = 5.5 V, IOL = 1.6 mA 0.15 0.4 V
10(on) On-state output current, Q outputs VOH = VCC+ - 10V -2 -5.5 mA
10(oft) Off-state output current, Q outputs VCC+ = 5.5 V, Vo = -140 V 5 p.A
IIH High-level input current VI = 5.5 V "5 p.A
IlL Low-level input current VI = 0.4 V 50 p.A
ICC+ Supply current from VCC + VCC+ = 5.5 V, VCC- = -13.2 V 12 30 mA
ICC- Supply current from VCC- VCC+ = 5.5 V, VCC- = -13.2 V -11 -28 mA
switching characteristics, CL 20 pF, TA

tpHL Q output from latch enable or 2.2 3
output enable RL = 25 k!l,
p's
tpLH Q output from latch enable or 0.75 2
output enable
tpHL 200 350
serial data from clock RL = 3 k!l,
ns
tpLH 180 350
serial data from clock
t All typical values are at V CC + 5V,VCC-
TEXAS . . 3-151
INSTRUMENTS
POST OFFICE BOX 655012 DALLAS. TEXAS 75265 .
SN75581
I+---tw(CKL)---I~~141-----tW(CKH)---~~
CLOCK
~________)i
I I
~_O%_.
I
______/
r___ 5 V
0 V
Iot-Isu--.l+-th-+l I
I I I ~ 5 V
cCi)'
'C
DATA IN _ _ _ _ _ _ --')k: i ~. .
~14
%_ _ _ _....
~14 ~I
j_-------- 0 V
--,I -----
tsu 14 tw(LEH) th
Dr
<
c.... LATCH ENABLE _ _ _ _ _ _ _ _ _ _ _ -.:..! ~~: n n -- : :
<'
CI)
....
en I I I
I I I 5 V
OUTPUT ENABLE
V~%-l--;-------i---
i i --------- /4---+tPXX*--+I I
OV
i i ! X__ ins:~~o:-n
I I I I VOH
SERIAL OUT
VOL
~tPlH 14- tPXX*--'/
-
tPHL--j.----.I j4-tPXX*-.!
\l I vr
I I I I
Q OUTPUTS x~~~:: VOH
-
*tpxx is tpHL or tpLH (whichever is appropriate)
A -----VOL
FIGURE 3. VOLTAGE WAVEFORMS
---41.--
r
a OUTPUTS -'- -.... TEST POINT Vcc+
25kn CL ~ 20 pF' ~3kn

SERIAL OUTPUT --l-y TEST POINT
-130 V
*Includes probe and jig capacitance

I ct. ~ 20 pF'
FIGURE 4. Q OUTPUT LOAD CONDITIONS

*Includes probe and jig capacitance
FIGURE 5. SERIAL OUTPUT LOAD CONDITIONS
3-152
TEXAS . .
INSTRUMENTS
ADVANCE SN751506, SN751516
INFORMATION DC PLASMA DISPLAY DRIVERS
D3005. DECEMBER 1986
Each Device Drives 32 Lines SN751506 ... FT PACKAGE

(TOP VIEWI
1 BO-V Open Drain Parallel Outputs
032 01
220-mA Parallel Output Sink Current
031 02
Capability
030 03
CMOS-Compatible Inputs 029 04
028 05
Strobe Input Provided 027 06
Serial Data Output for Cascade Operation 026 07
025 08
Inputs Have Built-in Electrostatic Discharge 024 09
Protection 023 010 en
a..
022 011 Q)
description 021 012 >
'a:;:
020 013
The SN751506 and the SN751516 are
019
C
014
monolithic integrated circuits designed to drive
018 015 >-
ca
the scan lines of a dc plasma panel display. The
SN751516 pin sequence is reversed from the
017 016 C.
NC NC en
SN751506 for ease in printed circuit board
layout.
GND GND C
NC NC
Each device consists of a 32-bit shift register and NC STR08E
32 OR gates. Serial data is entered into the shift CLOCK NC
register on the high-to-Iow transition of the clock VCC VCC
NC NC
input. When the strobe input is low, all Q outputs
SERIAL OUT DATA IN
are in the off-state. Outputs are open-drain JFET
transistors with a breakdown voltage in SN751516 ... FT PACKAGE
excess of 1BO volts. The outputs have a (TOP VIEWI
220-milliampere sink current capability in the on
state. Only one Q output should be allowed to 01 032
02 031
be in the on state at a time.
03 030
Serial data output from the shift register may be 04 029
used to cascade shift registers. This output is not 05 028
affected by the strobe input. All inputs are 06 027
CMOS compatible with ESO protection built in. 07 026
08 025
:2
The SN751506 and SN751516 are 09 024 0
characterized for operation from OC to 70C. 010 023 i=
011 022 <C
012 021
:E
013
014
020
019 a::
015 018 0
016 017 LL
NC
GND
NC
NC
GND
NC
-
:2
W
STROBE NC CJ
NC CLOCK :2
VCC VCC <C
NC
DATA IN
NC
SERIAL OUT
>
C
<C
information on new predoucts in the samplinp or
pre~roduction phase of development. Characteristic
TEXAS . . 3-153
DC PLASMA DISPLAY DRIVERS INFORMATION
logic symbols t
SN751506 SN751516
CMOS/ CMOS!
PLASMA DISP PLASMA DISP
STROBE (29) STROBE (20) EN
lEI
CLOCK .:.=.;:.:....J~> CLOCK ..;(_2B....;,)....&..;l'l:>
DATA IN DATA IN (24) 01

02 02
c
(ii'
"C
Q;

[>0

(16)
(33)
016
< 017 [>0 017

...C
...<'en
CD 031
032
SERIAL OUT
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
STROBE
Rl
CLK 01
R2
32BIT
STATIC 02
SHIFT
DATA IN REGISTER 28 OUTPUTS
(03 THRU 030)
NOT SHOWN

c 031
<
032
2 SERIAL
("') OUT
m
FUNCTION TABLE
2
-n CONTROL INPUTS SHIFT REGISTERS OUTPUTS
o FUNCTION
CLOCK I STROBE Rl THRU R32 SERIAL 01 THRU 032
:a LOAD
~ X Load and shift:t R32
Determined by STROBE
3: No~ X No change R32
STROBE
X
X
L
H
As determined above
R32
R32
All high impedance
R1 thru R32
::!
o H = high level, L = low level, X = irrelevant, ~ = high to low transition.
:tR32 takes on the state of R31, R31 takes on the state of R30, ... R2 takes on the state of Rl,
2 and R1 takes on the state of the data input.
3-154 TEXAS
INSTRUMENTS
-IJ1
CLOCK
JlflJU1f WUlJl~-----------------------
DATAINt VALID IRRELEVANT
SHIFT REGISTER --.,--------------"T""----------------

II
CONTENTS--~ _ _ _ _ _ INVALID
________ ~ _______ _ _ _ _ _ _ ____
VALID
STROBE
...U)
Q)
OUTPUTS OFF STATE VALID OFF STATE
'i:
>
t Only 1 bit in 32 should be low in the input data. C
>
ca
schematics of inputs and outputs Q.
U)
EQUIVALENT OF EACH INPUT TYPICAL OF ALL Q OUTPUTS TYPICAL OF SERIAL OUTPUT C

VCC----------~----~~ ----...........e_--------- VCC
INPUT .J\IV\r.......JVIo/lr-....... ....-4I~V\r.....~1'I.._ OUTPUT
GND----~----------~4_ ----~~----~~---GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.4 V to 7 V o
On-state Q output voltage, Va. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.4 V to 125 V i=
Off-state Q output voltage, Va . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4 V to 180 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4 V to Vec+O.4 V
~
Serial output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " - 0.4 V to Vec + 0.4 V a:
Q output on-state time duration (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 itS
Q output duty cycle (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1/200
oLL
Continuous total power dissipation at (or below) 25 DC free-air
temperature (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 De to 70 DC
-w
2
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55 DC to 150 DC ()

2
NOTES: 1. Voltage values are with respect to GND.
2. Only one Q output should be on at a time.
3. For operation above 25C freeair temperature, derate linearly to 656 mW at 70C at the rate of 8.2 mW/oe.
>
c

TEXAS 3-155
INSTRUMENTS

MIN NOM MAX UNIT
Supply voltage. VCC 4 5 6 V
Peak on-state Q output voltage. VO(on) 110 V
VCC = 4 V 3.2
High-level input voltage. VIH V
VCC = 6 V 4.8
VCC = 4 V 0.8
V
Low-level input voltage. VIL
= 1.2
lEI
VCC 6 V
Output current. 10 (T A = 25CI 220 mA
Clock frequency. fclock 200 kHz
Pulse duration. clock high or low. twCLK 1.5 t IlS
cC;;' Pulse duration. data. twD 5 IlS
Pulse duration. strobe. twSTRB 2 IlS
"C
or Setup time. data before clock!. tsu 1 IlS
-< Hold time. data after clock!. th 1.2 IlS
c... Operating free-air temperature. T A 0 70 c
<' t The minimum clock period is 5 Ils.

...
CD
en electrical characteristics, Vee 5 V, TA 25e (unless otherwise noted)
VOH High-level output voltage Serial out 10H = -0.1 mA 4.5 V
Q outputs 10L = 180 mA 6 10
Serial out 10L = 0.1 mA 0.5
10(oft) Off-state output current Q outputs VOH = 110 V 1 IlA
IOL Low-level output current Q outputs VOL = 16V 220 mA
IIH High-level input current VI = VCC 1 IlA
IlL Low-level input current VI = 0 -1 IlA
Ci Input capacitance 15 pF
All Q outputs off 1
ICC S'upply current mA
One Q output on 20 40
switching characteristics, Vee 5 V, TA

J>
c tpd Propagation delay time. clock to serial output CL = 15 pF 0.2 0.5 IlS
<
J>
tDHL
tDLH
Delay time. high-to-Iow-Ievel Q output from strobe or clock inputs
Delay time. low-to-high-Ievel Q output from strobe or clock inputs
CL =
RL = 470
150 pF.
n.
0.2*
0.35*
0.6
1
IlS
Ils
z tTHL
tTLH
Transition time. high-to-Iow-Ievel Q output
Transition time. low-to-high-Ievel Q output
See Figures 2 and 3
0.1
0.35
0.3
1
IlS
(') IlS
m *Typical values are for clock inputs. Typical times from strobe inputs will be less.
--nZ
o
::c
~
J>
::!
o
z
3-156 TEXAS . .
INSTRUMENTS
N751506, SN751516
C PLASMA DISPLAY DRIVERS
PARAMETER MEASUR
5V
DATA IN
Q2
150 ~
CLK
Q31
150 pF ~
Q32 t--........JV\IV-
470 n
STROBE
SERIAL J---e---
'OUT CL'
(SEE 1\
II ~;: A. Input pulses are supplied by generators having the following characteristics: tw = 1.25 IJ,s, PRR
tf s 30 ns, Zo = 50 n.
TeST CIRCUIT
FIGURE 3
TEXAS
INSTRUMENTS
I
SN751506 S\
DC PLASMA DlSPLJ 01
FIGURE 1. INPUT TIMING VOLTAGE WAVEFORMS c

(ii'
'C
---""- - - - - - - - - - - - - - - ---- or
-<
JCK~ LAST \_
,PUT PULSE :\50%
I~'-------------------------------
...c
I <'
...en
CD
/+-twSTRB -+\
STROBE I
I 'O%~ ,,'0%
k-tOHL ~ tOLH --I4--.J \414---I~tOHL NO'
I I
90%
Q OUTPUT
10% 10%
/.-tOLH-.I

o
<

2
("')
m
-
2
'"T1
0,
:lJ
S

:::!
o
2
TEXAS
INSTRUMENTS
l!1 3-158
CLOCK ~50% \50% /50% . 4V
i.--twCLKH .1 + - - - - - - - -1 V
I&...- ~twCLKL -+I
r tSUD~thD~
DATA IN *50% *50% ::
14 twD .1
II
...
en
CI)
>
''::
C
>
CtI
Q.
en
C
90%
Q OUTPUT
10% 10%
1"----- VOL
/.-tDLH~ 1 I
~tTHL
:2
o
i=

~.
a:
ou.
-w
:2
CJ
:2

c>

TEXAS 3-157
INSTRUMENTS
SN751506. SN751516 ADVANCE
II
c
(ii'
"C
Dr
<
...C
<'
...
CD
(I)
=
NOTES: A. Input pulses are supplied by generators having the following characteristics: tw = 1.25 p's, PRR :s 200 kHz, tr :s 30 ns,
tf :s 30 ns, Zo = 50 n.
TEST CIRCUIT
FIGURE 3
c
<
2
n
m
2-
."
0,
::JJ
S
:::!
o
2
3-158 TEXAS
INSTRUMENlS
LOW-LEVEL Q OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT Q OUTPUTS

vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
10 500
vee' - 5'V vee - 5 V
> IOL ... 180 mA I-VO - 16 V
E
II
I
~ 8 I 400
--
S E
- --- ---
15 ~
> :; r----
'5c.
'S
o
Qj
6
f.--- ~
~
~:::l
S-
:::l
o
300
i-----
- r-- r--- ...
"i:
tn
CD
>
~ 4 ~ 200 C
~ Q)
~ ..J >
ta
o ~
~ o C.
~ 2 "I 100 tn
o
> 9
-' C
o o
o 10 20 30 40 50 60 70 80 o 10 20 30 40 50, 60 70 80
TA-Free-Air Temperature- e TA-Free-Air Temperature- e
FIGURE 4 FIGURE 5
PROPAGATION DELAY TIME,

SUPPLY CURRENT CLOCK TO SERIAL OUTPUT
vs vs
26 0.5
vee - -5 V vee - 5 V
One Q eL - 15 pF
1/1
Output low
24 f 0.4
E
Q)
E 2:
.!.c i=
>-
o
~
:;
22 ~ 0.3 i=
c

-
(J
------
c
---
>-
c.
g. ~
.2
~ ~ ~
20
ca
0.2
- a:
oLL
(I)
0.
o
'b
9
Q:
1a
18
..
0.
0.1
-2:w
16 o (.)
o 10 20 30 40 50 60 70 80 o 10 20 30 40 50 6070 80 2:
T A - Free-Air Temperature - e T A - Free-Air Temperature - e
FIGURE 6 FIGURE 7 >
c

TEXAS
INSTRUMENTS
-1!1 3-159
POST OFF'CE BOX 655012 DALLAS. TEXAS 75265
DELAY TIME, DELAY TIME,

HIGH-TO-LOW-LEVEL Q OUTPUT LOW-TO-HIGH-LEVEL Q OUTPUT
vs vs
0.5 0.5
VI VC~ .. 5 V VI
::l.
VCC - 5 V
::l.
CL '" 150 pF I CL .. 150 pF
lEI
I
III
III
RL .,. 470 n RL .. 470 n
.5 0.4 .5 0.4
I-
>-
I-
>- ~r-
-
---
(0 (0
a:; a:;
C 0 o V
Ci)' a:; 0.3 a:; 0.3
"C > >
III
III
Di" ..J ..J
< ~
- 1:.
.;::-
Cl
S 0.2 :I: 0.2
C
E E
.
(t)
en
1:.
Cl
:I: 0.1
I
..J
~
o
..J
I 0.1
:I:
:I: ..J
51 51
o o
o 10_ 20 30 40 50 60 70 80 o 10 20 30 40 50 60 70 80
TA-Free-Air Temperature- c T A - Free-Air Temperature - c

FIGURE 8 FIGURE 9
TRANSITION TIME, TRANSITION TIME,

HIGH-TO-LOW-LEVEL Q OUTPUT LOW-TO-HIGH-LEVEL Q OUTPUT
vs vs
VI 0.5 VI 1.0
VC~
1
VC~
1
::l. ::l.
... 5 V I - 5 V
I Q)
III CL '" 150 pF CL ... 150 pF
E E
RL '" 470 n

c
j:: 0.4
c:
.g
j:: 0.8
c:
.g
RL "" 470 n
'iii
<

'iii
c:
~ 0.3
c:
~ 0.6
2 a:; a:; /
> > ,,-
---- -
III Q)
(") ..J ..J
~
m ~ 0.2 .g 0.4
-2 --
o
..J :I:
~
E
1:. ~
E ,..-
L--- ~ ~
"TI :f 0.1 S
o I
~
I
0.2
::D ..J
:I:
:I:
..J
S t" 0 t" 0
, o 10 20 30 40 50 60 70 80 o 10 20 30 40 50 60 70 80
::I T A - Free-Air Temperature - c T A - Free-Air Temperature - c

o FIGURE 10 FIGURE 11
2
3-160 TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 ' pALLAS, TEXAS 75265
D2984. JANUARY 1987
Each Device Drives 32 Lines SN751508 ... FT PACKAGE

(TOP VIEW)
- 120-V P-N-P Open-Collector Parallel
Outputs 032 01
e High-Speed Serially Shifted Data Inputs 031 02
030 03
o CMOS-Compatible Inputs 029 04
028 05
Strobe and Sustain Inputs Provided 027 06
Serial Data Output for Cascade Operation
description
The SN751508 and SN751518 are monolithic
026
025
024
023
022
07
08
09
010
011
II
. f/)
Q)
021 012
integrated circuits designed to drive the data 020 013 'i:
>
lines of a dc plasma panel display. The 019 014
SN751518 pin sequence is reve"rsed from the
C
018 015
SN751508 for ease in printed circuit board 017 016 >
CO
layout. GND GND Q.
NC SUSTAIN f/)
Each device consists of two 16-bit shift STROBE NC C
registers, 32 latches. 32 OR gates, and 32 NC LATCH ENABLE
P-N-P open-collector output AND gates. CLOCK NC
Typically. a 32-bit data string is split into two VCC VCC
1 6-bit data strings externally and then entered SERIAL OUT2 DATA IN2
SERIAL OUTl DATA INl
in parallel into the shift registers on the high-to-
low transition of the clock signal. A logic high
signal on the Latch Enable input transfers the SN751518 ... FT PACKAGE
data from the shift registers to the inputs of 32 (TOP VIEW)
OR gates through the latches. Data present in
the latch during the high-to-Iow transition of 01 032
Latch Enable is stored. When the Strobe input 02 031
is high. the latch is masked and a high will be 03 030
04 029
placed on the data input of the output AND
05 028
gates. When the Strobe input is low. and the 06 027
Sustain input is high. data from the latches is 07 026
reflected at the outputs. A logic low signal on 08 025
the Sustain input will force all outputs to their 09 024
2
off state. Drivers may be cascaded via the serial 010 023 0
data ou~puts of the static shift registers. These 011 022 i=
o outputs are not affected by the Latch Enable. 012
013
021
020
cd:
Strobe. or Sustain inputs. 014 019 ~
The SN751508 and the SN751518 are 015 018
017
a:
016
characterized from OOC to 70C.
GND GND
0
LL
SUSTAIN NC
NC STR08E 2
LATCH ENABLE NC
NC CLOCK W
VCC VCC
(.)
DATA IN2 SERIAL OUT2 2
DATAINl SERIAL OUTl cd:
NC- No internal connection.
>
C
cd:
Copyright 1987. Texas Instruments Incorporated
ADVANCE INFORMATION documents contain
data and other specifications are subiect to change
TEXAS . . 3-161
logic symbols t
SN751508
.l!!L- EN44 CMOS/EL DISP

SUSTAIN
STROBE1!l!L- V43
LATCH ENABLE ~ C42
CLOCK .!.illt:::.. >Z40
SRG16 ~
J.401C41 I-I
lEI
r
DATA INI ~41D Zl 1 42D t> 43.440~'01
Z3 242D t> 43.44 0 --1iZl,02
342D t> 43.44 0

442D t> 43.440
---1i!!!.,03
~ 04

Z15
Z17

1542D t> 43.440 ~ 015
1642D t> 43.440 ~ 016
Z29 17 42D t> 43.440 ,.......ill! 017
Z31 lB 42D t> 43.440 r---ill! alB
SRG16
,40IC45/-1 r
DATA IN2:~45D Z2 2942D t> 43.440 ~ 029
Z4 30420 t> 43.44~ ~ 030
Z16
31 420 t> 43.44~
32420 t> 43.440
1
r------ill 031
r----ill 032
241 SERIAL
ZIB 31 oun
Z30 32
1
~ SERIAL
OUT2
Z32
SN751518
SUSTAIN ~ EN44
CMOS/EL OISP
STROBE ~ V43
LATCH ENABLE
QL C42
CLOCK ~ p..Z40
DATA INI ~410

, SRG16
40(C41/-1
ZI 1 420 t> 43.44!;~'01

t>43.440~'Q2
l> Z3 2420
c 3420
4420
t> 43.440~03
t> 43.440~ 04
<
l>
Z15
Z17
2 15420
16420
t> 43.44~
t> 43.440
~ 015
~ 016
om Z29
Z31
17420
18420
t> 43.44~
t> 43.440
~ 017
~ alB
-2 DATA IN2 ~450

, SRG16
401C45/-1
r
Z2 29420

t> 43.440 ~ 029
"o Z4 30420 t> 43.44~ ~ 030

31 420 t> 43.44~ ~ 031
::D 32420 t> 43.440 ~ 032
s: Z16
ZIB 31
1
~ oun
SERIAL
l>
:::! Z30 32
1
~ OUT2
SERIAL
o Z32
2 tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
3-162 TEXAS
INSTRUMENTS
SUSTAIN
STROBE
LATCH

ENABLE
CLOCK
DATAIN1 Q1
...en
Q)
>
"a::
Q2
C
>
as
Q.
en
Q3 C
Q4

.. .

~

DATAIN2
Q29
Q30 z
o
i=
Q31 <t
~
a::
Q32
oLL
Z
>---- SERIAL OUT1 W
>---- SERIAL OUT2
U
z
<t
>
c
<t
TEXAS ~ 3-163
INSTRUMENTS

FUNCTION LATCH SERIAL
CLOCK STROBE SUSTAIN R1 THRU R32 LC1 THRU LC32 01 THRU 032
ENABLE 501 S02
! X X X Load and shift t Determined by Determined by
LOAD R31 R32
No! X X X No change Latch Enable ~ Sustain and Strobe
LATCH X L X X Stored data Determined by
As determined above R31 R32
ENABLE X H X X New data Sustain and Strobe
X X L H Determined by LC 1 thru LC32
lEI
STROBE As determined above R31 R32
X X H H Latch Enable t All on (high)
Determined by
SUSTAIN X X X L As determined above R31 R32 All off
Latch Enable t
H = high level, L = low level, X = irrelevant, ! = high-to-Iow transition

t Each even-numbered shift register stage takes on the state of the next-lower even-numbered stage, and likewise each odd-numbered
shift register stage takes on the state of the next-lower odd-numbered stage; i.e., R32 takes on the state of R30, R30 takes on the state
of R2a, ... R4 takes on the state of R2, R2 takes on the state of Data !n2, R31 takes on the state of R29, R29 takes on the state of
R27, ... R3 takes on the state of R1, and R1 takes on the state on Data In1.
t New data enters the latches while Latch Enable is high. This data is stored while Latch Enable is low.
CLOCK ~
nnro.Olfl
LJ LJ ~ ________________________
SHIFT ------------------...--------------------------
REGISTER INVALID VALID
CONTENTS------------------~-------------------------
LATCH ENABLE n
----------------~ ~-------------------
LATCH CONTENTS PREVIOUSLY STORED DATA I NEW DATA VALID
STROBE
:t> SUSTAIN
c
<
:t>
o OUTPUTS OFF-STATE I I
VALID OFF STATE
2
(")
m
2-
-n
o
:lJ
S
:t>
:::!
o
2
3-164 TEXAS
INSTRUMENTS
-1/1

EaUIVALENT OF EA.CH INPUT TYPICAL OF ALL a OUTPUTS TYPICAL OF SERIAL OUTPUT
vcc--------~.---~~~ ----~~~--------VCC
_ _JV\/\r-4~"""'- OUTPUT
II ...
tn
Q)
'i:
>
GND----~--------_4~- ----~~----~--~GND C
>-
m
absolute maximum ratings over operating free-air temperature (unless otherwise noted) 'E.
tn
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.4 to 7 V Q
On-state Q output voltage, Va. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -120 V to Vee + 0.4 V
Input voltage ............................................... -0.4 V to Vee +0.4 V
Serial output voltage ... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.4 V to Vee + 0.4 V
eontinuous total power dissipation at (or below) 25e free-air temperature
- (see Note 2) ............................................. '. . . . . . . . .. 1025 mW
Operating free-air temperature range .................................... " ooe to 70 0 e
Storage temperature range ......................................... - 65 e to 150 e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260 0 e
NOTES: 1. Voltages values are with respect to GND.

2. For operation above f5e free-air temperature, derate linearly to 656 mW at 70 0 e at the rate of 8.2 mW/oe.
2:
o
i=
<C
:2E
a::
oLL
-2:w
(.)
2:
<C
>
c
<C
TEXAS 3-165
INSTRUMENTS

MIN NOM MAX UNIT
Output voltage, Vo -75 V
VCC = 4.5 V 3.6
Highlevel input voltage, VIH V
VCC = 5.5 V 4.4
VCC = 4.5 V 0.9
V
VCC = 5.5 V 1
Output current, 10 (T A = 25C) -1.2 mA
Clock 75
c
(ii' Pulse duration, tw (see Figure 1)
Data In
Latch Enable
160
90
ns
"C Strobe 2
or Sustain 2
its
-< Data In before clock! 20
...c Clock low before latch enabler 50
...en<'
Setup time, tsu (see Figure 1) Latch-Enable low before clock! 0 ns
(1)
Latch-Enable high before strobe! 0
Latch-Enable high before sustainl 0
Hold time, Data In after clock!, th (see Figure 1) 50 itS
electrical characteristics, Vee 5 V, TA o e to 70 0

e (unless otherwise noted)
Q out IOH = -0.5 mA 4 4.5
IOH = -100 itA 4.3 4.6
VCC = 5.5 V
V
Serial Out
IOH = -20 itA 4.4
IOH = -100 itA 3.4 3.6
VCC = 4.5 V
3.6
IOH = -20 itA
IOL = 100 itA 0.9 1.2
VCC = 5.5 V
IOL = 20 itA 1.1
VOL Low-level output voltage Serial Out V
IOL = 101) itA 0.9 1.1
Vee = 4.5 V
IOL = 20 itA 0.9
c
IOH
IOL
High-level Q output current
Low-level Q output current
TA
TA
=
=
25C,
25C,
Vo = 3 V
Vo = -75 V
-1.2
-500
mA
itA
= VI = VCC
<
IIH
IlL
TA
TA =
25e,
25C, VI = 0 -1
1 itA
itA
All Q outputs high, VCC = 5.5 V 17 25
2 ICC Supply current
All Q outputs low 3
mA
(") Ci Input capacitance 15 pF
m
2 switching characteristics Vee 5 V, TA 25e (unless otherwise noted)
~
o PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
:xJ ted Propagation delay time, Clock to Serial Out CL = 15 pF 100 150 ns
S tDLH Delay time, low-to-high-Ievel Q output from Sustain or Strobe 0.3:1: 1 itS
::j
tDHL
tTLH
Delay time, high-to-Iow-Ievel Q output from Sustain or Strobe
Transition time, low-to-high-Ievel Q output
CL = 15 pF,
RL = 91 kO,
1:1:
2
2.5
5
itS
its
See Figures 1 and 2
o tTHL Transition time, high-to-Iow-Ievel Q output 11 18 itS
2 :l:Typical values for delay times are measured from the Sustain input.
3-166 TEXAS . .
INSTRUMENTS
ADVANCE SN751508. SN751518
r------------------- 4v
CLOCK
I '----1- - - - - - - - - - - - -1 V
It--tw ~I tw~
sU
+1 th
J *'-______--.;.___I~,..O-%--------------:: II
I+-t
DATA IN ! t/)
f4- tWT---+l
~
CD
>
'i:
~tpd C
I
---------~:I-~ ~r-----------------------VOH >
as
SERIAL OUT A /,\0% C.
t/)
I '------~. '-.- - - - - - - - - - - - V O L C
I+-tsu~ I+-tsu~
LATCH ENABLE
r--tw~
~:%-
I
------__ ---------4V
______________J. I . 1V
I
r-tsu~ I4- t W--i
I I*-tw~ I '
STRo~----------~i---~~O-%-----------I~,..----~-~:
I I I
~tsu1 : r-tW-t"-tW-i 2:
o
SUSTAIN ----------------....JX' i
I tDLH..j j4- I
U\------~:
+t lot- I
i=
<C
:!
tOHL
a:
I -+I
Q OUTPUTS
:
0. :
-----------4--,
tDLH..j j4-
I
l \ 1_h.
.i{ I
I
~ ~tDLH
j4"tDHL;
["'\:
I
90%----ON
10%
ou.
-2:w
tTltat j4- 1 I. I I I
I
I -.fj.tTlH
I OFF
o
tTlH~ j4- I I ~ J4-tTHL 2:
tTHL'" /4- <C
NOTE: Input tr and tf are less than or equal to 10 ns. >
C
FIGURE 1. INPUT TIMING AND SWITCHING TIME VOLTAGE WAVEFORMS
<C
TEXAS
INSTRUMENTS
-1!1 3-167
SN7515D8, SN751518 ADVANCE
PARAMETER MEASUREMENT'INFORMATION
5V -75 V
15 pF
VCC
DATA IN
91 kO
lEI
c
CLOCK
STROBE
(ii'
'C
Q) 031 1-----'."'1\,-......- ..
'<
..<'
C
SUSTAIN
..
CD
en LATCH ENABLE
SERIAL OUT1 1 - - - -.....- -
SERIAL OUT2 1--.---+--
CL - 15 pF
(see Note B)
TEST CIRCUIT
NOTES: A. Input pulses are supplied by generators having the following characteristics: tw = 100 ns, PRR oS 5 MHz, tr oS 10 ns,
tf oS 10 ns, Zo = 50 n.
. FIGURE 2

c
<

:2
(")
-m
:2
"o
:c
S

::j
o
:2
3-168 TEXAS
INSTRUMENTS
-1/1
TYPICAL CHARACT~RISTICS
SUPPLY CURRENT DELAY TIME,CLOCK TO SERIAL OUTPUT

vs vs
20 CII 125
l'---. c:
~ ;
I
~
~ - ~~
II
E- 100
"'~ -- I'-...... r--

~
~ 15
o
]
.!.c: Gi
en
:;
!!?
B
75
...
f/)
Q)
c;. 10
~
o
(J
'i:
:>
C. U
~
0. 50 C
en cD
I Vee - 5.5 V E >
CO
CJ i=
~ All Q outputs low Vee - 5 V C.
9 5
NT I
d
>-
111
Gl
c
"0
I
25
~CLI- 15( f/)
Q
o I ..
0.
o
o
o 10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80
T A - Free-Air Temperature - e TA-Free-Air Temperature- e
FIGURE 3 FIGURE 4
DELAY TIME, SUSTAIN INPUT TO Q OUTPUT, DELAY TIME, SUSTAIN INPUT TO Q OUTPUT,
LOW TO HIGH HIGH TO LOW
vs vs
CII
~ 0.5 1 :s. 2 1
I veb"" 5 V I ved"" 5 V
.z= l-eL - 15 pF 3: eL - 15 pF
Cl 0
...I
J: RL - 91 kO
B 0.4 t-RL - 91 k!l B
3:
.z= 1.5 2
o
...I
l---l---
~
I--
..
J:
Cl
o
~
;
E-
~
'0
0.3
~
~
0
~
E-
~
..- - cd:
c: 0 ~
Gl
0.2 cD a:
E
i=
>-
i=
E
>- 0.5
oLL
111
~ 0.1
-2w
I
Gl
c c
I I
...I
:J: :J:
...I
e o e 0
o U
o 10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80
2
TA-Free-Air Temperature- e
T A - Free-Air Temperature - e cd:
FIGURE 5 FIGURE 6 >
c
cd:
TEXAS -II} 3-169

INSTRUMENTS
TYPICAL CHARACTERrSTICS
TRANSITION TIME, Q OUTPUT, TRANSITION TIME, Q OUTPUT,
LOW TO HIGH HIGH TO LOW
vs vs
FREE-AIR TEMPERATURE 1/1 FREE-AIR TEMPERATURE
os.
I J
_ Vee - 5 V ~ 20 Ve~ _ 5 1V
CL - 15 pF oS CL - 15 pF
- RL - 91 kO g RL - 91 kO
.c
~ 15r--+---r--+-~~-+--~--+_~
...:r
C
iii" ~:r 3 So
:r
"C o o
d 10r--+---r--+---r--+--~--+_~
Dr d ~~
< ~ 2 -~ tD
I--' E
...c i= ~ i=
<" c
o
c
,g 5 r--+---r--+--r--+--~--+_--I
...
CD
(I)
-~
'iii
c
'iii
c
~ ~
I.
:sl:I 0
0 10 20 30 40 50 60 70 80
..J
:z::
l:
0 L - - - L_ _- ' -_ _...I....---lL----L.._ _--L..-_ _.l.----.J
0 10 20 30 40 50 60 70 80
T A -Free-Air Temperature- De TA-Free-Air Temperature- DC
FIGURE 7 FIGURE 8
l>
c
<
l>
:2
("')
m
-
:2
."
o::I:J
s:
l>
:::!
o
:2
3-170 TEXAS
INSTRUMENTS
TL4810BI, TL4810B
02715, DECEMBER 1984-REVISED FEBRUARY 1986
Each Device Drives 10 Lines N

DUAl-IN-L1NE PACKAGE
60-V Output Voltage Rating (TOP VIEW)
40-mA Output Source Current 08 09

06 SERIAL DATA OUT
CMOS-Compatible Inputs CLOCK VBB
Latches on All Driver Outputs VSS DATA IN
Improved Direct Replacement for

UCN4810A and TL4810A
description
VDD
LATCH ENABLE (STROBE)
05
04
BLANKING
01
02
03
II ...
(I)
Q)
The TL4810BI and TL4810B are monolithic DW >

'Ii:
SMAll OUTLINE PACKAGE
BIOFETt integrated circuits designed to drive a C
(TOP VIEW)
dot matrix or segmented vacuum fluorescent
display (VFO). These devices feature a serial data
>-
CO
08 09
output to cascade additional devices for large Q.
07 010 (I)
display arrays. 06
CLOCK
NC is
A 1O-bit data word is serially loaded into the shift SERIAL DATA OUT
register on the positive-going transitions of the VSS VBS
clock. Parallel data is transferred to the output NC DATA IN
buffers through a 10-bit O-type latch while the VDD BLANKING
LATCH ENABLE (STROBE) 01
latch enable input is high and is latched when
the latch enable is low. When the blanking input 05 02
is high, all outputs are low. 04 03
Outputs are totem-pole structures formed by NC - No internal connection

n-p-n emitter-follower and double-diffused MOS
(OM OS) transistors with output voltage ratings
of 70 volts and 40 milliamperes source-current
capability. All inputs are compatible with CMOS
and TTL levels, but each requires the addition of
a pull-up resistor to VOO when driven by TTL
logic.
The TL4810BI is characterized for operation
from -40C to 85C. The TL4810B is
characterized for operation from OC to 70C.
t BIDFET -Bipolar, Double-Diffused, N-Channel and P-Channel MOS transistors on same chip-patented process_
current as of publication date_ Products conform to
TEXAS 3-171
=~~~~:~~i~a{::I~~~ ~!~~~~ti~: fI~o::~:~:t::s~s not INSTRUMENTS
TL4810BI, TL4810B
logic symbol t logic diagram (positive logic)
BLANKING
LATCH ENABLE (7) C2 LATCH

BLANKING (13) ENABLE SHIFT
REGISTER LATCHES
OATAIN
CLOCK ~"---1>
II 10 20 t>
20 t>
20t>
20 t>
3
3
3
3
(12)
(11 )
(10)
(9)
01
02
03
04
(8)
20 t> 3 05
(3)
20 t> 3 06
(2)
20 t> 3 07
(1)
20 t> 3 08
(18)
20 t> 3 09
(17)
20 t> 3 010
(16)
SERIAL DATA OUT

FUNCTION TABLE

FUNCTION LATCH BLANK-
CLOCK Rl THRU Rl0* LCl THRU LC10 SERIAL al THRU al0
ENABLE ING
t X X . Load and shift: Determined by Latch Enable Rl0 Determined by Blanking
LOAD
Not X X No change Determined by Latch Enable Rl0 Determined by Blanking
X L X As determined above Stored data Rl0 Determined by Blanking
LATCH
X H X As determined above New data Rl0 Determined by Blanking
X X H As determined above Determined by Latch Enable Rl0 All L
BLANK
X X L As determined above Determined by Latch Enable Rla LC 1 thru LC 1a respectively

: Register Rla takes on the state of R9, R9 takes on the state of R8 ... R2 takes on the state of Rl, and Rl takes on the state of the data input.
New data enter the latches while Latch Enable is high. These data are stored while Latch Enable is low.
3-172 TEXAS ~
INSTRUMENTS
POST OFFICE BOX 65501 a DALLAS, TEXAS 75265
TL4810BL TL4810B
CLOCK
SR CONTENTS
LATCH
ENABLE
INVALID
__________________________ ________________ r1~

VALID
II
. U)
CD
LATCH
CONTENTS
PREVIOUSLY STORED DATA NEW DATA VALID
'i:
>
C
BLANKING >
CO
"E.
U)
Q OUTPUTS VALID
Q
_ _ _ _...._ _ VBB (Q OUTPUTS)
VDD--~------------~~
VDD (SERIAL OUTPUT)
INPUT-.....+-......- - . OUTPUT
100
TEXAS -I.!} 3-173

INSTRUMENTS
POST OFFICi BOll 1i66Q1iJ ' DA~LAS. nXAii 762116
TL4810BI, TL481 DB
Logic supply voltage, VOD (see Note 1) ......................................... 18 V
Driver supply voltage, VBB . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 70 V
Output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 70 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to VOO + 0.3 V
Continuous total dissipation at 25C free air-temperature (see Note 2):
DW package ........................................................ 1150 mW
N package ........................................................... 875 mW
Operating free-air temperature range: TL481 OBI .......... .'............... - 40C to 85 C
TL4810B ............................. OOC to 70C
c Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260C
en'
'C NOTES: 1. Voltage values are with respect to VSS.
iii' 2.' For operation above 25C free-air temperature. refer to the Dissipation Derating Table.
<
...c DISSIPATION DERATING TABLE
<'CD
...
(I)
PACKAGE
POWER
RATING
DERATING
FACTOR
ABOVE
TA
OW 1150 9.2 mW/oC
N 875 7.0 mW/oC

TL481 OBI TL4810B
PARAMETER UNIT
MIN NOM , MAX MIN NOM MAX
Supply voltage, VDD 4.75 15.75 4.75 15.75 V
Supply voltage. V8S 5 60 5 60 V
Supply voltage. VSS 0 0 V
High-level input voltage. VIH

Lfor VDD = 5 V 3.5 5.3 3.5 5.3
V
I for VDD = 15 V 13.5 15.3 13.5 15.3
Low-level input voltage. VIL -0.3 T 0.8 -0.3 T 0.8 V
Continuous high-level output current. IOH -25 -25 mA
t The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for logic
voltages only.
3-174 TEXAS
INSTRUMENTS
TL4810BI. TL481 DB
electrical characteristics over recommended operating free-air temperature range, Voo = 5 V to 15 V,

VBB = 60 V, Vss = 0 (unless otherwise noted)
Tl481 OBI Tl4810B
PARAMETER TEST CONOITIONSt UNIT
MIN TYP; MAX MIN TYP; MAX
High-level Q outputs IOH = -25 mA 57.5 58 57.5 58
VOH output VDD = 5 V, 10H = -100 JlA 4 4.5 4 4.5-- V
Serial output
voltage VOD = 15 V, 10H = -100 JlA 14 14.7 14 14.7
Low-level Q outputs 10H = 1 JlA, Blanking input at VDD 0.5 1 0.5 1
VOL output
voltage
Serial output
Low-level Q output current TA

VDD
VDD
=
=
15 V,
Va = 60 V,
= MIN to
5 V, 10L
10L
=
=
100 JlA
100 JlA
Blanking input at VDD,
70C
2.5
0.05
0.02
3.7
0.1
0.1
2.5
0.05
0.02
3.7
0.1
0.1
V
II ...
(I)
10L mA Q)
(pull-down current) Va = 60 V, Blanking input at VDD,
>
2
TA = 85C "i:
Va = 0, Blanking input at VDD, C
10(0ft) Off-state output current -1 -15 -1 -15 JlA
TA = MAX >
ca
IH High-level input current VI = VDD 30 50 30 50 JlA
All outputs low 0.5 1 0.5 1
C.
(I)
IBB Supply current from VBB All outputs high, T A = OOC to MAX 2.7 4 2.7 4 mA C
All outputs high, T A = - 40C 5
All inputs at 0 V, VDD = 5 V 10 50 10 50
One Q output high VDD = 15 V 10 100 10 100
IDD Supply current from VOD JlA
All inputs at 0 V, VDO = 5V 10 50 10 50
All outputs low VOO = 15 V 10 100 10 100
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
i All typical values are at TA = 25C, except for 10.
timing requirements over recommended operating free-air temperature range

VOO - 5 V VOO - 15 V
PARAMETER UNIT
MIN MAX MIN MAX
tw(CKH) Pulse duration, clock high 250 50 ns
tw(LEH) Pulse duration, latch enable high 250 50 ns
tsu(D) Setup time, data before clocki 125 25 ns
th(O) Hold time, data after clocki 125 25 ns
teKH-LEH Delay time, clock i to latch enable high 125 25 ns
switching characteristics, VBB 60 V, TA

PARAMETER MIN TYP MAX
Propagation delay time, latch enable to output

VDO = 5 V
tpd
VDD ,= 15 V 0.5
TEXAS . . 3-175
INSTRUMENTS
TL4810BI. TL481 DB
LAST - - - - - - - - - - - VIH
CLOCK CLOCK
I PULSE VIL
'------' I
I
VIL INPUT
I4-tCKH-LEH~ .! tw(LEH)
\50%--
_-r---r_
tsu(D) 14
I
~~ ~I
I
th(D)
VIH
LATCH 50%1
ENABLE _ _ _ _ _ _....J
I
VIH
VIL
c
DATA ~O%VALID 50%XXXX V"
I+-tpd-+i
OUTPUT _ _ _ _ _ _ _ _ _ _ _ 90_o/cJ}Fr-V-A-Ll-D~~
(ii"
"C FIGURE 1. INPUT TIMING FIGURE 2. OUTPUT SWITCHING TIMES
Q)
<
...C THERMAL INFORMATION
<"
...
CD
en
DW PACKAGE DUTY CYCLE N PACKAGE DUTY CYCLE
vs vs
100 N-1 to 6 100~~~~~~~-r~~~~Nu-
... ~1~t-o~4
\~ [\\ N-7, N-5

90
'#.
CI) 80 1\[\\ N-8 "

1
~
U
>
()
1
N"'9"
~ 70
:s
C , N ... 1b
E
:s VBB - 60 V VBB - 60 V
E 60
VOO - 15 V 60 VOO - 15 V
'xI'CI
IOH - -25 mA IOH - -25 mA
.~
50 IOL - 1 p.A 50 IOL - 1 p.A
N - Number of outputs high
All o~her 0lutPut~ low I
40 I 40L-~---L---L--~--~--L-~L-~
25 35 45 55 65 75 85 95 100 25 35 45 55 65 75 85 95 100
TA - Free-Air Temperature - C TA - Free-Air Temperature - C
FIGURE 3 FIGURE 4
3-176 TEXAS -I.!}

INSTRUMENTS
TL58121. TL5812
02914, OCTOBER 1985-REVISEO AUGUST 1986
Drives Up to 20 Lines N
40-mA Output Source Current ,Capability VBB VDD

High-Speed Serially-Shifted Data Input SERIAL DATA OUT DATA IN
020 01
o CMOS-Compatible Inputs 019 02
Direct Replacement for Sprague UCN5812A 018 03
description
The TL58121 and TL5812 are monolithic
BIOFETt integrated circuits designed to drive a
017
016
015
014
013
04
05
06
07
08
II
.t/)
Q)
dot matrix or segmented vacuum fluorescent 012 09 >
'i:
display (VFO). Each device features a serial data 011 010
output to cascade additional devices for large C
BLANKING LATCH ENABLE (STROBE)
display arrays. VSS CLOCK
>-
CO
A 20-bit data word is serially loaded into the shift
Q.
t/)
register on the low-to-high transition of the clock FN PACKAGE
input. Parallel data is transferred to the output (TOP VIEW)
C
buffers through a 20-bit Ootype latch while the I-
:::::>
Latch Enable input is high and is latched when o
the Latch Enable input is low. When the blanking e::(
l-
input is high, all outputs are low. e::(
~ ~
The outputs are totem-pole structures formed by e::(
n-p-n emitter-follower and double-diffused MaS ~~ffi ~~ ....
(OMOS) transistors with output voltage ratings 00(1> 0 0
of 70 volts and a source-current capability of 40 4 3 2 1 282726
milliamperes. All inputs are CMOS compatible. 018 25 02
The TL58121 is characterized for operation from 017 24 03
- 40C to 85 DC. The TL5812 is characterized 016 7 23 04
for operation from OOC to 70C. 015 8 22 05
014 9 21 06
013 10 20 07
012 11 19 08
12131415 1617 18
W
...J
co
e::(
2
w
I
U
l-
e::(
...J
t BIDFET - Bipolar, double-diffused, N-channel and P-channel MaS transistors on the same chip - patented process.
specifications per the terms of Texas Instruments TEXAS
~~~~~~~~i~a{~~I~tJ~ ~!~~~~ti~r :1~o::~:~~t:ros~S not INSTRUMENTS
3-177
TL58121, TL5812
logic symbol t
CMOSIVAC
FLUOR OISP
(13)
BLANKING
(16)
LATCH
ENABLE
(15)
II
CLOCK
(27) (26)
DATA IN 01
(25)
02
c
Ci)'
'C (17)
20 I> 3 010
iii" (12)
-< 20 I> 3 011
...C
<' 20 I> 3
(4)
019
...en
CD 20 I> 3
(3)
(2)
020
SERIAL
OUT
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
BLANKING-------<J
LATCH E N A B L E - - - - - - - - - - ,
SHIFT
REGISTER LATCHES
DATA I N - - - - I
CLOCK-.....- i >
3-178
TEXAS
INSTRUMENTS
TL58121, TL5812
FUNCTION TABLE

CLOCK R1 THRU R20 LC1 THRU LC20 SERIAL Q1 THRU Q20
ENABLE ING
LOAD
Not X X No change Latch Enable R20 Blanking
LATCH
X H X As determined above New data R20 Blanking
BLANK
X
X
X
X
H
L
As determined above
As determined above

Determined by
Latch Enable
R20
R20
All L
LC1 thru LC20, respectively
t R20 takes on the state of R 19, R 19 takes on the state of R18, ... R2 takes on the state of R1, and R 1 takes on the state of the data i~put.
II ...tn
Q)
New data enter the latches while Latch Enable is high. These data are stored while Latch Enable is low.
>
"i:
typical operating sequence C
>
CO
CLOCK
C.
tn
C
SR
CONTENTS
INVALID I VALID
LATCH
ENABLE
______________________________ ~rl ______
LATCH
PREVIOUSL Y STORED DATA NEW DATA VALID
CONTENTS
BLANKING
Q OUTPUTS
VCC1---------e~----~~---- - - - - - -....- - - - VCC2 - - - - - . - - 4 1 1 - e - VCC1
INPUT--~~~_4~. OUTPUT 9---~-OUTPUT
--------~~-------GND
GND--~------------~~---- ----------~~---- GND
TEXAS 3-179
, INSTRUMENTS
TL58121, TL5812
absolute maximum ratings over free-air operating temperature range (unless otherwise noted)
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Supply voltage, VBB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 70 V
Output voltage, Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '. . . .. 70 V
Input voltage, VI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to VDD +0.3 V
Output current, 10 ..................... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 40 mA
Continuous total power dissipation at (or below) 25C free-air temperature (see Note 2):
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11 50 mW
II
C
FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1400 mW
Operating free-air temperature range:
TL58121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C
TL5812 ..................... ,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OOC to 70C
iii"
"'C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260C
Q)
'< NOTES 1, All voltage values are with respect to VSS.
2. For operation above 25C freeair temperature, derate the N package linearly to 598 mW at 85C or to 736 mW at 70C
...
C at the rate of 9,2 mW/oC. Derate the FN package to 728 mW at 85C or to 896 mW at 70C at the rate of 11.2 mW/oC .
...<"
CD
t/)
MIN NOM MAX UNIT
Supply voltage, VOO 4.5 15 V
Supply voltage, VBB 0 60 V
Supply voltage, VSS 0 V
High-level input voltage, VIH VOO-1.5 VOO+0.3 V
Low-level input voltage, VIL -0.3' 0.8 V

I TL58121 -40 85
C
I TL5812 0 70
voltage levels.
electrical characteristics over operating free-air temperature range, VOO == 5 V to 15 V, VBB -= 60 V

PARAMETER TEST CONDITIONS MIN Tvpt MAX UNIT
Q outputs IOH = .:..25 mA 57.5 58.2
VOH High-level output voltage VOO - 5 V, IOH - 20 p.A 4.5 4.9 V
Serial outputs
VOO = 15 V, IOH = -20 p.A 14.5 14.9
Q outputs IOL = 1 mA, Blanking at VDO 0.7 1.5
VOL Low-level output voltage VOO = 5 V, IOL = 20p.A 0.06 0.3 V
Serial outputs
VOO = 15 V, IOL - 20 p.A 0.03 0.3
IIH High-level input current VI = VOO 0.3 1 p.A
IlL Low-level input current VI = 0 -0.3 -1 p.A
IOL Low-level output current (pull down current) Vo = 60 V, Blanking at VOO 2.5 3.2 mA
IO(oft) Off-state output current Vo = 0, Blanking at VOD < -1 -15 p.A
Outputs high 3.5 8
IBB Supply current from VBB mA
Outputs low 0.02 0.5
VOO = 5 V 1.5 3
100 Supply current from VOO mA
VOO = 15 V 1.7 4
t All typical characteristics are at T A = 25C.
3-180 TEXAS ~
INSTRUMENlS
TL58121, TL5812
timing requirements over operating free-air temperature range

PARAMETER MIN MAX UNIT
VOO = 5 V 500
twCKH Pulse duration, clock high ns
VOO = 15 V 100
VOO = 5 V 500
twLEH Pulse duration, latch enable high ns
VOO = 15 V 100
VOO = 5 V 150
tsuo Setup time, data before clockt ns
VOO = 15 V 75
thO
tCKH-LEH
Hold time, data after clockt
Delay time, clockt to latch enable high

VOO
VOO
VOO
VOO
=
=
=
=
5 V
15 V
5 V
15 V
150
150
75
75
ns
ns
II
... tI)
OJ
switching characteristics, VBB 60 V, TA :>
'a::::
C
PARAMETER I MIN TYP MAX UNIT
Propagation delay time, I Voo = 5 V I .2.2
co
>
tpd JlS
latch enable to output I VOO = 15 V
I 0.8 Q.
tI)
is
CLOCK
I
I
j4---tsUO~thO--.l
I I
-----,. I I VIH
DATA _ _ _ .....1'1\0% -x'"~_0_% _ _ _ _ _. VIL
FIGURE 1. INPUT TIMING
CLOCK
I
I
I+tCKH-LEH+!
I+-twLEH -+I
I
~reH
ENABLE _ _ _ _ _ _-'
A I
I 50%
I+-- tpd-----+lI
I 0
"'50__Yo_ _ _ __
OUTPUT
FIGURE 2. OUTPUT SWITCHING TIMES
TEXAS 3-181
INSTRUMENTS
TL58121. TL5812
THERMAL INFORMATION
DUTY CYCLE
vs
100~~~~~~~~~~--~--~~
90~~~~~~~~~~~+-~~~
II
c(ii"
'#.
~
I
CD
(j
80~~~~~~~~~~~~~~~
70~~~~~~~~~~~~~~~
60~~~~~~~~~~~~~r-~
> 12
"C 5 50 ~~---t----+-~...,p."""""~""""'~13
C
Dr E 40
14
-< ::J
15
16
E 18
...C oj( 30 N - Number of outputs high and _ N - 20
<" ::\E conducting IOH - - 25 mA
...
CD
en
20 All other outputs low. IOL - 1 mA....,....-+----i
10 VBB - 60 V
Vee - 15 V
O~~~~--~--~--~--~--~~
20 30 40 50 60 70 80 90 100
TA-Free-Air Temperature- C
FIGURE 3
3-182 TEXAS
INSTRUMENTS
UCN4810A
VACUUM FLUORESCENT DISPLAY DRIVER
D2676. OCTOBER 1982-REVISED NOVEMBER 1986
Each Device Drives 10 lines N

DUAL-IN-lINE PACKAGE
60-V Output Voltage Rating (TOP VIEW)
40-mA Output Source Current 08 09

06 SERIAL DATA OUT
CMOS-Compatible Inputs CLOCK VBB
Latches on All Driver Outputs VSS DATA IN

Sprague UCN4810A
description
VDD
LATCH ENABLE (STROBE)
05
04
BLANKING
01
02
03
II
...
U)
Q)
The UCN481 OA is a monolithic BIOFETt integrated circuit designed to drive a dot matrix or segmented >
"i:
vacuum fluorescent display (VFO). This device features a serial data output to cascade additional devices C
for large display arrays.
>
CO
A 1O-bit data word is serially loaded into the shift register on the positive-going transitions of the clock.
C.
Parallel data is transferred to the output buffers through a 10-bit Ootype latch while the latch enable input U)
is high and will be latched when the latch enable is low. When the blanking input is high, all outputs are low. is
Outputs are totem-pole structures formed by n-p-n emitter-follower and double-diffused MOS (OMOS)
transistors with output voltage ratings of 60 volts, and 40 milliamperes source-current capability. All
inputs are compatible with CMOS and TTL levels, but each requires the addition of a pull-up resistor to
VOO when driven by TTL logic.
The UCN4810A is characterized for operation from OOC to 70C.
logic symbol* logic diagram (positive logic)

BLANKING
CMOS/
VAC LATCH - - - - - - - - ,
LATCH ENABLE m ENABLE SHIFT
BLANKING (13)
REGISTER
DATA IN
CLOCK
(12)
10 3 01
(11)
20 [> 3 02
(10)
20[> 3 OJ
(9)
20 [> 3 04
(8)
20 [> 3 05
(3)
20 [> 3 06
(2)
20 [> 3 07
(1)
20 [> 3 08
(18)
20 [> 3 Q9
(17)
20 [> 3 010
(16)
SERIAL DATA OUT
t BIDFET - Bipolar Double-Diffused. N-Channel and P-Channel MOS transistors on same chip - patented process.
~This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
current 8S of publication date. Products conform to
~~~~~:~~i~ai~:I~~'; ~!~~~~tigr fI~o~:~:~:t:r~~s not INSTRUMENTS
UCN4810A
FUNCTION TABLE
CLOCK R1 THRU R10' LC1 THRU LC10 t SERIAL 01 THRU 010
ENABLE ING
1 X X Load and shift* Determined by Latch Enable t Rl0* Determined by Blanking
LOAD
No 1 X X No change Determined by Latch Enable t Rl0 Determin'ed by Blanking
X L X As determined above Stored data Rl0 Determined by Blanking
LATCH
X H X As determined above New data Rl0 Determined by Blanking
II
c
(j)'
BLANK
X
X
X
X
H
L
As determined above
As determined above
Determined by Latch Enable T
Determined by Latch Enable t
H = high level. L = low level. X = irrelevant. 1 = low-to-high-Ievel transition.

t New data enter the latches while Latch Enable is high. These data are stored while Latch Enable is low.
Rl0
Rl0
All L
LC 1 thru LC 1 2 respectively
* R10 takes on the state of R9. R9 takes on the state of R8 ... R2 takes on the state of R1. and Rl takes on the state of the data input.
"C
D) typical operating sequence
-<
...C
<' CLOCK
...
CD
en
LATCH r-l
ENABLE ------------------------------------~ ~-------------------------
CONTENTS
LATCH ____________________________________
PREVIOUSLY STORED DATA ~ ________________________
NEW DATA VALID ___
BLANKING
'Q OUTPUTS VALID

EOUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS
VDD - - - -__~----------------~_e---- -------~----------VBB
INPUT ---4IJ----4I--__- -. . . - - - - - - - - - OUTPUT
100
kfl
VSS----------~--4.-------~~__~--
VSS
3-184 TEXAS . "

INSTRUMENTS
UCN4810A
Logic supply voltage, VDD (see Note 1) ......................................... 18 V
Driver supply voltage, VBB ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 60 V
Output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 60 V
Input voltage ............................................... -0.3 V to VDD+0.3 V
Continuous output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 40 mA
Continuous total dissipation at 25C free-air temperature (see Note 2) . . . . . . . . . . . . . .. 1150 mW
Operating free-air temperature range ............ ,' ........................ , OOC to 70C
NOTES:
1. Voltage values are with respect to VSS.

II fA
a...
Q)
'i:
>
C
MIN NOM MAX UNIT > CO
Supply voltage, VOO 4.75 15.75 V
Supply voltage, VBB 5 60 V C. fA
Supply voltage, VSS 0 V
C
I for VDD = 5 V 3.5 5.3
V
I for VDD = 15 V 13.5 15.3
low-level input voltage, VIL. -0.3 t 0.8 V
Continuous high-level output current, IOH -25 mA
Operating free-air temperature, T A 0 70 C
voltage levels only.
electrical characteristics, VOO 4.75 V to 15.75 V, VSS 60 V, VSS 0, TA 25C (unless

otherwise noted)
VOH High-level output voltage IOH = -25 mA 57.5 V
VOL Low-level output voltage IOL = 1 p.A, Blanking input at VDD 1 V
Low-level output current
IOL Vo = 60 V, Blanking input at VDD 0.4 0.85 mA
(pull-down current)
Vo = 60 V, VSS = 0 V,
IO(oft) Off-state output current 15 p.A
All other terminals open, TA = 70C
VDD = 5 V, VI = 5 V 0.1
IIH High-level input current mA
VDD = 15V, VI = 15 V 0.3
q Input resistance VDD = 5 V 50 kO
VDD = 5 V 20
ro Output resistance kO
VDD = 15 V 6
All outputs high 13
IBB Supply current from VBB mA
All outputs low 1.3
All inputs at 0 V, VDD = 5 V 1
One output high VOO = 15 V 3
IDO Supply current from VOO mA
All inputs at 0 V, VOO = 5 V 0.1
All outputs low VOO = 15 V 0.2
TEXAS . . 3-185
INSTRUMENlS
UCN4810A
timing requirements for VOO = 5 V and VOO == 15 V, TA == oDe to 70 De

Voo - 5 V Voo -15 V
PARAMETER UNIT
MIN MAX MIN MAX
Pulse duration, clock high, tw(CKH) 1000 250 ns
Pulse duration, latch enable high, tw(LEH) 500 300 ns
Setup time, data before clock i. tsu(D) 250 150 ns
Hold time, data after clock i. th(D) 250 150 ns
Delay time. clock i to latch enable high. tCKH-LEH 1000 400 ns
lEI
C
switching characteristics, VOO = 5 V or 15 V, TA
PARAMETER
Propagation delay time. latch enable to output
MIN TYP MAX UNIT
p's
Ci)'
'C
or
-< PARAMETER MEASUREMENT INFORMATION
...c 14- tw(CKH)-+t
<' I I
u---
...en
CD
CLOCK
1 VIH CLOCK
INPUT
I
'----.....JI I 14 ~I tw(LEH)
11'III"'r--.~t-1-th(D)
1+- tCKH-LEH ~ 1
tSU(O)-;':4'--~~1 I ureH
ENABLE _ _ _ _ _ _ _1-
I 1
,'--__ _
I
NV\JW ~VIH
M/\I\I I4-tpd--+l
OATA\I\M1\ VALID
OUTPUT _ _ _ _ _ _ _ _ _ _ _-"_ ,I_-_\...
VALID
'------ _~.._......K._ VIL
FIGURE 1. INPUT TIMING FIGURE 2. OUTPUT SWITCHING TIMES
THERMAL INFORMATION
DUTY CYCLE
vs
, r-..... i'--.r-.... ,
100 ........... ....... ~ ~-6
........... ............ ~ ~
90
7
80 r......... .......
...........
70 ,
:---... ................. ......... 89-
::R
D
I
Gl
1i
60
50
1" 10-
>
u
~ 40
~
Q N = Number'of outputs conducting
30 simultaneously r--
10 .. 25 mA
20 r--
VSS == 60 V
10 VOO'" 15 V r--
o
25 30 35 40 45 50 55 60 65 70 75
TA-free-Air Temperature- DC
3-186
INSTRUMENTS
TEXAS l!1
__e_n_er_a_I_,ln_f_o_r_m_8_t_io_n______~~~1IIII
___G
Alphanum!i!ric Index
Selection Guide
, '
',Data Acqui'sition 'Circuits"

Data Sheets
Data Sheets
___L_in_e_D_r_iv_e_r_S_8_n_d_R_e_c_e_iv_e_r_s_ _ __
Data ,Sheets
... P;ri~h;..aID~j~~~/ActJat()rs ..
Data Sheets
Data Sheets
Data Sheets
r-
:i'
(1)
c..,
<"
..,
(1)
til
i
(1)
(')
(1)
<"
..,
(1)
til
4-2
(manufacturers !lrranged alphabetically)
Replacements were based on similarity of electrical and mechanical characteristics as shown in currently published
data. Interchangeability in particular applications is not guaranteed. Before using a device as a substitute, the
user should compare the specifications of the substitute device with the specifications of the original.
I
Texas Instruments makes no warranty as to the information furnished and buyer assumes all risk in the use
thereof. No liability is assumed for damages resulting from the use of the information contained in this list.
SUGGESTED PAGE SUGGESTED PAGE

AMD FAIRCHILD
TI REPLACEMENT NO. TI REPLACEMENT NO.
AM26LS31C AM26LS31C 4-5 I'A9637AC uA9637AC 4-529
AM26LS32C AM26LS32AC 4-13 I'A9637AM uA9637AM 4-529
AM26LS33C AM26LS33AC 4-13 I'A9638C uA9638C 4-535
AM26S10C AM26S10C 4-23 I'A9639AC uA9639C 4-539
AM26S10M AM26S10M 4-23 I'A9640C AM26S10C 4-23
AM26S11C AM26S11C 4-23 I'A9640M AM26S10M 4-23
AM26S11M AM26S11M 4-23 I'A9641C AM26S11C 4-23
FAIRCHILD
SUGGESTED PAGE
I'A9641M AM26S11M 4-23
...en
Q)
TI REPLACEMENT NO. SUGGESTED PAGE :>
MOTOROLA
I'A1488C SN75188 4-391 TI REPLACEMENT NO. 'Q)
I'A1489AC SN75189A 4-397 AM26LS31 AM26LS31C 4-5 CJ
Q)
-...
I'A1489C SN75189 4-397 AM26,LS32 AM26LS32AC 4-13
I'A26LS31C AM26LS31C 4-5 MC1488 SN75188 4-391 a:
I'A26LS32C AM26LS32AC 4-13 MC1489 SN75189 4-397 en
I'A3486C MC3486 4-47 MC1489A SN75189A 4-397 Q)
I'A3487C MC3487 4-53 MC26S10 AM26S10C 4-23 :>
I'A55107AM SN55107A 4-73 MC26S11 AM26S11C 4-23 'i:
I'A551078M SN551078 4-73 MC3446A MC3446 4-31 C
I'A55108AM SN55108A 4-73 MC3450 MC3450 4-35 Q)
I'A55108M . SN55108B 4-73 MC3452 MC3452 4-35 t:
I'A55110M SN55110A 4-89 MC3453 MC3453 4-43 :.:i
I'A55121M SN55121 4-143 MC3481 SN75ALS126 4-43
I'A55122M SN55122 4-147 MC3485 SN75ALS130 4-43
I'A75107AC SN75107A 4-73 MC3486 MC3486 4-47
I'A75108AC SN75108A 4-73 MC3487 MC3487 4-53
I'A751088C SN75108B 4-73 MC55107 SN55107A 4-73
I'A75108C SN75107B 4-73 MC55108 SN55108A4-73
I'A75110C SN75110A 4-89 MC75107 SN75107A 4-73
I'A75150C SN75150 4-205 MC75108 SN75108A 4-73
I'A75154C SN75154 4-237 MC75125 SN75125 4-163
I'A8T13C SN75121 4-143 MC75127 SN75127 4-163
I'A8T13M SN55121 4-143 MC75128 SN75128 4-169
I'A8T14C SN75122 4-147 MC75129 SN75129 4-169
I'A8T14M SN55122 4-147 MC75140 SN75140 4-191
I'A8T23C SN75123 4-153 MC75S110 SN75110A 4-89
I'A8T24C SN75124 4-157 SN75172 SN75172 4-319
I'A9614C SN75114 4-113 SN75173 SN75173 4-327
I'A9614M SN55114 4-113 SN75174 SN75174 4-335
I'A9615C SN75115 4-121 SN75175 SN75175 4-343
I'A9615M SN55115 4-121 SN75176 SN75176B 4-351
I'A96172C SN75172 4-319 SN75177 SN75177B 4-361
I'A96173C SN75173 4-327 SN75178 SN75178B 4-361
I'A96174C SN75174 4-335
I'A96175C SN75175 4-343
I'A96176 SN751768 4-351
I'A96177 SN751778 4-361
I'A96178 SN75178B 4-361
I'A9636AC uA9636AC 4-523
TEXAS ~ 4-3
INSTRUMENlS
SUGGESTED PAGE SUGGESTED PAGE

NATIONAL SIGNETICS
TI REPLACEMENT NO. TI REPLACEMENT NO.
051488 5N75188 4-391 8T125 5N75125 4-163
051489 5N75189 4-397 8T126 5N75AL5126 4-163
051489A 5N75189A 4-397 8T127 5N75127 4-163
0526L531 AM26L531C 4-5 8T128 5N751284-169
0526L532 AM26L532AC 4-13 8T129 5N75129 4-169
0526L532M AM26L532AM 4-13 8T13 5N75121 4-143
0526L533C AM26L533AC 4-13 8T14 5N75122 4-147
0526L533M AM26L533AM 4-13 8T23 5N75123 4-153
0526510C AM26510C 4-23 8T24 5N75124 4-157
0526510M AM26A10M 4-23 8T26 N8T26 4-57
0526511C AM26511C 4-23 OM7820 5N55182 4-377
0526511M AM26511M 4-23 OM7830 5N55183 4-385
053486 MC3486 4-47 OM8820 5N75182 4-377
053487 MC3487 4-53 OM8830 ,5N75183 4-385
0555107 5N55107B 4-73 MC1488 5N75188 4-391
0555108 5N55108 4-73 MC1489 5N75189 4-397
0555109 5N55109A 4-89 MC1489A 5N75189A 4-397
0555110 5N55110A 4-89
0555113 5N55113 4-101
r- 0555114 5N55114 4-113
5" 0555115 5N55115 4-121
CD
...2"
0555121 5N55121 4-143
C 0555122 5N55122 4-147
0575107 5N75107B 4-73
. 0575108 5N75108B 4-73
-
CD
0575109 5N75109A 4-89
f/j
0575110 5N75110A 4-89
:0 0575113 5N75113 4-101
CD 0575114 5N75114 4-113
C1
CD 0575115 5N75115 4-121
.<"
CD
f/j
0575121
0575122
0575123
0575124
5N75121
5N75122
5N75123
5N75124
4-143
4-147
4-153
4-157
0575125 5N75125 4-163
0575127 5N75127 4-163
0575128 5N75128 4-169
0575129 5N75129 4-169
0575150 5N75150 4-205
0575154 5N75154 4-237
0575207 5N75207B 4-405
0575207 5N75207 4-405
0575208 5N75208 4-405
0575208 5N75208B 4-405
0575108 5N75108B 4-73
057820A 5N55182 4-377
0578220 5N55182 4-377
057830 5N55183 4-385
058820 5N75182 4-377
058820A 5N75182 4-377
058830 5N75183 4-385
4-4 TEXAS ~
INSTRUMENTS
AM26LS31M, AM26LS31C
QUAD.RUPLE DIFFERENTIAL LINE DRIVERS
02433. JANUARY 1979-REVISED OCTOBER 1986
Meets EIA Standard RS-422-A AM26LS31 M .. J PACKAGE

AM26LS31C ... D. J. OR N PACKAGE
Operates from a Single 5-V Supply ITOP VIEW)
TTL Compatible 1A VCC
Complementary Outputs 1Y 4A
1Z 4Y
High Output Impedance in Power-Off ENABLE G 4Z
Conditions 2Z ENABLE G
Complementary Output Enable Inputs 2Y 3Z
2A 3Y
description GND 3A
The AM26LS31 M and AM26LS31 e are AM26LS31M ... FK PACKAGE
quadruple complementary-output line drivers (TOP VIEW)
designed to meet the requirements of EIA
U
Standard RS-422-A and Federal Standard 1020. >- <l: U U <l:
........ Z>o:t
The three-state outputs have high-current
capability for driving balanced lines such as
twisted-pair or parallel-wire transmission lines,
and they provide a high-impedance state in the
1Z 4
3 2 1 2019
18 4Y
. en
Q)
>
ENABLE G 5 17 4Z
power-off condition. The enable function is NC 6 16 NC "Qi
CJ
-.
common to all four drivers and offers the choice 2Z 7 15 ENABLE G Q)
of an active-high or active-low enable input. 2Y 8 14 3Z a:
Low-power Schottky circuitry reduces power 9 1011 1213
en
Q)
consumption without sacrificing speed.
<l:OU<l:>- >
The AM26LS31 M is characterized for operation
NZZMM
t::l
".::
C
over the full military temperature range of
NC-No internal connection Q)
-55e to 125e. The AM26LS31e is c::
characterized for operation from ooe to 70 oe. :::i
FUNCTION TABLE (EACH DRIVER)
logic symbol t INPUT ENABLES OUTPUTS

A G G Y Z
;;:1 H H X H L
G (4) EN
L H X L H
H X L H L
G
L X L L H
X L H Z Z
1Y
1Z H = high level
L = low level
2Y X = irrelevant
2A
2Z
Z = high impedance (off)
3Y
3A
3Z
4Y
4A
4Z
t This symbol is in accordance with ANSIIIEEE Std 911984 and

lEG Publication 617-12.
Pin numbers shown are for D. J, and N packages.
:~~~~:~~i~8{::I~'l~ ~!=~~~ti:i :I~o::~:~:t::'s~s not INSTRUMENTS
AM26LS31 M. AM26LS31 C
QUADRUPLE DIFFERENTIAL LINE DRIVERS
Pin numbers shown are for D. J. and N packages.
schematic (each driver)

INPUT A
90
90
OUTPUT Y OUTPUT Z
ENABLE
G
t---1:r--l--41-} E~~~E
EN~BLE --t--...;fIf-<II-W--t-----t---...J I
I
I
I
L _ _ _ _ _ _ _ _ _ ._ _ _ _ _ _ _ _ _ _ _ _ _ -.JI
4-6 TEXAS
INSTRUMENTS
AM26LS31M AM26LS31C UNIT
Supply voltage, VCC (see Note 1) 7 7 V
Input voltage 7 7 V
Output off-state voltage 5.5 5.5 V
D package 950
Continuous total dissipation at (or below) 25C free-air temperature FK package 1375
mW
(see Note 2) J package 1375 1025
N package 1150
Operating free-air temperature range -55 to 125 o to 70 C
Storage temperature range -65 to 150 -65 to 150 C
Case temperature for 60 seconds: FK package 260 C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package 300 300 C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package 260 C
NOTES: 1. All voltage values, except differential output voltage VOD, are with respect to network ground terminal.
2. For operation above 25C free-air temperature, refer to the Dissipation Derating Curves in Appendix A. In the J package,
AM26LS31 M chips are alloy mounted and AM26LS31 C chips are glass mounted. In the N package, use the 9.2mW/ C curve
for these devices.
III
... t/)
Q)

>
03
(J
AM26LS31M AM26LS31C Q)
Supply voltage, VCC

MIN
4.5
2
NOM
5
MAX
5.5
MIN
4.75
2
NOM
5
MAX
5.5
UNIT
V
V
-c:...
t /)
Q)

>
.i:
High-level output current, 10H -20 -20 mA C
Low-level output current, 10L 20 20 mA Q)
Operating free-air temperature, T A - 55 125 0 70 C
c:
:::i
TEXAS
INSTRUMENTS
-1!1 4-7
AM26LS31 M. AM26LS31 C
QUADRUPLE DIFFERENTIAL' LINE DRIVERS
electrical charcteristics over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP* MAX UNIT
VIK Input clamp voltage Vee = MIN, II = -18 rnA -1.5 V
VOH High-level output voltage Vec = MIN, 10H = -20 rnA 2.5 V
VOL Low-level output voltage VCC = MIN, IOL = 20 rnA 0.5 V
10Z Off-state (high-impedance-state) output current Vce = MAX I Vo - 0.5 V -20

p.A
I Vo = 2.5 V 20
II Input current at maximum input voltage VCC = MAX, VI = 7 V 0.1 rnA
IIH High-level input current Vec = MAX, VI = 2.7 V 20 p.A
IlL Low-level input current Vee - MAX, VI - 0.4 V -0.36 rnA
lOS Short-circuit output current Vec = MAX -30 -150 rnA

lee Supply current (both drivers) Vee = MAX, All outputs disabled 32 80 rnA
III
r-
*All typical values are at Vec = 5 V and T A = 25C.
Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
switching characteristics, Vee == 5 V, T A -= 25C

5' PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1)
...c tpLH
Propagation delay time,
low-to-high-Ievel output
14 20 ns
<' Propagation delay time, CL = 30 pF, See Figure 1, S 1 and S2 open

...
-
(1) 14 20 ns
tpHL
CI)
high-to-Iow-Ievel output
Output-to-output skew 1 6 ns
~
(1) tpZH Output enable time to high level CL = 30 pF, RL = 750, See Figure 1 25 40 ns
n tpZL Output enable time to low level CL = 30 pF, RL = 1800, See Figure 1 37 45 ns
(1)
<' tpHZ Output disable time from high level

CL=10pF, See Figure 1, S 1 and S2 closed
21 30 ns
...
(1)
CI)
tpLZ Output disable time from low level 23 35 ns
4-8
INPUTAYI
1.3V 1.3~ - - - - 3V
. I 0 v
(See Note BI I ~I 114 ~I tpHL
j4--tPLH--'"
I l:-i- - VOH
OUTPUT Y I / . I ~1.5 V
1
Skew-.!
1
!+"
1
I
~VOL
Skew ~
tpHL 14 .1 I4-tPLH-+t
OUTPUT Z .~V________
'J~~ ~_VVOOLH
- J/ ' "
-
.,. ..
PROPAGATION DELAY TIMES AND SKEW
ENABLEG~ ...
1.5 ~~
r------- (See Note CI 1.5 V
3V
U)
ENABLEG--J I . -+~------OV Q)
j.--tPZL---+I tPLZ-k---+l :>
I I I S1 CLOSED 'Q)
(,)
WAVEFORM--1---li-S-1-C-L-O-S-E-D"""'\.':-I----""4.5V I I S2 CLOSED
y __ 1:
(See Note 01 1 S2 OPEN
1
t+--tPZH~
1.5 V
I
I
tpHZ
1
14
-,,&---VOL
.1 0.5 V LO.5 V
~_----VOH
""1.5 V
--
a:
Q)
U)
Q)
:>
'i:
WAVEFORM 2 S1 OPEN =! ""1.5 V C
--------
(See Note 01 S2 CLOSED S1 CLOSED
S2 CLOSED Q)
s::::::
ENABLE AND DISABLE TIMES ::i
VOLTAGE WAVEFORMS
FROM OUTPUT _ _....-4>--......

TEST
POINT
-<)"'S~1
J VCC
180 n
UNDER TEST
CL
75 n
52
(See Note E l l
TEST CIRCUIT
NOTES: A. All input pulses are supplied by generators having the following characteristics: PRR s 1 MHz, Zout "" 50 n, tr S 15 ns,
and tf S 6 ns.
B. When measuring propagation delay times and skew, switches S1 and S2 are open.
C. Each enable is tested separately.
D. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
E. CL includes probe and jig capacitance.
TEXAS ~ 4-9
INSTRUMENTS
TYPICAL CHARACTERISTICSt
OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
ENABLE G INPUT VOLTAGE ENABLE G INPUT VOLTAGE
4 4
T~
I
Vee - 5.5 V - 125 0 e
Vee'" 5 V
> 3 > 3 TA ... 55e-
TA ... 25e ....... ~
I I
CI)
Cl
Vee" 4.5 V CI)
Cl
!9 !9
'0 '0
>
~:::l 2
.. 2
:::l
C.
:i So
:::l
o o
I I
o I- Load - 470 n o
> > 1 t- Vee" 5 V
r- to Ground Load .. 470 n
5' See Note 3 to Ground
CD t-
I-TA .. 25 0 e See Note 3
...C o I I o I I
...<'
o 2 3 o 2 3
-
CD
en VI-Enable'G Input Voltage-V VI-Enable G Input Voltage-V
:l:J FIGURE 2 FIGURE 3
CD
n
CD OUTPUT VOLTAGE OUTPUT VOLTAGE
...en<'
CD vs
ENABLE G INPUT VOLTAGE
vs
ENABLE G INPUT VOLTAGE
6 6
Vee - 5.5 V Load .. 470 n to Vee Vee" 5 V
TA - 25e Load .. 1 kn to Vee
Vee - 5 V
5 See Note 4 5 See Note 4
Vee - 4.5 V
> TA - 125e
>
I
CI) 4
I
CI) 4 1
Cl
!9
Cl
!9
'0
I
'0 TA - 25e
..
>
:::l
3
> 3
:i
So
I
I ~
So
:::l :::l TA - -55e.....
0 0 r-..,
I 2 I 2
0 0 ....... ~
> >
o o
o 2 3 o 2 3
VI-Enable G input Voltage-V VI-Enable G Input Voltage-V
FIGURE 4 FIGURE 5
t Data for temperature below ooe and above 70 e are applicable to AM26LS31 M circuits only.
0
NOTES: 3. The A input is connected to Vee during the testing of the Y outputs and to ground during testing of the Z outputs.
4, The A input is connected to ground during the testing of the Y outputs and to Vee during the testing of the Z outputs.
4-10 TEXAS
INSTRUMENTS
AM26LS31 M, AM26LS31 C
TYPICAL CHARACTERISTICS t
HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE
vs vs
FREE-AIR TEMPERATURE OUTPUT CURRENT
5 4
-t--r-- ~VO~ .. IS 1
>
1
CD
4
>
1
CD -t-- t--.~c~
.. sv r--.
-
CI
-
CI
j9
'0
>
t--- rlOH .. -20 mA '0
>
j9
..
3
r-- r-- ~C
v .. 4.5 1:-r:F 1\
r----
:;
So
:J
0
Qj
3
--- ~r---::t:=
!---" IOH - -40 mA
0
Qj
:J
So
:J
>
2
-~r---
r--. ~
~
II
>
CD 2 CD
...I ...I
J: J:
CI CI
:f :f
1
::J:
0
1
::J:
0
... CI)
(1)
__ VCC - 5 V > ~ TA .. 25C
> >
See Note 3 Si e Nlte 3 . 'Q)
o 1 1 o 1 (.)
-75 -50 -25 0 25 50
TA - Free-Air .Temperature - C
FIGURE 6
75 100 125 o -20 -40
IOH-High-Level Output Current-mA
FIGURE 7
- 60 -80 -100
-...
a::
(1)
CI)
(1)
>
'i:
LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
C
(1)
vs vs r:::
FREE-AIR TEMPERATURE OUTPUT CURRENT ::;
0.5 1.0
I
> > 0.9 I- TA - 25C
See Note 4
I
1 1 I
II)
0.4 CD 0.8
/
CI
CI
j9 'I'-- r-- j9
'0
..
'0
>
:J 0.3
>..So
:J
0.7
0.6 ~
So
0
:J
0
:J
0.5
Vce - 4.5 V ~
Qj
> 0.2
Qj
>
CD 0.4 .........:: ~C-5.5V_
~
CD ...I
...I
~ ~
0 0.3
h
0 ...I ~
~
...I
1 1
0.1 t-VCC - 5 V ...I 0.2
~
...I
0 0
> IOL - 40 mA >
See Note 4 0.1
o I I o
-75 -50 -25 0 25 50 75 100 125 o 20 40 60 80 100 120
TA-Free-Air Temperature- C IOL -Low-Level Output Current-mA
, FIGURE 8 FIGURE 9
,t,Data for temperature below ooe and above 70 0 e are applicable to AM26LS31 M circuits only.
NOTES: 3. The A input is connected to Vee during the testing C?f the Y outputs and to ground during testing of the Z outputs.
4. The A input is connected to ground during the testing of the Y outputs and to Vee during the testing of the Z outputs.
TEXAS ~ 4-11
INSTRUMENTS
POST OFFICE BOX 65501 ~ , DALLAS, TEXAS 75265
y OUTPUT VOLTAGE y OUTPUT VOLTAGE

vs vs
DATA INPUT VOLTAGE DATA INPUT VOLTAGE
5 5
I
f- No LJad _ VCC - 5 V
4
TA - 25C vcb - 5.5 v 4
No Load
I 1
TA - 125C-
> f . VCC - 5 V > { I
I I
CD
Cl VCC - 4.5 V
CD
Cl ,r I
f! 3 f! 3 TA - -55C_
I
"0
> ..So
'0
>
:J
TA - 25C ....
f
r- >
o
2 :J
0
0
>
I
2
5'
CD
...c o
1 o
J J
<'CD o 2 3 o 2 3
...en
-
::a
CD
(')
CD
VI-Data Input Voltage-V
FIGURE 10
FIGURE 11
tO ata for temperature below OOC and above 70C are applicable to AM26LS31M circuits only.
<'
...
CD
en
4-12 TEXAS ~
INSTRUMENTS
AM26LS32AM, AM26LS33AM, AM26LS32AC, AM26LS33AC
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
02434, OCTOBER 19BO-REVISEO SEPTEMBER 1986
AM26LS32A Meets EIA Standards AM26LS32AM. AM26LS33AM ... J PACKAGE

AM26LS32AC. AM26LS33AC ... D. J, OR N PACKAGE
RS-422-A and RS-423-A
(TOP VIEW)
AM26LS32A has 7-V Common-Mode
Range with 200-mV Sensitivity 18 VCC
lA 48
AM26LS33A has 15-V Common-Mode 1Y 4A
Range with 500 mV Sensitivity G 4Y
Input Hysteresis ... 50 mV Typical 2Y G
2A 3Y
Operates from a Single 5-V Supply 28 3A
Low-Power Schottky Circuitry GND 38
3-State Outputs AM26LS32AM. AM26LS33AM . FK PACKAGE

Complementary Output Enable Inputs (TOP VIEW)

Input Impedance ... 12 kO Min
Advanced Micro Devices AM26LS32C and
<t:coUUco
.-.-z>q-
3
U
2 1 2019
II
...
(I)
1Y 4 18 4A Q)
AM26LS33C
G 5 17 4Y >
'Q)
description NC 6 16 NC (.)
The AM26LS32A and AM26LS33A are

quadruple line receivers for balanced .and
unbalanced digital data transmission. The enable
function is common to all four receivers and
2Y
2A 8
7
9 1011 1213
15
14 3Y
-...
a:
Q)
( I)
Q)
>
'i:
offers a choice of active-high or active-low input. C
Three-state outputs permit connection directly NC-No internal connection
Q)
to a bus-organized system. Fail-safe design t:
ensures that if the inputs are open, the outputs
::J
will always be high.
Compared to the AM26LS32C and the AM26LS33C, the AM26LS32A and AM26LS33A incorporate an
additional stage of amplification to improve sensitivity. The input impedance has been increased resulting
in less loading of the bus line. The additional stage has increased propagation delay; however, this will
not affect interchangeability in most applications.
The AM26LS32AM and the AM26LS33AM are characterized for operation over the full military temperature
range of - 55C to 125C. The AM26LS32AC and AM26LS33AC are characterized for operation from
OC to 70C.
FUNCTION TABLE(EACH RECEIVER)
DIFFERENTIAL ENABLES
OUTPUT
INPUT G G
H X H
VID ;;" VTH
X L H
H X ?
VTL s VID s VTH
X L ?
H X L
VID s VTL
X L L
X L H Z
H = high level. L = low level. X = irrelevant

Z = high impedance (off). ? = indeterminate
specifications per the terms of Texas Instruments . TEXAS. 4-13
~~~~~:~~i~at::I~~~ ~!:~:~ti:r :1~o::::~:t::s~S not INSTRUMENTS
1A (3) 1Y ">--+-....:.(.::.;.3) 1Y
1B
2A (5) 2Y
2B
3A (11) 3Y
3B
4A (13) (11) 3Y
4B (15) 4Y
III
r-
tThis symbol is in accordance with ANSI/lEEE Std 91-1984 and
Pin numbers shown are for D, J, and N packages.
(13) 4Y
5'
CD
..<'
C
..
CD EQUIVALENT OF EACH EQUIVALENT OF EACH ENABLE INPUT TYPICAL OF ALL OUTPUTS
-
en
:JJ
CD
(')
DIFFERENTIAL INPUT
VCC------~---4-- VCC----------~-----
B.3 kfl
CD NOM
<'CD
..
en 20 kfl
NOM
ENABLE-..........~
INPUT--IIJ"'--~':"':"-l-_
4-14 TEXAS
INSTRUMENTS
AM26LS32AM AM26LS32AC
UNIT
AM26LS33AM AM26LS33AC
Input voltage, any differential input 25 25 V
Differential input voltage (see Note 2) 25 25 V
D package 950
Continuous total dissipation at (or below) FK package 1375
mW
25C free-air temperaure (see Note 3) J package 1375 1025
N package 1150
Operating free-air temperature range -55t0125 o to 70 C
Lead temperature 1,6 mm(1/16 inch)

D or N package 260 C
Case temperature for 60 seconds FK package 260 C
Lead temperature 1,6 mm (1/16 inch)
J package 300 300 C
rJ)
a-
NOTES: 1. All voltage values, except differential voltages, are with respect to the network ground terminal. Q)
2. Differential voltage values are at the noninverting (A) input terminals with respect to the inverting (B) input terminals. >
3. For operation above 25C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the J package, 'Q)
(,)
AM26LS32AM and AM26LS33AM chips are alloy mounted and AM26LS32AC and AM26LS33AC chips are glass mounted.
Q)
In the N package, use the 9.2 mW/oC curve.

-a: r J)
a-
Q)
AM26LS32AM AM26LS32AC ''::

>
AM26LS33AM AM26LS33AC UNIT C
MIN NOM MAX MIN NOM MAX Q)
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V t:
High-level input voltage, VIH 2 2 V :.::l
Common-mode input voltage, VIC

I AM26LS32AM, AM26LS32AC 7 7
V
I AM26LS33AM, AM26LS33AC 15 15
High-level output current, 10H -440 -440 p.A
Low-level output current, IOL 8 8 mA
Operating free-air temperature, T A -55 125 0 70 c
TEXAS -II} 4-15

INSTRUMENTS
electrical characteristics over recommended ranges of Vee, VIC, and operating free-air temperature
Differential input AM26lS32A 0.2
VTH Vo = VOHmin, 10H = -440 p.A V
high-threshold voltage AM26lS33A 0.5
Differential input AM26lS32A -0.2~
VTL Vo = 0.45 V, 10l = 8 mA V
low-threshold voltage AM26lS33A -0.5~

Vhys Hysteresis, VT + - VT- 50 mV
VIK Enable input clamp voltage VCC - MIN, II - -18 mA -1.5 V

VCC = MIN, VID = 1 V, '32AM, '33AM 2.5
VOH V
VI('G) = 0.8 V, 10H = -440 p.A '32AC, '33AC 2.7
VCC = MIN, VID = -1 V, 10l = 4 mA 0.4
VI('G) = 0.8 V 10l - 8 mA 0.45
Off-state (high-impedance-state) Vo - 2.4 V 20
10Z VCC = MAX p.A
output current Vo = 0.4 V -20
VI = 15 V, Other input at -10 V to 15 V 1.2
...:5" II
II(EN)
Line input current
Enable input current

VI = .,.15 V,
VI = 5.5 V
Other input at - 15 V to 10 V -1.7
100
mA
p.A
c IIH High-level enable current VI = 2.7 V 20 p.A
...:;::-c III
q
low-level enable current
Input resistance
VI = 0.4 V
VIC = -15Vto15V, One input to AC ground 12 15
-0.36 mA
kfl
...c Short-circuit output current' Vec = MAX
-
lOS -15 -'85 mA
(I) ICC Supply current VCC = MAX, All outputs disabled 52 70 mA
.JJ
c(') t All typical values are at VCC = 5 V, TA = 25C, and VIC = O.
c * The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold
levels only.
:;;:- Hysteresis is the' difference between the positive-going input threshold voltage, VT +, and the negative-going input threshold voltage,
c... VT _. See Figures 10 and 11 .
(I)
, Not more than one output should be shorted at a time.
switching characteristics, Vee'" 5 V, TA - 25C

tplH Propagation delay time, low-to-high-Ievel output 20 35 ns
Propagation delay time, high-to-Iow-Ievel output
Cl = 15 pF, See Figure 1
22 35 ns
tPHl
tpZH Output enable time to high level 17 22 ns
tpZl Output enable time to low level
20 25 ns
tpHZ Output disable time from high level 21 30 ns
4-16 TEXAS
INSTRUMENTS
AM26LS32AM. AM26LS33AM. AM26LS32AC. AM26LS33AC
TEST
oV\-_-__
- - -+2.5 V
POINT
2 kO
INPUTJOV
I 2.5 V
tpLH -fo14t---~~1 ~I tpHL
l,3V '.3vtVOH
FROM OUTPUT _ _. -.........~............ 1111
UNDER TEST See Note B
CL OUTPUT
See Note A
_ _ _---J S1 and S2 closed VOL
'-----+-<~
VOLTAGE WAVEFORMS FOR tpLH. tpHL
II
TEST CIRCUIT
/+-:55 ns ~
ENABLE
G
ENABLE
G
... U)
Q)
~.;.;..;..;.....-oV >
"a;
(,)
1r:9~0~%~- 3 V Q)
ENABLE
G
1.3 V
- - -
0.5 V"}
-OV
ENABLE
G
-...
a:
U)
Q)
+-x:! :-VOH I S2 closed "i:

>
~""1.4V 14 ~""1.4V C
S1 open tpLZ
1.3V I
~-
S2 closed OUTPUT
OUTPUT
----- tPHZ~ S1 closed
S2 closed
S2 open
0.5 V
-~-VOL
::J
Q)
c:
VOLTAGE WAVEFORMS FOR tpHZ. tpZH VOLTAGE WAVEFORMS FOR tpLZ. tpZL
~OTES: A. CL includes probe and jig capacitance.

B. All diodes are 1N3064 or equivalent .
. C. Enable G is tested with G high; G is tested with Glow.
FIGURE 1
TEXAS
INSTRUMENTS
-1!1 4-17
HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE
vs vs
HIGH-LEVEL OUTPUT CURRENT FREE-AIR TEMPERATURE
5 5
.1 I ,I
VIO '" 0.2 V_
> TAD 25C >
I I
G)
Cl 4 G)
Cl 4
fl fl
'0 ~ '0
>....
::I
C. 3
~~ >
....::I
3
~~
:; c.
:;
0 0
Qj
> ~ ~ /VCC"I 5.25 V Qj
III
G) 2 I I > 2
~~
G)
.....I
.i:.Cl VCC" 5 V .....I
.i:.Cl
~~
J: VCC .. 4.75 V J:
I I r- VCC .. 5 V
r- :I:
S ~~
:I:
0 0 VID - 0.2 V
CD > > r-10H - -440 Jl-A
..,C o ~~ o I I I
<' o -10 -20 -30 -40 -50 o 10 20 30' 40 50 60 70 80
..,
CD
- IOH-High-Level Output Current-mA TA"-Free-Air Temperature- c

C/J
:0 FIGURE 2 FIGURE 3
CD
()
CD LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
<' vs vs
..,
CD
LOW-LEVEL OUTPUT CURRENT FREE-AIR TEMPERATURE
C/J
0.6 0.5
>
VCC - 5 V
TA .. 25 D C
/ >
G)
I 0.5 / I
Cl ,/ G)
Cl
0.4
fl
'0
>.... 0.4 / fl
'0
>
::I
C.
:;
0 0.3
/V :;
c.
:;
0
0.3
Qj
>
G)
/' Gi
> 0.2
.....I
~ 0.2 / CD
...I
~
0
.....I
I
V 0
.....I
I
.....I ...I 0.1 VCC" 5 V
0 0.1 0
> VID == -0.2 V
>
IOL == 8 mA
o 0 I I
o 5 10 15 20 25 30 o 10 20 30 40 50 60 70 80
IOL -Low-Level Output Current-mA T A - Free-Air Temperature - DC
FIGURE 4 FIGURE 5
4-18 TEXAS
INSTRUMENTS
-1!1
POST OFFicE BOX 655012 DALLAS, TEXAS 75265
vs vs
ENABLE G VOLTAGE ENABI-E G VOLTAGE
5 5
VID = 0.2 V Vee = 5 V
r-TA = 25e VID = 0.2 V I I
4 I--
Load = 8 kil V~e=5.~V 4
Load = 8 kll to ground
0
to ground Vee= 5 V > TA = 70 e / TA = 25e
>I 1
Q)
C>
Vee = 4.5 Y CI>
C> I
~ 3 !:! 3 TA = 0 e-
o "0
>.... >....
:::J :::J
a.
;3 2
e-
:::J 2
0
I I
o
> 0
>
...rn
Q)
>
'Q)
CJ
o o Q)
o 0.5 1.5
Enable G Voltage-V
FIGURE 6
2 2.5 3 o 0.5 1.5
Enable G Voltage - V
FIGURE 7
2 2.5 3
-...
a:
rn
Q)
';::
>
OUTPUT VO LTAG E OUTPUT VOLTAGE C
vs vs Q)
t:
ENABLE G VOLTAGE ENABLE G VOLTAGE
6 6 :.:J
Vee = 5.5 V I
1
VID = -0.2 V
.1 Vee l5
V
>I
5
Vee= 5 V
Vee= 4.5 V
TA=25e
Load = 1 kil to Vee
-
>
5
Lo,d f
VID = -0.2 V
1 kn to Vee
I
4
~ 4
CI>
~ TA=25e- ~
~ TA=O
I 0
e
(5
> g I I
5 3 .... 3
~ A = 70ole-t>
:::J
So
:::J
e-
:::J
o
o
I 2 ~ 2
> o
>
o o
o 0.5 1.5 2 2.5 3 o 0.5 1.5 2 2.5 3
Enable G Voltage-V Enable G Voltage - V
FIGURE 8 FIGURE 9
TEXAS ~ 4-19
INSTRUMENTS
AM26LS32A AM26LS33A
vs vs
DIFFERENTIAL INPUT VOLTAGE DIFFERENTIAL INPUT VOLTAGE
5 5
VCC= 5 V vbc= ~V 10 = 0 TA = 25C
10= 0
TA = 25C ~ I , I r
4 4 f - I-VIC = I--- I--VIC = f-f-VIC= t - - -
> ~IC:= ~IC= tvlC = > -15 V OV 15V
I 7V o V- f- 7V I
I~
Q> Q)
C'l
I I ~
C'l
~
"0
3
VT- VT+ ~T+ VT+- - "0
3
VT- ~ VT- VT- VT-
>.... VT
>....
II
::I ::I VT+ VT+ VT+
B- B-
::I 2 ::I 2
o 0
I I
r- o 0
> >
S
(1)
...c
<' o o
...
-
(1) -200 -150 -100 -50 0 50 100 150 200 -200 -150 -1 00 -50 0 50 100 150 200
t/)
VID - Differential Input Voltage - mV VID - Differential Input Voltage - mV
:0
(1) FIGURE 10 FIGURE 11
n
(1)
<' INPUT CURRENT

...
(1)
t/)
vs
INPUT VOLTAGE
21---+--l----f>,~~~~~_+____l-+-___1
E
I
....c
~
8 OI---+--l--~""~~~r.-.-..4--
....::I
g- -1
-4 ~~--~~~~~~~~~--~~
-25 -20 -15 -10 -5 0 5 10 15 20 25

VI - Input Voltage - V
FIGURE 12
4-20 TEXAS
INSTRUMENlS
TYPICAL APPLICATION
Y. AM26LS31 C Yo AM26LS32AC
DATA DATA
IN OUT
Yo AM26LS32AC Yo AM26LS33AC
DATA DATA
OUT OUT
*Rr equals the characteristic impedance of the line.
FIGURE 13. CIRCUIT WITH MULTIPLE RECEIVERS

II CJ)
a..
Q)
>
"cu
CJ
Q)
-
a:
CJ)
a..
Q)
>
".:
C
Q)
I:
:.:i
TEXAS . . 4-21
INSTRUMENTS
II
r-
5'
CD
...
C
<'
...en
CD
.~
CD
o
CD
<'
...
CD
en
4-22
AM26S10M, AM26S1 ~C, AM26S11 M, AM26S11 C
QUADRUPLE BUS TRANSCEIVERS
02298. JANUARY 1977 - REVISED SEPTEM8ER1986
Schottky Circuitry for High Speed, Typical AM26S10M. AM26S11M ... J PACKAGE
Propagation Delay Time . . . 12 ns AM26S 1 OC. AM26S 11 C ... D. J. OR N PACKAGE
(TOP VIEW)
Drivers Feature Open-Collector Outputs for
Party-line (Data Bus) Operation GNO Vee
1B 4B
Driver Outputs Can Sink 100 mA at 0.8 V 1R 4R
Maximum 10 40
P-N-P Inputs for Minimal Input Loading 20 S
2R 30
Designed to be Interchangeable with 2B 3R
Advanced Micro Devices AM26S 10 and GNO 3B
AM26S11
AM26S10M. AM26S11M ... FK PACKAGE
description
(TOP VIEW)
The AM26S 10 and AM26S 11 are quadruple bus
transceivers utilizing Schottky-diode-clamped
transistors for high speed. The drivers feature
open-collector outputs capable of sinking
o U
ccZUUcc
.... <.!)Z>'<t
3 2 1 20 19
II
...
(I)
100 mA at 0.8 V maximum. The driver and 4 18 Q)

5 17 >
strobe inputs use p-n-p transistors to reduce the 'Q)
input loading. 6 16 (.)
The driver of the AM26S 10 is inverting; the

driver of the AM26S 11 is non inverting. Each
device has two ground connections for improved
ground current-handling capability. For proper
7
8
9 1011 12 13
15
14
-...
a:
Q)
( I)
Q)
>
'i:
operation, the ground pins should be tied C
together. NC - No internal connection
Q)
c:
The AM26S 1OM and AM26S 11 M are characterized for operation over the full military temperature range :::i
of - 55C to 125C. The AM26S 1OC and AM26S 11 C are characterized for operation over the temperature
range of OOC to 70C.
AM26S10 AM26S11
(TRANSMITTING) (TRANSMITTING)
INPUTS OUTPUTS INPUTS OUTPUTS

S D B R S D B R
L H L H L H H L
L L H L L L L H
AM26S10 AND AM26S11

FUNCTION TABLE
(RECEIVING)
INPUTS OUTPUT
S B D R
H H X L
H L X H
H = high level. L = low level, X = Irrelevant
~
specifications per the terms of Texas Instruments TEXAS
~~~~~:~~i~a{~~I~~~ ~!~~~~ti:r :I~o::::~:t:~~s not 4-23
INSTRUMENTS
logic symbols t
AM26S10 AM26S11
1-"""_ _12_) 1 B
1-------=4
20
p................:.;17;.;.) 2B po.-.....--:.17;:..:.) 2 B
2R
3D
p...............:.;19:..:.) 3B 1-"""-..----:.19=) 3B
3R
(15) 4B (15) 4B
II
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
Pin numbers shown are for 0, J, and N packages.

r- AM26S10 AM26S11
:r
CD
c...
<' (2) 18 p----Hfoi-.........:.;12;;.;..) 1 B
... 14:..:.)_ _ _ _-+--f
10.:..
-
CD
en
1R~13:..:.)------4_----C
:CDn
o (7) 28 (7) 28
CD 20 ~15:..:.)-------4_--1
<'
...en
CD
2R~16~)--------4_----<
(9) 38 (9) 38
3D (11)
3R (10)
(15) 4B (15) 48
40 (13)
4R (14)
4-24 TEXAS
INSTRUMENlS
"'II
AM26S10M, AM26S1 DC, AM26S11 M, AM26S11 C
schematic (each transceiver)
B
:.,., V
2 kn I . 110 (}
NOM i ! NOM
i I
i
AM26S11i
'I
I .
I ! R
I !
,---+~~I
L. I
__I___ ~
I AM26S10
II
I
o I
I
I
~--~------~------~--~--~~----~-+~----~~~--~--~~~----GND
r------------ --------- --------, ...

~
Cl)
I V 2.7 kn I >
'Q)
I NOM I
I L ____ ~~ U
Cl)
I
TO THREE
OTHER
COMMON
CIRCUITRY I
I
-...
a::
~
Cl)
I DRIVERS TO ONE TO TWO I 'i:

>
C
I S ~:~~~ER ~:~:I~ERS . I Cl)
I I c:
I I ::J
I ___________________________________ I
L ~
TEXAS 4-25
INSTRUMENTS
Supply voltage, VCC (see Note 1) ...................................... - 0.5 V to 7 V
Driver or strobe input voltage .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.5 V to 5.5 V
Bus voltage, driver output off: AM26S10M, AMS26S11M '" ............... -0.5 V to 5.5 V
AM26S10C, AM26S11 C . . . . . . . . . . . . . . . . . .. -0.5 V to 5.25 V
Driver or strobe input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 30 mA to 5 mA
Driver output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 200 mA
Receiver output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30 mA
Continuous total dissipation at (or below) 25 DC free-air temperature (see Note 2):
D package ...........'.............................................. 950 mW
FK package .... ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1375 mW
J package (AM26S10M) ............................................ " 1375 mW
J package (AM26S10P ............................................ " 1025 mW
N package ........................................................ 11 50 mW
III
r-
Operating free-air temperature range: AM26S 10M, AM26S 11 M ............. - 55 DC to 125 DC
AM26S10C, AM26S11C .................. ODC to 70 DC
Storage temperature range ....................................... : '. - 65 DC to 150 DC
Case temperature for 60 seconds: FK package .............. '. . . . . . . . . . . . . . . . . . . .. 260 DC
:i' Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package. . . . . . . . . . . .. 300 DC
CD Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package. . . . . . . .. 260 DC
C
""l
NOTES: 1. All voltage values are with respect to network ground terminals connected together.
C' 2. For operation above 25C free-air temperature. see Dissipation Derating Curves in Appendix A. In the J package, AM26S 10M
CD
-
""l and AM26S 11 M chips are alloy mounted and AM26S 1OC and AM26S 11 e chips are glass mounted. For these devices in
en the N package, use the 9.2-mW/oe curve.
::JJ
CD
(') recommended operating conditions
CD
C' AM26S10M AM26S10C
CD AM26S11M AM26S11C UNIT
""l
en MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
Dor S 2 2
B 2.4 2.25
D orS 0.8 0.8
B 1.6 1.75
Receiver high-level output current, IOH -1 -1 mA
Driver 100 100
Low-level output current, IOL mA-
Receiver 20 20
4-26 TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 ' DAllAs. TEXAS 75265
AM26S,10M. AM26S10C. AM26S11M. AM26S11C
noted)
AM26S10M AM26S10C
PARAMETER TEST CONDITIONSt AM26S11M AM26S11C UNIT
Input clamp D or
VIK Vee = MIN, II = - 18 mA -1.2 -1.2 V
voltage S
High-level Vee = MIN, VIH = 2 V; VIL = VIL max,
VOH R 2.5 3.4 2.7 3.4 V
output voltage IOH = -1 mA
R IOL = 20 mA 0.5 0.5
Low-level - Vee = MIN,
IOL = 40 mA 0.33 0.5 0.33 0.5
VOL
output voltage B
VIH = VIHMIN, 0.42 0.7 0.42 0.7
V
IOL - 70 mA
VIL = 0.8 V 0.51 0.51
IOL - 100 mA 0.8 0.8
IVee = MAX, Vo = 0.8 V -50 -50
II
Off-state
IO(oft) B VIH = 2 V'I Vee = MAX, Vo = 4.5 V 200 100 p.A
output current VIL = 0.8 V
I Vee = 0, Vo = 4.5 V 100 100
High-level 0 30 30
= = p.A
IIH
input current ~ Vee MAX, VI 2.7 V
20 20
...rn
Input current Q)
o or >
II at maximum Vee = MAX, VI = 5.5 V 100 100 p.A
'Q)
S
input voltage (,)
-...
Low-level 0 -0.54 -0.54 Q)
IlL
input current S
Vee = MAX, VI = 0.4 V
-0.36 -0.36
mA a:
Short-circuit
rn
Q)
lOS output R Vee = MAX -20 -55 -18 -60 mA
>
current ''::::
I Supply AM26S10 Vee = MAX, Strobe at 0 V, No load, 45 70 45 70 C
lec mA
I current AM26S11 All driver outputs low 80 80 Q)
s:::
t For conditions shown as MIN or MAX, use the appropriate value shown under re~ommended operating conditions. ::i
t All typical values are at T A = 25e and Vee = 5 V.
Not more than one output should be shorted to ground at a time, and duration of the short circuit should not exceed one second.
switching characteristics, Vee = 5 V, TA = 25e

TEST AM26S10 AM26S11
PARAMETER FROM TO UNIT
CONDITIONS MIN TYP MAX MIN TYP MAX
tPLH Propagation delay time, low-to-high-Ievel output 10 15 12 19
D B ns
tpHL Propagation delay time, high-to-Iow-Ievel output 10 15 12 19
tpLH. Propagation delay time, low-to-high-Ievel output 14 18 15 20
S B ns
See Figure 1
tpLH Propagation delay time, low-to-high-Ievel output 10 15 10 15
B R ns
tTLH Transition time, low-to-high-Ievel output 4 10 4 10
B ns
tTHL Transition time, high-to-Iow-Ievel output 2 4 2 4
TEXAS 4-27
INSTRUMENTS
AM26S10M. AM26S1 ~C. AM26S11 M. AM26S11 C
Vee
I-----------------~I 500
AM26S11 r----------~I----~~------~
....--..-....,--- - -{>o-- -l 2800

I I RECEIVER
I
iL __ ._. _______________ ._____ J. (See Note e)
III
r-
50 pF
IS".O"BIJ IS"."'B'J
15 pF
S'
CD
...C o S B R
<' TEST CIRCUIT
...en
-
CD
:lJ
CD
(')
CD
<'
~~~;R] ___--,*r_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_- :.:V
AM26S11
...
CD
en I AM26S10 I 0 V
I I
SINTpRUOTBE _ _ ~I------rI-----..Jil
! i .' '"~----
- - - - -- 3 V
1.5V
i I 0 V
~ 14- tpLH -.j 14- tpHL --.j j4- tpLH ---t 14- tPHL
I 0 to B I D to B I S to B I S to B
BUS -1 \. ----..Jt
-+I j+- ~~~LR -+I 1+ tPLH -+\ I+-
tpHL ~ tpLH
\~~~ =~:~v
....j
I I B to R I B to R I B to R
~~~~~~R---~~~ ___ _..J)' ~'-___-L~:::

VOLTAGE WAVEFORMS
NOTES: A. The pulse generators have the following characteristics: Zout = 50 0, tr = 10 5 ns.
B. Includes probe and jig capacitance.
C. All diodes are 1 N916 or equivalent,
FIGURE 1
4-28 TEXAS
INSTRUMENTS
AM26S10M, AM26S1 DC, AM26S11 M, AM26S11 C
OUADRUPLE BUS TRANSCEIVERS
TYPICAL APPLICATION
STROBE STROBE STROBE

DRIVER DRIVER DRIVER
INPUTS ,RECEIVER INPUTS RECEIVER INPUTS RECEIVER
OUTPUTS ~ OUTPUTS OUTPUTS
1IIT
DODD
~ 1111
DODD
~
1IIT ~
SR SR DODD SR
5 V AM26S101 R- AM26S101 R- AM26S101 R- 5 V
AM26S11 R- AM26S11 R- AM26S11 R-
B B B B R- B B B B R_ B B B B R_
100 n
1 I 1 I 1 I 100 n
- -1
AAA
100 n
"" 1- 1 1000
100 n 1000 t/)

y a-
CD
100 n 1000 >
'0)
100-n TRANSMISSION LINE U
FIGURE 2. PARTY-LINE SYSTEM

-
a:
CD
t /)
a-
CD
>
';:
C
CD
c:
::i
TEXAS . " 4-29

INSTRUMENlS
II
r-
:i'
CD
.
c
<'
..
CD
en
~
CD
o
CD
..<'
CD
en
4-30
MC3446
QUADRUPLE BUS TRANSCEIVER
02290. JANUARY 1977-REVISEO SEPTEMBER 19B6
D. J. OR N DUAL-IN-LiNE PACKAGE
Driver Inputs Compatible with TTL and MOS
Circuitry (TOP VIEW)
Driver Outputs Stay Off During Power Up 1R Vee

and Power Down 18 4R
10 48
Drivers Feature Open-Colle~tor Outputs for 1,2,3S 40
Party-Line Operation 20 4S
Designed for Interchangeability with 28 30
Motorola MC3446 2R 38
GNO "'""i.,;;;_~t-' 3R
. Meet IEEE Standard 488-1975
description
1B (2)
These circuits are quadruple single-ended line
transceivers designed for bidirectional flow of
data and instructions. The bus terminal
characteristic complies with paragraph 3.5.3 of
IEEE Standard 488 (see Figure 3). Each driver
vcc~~~----------~~
1.2.3S
II
...en
Q)
output is tied to the junction of an internal
voltage divider that sets the no-load output os>
voltage and provides bus termination. The driver CJ
outputs are guaranteed to be "off" during power
up and power down if either input is high. The
receivers feature 950 millivolts typical hysteresis
for noise immunity. 3B~~~-+----------;-'
-...
Q)
a:
en
Q)
>
0i:
The MC3446 is characterized for operation from C
OOC to 70C. 3D -----------,Jl.-.;' Q)
I:
FUNCTION TABLE
::::i
4B~~~~----------~-'
(TRANSMITTING)
4S
INPUTS OUTPUT
40 -'-'~-------,JL-.;'
S 0 B R
L H H H
L L L L
R1 = 2.4 kn NOM. R2 = 5 kn NOM
FUNCTION TABLE logic symbol t

(RECEIVING)
1.2.3S
INPUTS OUTPUT
S B 0 R
10
H H X H
1R
H L X L ~--<.....;..(6-,-) 2B
20
2R
3D (10) 3B
3R
4S (14) 4B
40
4R
t This symbol is in accordance with ANSIIIEEE Std 91-1984 and

PRODUCTION DATA documents contain information Copyright 19B6. Texas Instruments Incorporated
~~~~~:~~i~a{:~I~~~ ~!~~~~ti~f :I~o::~:~:t:r~~s not INSTRUMENTS
MC3446
EQUIVALENT OF EACH EQUIVALENT OF RECEIVER OUTPUTS

DRIVER AND DRIVER OUTPUTS/RECEIVER INPUTS ___________- .__~~_Vec
STROBE INPUT
20kn
NOM
BUS
Vec---+--- ~_-----4~-- - Vee
2.4 kn 13.6 kn
NOM NOM
D
OR
S
OUTPUT
II
r-
S"
(1)
...c
<" Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " 7 V
...
-
(1)
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
VI Driver output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. 150 mA
::xJ Continuous total dissipation at (or below) 25C free-air temperature (see Note 2):
(1)
n D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950 mW
(1)
J package . . . . . . . . . . . . . . . . . . . . . . . ". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " 1025 mW
<" N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050 mW
...
(1)
VI
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooC to 70C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package .... ,....... 300C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D and N package . . . . . .. 260C

2. For operation above 25C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the J package, use
the 8.2 mW/oC curve, in the D package, use the 7.6 mW/oC curve, and in the N package, use the 9.2-mW/oC curve.

MIN NOM MAX UNIT
High-level input voltage, VIH DorS 2 V
Low-level input voltage, VIL D or S 0.8 V
High-level output current, IOH Receiver -0.4 mA
Driver 48
Low-level output current, IOL mA
Receiver 8
4-32 TEXAS . "

INSTRUMENTS
MC3446
electrical characteristics over recommended ranges of Vee and operating free-air temperature (unless
otherwise noted)
VIK Input clamp voltage Dar S II = -12 mA -1.5 V
Positive-going input
VT+ B 1.5 l.B 2 V
threshold voltage
Negative-going input
VT- B 0.6 0.85 1.1 V
threshold voltage
Vhys Input hysteresis, (VT + - VT-) B 400 950 mV

B VIH = 2.4 V, 10H =0 2.5 3.3 3.7
V
VOH
R VIH = 2 V, 10H = -400 p.A 2.4
B VIL = 0.8 V. 10L = 48 mA 0.4
R VIL = 0.8 V, 10L = 8 mA 0.4
VIH = 2.4 V. Vo = 5.5 V 2.5
10(bus)
VOK
Bus current
Output clamp voltage

Input current at maximum
B
B
VIH = 2.4 V,
VIH = 2.4 V,
10 = -12 mA
Vo = 5 V
Vo = 0.4 V
0.7
-1.3 -3.2
-1.5
rnA
V
II
... CI)
II Dar S VI = 5.5 V 1 rnA Q)
input voltage
High-level input current Dar S VIH = 2.4 V 5 20 p.A 'Q)
>
IIH
IlL Low-level input current Dar S VCC = 5 V. VIL = 0.4 V, TA = 25C 0.2 0.36 rnA CJ
lOS
ICCH
ICCL
Short-circuit output current
Supply current, all outputs high
Supply current, all outputs low
R . VIW= 2 V
No load
No load
4
10
32
14
19
39
mA
mA
mA
-...
a:
Q)
CI)
Q)
>
tAli typical values are at VCC = 5 V, TA = 25C. 'i:
C
switching characteristics, Vee 5 V, TA Q)
t:
PARAMETER FROM TO TEST CONDITIONS MIN MAX UNIT ~
tpLH 40
D B ns
tpHL 50
See Figure 1
tpLH 50
S B ns
tpHL 50
tpLH 50
B R See Figure 2 ns
tpHL 40
TEXAS 4-33
INSTRUMENTS
MC3446

r---- 1
~O%
-~~--3V
RECEIVER OUTPUT +SV
OPEN .rr I
I I INPUT
STROBE or DRIVER
INPUT MONITOR I I 100 n I I
I I I I OV
I I
~......,..I-+-......_ O~BTJ~T tpLH ~ 14- -+I t4- tPHL
~
SO pF
I : -I---VOH
(See Note B) I . I
OUTPUT 1.S V 1.S V
VOL
FIGURE 1
III INPUT (BUS)

MONITOR
r-
S
CD
...<.
C
+SV
400n
OUTPUt
(RECEIVER) .
INPUT :I v:-- I
I
I
I
3.
OV
...
CD
(See Note C)
tPLH-+l 14- ~ /4-tPHL
~
:
(n
~
CD
-1--. -VOH
n OUTPUT 1.S V 1.S V
CD
<.
...
CD
(n
VOL
FIGURE 2
NOTES: A. The input pulse is supplied by a generator having the following characteristics: tw = 100 ns, PRR :5 1 MHz, tr :5 10 ns,
tf :5 10 ns, Zout '" 50 n.
B. This value includes probe and jig capacitance.
C. All diodes are 1 N916 or 1 N3064.
DRIVER OUTPUT CHARACTERISTCSt RECEIVER TRANSFER CHARACTERISTICS
..:
f:c. : . >
~ 4
~ -218{+-f--j;.--4-+--+- !l
~
;-4
~ -6 :.: 9o
1
2 1--I--
E -814+1--1- >
Vcc= 5 V
f-- 1-1- 10 =0
-10
~A=215C
-12 ... o
-2 -1 o 0.5 1 1.5 2 2.5 3 3.5 4
Va-Oriver Output Voltage-V VI-Input Voltage-V
FIGURE 3 FIGURE 4
tConditions for typical curve are VCC = 5 V, TA = 25C.
4-34 TEXAS "I}

INSTRUMENTS
MC3450, MC3452
D3006, FEBRUARY 1986-REVISED OCTOBER 1986
Four Independent Receivers with Common D, J. OR N PACKAGE

Enable Input (TOP VIEW)
High Input Sensitivity ... 25 mV Max 18 Vcc+

1A 48
High Input Impedance 1Y 4A
MC3450 has Three-State Outputs EN 4Y
2Y Vcc-
MC3452 has Open-Collector Outputs 2A 3Y
Glitch-Free Power-Up/Power-Down 28 3A
Operation GND 38
description FUNCTION TABLE

The MC3450 and MC3452 are quadruple DIFFERENTIAL INPUTS ENABLE OUTPUT
II
differential line receivers designed for use in A-B EN Y
balanced and unbalanced digital data VIO 2: 25 mV L H
transmission. The MC3450 and MC3452 are the - 25 mV < VIO < 25 mV L ?
same except that the MC3450 has three-state
ouputs whereas the MC3452 has open-collector
VIO oS 25 mV
X
L
H
L
Z
... tn
Q)
outputs, which permit the wire-AND function >
with' similar output devices. Three-state and H = high level, L = low level. ? = indeterminate. 'il)
(.)
open-collector outputs permit connection Z = impedance (off) Q)
directly to a bus-organized system.
The MC3450 and MC3452 are designed for
-ex:...
tn
Q)
optimum performance when used with either the
'~
>
MC3453 quadruple differential line driver or
SN75109A, SN75110A, and SN75112 dual
C
Q)
differential drivers. c:
The MC3450 and MC3452 are characterized for :::i
logic symbols t
MC3450 MC3452
EN
1A 1A
(3) 1Y (3) 1Y
18 18
2A (5) 2Y 2A (5)
2Y
28 28
3A (11 ) 3A (11 )
3Y 3Y
38 38
4A (13) 4A (13)
4Y 4Y
48 48
~
TEXAS
~~~~~:~~i~a{~:I~~~ ~!~~~~ti~; ~~o~:::~:t::s~s not INSTRUMENTS
4-35
MC3450. MC3452
1A .....;,.(2...;,)_ _ _ _+ - _.. ""'" (3)

1 B .....;,.(1...;,)_ _ _ _+--<11"""" >----..,;-.;... 1Y
2A . (6)
(5) 2Y
2B~(7~)_ _ _ _+--<II""""
3A (10)
(11 )
>----3Y
3B (9)
4A (14)
r- (13) 4Y
4B (15)
:i'
CD
..,c schematics of inputs and outputs

<'
..,CD
-
Ul
::JJ
CD
n
CD
EQUIVALENT OF
A OR B INPUT
Vcc +---4--"'-
EQUIVALENT OF
ENABLE INPUT
VCC+---e-----
TYPICAL OF MC3450
OUTPUT
---,-------.-VCC
TYPICAL OF MC3452
OUTPUT
<'CD.., 1 kf!
NOM
3 kf!
NOM
140 f!
Ul
INPUT INPUT OUTPUT
OUTPUT
200 f! VCC--+--........- - - -
NOM
" - -....-GND
VCC---4~a- GND ~__- ---- -41>-~ __- ...-GND
4-36 TEXAS . .
INSTRUMENTS
POST OFFice BOX 655012 ' DALLAS. TeXAS 75265
MC3450, MC3452
absolute maximum ratings ov~r operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC + (see Note 1) ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Supply voltage, VCC - ..................................................... - 7 V
Differential input voltage (see Note 2) .......................................... 6 V
Common-mode input voltage (see Note 3) ............................. '. . . . . . . . .. 5 V
Enable input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
D package ......................................................... 950 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package ........................................................ 1150 mW
Operating free-air temperature range ..................................... , OOC to 70C
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds: D or N package ......... 260C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . .. 300C
NOTES: 1.
2.
3.
4.
All voltage values, except differential input voltage, are with respect to network ground terminal.
Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.
Common-mode input voltage is the average of the voltages at the A and B inputs.
For operation above 25C free-air temperature, derate the D package to 608 mW at 70C at the rate of 7.6 mW/oC, the
II
...
o
J package to 656 mW at 70C at the rate of 8.2 mW/oC, and the N package to 736 mW at 70C at the rate of 9.2 mW/oC. CD
In the J package, MC3450 and MC3452 chips are glass mounted.
>
'Q)
CJ
Supply voltage, VCC +

Supply voltage, VCC-
MIN
4.75
-4.75
NOM
5
MAX
5.25
-5 -5.25
UNIT
V
V
-...
a:
CD
o
CD
>
'':
High-level enable input voltage, VIH 2 V C
Low-level enable input voltage, VIL 0.8 V CD
Low-level output current, IOL -16 mA r::::
Differential input voltage, VID (see Note 5) -5 T 5 V ~
Common-mode input voltage, VIC (see Note 5) -3 T 3 V
Input voltage range, any differential input to ground -5 t 3 V
Operating free-air temperature, T A a 70 c
t The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-
mode input voltage.
NOTE 5: The recommended combinations of input voltages fall within the shaded area of Figure 1.
RECOMMENDED COMBINATIONS OF INPUT VOLTAGES
>
~
1S 0
>
1-1
t;
-4 -3 -2 -, 0
Input B to Ground Voltage-V
FIGURE 1
TEXAS 4-37
INSTRUMENTS
MC3450, MC3452
electrical characteristics over recommended operating free-air temperature range, Vee = 5.25 V
MC3450 MC3452
A inputs VID = -2 V 30 75 30 75
p.A
High-level B inputs VID = -2 V 30 75 30 75
IIH
input current VIH = 2.4 V 40 40 p.A
EN
VIH = 5.25 V 1 1 mA
A inputs VIO = 2 V -10 -10
Low-level. p.A
IlL B inputs VIO = 2 V -10 -10
input current
EN VIL = 0.4 V -1.6 -1.6 mA
VCC = 4.75 V, VID = 25 mV,
High-level output
VOH EN at 0.8 V, 10H = -400 p.A, 2.4 V
voltage
VIC = -3 V to 3 V
III
r
10H
VOL
High-level output
current
Low-level output
VCC = 4.75 V, VOH
VCC = 4.75 V, VIO

EN at 2 V, 10L
= 5.25 V
= -25 mV,
= 16 mA, 0.5
250
0.5
p.A
V
:i' voltage
VIC = -3 V to 3 V
CD
High-impedance-state Vo = 2.4 V 40
...c 10Z
output current Vo = 0.4 V -40
p.A
<'CD Short-circuit VID = 25 mV, Vo = 0,

...en. lOS
output current; EN at 0.8 V
-18 -70 mA
Supply current from

~ ICCH+
VCC +, outputs high
60 60 mA
CD
(") Supply current from
CD ICCH- -30 -30 mA
<' VCC -, outputs high
...en
CD
t All typical values are at VCC + = 5 V, VCC _ = - 5 V, T A = 25C .
t Not more one output should be shorted at a time.
switching characteristics, Vee;t = 5 V, TA

FROM TO MC3450 MC3452
(INPUT) (OUTPUT) MIN Typt MAX MIN Typt MAX
CL = 50 pF, See Figure 2 17 25
tPLH A and B Y ns
tpHL A and B Y ns
tpZH EN Y 21
CL = 50 pF, See Figure 2 ns
tpZL EN Y 27
tpHZ EN Y 18
EN Y
CL = 15 pF, See Figure 3 ns
tpLZ 29
tpLH EN Y CL = 15 pF, See Figure 4 25 ns
tpHL EN Y CL = 15 pF, See Figure 4 25 ns
t All typical values are at VCC + 5 V, VCC-
4-38 TEXAS
INSTRUMENTS
-1!1
MC3450, MC3452
OUTPUT SV SV
~
390 fl
GENERATOR
SO fl
(SEE NOTE AI
100 mV FOR
MC34S2
FOR
MC34S0
(SEE NOTE CI
TEST CIRCUIT
------200mV ~
FE
Q)
INPUT 100 ,:;,V 100 mV >
'Q)
I I (.)
I I 0 V Q)
tpLH
I
--M--+I
I
I
tpHL --M-+I
I -
ex:
en
"-
~
-I----VOH Q)
I . I >
OUTPUT 1.SV 1.SV 'i:
C
VOL Q)
s:::
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ~ 1 MHz, duty cycle = SO%, tr ~ 6 ns,
:.:l
tf ~ 6 ns.
C. All diodes are 1 N916 or equivalent.
VOLTAGE WAVEFORMS
FIGURE 2. PROPAGATION DELAY TIMES
TEXAS -Ij} 4-39

INSTRUMENTS
MC3450, MC3452
A B S1 S2
tpZH 100 mV GND Open Closed S1
tpZL 390 f!
o-5V
GENERATOR
(SEE NOTE AI
50 fl CL
ISEE NOTE B, I 1 kf! (SEE NOTE CI
III ~~:---- JV
TEST CIRCUIT
ENABLE '\::: - - - - J V
ENABLE
I OV I OV
tPZH+-+t tPZL~
OUTPUT,\:5~--- 5V
I
-J,f
VOH
OUTPUT_ _ _ _ V __ 0 V
"'.----VOL
,p --r--
ENAB~ _ _ _ _ _ _ _ ov
3V
I .
~ tptz~".5V

OUTPU~':~~ :~_ VOL
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR :5 1 MHz, duty cycle = 50%, tr :5 6 ns,
tf :5 6 ns.
C. All diodes are 1N916 or equivalent.
FIGURE 3. MC3450 ENABLE AND DISABLE TIMES
4-40 TEXAS ~
INSTRUMENTS
MC3450, MC3452
5V
390 n
~--~--__- - - OUTPUT
GENERATOR
(SEE NOTE A)
50 n
CL
ISEE NOTE BJ I
ENABLE r-E'5
TEST CIRCUIT
V -~.~V-----3V
III
...
U)
Q)
I I >
I I 0 V 'CD
I I (J
tpLH~ tpHL~ Q)
ex:
OUTPUT
I
I
I
I
:-i - - - -
I
VOH
--...
U)
Q)
>
';::
C
VOLTAGE WAVEFORMS Q)
:
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ~ 1 MHz, duty cycle = 50%, tr ~ 6 ns, ::i
tf ~ 6 ns.
FIGURE 4. MC3452 PROPAGATION DELAY TIMES FROM ENABLE
TEXAS 4-41
INSTRUMENTS

r-
S'
CD
..<'
C
..
CD
en
iCD
n
CD
.<'
CD
en
4-42
MC3453
QUADRUPLE LINE DRIVER WITH COMMON ENABLE
D3000. FEBRUARY 1986
Similar to a Dual Version of SN7511 OA Line D. J. OR N

Driver DUAL-IN-L1NE PACKAGE
(TOP VIEW)
Improved Stability Over Supply Voltage and
Temperature Ranges 1A Vcc+
1Y 4A
Constant-Current Outputs 1Z 4Y
High Output Impedance 2Z 4Z
2Y 3Z
High Common-Mode Output Voltage Range ENABLE 3Y
(-3 V to 10 V) 3A
2A
Glitch-Free Power-Up/Power-Down GND VCC-
Operation
FUNCTION TABLE
frL Input Compatibility

Common Enable Circuit
Motorola MC3453
LOGIC
INPUT
H
ENABLE
INPUT
H
OUTPUT
CURRENT
Z
ON
Y
OFF
II
...
I/)
L H OFF ON Q)
description H L OFF OFF :>
'Q)
L L OFF OFF (.)
The MC3453 features four line drivers with a Q)
common enable input. When the enable input is
high, a constant output current is switched
between each pair of output terminals in
L = low logic level
H = high logic level -...
a:
I /)
Q)
response to the logic level at that channel's :>
'i:
input. When the enable is low, all channel logic symbol t C
outputs are non conductive (transistors biased to Q)
cutoff). This minimizes loading in party-line I:
systems where a large number of drivers share :::i
the same line.
1Y
The driver outputs have a common-mode voltage
1Z
range of - 3 volts to 10 volts, allowing common-
mode voltages on the line without affecting 2Y
driver performance. 2Z
3Y
All inputs are diode clamped and are designed 3Z
to satisfy TTL-system requirements. The inputs
4Y
are tested at 2 volts for high-logic-level input
4Z
conditions and 0.8 volt for low-logic-level input
conditions. These tests guarantee 400 millivolts t This symbol is in accordance with ANSI/lEEE Std 91-1984 and
of noise margin when interfaced with Series lEe Publication 617-12.
54/74 TTL.
The MC3453 is characterized for operation from
ODC to 70 DC.
~~~~~:~~i~a{:~I~'l8 ~~:~~~ti:r ~~o::~:~:t:ros~s not
TEXAS ~ 4-43
INSTRUMENTS
POST OFFICE BOX 655012 bAllAS. tEXAS 75265
MC3453
ENABLE
1Y
1A - - - - - f - - t
1Z
2Y
2A -----1---4
2Z
3Y
3A - - - - - 1 - - 1
3Z
4Y
4A------I
4Z
r-
:r
CD
. - - - - - - - OUTPUT
Vcc+ - - - -.....- - -
INPUT -il1--_e_-t
' - - - - - - - - OUTPUT
Vcc-~------~~-----
---~.------ VCC-
GND------
4-44 TEXAS -1.!1

INSTRUMENTS
MC3453
Supply voltage, Vcc + (see Note 1) ........... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Supply voltage, VCC _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 7 V
Input voltage (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Output voltage range (any output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 5 V to 12 V
D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95'0 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooC to 70C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ~ 65C to 150C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N package .......... 260C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package. . . . . . . . . . . .. 300C
2. For operation above 25C free-air temperature, derate the D package to 608 mW at 70C at the rate of 7.6 mW/oC, derate
the J package to 656 mW at 70C at the rate of 8.2 mW/oe, and the N package to 736 mW at 70C at the rate of 9.2
mW/oe. In the J package the MC3453 is glass mounted.
III
...
en
Q)
recommended operating conditions >
'0)
MIN NOM MAX UNIT (.)
Supply voltage, Vce +
Supply voltage, VCC-
4.75
-4.75
2
0
5 5.25
-5 -5.25
5.5
0.8
V
V
V
V
-...
a:
Q)
en
(1)
>
I VOeR+ 0 10 V 'I:
Common-mode output voltage range C
I VOCR- 0 -3 V
Q)
t:
NOTE 3: All unused outputs must be grounded.
::;
electrical characteristics over recommended operating free-air temperature range, Vee + 5.25 V,
VIK Input clamp voltage 11= -12 mA -0.9 -1.5 V
On-state output current

VCC + = 5.25 V, VCC- = -5.25 V 11 15
mA
10(on)
Vec+ = 4.75 V, VCC- = - 4.75 V 6.5 11
10(0ft) Off-state output current VCC+ = 4.75 V, VCC- = -4.75 V 100 p.A
VI = 2.4 V 40 p.A
IIH High-level input current
VI = 5.25 V 1 mA
IlL Low-level input current VI = 0.4 V -1.6 mA
Enable at 2 V 33 50
lec+ Supply current from Vee + A inputs at 0.4 V mA
Enable at 0.4 V 33 50
Enable at 2 V -68 -90
lec- Supply current from Vce- A inputs at 0.4 V mA
Enable at 0.4 V -31 -40
t All typical values are at VCC + = 5 V, VCC- -5 V, and TA = 25C.
TEXAS . . 4-45
INSTRUMENTS
MC3453
OUADRUPLE LINE DRIVER WITH COMMON ENABLE
switching characteristics, Vec + 5 V, VCC- -5 V, RL 500, CL 40 pF, TA

FROM TO TEST
PARAMETER MIN TVP MAX UNIT
(lNPUTI (OUTPUTI CONDITIONS
tpLH Propagation delay time, low-to-high-Ievel output A V or Z 9 15 ns
tpHL Propagation delay time, high-to-Iow-Ievel output A V or Z 7 15 ns
See Figure 1
tpLH Propagation delay time, low-to-high-Ievel output Enable Y or Z 14 25 ns
tpHL Propagation delay time, high-to-Iow-Ievel output Enable V or Z 15 25 ns

AINPuT--------------~ r-------.-----....---- OUTPUT Y
CL .. 40 pF
III ENABLE--------------~ o-------~.----- ....----OUTPUTZ

CL .. 40 pF
TEST CIRCUIT
A INPUT ~O% 50%

I
I
I
I r---- OV
I+- tw 1---+1
I 1
I I
I I
I I
50%
ENABLE 1 I
I I
I I OV
I ~tPHL
tpLH --f4-+I
I I
I 1 off
I I
OUTPUT Y
on
,..--nf---------------- off
OUTPUT Z
I
-1------------------ on
k-.J-tPLH
VOLTAGE WAVEFORMS
NOTES: A. The pulse generators have th'e following characteristics: Zo = 500, tr = tf = 10 5 ns, tw1 = 200 ns, PRR :s 1 MHz,
tw2 = 1 1'5, PRR :s 500 kHz,
4-46 TEXAS
INSTRUMENTS
'I.!I
MC3486
QUADRUPLE LINE RECEIVER WITH 3STATE OUTPUT
02434. JUNE 1980- REVISED SEPTEMBER 1986
Meets EIA Standards RS-422-A and D. J OR N PACKAGE

RS423-A and Federal Standards 1020 and (TOP VIEW)
1030
Three-State, TTL-Compatible Outputs 1B Vee
1A 4B
o Fast Transition Times 1Y 4A
Operates from Single 5-Volt Supply 1.2EN 4Y
2Y 3,4EN
o Designed to be Interchangeable with 2A 3Y
Motorola MC3486 2B 3A
GND 3B
description
The MC3486 is a monolithic quadruple FUNCTION TABLE (EACH RECEIVER)
differential line receiver designed to meet the
specifications of EIA Standards RS-422-A and
RS-423-A and Federal Standards 1020 and
1030. The MC3486 offers four independent
differential-input line receivers that have TTL-
DIFFERENTIAL INPUTS
A-B
VID ~ 0.2 V
- 0.2 V < VID < 0.2 V
VID :s -0.2 V
ENABLE
H
H
H
OUTPUT
Y
H
?
L
II
...en
Q)
compatible outputs. The outputs utilize three- >
Irrelevant L Z
state circuitry to provide a high-impedance state "a;
at any output when the appropriate output H = high level. L = low level. Z = high-impedance CJ
-...
Q)
(off). ? = indeterminate
enable is at a low logic level. a:
The MC3486 is designed for optimum en
logic diagram (positive logic) Q)
performance when used with the MC3487
>
quadruple differential line driver. It is supplied in 'a::::
a 16-pin package and operates from a single C
5-volt supply. Q)
c:
The MC3486 is characterized for operation from lA (31 lY :.:J
ODC to 70 DC. lB--~I_
logic symbol t 2A ,.-. .~
(51 2Y
2B---<-J' ~
1.2EN
lA (31 lY 3.4EN
lB
2A (51 2Y
3A (111 3Y
26
3B--~.~
3.4EN
4A (13) 4Y
3A 4B--~.-
(111 3Y
36
4A (131 4Y
46

specifications per the terms of Texas Instruments TEXAS ~ 4-47
~~~~~:~~i~ar~:I~~~ ~!~~~~ti~f :llo;:~:~:t:ros~S not INSTRUMENTS
MC3486
EQUIVALENT OF EACH INPUT EQUIVALENT OF OUTPUT ENABLE TYPICAL OF ALL OUTPUTS

EXCEPT OUTPUT ENABLE
VCC .....----~~-~__-
85!l VCC
VCC---------1~---- NOM
8.3 k!l
NOM
16.8 k!l
NOM
INPUT.J\of'll'v--. OUTPUT -tI..-...--t
....---+-- ENABLE
OUTPUT
r-
:r
CD
...c
<'
...
CD
-
o
:lJ
CD
(')
Supply voltage, VCC (see Note 1) .............................................. , 8 V
CD Input voltage, A or 8 inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
<' Differential input voltage (see Note 2) ....................... :................. 25 V
...o
CD
Enable input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 8 V
Low-level output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
D package ......... 950 mW
J package ....... , 1025 mW
N package ....... , 11 50 mW
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ......... 260C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . .. 300C
NOTES: 1. All voltage values, except differential-input voltage, are with respect to network ground terminal.
2. Differential-input voltage is measured at the noninverting input with respect to the corresponding inverting input.
3. For operation above 25C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the J package, MC3486
chips are glass mounted. In the N package, use the 9.2-mW/oC curve for these devices. In the D package, use 7.6 mW/oC curve.

MIN NOM MAX' UNIT
Common-mode input voltage, VIC 7 V
Differential input voltage, VID 6 V
High-level enable input voltage, VIH 2 V
Low-level enable input voltage, VIL 0.8 V
Operating free-air temperature, TA 0 70 ,oc
4-48 TEXAS . .
INSTRUMENlS
MC3486
OUADRUPLE LINE RECEIVER WITH 3-STATE OUTPUT
electrical characteristics over recommended ranges of common-mode input voltage, supply voltage,
and operating free-air temperature (unless otherwise noted)
VTH Differential-input high-threshold voltage Va = 2.7 V, 10 = -0.4 mA 0.2 V
VTL Differential-input low-threshold voltage Va =0.5 V, 10 = 8 mA -0.2t V
VIK Enable-input clamp voltage II = -10 mA -1.5 V
VID* = 0.4 V, 10 = -0.4 mA,
VOH High-level output voltage 2.7 V
See Note 4 and Figure 1
VID* = -0.4 V,IO = 8 mA,
VOL Low-level output voltage 0.5 V
See Note 4 and Figure 1
VIL ,;, 0.8 V, VID = -3 V, Va = 2.7 V 40
10Z High-impedance-state output current Il A
VIL = 0.8 V, VID = 3 V, Va = 0.5 V -40
VI = -10 V -3.25
VCC = 0 V or 5.25 V, VI = -3 V -1.5
II
liB Differential-input bias current mA
Other inputs at 0 V VI = 3 V 1.5
VI = 10 V 3.25
VI = 5.25 V 100
IIH High-level enable input current
VI = 2.7 V 20
Il A
...en
Q)
IlL Low-level enable input current VI = 0.5 V -100 IlA :>
lOS Short-circuit output current VID = 3 V, Va = 0, See Note 5 -15 -100 mA 'Q)
ICC Supply current VIL = 0 85 mA u
t The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet for threshold
voltages only.
NOTES: 4. Refer to EIA Standards RS-422-A and RS-423-A for exact conditions.
5. Only one output at a time should be shorted.
-Q)
a:
...en
Q)
:>
'~
C
switching characteristics, Vee = 5 V, TA = 25e Q)

c:
:..:J
tPHL Propagation delay time, high-to-Iow-Ievel output 28 35 ns
CL = 15 pF, See Figure 2
tPLH Propagation delay time, low-to-high-Ievel output 27 30 ns
tpZH Output enable time to high level 13 30 ns
tpZL Output enable time to low level 20 30 ns
tpHZ Output disable time from high level 26 35 ns
TEXAS 4-49
INSTRUMENlS
MC3486
I IOH
.. (-I
FIGURE 1. VOH, VOL
III
~
' --- 3V
GENERATOR INPUT
(see Note Al 51 n 1.5 V 1.5 V
I I
I I 0 V
~tPLHj4- ~tPHLj4-
I -J - -VOH
1.5 V I I
OUTPUT
2 V--------~

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ~ 1 MHz, duty cycle"" 50%, tr ~ 6 ns,
tf ~ 6 ns.
B. Cl includes probe and stray capacitance.
4-50 TEXAS ~
INSTRUMENTS
MC3486
- - ---,
SW1
-1.5 V
I OUTPUT
I SW2
1.5 V---O 2 k!1
I 0-5 V
I
I
(see Note C)
I
I
I
I I
GENERATOR
(see Note .A) 51 !1
L ________ J
*' CL - 15 pF
(see Note B)
II
TEST CIRCUIT ... CJ)
(1)
:>
cu
CJ
tpZL (1)
tpZH
IN:U:~ -... L
CC
~
3V CJ)
, SW1T01.5V 1 .5 V
~_~~-SW1TO-1.5V
(1)
INPUT - -1.5 V SW2 OPEN
:>
I SW3 CLOSED -1-0 V SW2 CLOSED "i:
-+-- 0 V
~ /+- C
tPZH-+! t+- tpZL SW3 OPEN
(1)
I
.. ~-t---- c
~
VOH 4 5V
. :.J
OUTPUT -
---OV
-1:5 V
OUTPUT J -C 1 . 5V
VOL
tPLZ
~
tPHZ
3V~~;1TO_1'5V
3V
SW1 TO 1.5 V
INPUT 1.5 V SW2 CLOSED
INPUT 1.5 V SW2 CLOSED
I SW3CW~D
I . SW3CW~D
-OV
I --OV 'I
tPHZ~ \4-- tpLZ --./ 14"-
I
I
~
~--1.3V
I
OUTPUT 0.5 V_ _
VOH
OUTPUT - - - - 1 ' " 0 . 5 V L
f ~- -1.3V VOL
VOLTAGE WAVEFORMS
FIGURE 3. ENABLE AND DISABLE TIMES
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ~ 1 MHz, duty cycle'" 50%, tr ~ 6 ns,
tf ;5 6 ns.
B. CL includes probe and stray capacitance.
TEXAS ~ 4-51
INSTRUMENTS
II
r-
5'
(1)
.
c
..
c'
-
(1)
en
: ll
(1)
(')
(1)
.c'
(1)
en
4-52
MC3487
QUADRUPLE DIFFERENTIAL LINE DRIVER
WITH 3-STATE OUTPUTS
02578, MAY 1980-REVISED SEPTEM8ER 1986
Meets EIA Standard RS-422-A and Federal 0, J, OR N DUAL-IN-LiNE PACKAGE

Standard 1020 (TOP VIEW)
Three-State, TTL-Compatible Outputs 1A Vee

1Y 4A
Fast Transition Times 1Z 4Y
o High-Impedance Inputs 1,2EN 4Z
2Z 3,4EN
Single 5-Volt Supply 2Y 3Z
o Power-Up and Power-Down Protection 2A 3Y
GNI) 3A
Motorola MC3487
description
The MC3487 offers, four independent differential line drivers designed to meet the specifications of EIA
Standard RS-422-A and Federal Standard 1020. Each driver has a TTL-compatible input buffered to reduce
current and minimize loading.
The driver outputs utilize 3-state circuitry to provide high-impedance states at any pair of differential outputs
II
...
en
Q)
when the appropriate output enable is at a low logic level. Internal circuitry is provided to ensure a high- >
impedance state at the differential outputs during power-up and power~down transition times, provided 'Ci)
(,)
the output enable is low. The outputs are capable of source or sink currents of 48 milliamperes.
The MC3487 is designed for optimum performance when used with the MC3486 quadruple line receiver.
It is supplied in a 16-pin dual-in-line package and operates from a single 5-volt supply.
The MC3487 is characterized for operation from OOC to 70C.
-...
a:
Q)
en
Q)
>
'i:
C
logic symbol t logic diagram (positive logic) Q)
t:
:::l
(2) 1V
(3) 1Z
(6) 2V
(5)
0----2Z
(10) 3V
(11) 3Z
(14) 4V
(13)
0----4Z
t This symbol is in accordance with ANSI/lEEE Std 91-1984 and

lEG Publication 617-12_
current 8S of publication date_ Products conform to
specifications per the terms of Texas Instruments TEXAS . .
:~~~~:~~i~ar~~I~~e ~!~~~~ti:r ~~o::~:~:t:ros~S not 4-53
INSTRUMENTS
POST OFFiCe BOX 655012 DALLAS, TeXAS 75265
MC3487
WITH 3STATE OUTPUTS
FUNCTION TABLE (EACH DRIVERI
OUTPUT OUTPUTS
INPUT
ENABLE Y Z
H H H L
L H L H
X L High-Impedance High-Impedance
H = TTL high level X = irrelevant

L = TTL low level

vcc------_e------- ----------4~----------Vcc
III
r-
:i" INPUT
CD
...c
<'
...
CD
en
9!l NOM
:c
CD
e-----~-----4~-- OUTPUT
n
CD
<'
...
CD
en
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
o package ......................................................... 950 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package ........................................................ 11 50 mW
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............. 300C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: 0 and N packages. . . . . .. 260C
NOTES: 1. All voltage values, except differential output voltage, VOD, are with respect to the network ground terminal.
MC3487 chips are glass mounted. In the N package, use the 9.2-mW/oC curve for these devices.

MIN NOM MAX UNIT
Operating free-air temperature, T A 0 70 C
4-54
TEXAS . .
INSTRUMENTS
MC3487
OUDRUPLE DIFFERENTIAL LINE DRIVER
WITH 3STATE OUTPUTS
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
VIK Input clamp voltage II = -18 mA -1.5 V
VOH High-level output voltage VIL = 0.8 V. VIH = 2 V. 10H = -20 mA 2.5 V
VOL Low-level output voltage VIL = 0.8 V. VIH =2 V. IOL = 48 mA 0.5 V
IVODI Differential output voltage RL = 100 n. See Figure 1 2 V
Change in magnitude of
/lIVODI
differential output voltage t
RL = 100 n. See Figure 1 0.4 V
VOC Common-mode output voltage t RL = 100 n. See Figure 1 3 V

/lIVocl
com'mon-mode output voltage t _
RL = 100 n. See Figure 1 0.4 V
Vo = 6 V 100
10 Output current with power off VCC = 0 p.A
Vo = -0.25 V -100
High-impedance-state Output enables Vo = 2.7 V 100
102 p.A
output current at 0.8 V Vo = 0.5 V -100
Input current at maximum
II
input voltage
VI = 5.5 V 100 p.A ...
U)
Q)
IIH High-level input current VI = 2.7 V 50 p.A >
IlL Low-level input current VI = 0.5 V -400 p.A 'Q)
(,)
lOS Short-circuit output current VI = 2 V -40 -140 mA Q)
ICC Supply current (all drivers)

Outputs disabled
Outputs enabled. No load
105
85
mA
-...
a:
U)
Q)
t/lIVODland /lIVocl are the changes in magnitude of VOD and VOC. respectively. that occur when the input is changed from a high
'i:
>
level to a low level.
tin EIA Standard RS-422-A. VOC. which is the average of the two output voltages with respect to ground. is called output offset voltage. VOS. C
Only one output at a time should be shorted and duration of the short-circuit should not exceed one second. Q)
s:::::
switching characteristics over recommended range of operating free-air temperature, Vee = 5 V

::::i
PARAMETER TEST CONDITION MIN MAX- UNIT
tpLH Propagation delay time. low-to-high-Ievel output 20 ns
tpHL Propagation delay time. high-to-Iow-Ievel output CL = 15 pF. See Figure 2 20 ns
Skew 6 ns
tTD Differential-output transition time CL = 15 pF. See Figure 3 20 ns
tpZH Output enable time to high level 30 ns
tpZL Output enable time to low level 30 ns
CL = 50 pF. See Figure 4
tpHZ Output disable time from high level 25 ns
tPLZ Output disable time from low level 30 ns
FIGURE 1. DIFFERENTIAL AND COMMON-MODE OUTPUT VOLTAGES
TEXAS "J} 4-55

INSTRUMENTS
MC3487
WITH 3STATE OUTPUTS
INPUT--Al.5 V
1.
5V
t ----- '-._ _ _ _ _ _ 0 V
--3V
5V
l.tPLH~ ~tPHL
200 n
Y OUTPUT I --~-~r --- VOH
GENERATOR I I '-----VOL
(See Note AI ~ CL = 15 pF I
:(See Note BI I Skewt-1
~tPHL--t
I I
\ r
I _ _ _ _ _ _ 1
3V L ...J Ioe-tPLH--!
(See Note CI -= VOH
Z OUTPUT
,1~5 V 1.5 V _ _ -VOL
11
sCDr-
TEST CIRCUIT

VOLTAGE WAVEFORM
INPUT r--\---3V
J "---0 V
...c GENERATOR
(See Note AI 50n OUTPUT tTD~ :-- ---: : - - tTD
<' L-~~_~_ _- L
OUTPUT
J:\L90%I
I I
...
CD
en
3V
IL.. _ _ _ _ _ ..J 10%
~ TEST CIRCUIT VOLTAGE WAVEFORMS

CD
(') FIGURE 3. DIFFERENTIAL-OUTPUT TRANSITION TIMES
CD
<' r-----'I
...
CD
en I
I I
Oor 3V I
I
I
GENERATOR L_ _ _ _ _ J
(Site Nota AI 50 n
TEST CIRCUIT
OUTPUT ~---- 3 V OUTPUT ,----3V
ENABLE 1.5 V , ENABLE .1,.5 V
INPUT 1'-- - - 0 V INPUT OV-" '
tPHZ-.I ~ V tpZL ~ =-i
OUTPUT ~.5
1
V ~~ closed
SW2 closed
OUTPUT
--r\Lp; v
~ ~2opan
~1 closed
I "'1.5 V I VOL
OUTPUT A :+-
tPLZ -..
0.5 V
"'1.5 V
SWl closed
SW2 closed
VOL
OUTPUT
tPZH~
~
I
~
~lopen
..... v
VOH
SW2 closed
VOLTAGE WAVEFORMS
FIGURE 4. DRIVER ENABLE AND DISABLE TIMES

NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr ~ 5 ns, tf ~ 5 ns, PRR ~ 1 MHz, duty
cycle = 50%, Zo = 50 n.
C. All diodes are 1 N916 or 1N3064.
4-56 TEXAS
INSTRUMENTS
"'!1
POST OFFiCe BOX 655012 DALLAS. TeXAS 75265
NaT26
WITH 3STATE OUTPUTS
02462. MAY 1978-REVISED SEPTEMBER 1986
P-N-P Inputs for Minimal Input Loading D. J. OR N PACKAGE

(200 p.A Maximum) (TOP VIEW)
High-Speed Schottky Circuitry
RE Vee
3-State Outputs for Driver and Receiver 1R DE
Party-Line (Data-Bus) Operation 18 4R
10 48
Single 5-V Supply 2R 40
Designed to be Interchangeable with 28 3R
Signetics N8T26, also Called 8T26 20 38
GNo"-i..:::'-"-_::J-' 3D
description
The N8T26 is a quadruple transceiver utilizing logic symbol t
II
Schottky-diode-clamped transistors. Both the
driver and receiver have three-state outputs. DE
RE
With p-n-p inputs, the input loading is reduced
to . a maximum input current of 200 micro-
amperes. This device is capable of high 1D (3) 1B ...
rn
Q)
switching rates into high-capacitance loads and 1R
>
are suitable for driving long bus lines. 2D (6) 2B 'Ci)
CJ
-...
2R Q)
The N8T26 is characterized for operation from 3D a::
(10) 3B
ooe to 70C. 3R rn
4D (13) 4B Q)
FUNCTION TABLE (DRIVER)
4R >
'i:
INPUT OUTPUT C
DE D B t This symbol is in accordance with ANSI/IEEE SId 91-1984 and
Q)
lEG Publication 617-12. -
H L H c:
H H L :.:i
L X Z
R'E...:.:..:..------cj
FUNCTION TABLE (RECEIVER)
INPUT OUTPUT
(2)
RE B R 1R
(3)
L L H 1B
L H L
(5)
H X Z 20 2R
(6)
2B
H = high level
L = low level
X = irrelevant 3D 3R
Z = high impedance 3B
4R
13)
4B
. specifications per the terms of Texas Instruments
~~~~:~~i~a{~~I~'JB ~!~~~~ti~; ~~o::~:~:t:~~s not
TEXAS ~ 4-57
INSTRUMENTS
N8T26

VCC-------.--------- VCC
5 kn NOM
INPUT
OUTPUT
II Drivers:
Receivers:
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . .. 5.5 V
D package ......................................................... 950 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package ....................................................... 11 50 mW
lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300C
lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ........ 260C

2. For operation above 25C free-air temperature. refer to Dissipation Derating Curves in Appendix A. For NST26 in the N package.
use the 9.2-mW/oC curve. In the J package. NST26 chips are glass mounted.

MIN NOM MAX UNIT
Supply voltage. VCC 4.75 5 5.25 V
High-level input voltage. VIH B. D. DE. RE 2 V
Low-level input voltage. VIL B. D. DE. RE 0.S5 V

Driver. B -10
High-level output current. IOH mA
Receiver. R -2
Driver. B 40
Low-level output current. IOL mA
Receiver. R 16
Operating free-air temperature. T A 0 70 C
4-58 TEXAS
INSTRUMENTS
-1!1
POST OFFICE BOX 665012 DALLAS. tEXAS 75265
NaT26
WITH 3STATE OUTPUTS
electrical characteristics over recommended operating freeair temperature and supply voltage range
VIK Input clamp voltage B,D,DE,RE II = -5 mA -1 V
B VIH = 2 V, VIL =
0.85 V, IOH = -10 mA 2.6 3.1
R VIL = 0.85 V IOH-2mA 2.6 3.1
B VIH = 2 V, IOL = 40 mA 0.5
R VIH = 2 V, VIL = 0.85 V, IOL = 16 mA 0.5
Off-state (high-impedance B,R DE at 0.85 V REat2V, Vo = 2.6 V 100
10Z JLA
state) output current R RE at 2 V, Vo = 0.5 V -100
IIH High-level input current D,DE,RE VI = 5.25 V 25 JLA
IlL Low-level input current B,D,DE,RE VI = 0.4 V -200 p.A
B -50 -150
II
lOS Short-circuit output current t Vee = 5.25 V mA
R -30 -75
lee Supply current Vee = 5.25 V, No load 87 mA
t All typical values are at T A = 25e and Vee = 5 V.

tOnly one output should be shorted to ground at a time, and duration of the short circuit should not exceed one second.
... C/)
Q)
:>
'0)
switching characteristics, Vee = 5 V, TA = 25e u
PARAMETER
tpLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay time, high-to-Iow-Ievel output
tPLH Propagation delay time, low-to-high-Ievel output
FROM
D
TO
B
TEST CONDITIONS
CL = 30 pF,
See Figure 1
CL = 300 pF,
MIN TYP
14
8
7
MAX
18
10
20
UNIT
ns
ns
-...
Q)
a:
C/)
Q)
:>
'i:
tpHL Propagation delay time, high-to-Iow-Ievel output See Figure 2 12 20
C
tpLZ Output disable time from low level eL = 30 pF, 9 17
RE R ns Q)
tpZL Output enable time to low level See Figure 3 15 30 t:
tpLZ Output disable time from low level
DE B
eL = 300 pF, 20 43
ns
:..:J
tPZL Output enable time to low level See Figure 4 20 38
TEXAS -1.!1 4-59

INSTRUMENTS
NBT26

VCC 2.6V
TEST
POINT 92n
CIRCUIT (see Note DI

B R
UNDER
DE TEST
(see Note BI D (alII CL = 30 pF
RE 1.3kn
OPEN (see Note CI
GND
TEST CIRCUIT
~ <;S ns t-- ~ ~_"~n..:. -:- _ 2.6 V

90%~
I
I N P U T J 90%
I 1.SV 1.SV I
r- 10% 1 : 10% 0V
:i' ~tPHL' tpLH~
CD
...c OUTPUT
-----\l, -\:.....
1._S_V_ _ _ _ _ _ _ _
1._S.JVr
~VOH
<' - VOL
...Vl
-
CD VOLTAGE WAVEFORMS
FIGURE 1. PROPAGATION DELAY TIMES FROM BUS TO RECEIVER OUTPUT
:lJ
CD
o 2.6V
CD
<'
...
CD
Vl
30 n
(see Note DI
CL = 300 pF
(see Note CI
~ . 14-- <;S ns ~ 14-- <;S ns
~
: 90% 90%~r -- - - 2.6V
INPUT I 1.S V 1.S V
10% I I 10% 0V
:'--""tPHL tPLH~
OUTPUT \.s
I
V
Io.. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
.~: VOH
1.S V ,
-J -VOL
VOLTAGE WAVEFORMS
FIGURE 2. PROPAGATION DELAY TIMES FROM DRIVER INPUT TO BUS

NOTES: A. The pulse generator in Figures 1 and 2 has the following characteristics: PRR :S 10 MHz, duty cycle = 50%, Zout '" 50 n.
B. All inputs and outputs not shown are open.
C. CL includes probe and jig capacitance.
D. All diodes are 1N916 or 1N3064.
4-60 TEXAS ~
INSTRUMENTS
N8T26
WITH 3STATE OUTPUTS

2.6V Vcc 5V
TEST
POINT
CIRCUIT 2.4kn 240 n
RE UNDER R
TEST
D (all! (500 Noto B)
DE 5kn (500 Noto D)
GND
CL = 30 pF
(Probo)
(seo Note C)
TEST CIRCUIT
INPUT
~"5ns
: irl=--~~..,,;
I
2.6V
II
... en
Q)
~tPL~Z~_ _--.;..... >
OUTPUT ~~ 'Q)
(,)
Q)
-a::...
_ _ _ _....
/,0%
VOLTAGE WAVEFORMS en
Q)
FIGURE 3. RECEIVER ENABLE AND DISABLE TIMES >
'i:
vee 5V C
2.6V Q)
TEST t:
D (all)
POINT ::i
CIRCUIT
2.4kn 70 n
UNDER B
TEST
DE R (all)
(soe Note B) OPEN
GND (soe NoteD)
5kU
(Probe)
TEST CIRCUIT
~"5ns
: .il1~-----=
INPUT I
I
10% I
I
_ _ _ _~
__~ tpZL
OUTPUT \5V
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator in Figures 3 and 4 has the following characteristics: PRR s 5 MHz. duty cycle = 50%. Zout "" 50 0.
D. All diodes are 1N916 or 1 N3064.
TEXAS' -II} 4-61

INSTRUMENTS
II
r-
:r
C'D
c..
..
<"
C'D
-::c
en
C'D
(')
C'D
..<"
C'D
en
4-62
ADVANCE SN75061
INFORMATION DRIVER/RECEIVER PAIR WITH SQUELCH
02959. JANUARY 1987
IEEE 802.3 1 BASE5 Driver and Receiver OW. J. OR N PACKAGE

(TOP VIEW)
On-Chip Receiver Squelch with Adjustable
Threshold DRDLAJ
DRO+
Adjustable Squelch Delay
DRO-
Direct TTL-Level Squelch Output SODLAJ
RX)+
Squelch Circuit Allows for External Noise
RXI-
Filtering
SOTHAJ SODU
Two Driver-Enable Options GND SORXO
On-Chip Start-of-Idle Detection and Disable
Driver Guarantees 2.0 Volts Minimum into a 50-Ohm Differential Load to Allow for Use with
Doubly-Terminated Lines and Multipoint Architectures
On-Chip Driver Slew-Rate Control for Very Closely Matched Output Rise and Fall Times
PIN
DESCRIPTION
II ...
t/)
NAME NUMBER Q)
DATEN 15 Driver Data Enable. When low. places driver outputs in an active state. When high. the driver outputs
>
'Q)
are in a high-impedance state if OLEN is also high. (.)
Q)
OLEN 13 Driver Delay Enable. When this signal is low and DATEN is high. the driver outputs are active for a
period of time set by DRDLAJ after a positive-going transition on DRI. If there is no active data on DRI.
the outputs are in a high-impedance state.
-...
0:'
t /)
Q)
DRDLAJ 1 Driver Delay Adjust is a connection for the external R-C combination that determines the duration of >
'i:
the driver output active state after a positive transition on DRI when OLEN is low and DATEN is high.
C
DRI 14 Driver Data Input
Q)
DRO+ 2 Noninverting Driver Output c
DRO- 3 Inverting Driver Output ::i
GND 8 Ground. Common for all voltages
RXI+ 5 Noninverting Receiver Input
RXI- 6 Inverting Receiver Input
RXO 12 Main Receiver Output
SODLAJ 4 Squelch Delay Adjust is a connection for an external R-C combination that determines the duration
of the receiver unsquelch after a negative-going transition on SODLI.
2
SODLI 10 Squelch Delay Input is the input to the one-shot that controls the duration of the receiver unsquelch
period. The main receiver output remains unsquelched as long as SODLI is held high. Timing of the
o
unsquelch period begins on the high-to-Iow transition of SODLI. j:::
SOO 11 Squelch Output is high while the receiver is squelched. <t
SORXO 9 Squelch Receiver Output is high only when the differential receiver input exceeds the threshold set
~
by SOTHAJ.
a:
SOTHAJ 7 Squelch Receiver Threshold Adjust. The voltage at this input determines the threshold of the squelch
receiver in a ratio of - 2. SOTHAJ to threshold. If left open. the squelch receiver threshold defaults
oLL
VCC 16
to -600 mV.
Supply voltage input
-w
2
U
2
<t
>
c
<t
data and other specifications are subject to change TEXAS ~ 4-63
POST OFFICE BOX 655012 ' DALLAS. TExAS 75265
SN75061 ADVANCE
DRIVER/RECEIVER PAIR WITH SQUELCH INFORMATION
FUNCTION TABLES
DRIVER RECEIVER
DRIVER DATA . DELAY CONDITION RECEIVER SQUELCH
OUTPUT + OUTPUT- IN+ IN-
IN ENABLE ENABLE OUT THRESHOLD
L L X L H No active signal' X X H H
H L X H L L H L L
Active signal'
X H H Z Z H L H L
H H L Ht Lt
L H L Lt Ht
t This condition is valid during the time period set by Driver Delay Adjust followin-g a rising transition on Driver In. Following
this, if no subsequent positive transition occurs on Driver In, the outputs will go to the high impedance state.
t This condition is valid if it occurs within the enable time set by Driver Delay Adjust after a rising transition on Driver In. Otherwise
III
the outputs will be in the high-impedance state.
Pins 9 and 10 are tied together.
, An active signal is one that has an amplitude greater than the threshold level set by Squelch Threshold Adjust.
.-
S'
(I) SLEW CONTROL
...c
<:'
...
-
(I)
DRIVER DATA..:..(1;...4:..:.)______-----------~
fA INPUT, DRI
(3) INVERTING
::ll ">---........:...;.;.DRIVER OUTPUT,
(I)
(") DRIVER DATA..:..(1:...:5:..:.)_ _ _+ ________-<1 DRO-
(I) ENABLE, DATEN
<:'
...
(I)
fA
DRIVER DELAY (13)
ENABLE, DLEN
DRIVER DELAY
ADJUST, DRDLAJ
-:;rCT

c NON INVERTING
<
2
RECEIVER ..:.(.:.;5):....-....._"M~......_+-~ . . . .
INPUT, RXI+
(12) MAIN RECEIVER
INVERTING ...:(.;:.;6):....--+___"M...-+--___~
OUTPUT, RXO
RECEIVER
("') INPUT, RXI-
-:m2
-n
___..:..(1.;...1;.:..) saUELCH
OUTPUT, sao
o
::rJ
S SQUELC~H~i;~~~~ ..:(~7~)~"NI""'"

(9) (10)
ADJUST, SQTHAJ SQUELCH SQUELCH saUELCH
RECEIVER DELAY DELAY
-I OUTPUT, INPUT, ADJUST,
o SaRXO saDU SaDLAJ
:2
4-64 TEXAS
INSTRUMENTS
ADVANCE SN75061
description
The SN75061 is a single-channel driver/receiver pair designed for use in IEEE 802.3, 1 BASE5 applications
as well as other general data communications circuits. The SN75061 offers the system designer both a
driver and a receiver that are easily configured for use with a variety of controllers and data
encoder/decoders.
The receiver features a full analog squelch circuit with an adjustable threshold and a programmable squelch
delay. Internal nodes of the squelch circuitry are brought out to external connections to allow for the insertion
of noise filtering circuitry of the designer's choice.
As with the receiver, the driver offers the user a variety of implementation options. Driver enabling may
be controlled directly by an external logic input, or by use of an on-chip one-shot that is retriggered as
long as data is being sent to the driver. The driver will t~en automatically go to the high-impedance state
when end-of-packet occurs. The driver features internal slew-rate control for optimal matching of rise and
fall times allowing for reduction of driver-induced jitter.
receiver
The SN75061 receiver implements full analog squelch functions by integrating both a separate, parallel
II
. en
squelch receiver with an externally programmable threshold, and a programmable one-shot. The output Q)
of the squelch receiver and the input to the high~level dc-triggered one-shot are brought out to external >
connections. These pins can be shorted for direct implementation, or used for the insertion of noise-filtering 'Q)
CJ
circuitry of the implementer's design. The receiver one-shot can be effectively bypassed by applying a
high logic level to Squelch Delay In. The squelch threshold may be set externally by applying an external
voltage set to a level that is - 2 times the desired threshold voltage. If Squelch Threshold Adjust is left
open, the squelch receiver will default to its internal preset value of - 600 millivolts. The receiver also
outputs a high logic "squelch" signal when there is no active data present at the receiver inputs. When
-..
a:
en
Q)
Q)
>
'i:
no data is present on the transmission line, the receiver output assumes a high level. The "unsquelch" C
duration is set externally with an R-C combination at Squelch Delay Adjust. Q)
I:
driver :;:l
The driver offers the user a variety of implementation options. Driver enabling may be controlled directly
by an active-low external logic input on Data Enable, or by use of another on-chip one-shot that retriggers
with positive-going transitions on the driver input line. If no positive transition occurs within the pulse
duration set by an external R-C combination, the one-shot times out and the driver is automatically put
into a high-impedance state. When operating in the delay-enable mode, the 2-bit-time high-level start-of-
2
idle pulse prescribed by IEEE 802.3 1 BASE5 causes the one-shot to time out and automatically place the
driver outputs in the high-impedance state. This delay time is also adjustable for use in other applications.
o
l=
The driver implements an output slew-rate control that is internally set for nominally 40 mV/ns. (This is
roughly a 1OO-ns peak-to-peak differential transition time.) The driver outputs are capable of driving a 50-ohm
differential load with a guaranteed minimum output level of 2 volts. Short-circuit output current is guaranteed ~
to be greater than 100 milliamperes. a:
ou.
-2w
(.)
2

c>

TEXAS ~ 4-65
INSTRUMENTS
SN75061 ADVANCE
Supply voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (any logic input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Receiver differential input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25 V
Receiver input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 5 V
Driver output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.5 V to 15 V
OW or J package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " 1025 mW
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " 11 50 mW
Lead temperature 1.6 mm (1/16 inch) from case for 60.seconds: J package. . . . . . . . . . . .. 300C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: OW or N package . . . . . .. 260C
_ NOTE 1: For operation above 25C freeair temperature, derate the OW and J packages to 656 mW at 70C at the rate of 8.2 mW/oC,
_ and the N package to 736 mW at 70C at the rate of 9.2 mW/OC.

MIN NOM MAX UNIT
Driver highlevel input voltage, VIH 2 V
Driver lowlevel input voltage, VIL 0.8 V
Driver high level output current, IOH -150 mA
Driver lowlevel output current, IOL 150 mA
Receiver commonmode input voltage, VIC (see Note 2) -2.5 5 V
External timing resistance, Rext 5 260 k!1
External timing capacitance, Cext No restriction
Operating free air temperature, T A 0 70 c
NOTE 2: The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet
for commonmodeinput voltage VIC and threshold levels VTH and VTL'

c
<

2
(")
m
2!
."
o
::xJ
S

::!
o
2!
4-66 TEXAS
INSTRUMENTS
ADVANCE SN75061
electrical characteristics over recommended operating free-air and supply voltage range (unless
otherwise noted)
driver
VIK Input clamp voltage II= -18 mA -1.5 V
RL = 50 fl 2 2.4 3.3
VOD Differential-output voltage V
RL = 115 fl 3.65
Change in differential-output voltage
AVOD 50 mV
for a change in logic input state
IIH High-level input current VI = 2.4 V 20 p.A
IlL Low-level input current VI = 0.5 V -35 p.A
lOS Short-circuit output current Vo = 0 V or 6 V, VI = 0.8 V or 2.5 V 100 300 mA
10Z High-impedance output current VCC = 5.25 V

I VOC = 10 V 100
p.A
I VOC
01
= 0 -100
receiver
PARAMETER TEST CONDITIONS MIN Typt MAX UNIT en
110.
VIK Input clamp voltage, squelch delay II = -18 mA -1.5 V Q)
Vo = 2.7 V, 10 = -0.4 mA, >

VTH Differential-input high-threshold voltage 50 mV 'iii
VIC =5V (.)
Vn
Differential-input low-threshold
voltage (see Note 2)
Vhys Hysteresis (VTH - Vn)
VIC Common-mode input voltage
Vo = 0.5 V,
VIC = 5 V
10 = 16 mA,
-50
50
5
mV
mV
V
-
a::
Q)
en
110.
Q)
>
RXO VCC = 4.75 V, 10H = -400 p.A, 2.7 'i:
sao SODLAJ at 0.8 V 2.7 3.5 C
VOH High-level output voltage V Q)
VCC = 4.75 V, 10H = -20 p.A, c
SORXO 2.7 4.65
VID(RXI) = -0.7 V, SODLAJ open :,:j
RXO 10L = 8 mA 0.45
VCC = 4.75 V,
10L = 16 mA 0.5
sao SODLAJ at 2 V
VOL Low-level output voltage 10L = 8 rnA 0.35 0.5 V
VCC = 4.75 V, 10L = 8 mA 0.45
SORXO
VID(RXI) = 50 mV IOL = 16 mA 0.5
VI = 2.4 V
SODU
20 p.A
z
RXO
VI = 0.5 V
= =
-15
-35
-85
p.A
o
lOS Short-circuit output current sao
Vcc 5.25 V, Va 0
-15 -100 mA i=
SORXO VCC = 5 V, Va = 0 -0.8 -1 -1.2

q Input resistance 10
-630
kfl
~
Squelch preset threshold voltage -570 -600 mV
a:
Ratio of Squelch Threshold Adjust input
voltage to actual squelch threshold voltage
SOTHAJ at 200 mV to 4 V -1.9 -2.1 oLL
driver and receiver
ICC Supply current

VCC = 5.25 V, Driver outputs disabled,
70
-w
Z
No loads (.)
z
t All typical values are at VCC = 5 V, T A = 25C.
NOTE 2: ,The algebraic convention, in which the less-positive (more negative) limit is designated as minimum, is used in this data sheet
for common-mode input voltage VIC and threshold levels VTH and VTL. >
c

TEXAS . . 4-67
INSTRUMENTS
POST OFFICE BOX 655012' OALLAS. TEXAS 75265
SN75061 ADVANCE
switching characteristics, vee = 5 V, T A

driver
SR Differential-output slew rate

Vo = -2 V to 2 V,
40 mV/ns
28 52
R1 = 100 n (differential), See Figure 1
Differential-output delay time C1 = 15 pF,
tOD 128 140 ns
(too + and tOD - ) R1 = 100 0 (differential), See Figure 2
Differential-output delay time
tDD+ -tDD- R1 = 100 n (differential), See Figure 2 5 ns
difference
....!!:!:!L 220 ns
Disable time from DATEN
tpLZ 250 ns
See Figures 3, 4, and 5 ns
~ Enable time from DATEN
220
tpZL 290 ns
III
tpZH Enable time from DLEN 250 ns
Enable duration time
tw(en) Cext ' = 100 pF, Rext = 62 kn, See Figure 6 2 2.5 3 /ls
(with DLEN low)
I'"'"
5' receiver
(1)
c... ten(RX) Receiver enable time Squelch off, See Figure 7 56 ns
c' tpLH Propagation delay time, low-to-high-Ievel output Squelch off, See Figure 8 20 35 ns
...VI
(1)
tpHL Propagation delay time, high-to-Iow-Ievel output Squelch off, See Figure 8 22 35 ns
Cext = 50 pF, Rext = 51 kn,
i(1) t unsq Unsquelch duration time
See Figure 9
1 1.2 1.45 /ls
C') Cext = 0, Rext = 6.8 kn,

(1) 180 ns
See Figure 9
c'
...VI
(1)
5V
Rext - 62 kn
ORDLAJ
~
. ---3V

c OLEN at 3 V - - - - - ,
~ Cext - 100 pF INPUT
OV
<
~-e----~--ORO+
OUTPUT
:2
(")
o-"'---'--DRO - OUTPUT-- _ I- ______~2::'" --OV
m ~~I I
- --2 V
-
:2
-n
DATEN at 0.5 V
tr -+\ /4- SR _-1JL
-+I
tr or tf
j4- tf
o TEST CIRCUIT
FIGURE 1. DRIVER SLEW RATE MEASUREMENTS

VOLTAGE WAVEFORMS
::JJ
s: NOTE A: The input pulse is supplied by a generator having the following characteristics: PRR !> 1 MHz, Duty Cycle!> 50%, tr !> 6 ns,
tf!> 6 ns, Zout = 50 n.
::!
o
:2
4-68 TEXAS ~
INSTRUMENlS
ADVANCE SN75061

SV
Rext - 62 kfl
DRDLAJ
~
--3V
*,C cxt - 100 pF INPUT 1.S V 1.5 V

OLEN at 3 V - - - . . . ,
I i 0 V
r--~------~----~DRO+ I+-
tDD+~ It- tDD-~
~
+-_VO+
RL -
OUTPUT OUTPUT SO%
100 fl
~~--------e-----~DRO- VO-
DATEN at O.S V
TEST CIRCUIT
FIGURE 2. DRIVER DIFFERENTIAL DELAY TIMES

VOLTAGE WAVEFORMS
II
...
en
Q)
SV
Rext - 62 kfl
>
'4)
DRDLAJ (,)
INPUT 1.SV 1.SV

3V -...
Q)
a:
en
Q)
>
I + ---OV 'i:
C
tPZH-H tPHZ~ O.S V
~
i.-VOH Q)
E:
OUTPUT -f :::i
2.3 V _

2
o
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR s 1 MHz, Duty Cycle s SO%, tr S 6 ns,
i=
tf s 6 ns, Zout = SO fl.
C. The input pulse is supplied by a generator having the following characteristics: PRR s SOO kHz, Duty Cycle s SO%,
~
tr S 6 ns, tf S 6 ns, Zout = SO fl.
a:
oLL
-2w
CJ
2

c>

TEXAS
INSTRUMENTS
-111 4-69
SN75061 ADVANCE

5V
Rext - 62 kfl
DRDLAJ
'::I:' Cext - 100 pF
~
3V
OLEN at 3 V - - - . . . , _ SV
INPUT 1.5V 1.SV .
- RL -
100 fl I ~---OV
DRI at
'"'O-......- ...-OUTPUT
I I
av or 3 V tPZL--t I+- tPLZ-+! 14-
I I
~
I ==5V
OUTPUT 2.3 V 1..
II
- "" -VOL
0.5 V
r TEST CIRCUIT VOLTAGE WAVEFORMS

:i'
(I) FIGURE 4. DRIVER ENABLE AND DISABLE TIMES
...c 5V
<'
...
-
(I) Rext - 62 kfl
C/I DRDLAJ
:c
LI1.SV
INPUT " ---3V
CD
n ~ '----OV
k- tPZH1
CD
<'
...
CD
,",o-....--4I~OUTPUT
~
C/I ---VOH
RL - OUTPUT 2.3 V "
100 fl
--==QV
c FIGURE 5. ENABLE TIMES FROM DELAY ENABLE
<
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ::5 500 kHz, Duty Cycle ::5 50%,
tr ::5 6 ns, tf ::5 6 ns, Zout = 50 fl.
:2 C. The input pulse is supplied by a generator having the following characteristics: PRR::5 1 MHz, Duty Cycle ::5 50%, tr ::56 ns,
(") tf::5 6 ns, Zout = 50 fl.
m
:-2
."
o
:ll
S
::!
o
:2
4-70 TEXAS
INSTRUMENlS
ADVANCE SN75061

SV
Rext - 62 kfl
DRDLAJ
~ Cext - 100 pF
OLEN at 0.5 V - - - - . .
RL -
100 fI
DATEN at 3 V
TEST CIRCUIT
rtw/en)~ O.S V 'a;

-
en
CD
:>
(.)
.
OUTPUT---.7""2.3 V
~:-VOH
~
. OV
--
a::
CD
en
CD
:>
VOLTAGE WAVEFORMS ''::::
C
FIGURE 6. ENABLE DURATION TIME WITH DELAY ENABLE LOW
CD
c:
SV :::i
Rext - 51 kfl
SODLAJ
INPU 3V
* C ext - SO pF I ----OV
-+I I+- ten/RX)
2
~
VOH
1.SV-......;.;.;..;.;...-a >----~ ....-OUTPUT OUTPUT 1.3 V 1.3 V

o
OPEN----i - - -VOL i=
<C
SORXO SODU
~
TEST CIRCUIT VOLTAGE WAVEFORMS a:
FIGURE 7. RECEIVER ENABLE (UNSQUELCH) TIMES o
LL
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR S 500 MHz, Duty Cycle s 50%,
tr S 6 ns, tf S 6 ns, Zout = 50 fl.
-2w
C. The input pulse is supplied by a generator having the following characteristics: PRR s 200 kHz, Duty Cycle s 50%, tr s6 ns, (.)
tfs 6 ns, Zout = 50 fl.
2
<C
>
c
<C
TEXAS ~ 4-71
INSTRUMENTS
SN75061 ADVANCE
5V
SODLAJ
Rext - 51 kfl
--3V
INPUT 1.5V 1.5V
I I OV
tPLH~ I+- tPHL-+! If-
~
+--VOH
~----e---OUTPUT
OUTPUT 1.3 V 1.3 V
VOL
3V
FIGURE 8. RECEIVER PROPAGATION DELAY TIMES
5V
3V
INPUT 1.5 V 1.5 V
+-~OV
tunsq~ 14-
~
VOH
1.5 V _--..,;.R;.;.;X;.;.;I--CI OUTPUT 1.3V 1.3V
OPEN SOTHAJ - - -VOL

I---....;;",;;;~OUTPUT

FIGURE 9. UNSQUELCH DURATION TIME
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR :5 1 MHz, Duty Cycle :5 50%, tr :5 6 ns,
o
tf :5 6 ns, Zout = 50 n.
C. The input pulse is supplied by a generator having the following characteristics: PRR :5 100 kHz, Duty Cycle :5 50%,
<
tr :5 6 ns, tf :5 6 ns, Zout = 50 n.
2
(")
m
-
2
."
o
::a
3:
:::!
o
2
4-72 TEXAS . .
INSTRUMENTS
SN55107A, SN551078, SN55108A, SN551088
SN75107A, SN751078, SN75108A, SN751088
DUAL LINE RECEIVERS
02304, JANUARY 1977 - REVISED OCTOBER 1986
High Speed SN55107A, SN55107B.SN55108A

SN55108B ... J PACKAGE
Standard Supply Voltage SN75107A, SN75107B, SN75108A
SN75108B ... D. J. OR N PACKAGE
o Dual Channels (TOP VIEW)
High Common-Mode Rejection Ratio 1A VCC+
o High Input Impedance 18 VCC-
NC 2A
High Input Sensitivity 28
Differential Input Common-Mode Range of NC
3 V 2Y
GND 2G
Strobe Inputs for Receiver Selection
Gate Inputs for Logic Versatility SN55107A.SN55107B. SN55108A.
III
SN55108B ... FK PACKAGE
TTL Drive Capability (TOP VIEW)
High DC Noise Margin + I
UU
m<l:UUU t/)
'107A and '1078 Have Totem-Pole Outputs ...... Z a..
Q)
'108A and '1088 Have Open-Collector 3 2 1 20 19 >
Outputs NC 4 18 2A
'Q)
(,)
NC NC Q)
-a::
5 17
"8" Versions Have Diode-Protected Input
for Power-Off Condition 1Y 6 16 28
t /)
NC 7 15 NC a..
Q)
1G 8 14 NC
description >
'Ii::
9 1011 1213
These circuits are TTL-compatible high-speed C
cnoUCD>-
line receivers. Each is a monolithic dual circuit ZZNN Q)
CD ~
featuring two independent channels. They are
::;
designed for general use as well as such specific NC-No internal connection
applications as data comparators and balanced,
unbalanced, and party-line transmission
systems. These devices are unilaterally
interchangeable with and are replacements for
the SN55107, SN55108, SN75107, and
SN751 08, but offer diode-clamped strobe inputs
to simplify circuit design.
The essential difference between the" A" and "B" versions can be seen in the schematics. Input-protection
diodes are in series with the collectors of the differential-input transistors of the "8" versions. These diodes
are useful in certain "party-line" systems that may have multiple Vee + power supplies and may be operated
with some of the Vee + supplies turned off. In such a system, if a supply is turned off and allowed to
go to ground, the equivalent input circuit connected to that supply would be as follows:
INPUT-"~M-d-lIM-""'''''''*
"A" VERSION "B" VERSION
This would be a problem in specific systems that might possibly have the transmission lines biased to
some potential greater than 1.4 volts.
The SN551 07 A, SN55107B, SN55108A, and SN55108B are characterized for operation over the full
military temperature range of - 55 e to 125 e. The SN75107 A, SN75107B, SN751 08A, and SN751 08B
are characterized for operation from 0 C to 70 o e.
Copyright 1981, Texas Instruments. Incorporated
PRODUCTION DATA documents contain information
to specifications per the terms of Texas Instruments
TEXAS-. 4-73
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
logic symbols t
SN55107 SN5510a
SN75107 SN7510a
S S
1A 1A
1B 1B
1G 1G
2A 2A
2B 2B
2G (8) 2G (B)
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
_ Pin numbers shown are for 0, J, and N packages.
_ _ logic diagram (positive logic)

S (6)
r-
5'
(1)
...c
<'
...
(1)
-
en
::JJ
(1)
(')
1G...:..;;..:..----...J
2G...:..;;..:..----...,
(1)
<' 2A
...
(1)
en
FUNCTION TABLE
DIFFERENTIAL
INPUTS STROBES OUTPUT
A-B G S Y
VID 2: 25 mV X X H
X L H
- 25 mV < VIO < 25 mV L X H
H H Indeterminate
X L H
VID :5 -25 mV L X H
H H L
4-74 TEXAS ~
INSTRUMENTS
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107~ SN75108A, SN7510BB
DUAL LINE RECEIVERS
schematic (each receiver)

114} ,
VCC+--'--1~--~---1~-4'-------~'-------_'----
1 kG 1 kG 400 G 4 kG 1.6 kG
y
11.12}
1A
INPUTS
GND
1B 12. 11}
STROBE
G
3 kG 3 kG
II tJ)
~
113} STROBE Q)
VCC_--+-----.------1~-4~-----.--~------------
S :>
'0)
CJ
Q)
-
TO OTHER RECEIVER
ex:
tR = 1 kO for '107A and '1078, 750 n for '10BA and '10B8. tJ)
NOTES: 1. Resistor values shown are nominal. ~
Q)
2. Components shown with dashed lines in the output circuitry are applicable to the '107A and '1078 only. Diodes in series
with the collectors of the differential input transistors are short-circuited on '107 A and '10BA.
:>
'i:
C
absolute maximum ratings over operating free-air temperature range. (unless otherwise noted) Q)
'C
Supply voltage, VCC + (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V :::i
Supply voltage, VCC - ... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 7 V
Differential input voltage (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Common-mode input voltage (see Note 5) ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 V
Strobe input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
D package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 950 mW
FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1375 mW
J package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package .. ' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; . . . . . . . . . .. 1150 mW
Operating free-air temperature range: Series 55 . . . . . . . . . . . . . . . . . . . . . . . . .. - 55C to 125C
Series 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OC to 70C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package. . . . . . . .. 260C
NOTES: 3. All voltage values, except differential voltages, are with respect to network ground terminal.
4. Differential voltage values are at the noninverting (A) terminal with respect to the inverting (8) terminal.
5. Common-mode input voltage is the average of the voltages at the A and 8 inputs.
6. For operation above 25C free-air temperature. derate linearly at the following rates: 7.6 mW/oC for the D package. 11.0
mW/oC for the FK package. B.2 mW/oC for the J package. and 9.2 mW/oC for the N package.
TEXAS 4-75
INSTRUMENTS
POST bFFICE BOX 655012 ' DALLAS. TEXAS 75265
SN55107A, SN551078, SN5510BA, SN5510B8
SN75107A, SN751078, SN7510BA, SN7510B8
DUAL LINE RECEIVERS
recommended operating conditions (see Note 7)

SN55107A, SN55107B SN75107A, SN75107B
SN5510BA, SN5510BB SN7510BA, SN7510BB UNIT
Supply voltage, VCC+ 4.5 5 5.5 4.75 5 5.25 V
Supply voltage, VCC- -4.5 -5 -5.5 -4.75 -5 -5.25 V
High-level input voltage between differential inputs,
0.025 5 0.025 5 V
VIDH (see Note B)
Low-level input voltage between differential inputs,
-5 t -0.025 -5 t -0.025 V
VIOL (see Note B)
Common-mode input voltage, VIC (see Notes Band 9) -3 t 3 -3 t 3 V
Input voltage, any differential input to ground (see Note B) -5 t 3 -5 t 3 V
High-level input voltage at strobe inputs, VIH(S) 2 5.5 2 5.5 V
Low-level input voltage at strobe inputs, VIL(S) 0 O.B 0 0.8 V

Low-level output current, IOL -16 -16 mA
Operating free-air temperature, T A -55 125 0 70 DC
t The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for input
voltage levels only.
NOTES: 7. When using only one channel of the line receiver, the strobe G of the unused channel should be grounded and at least one
of the differential inputs of the unused receiver should be terminated at some voltage between - 3 V and 3 V.
B. The recommended combinations of input voltages fall within the shaded area of the figure shown.
9. The common-mode voltage may be as low as - 4 V provided that the more positive of the two inputs is not more negative
than -3 V.
RECOMMENDED COMBINATIONS
OF INPUT VOLTAGES
3 ...--~-..--
>
~ 2
Cl
S
"0
::::- 0
"C
-1
o
0-2
o
; -3
~ -4
.E -5
-5 -4 -3-2 -1 0 2 3
Input B to Ground Voltage-V
4-76 TEXAS . .
INSTRUMENTS
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
electrical characteristics over recomlTllded free-air temperature range (unless otherwise noted)
'107A, '1078 '10BA, '10BB
PARAMETER TEST CONDITIONst UNIT
High-level A VIO = 5 V 30 75 30 75
IIH Vcc = MAX p.A
input current --S VIO = -5 V 30 75 30 75
Low-level A VIO = -5 V -10 -10
IlL VCC = MAX p.A
input current E3 VIO = 5 V -10 -10
High-level input current VCC = MAX, VIH(S) = 2.4 V 40 40 p.A
IIH
into lG or 2G VCC = MAX, VIH(S) = MAX VCC + 1 1 rnA
IlL VCC = MAX, VIL(S) = 0.4 V -1.6 -1.6 rnA
into lG or 2G
High-level input VCC = MAX, VIH(S) = 2.4 V BO 80 p.A
IIH
current into S VCC = MAX, VIH(S) = MAX VCC 2 2 rnA

Low-level input
IlL VCC = MAX, VIL(S) = 0.4 V -3.2 -3.2 rnA
current into S
High-level VCC = VIL(S) = O.B V, VIDH
MIN, = 25 mV,
VOH 2.4 V
output voltage IOH = -400p.A,VIC = -3Vt03V
VOL
Low-level
output voltage
VCC = MIN,
IOL = 16 rnA,
VIH(S) = 2 V, VIOL
VIC = - 3 V to 3 V
= -25 mV,
0.4 0.4 V ...
t/)
Q)
High-level >
10H VCC = MIN, VOH = MAX VCC + 250 p.A '0)
output current (J
lOS
Short-circuit
output current
Supply current from
ICCH + VCC +, outputs high
VCC
VCC
=
=
MAX
MAX, TA = 25C
-18
lB
-70
30 lB 30
rnA
rnA
-...
a:
Q)
t /)
Q)
>
'i:
Supply current form
ICCH - VCC _, outputs high VCC = MAX, TA = 25C -8.4 -15 -8.4 15 rnA C
Q)
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating ~onditions. c
* All typical values are at VCC+ = 5 V, VCC- = -5 V, TA = 25C.
::i
Not more than one output should be shorted at a time.
switching characteristics, Vee -+ = 5 V, TA 25e, see Figure 1

'107A, '1078 '10BA, '10BB
Propagation delay time, low-to-high-Ievel RL = 3900, CL = 50 pF 17 25
tpLH(O) ns
output, from differential inputs A and B RL = 3900, CL = 15 pF 19 25
Propagation delay time, high-to-Iow-Ievel RL = 3900, CL = 50 pF 17 25
tpHL(O) ns
output, from differential inputs A and B RL = 3900, CL = 15 pF 19 25
Propagation delay time, low-to-high-Ievel RL = 3900, CL = 50 pF 10 15
tpLH(S) ns
output, from strobe input G or S RL = 3900, CL = 15 pF 13 20
Propagation delay time, high-to-Iow-Ievel RL = 3900, CL = 50 pF B 15
tpHL(S) ns
output, from strobe input G or S RL = 3900, CL = 15 pF 13- 20
TEXAS 4-77
INSTRUMENTS
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
DIFFERENTIAL VCC-
INPUT
r----- 1 ------, OUTPUT
'107A, '107B
lA' I
'~r---------~I~ 11y
390 !1
OUTPUT
.....-----i'-"IN'I,----..........- '1 OSA, '10SB
~-+-e--+-"'----I CL !, 5 pF
STROBE
J.(see Note C)
INPUT
(See Note B)
TEST CIRCUIT
IN~UT ---F\::oo
m~ mV 100
II I
I ~ ____J '------OV
I . I
14----tp2----~
~tpl~
I I
I 3V
STROBE I I
INPUT II II 1.5V 1.5V
G or S I -+I k-tPHL(D) '___ _ _ _ _ -JJ. ____ 0 V
tPLH(D)-+j ~ I I I
OU~UT ~1-:H_(_S_)-+I_J75 V : {L~~:

VOLTAGE WAVEFORMS
NOTES: A. The pulse generators have the following characteristics: Zout = 50 fl, tr = 10 5 ns, tf = 10 5 ns, tpd 1 = 500 ns,
PRR :s 1 MHz, tpd2 = 1 "'s, PRR :s 500 kHz.
B. Strobe input pulse is applied to Strobe 1G when inputs 1 A-l B are being tested, to Strobe S when inputs 1A-l B or 2A-2B
are being tested, and to Strobe 2G when inputs 2A-2B are being tested.
D. All diodes are 1 N916.
4-78 TEXAS . .
INSTRUMENTS
SN55107A, SN551078, SN55108A, SN551088
SN75107A, SN751078, SN75108A, SN751088
DUAL LINE RECEIVERS
OUTPUT VOLTAGE HIGH-LEVEL INPUT CURRENT INTO 1A or 2A
vs vs
DIFFERENTIAL INPUT VOLTAGE. FREE-AIR TEMPERATURE
6
L
rs: 11 08A,I'1
1 1
08~
<t
100
I
VCC -
I 5 V
I
5
Nl~v~rting
::1.
> 1.
Invertlng
E
I 80
I Inputs _ Inputs - ~
~ 4 ~
:;
!!
"0
\ II u
:;
60
~:l 3 r\ \
'\
1\ '107A, '1078
Co
.E
Co
II
:; Gi "t--..,
--
> 40 ...........
~
CP
2 ...I
i'---.
o
> VCC-5V
RL - 400 n
TA - 25C
1:
E
CI
:f
I 20 --- r--
r-- ... (f)
Q)
:>
I I 1 'Q)
o o (.)
- 40 - 30 - 20 - 10 0
VID-Differential Input Voltage-mV
FIGURE 2
10 20 30 40 -75 -50 -25 0
T A - Free-Air Temperature -
FIGURE 3
25 50 75 100 125
c -...
a:
Q)
( f)
Q)
:>
'i:
'107A, '1078 C
PROPAGATION DELAY TIME Q)
SUPPLY CURRENT, OUTPUTS HIGH (DIFFERENTIAL INPUTS) c:
vs vs
::J
30 40
~
I
1
VCC _I 5 ~ VCC _I 5
35 -RL - 390 n
25
<t UI CL - 50 pF
E c 30
I
.!.c CP
---
20 ICC+ E
~
:;
U r-- - i=
>
co
25
......-V
> 15 Gi 20 _tPLH(D)
--- --
C. C
V-
Co
:l
CI)
I 10 ICC-
;
c
.2 15 l-
tPHL(D)
t--
--
CI
:I: co
Co
U 0 10
!:} Ii:
5
5
o o
-75 -50 -25 0 25 50 75 100 125 - 75 - 50 - 25 0 25 50 75 100 125
T A - Free-Air Temperature - c T A - Free-Air Temperature - DC
FIGURE 4 FIGURE 5
tValues below ooe and above 70 c e apply to SN55 Series only.
TEXAS . . 4-79
INSTRUMENTS
SN55107A, SN55107B, SN5510BA, SN5510BB
SN75107A, SN75107B, SN7510BA, SN7510BB
DUAL LINE RECEIVERS
'108A, '1088 '108A, '1088
PROPAGATION DELAY TIME, LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME, HIGH-TO-LOW LEVEL
(DIFFERENTIAL INPUTS) (DIFFERENTIAL INPUTS)
vs vs
120 40
UI
Vcc ~ 5 V
1
UI
111
C CL - 15 pF c f- vcc - 5 V
35
~ 100 V
I
CD
CL - 15 pF
E
i= ~
V E
i= 30
I---- ~ >
~ 80 m RL - 390 n""\
Qj Qj
c RL - 3900 n c 25
~
c
0
::~'- \
.;:; 20
~
f.-""" m
CI
r-.:::::: I----:
_L--- ~ m / ,I
r-rrr-
Q.
15
r-
0
c::
I
RL - 1950 n ,J
:i' / 10 RL - 3900 n
l...-- V
i5
CD ::i
J:
...c RL - 390 n So 5
:c' o I II o ,
...
-
CD
-75 -50 -25 0 25 50 75 100 125 -75 -50 -25 0 25 50 75 100 125
en
:JJ TA-Free-Air Temperature- C TA -Free-Air Temperature- C
CD
(') FIGURE 6 FIGURE 7
CD
:c' '107A, '1078 '108A, '1088
...en
CD
PROPAGATION DELAY TIME (STROBE INPUTS) PROPAGATION DELAY TIME (STROBE INPUTS)
vs
vs
40 40
1
VCC - 5V
1 1
VCb' 5 V
35 RL - 390 n 35 I- RL - 390 n
UI CL - 50 pF UI
CL - 15 pF
c c
I 30 I 30
CD CD
E E
i= 25 i= 25
~
> >
m
m
Qj Qj
c 20 c 20
V
c
.g
m
CI
m
Q.
0
c::
15
10
t!:H(S)
.-+-= T
_f--- ~
V
c
.g
m 15
CI
m
Q.
0
c::
10
t~(S)
~
tP~L(S)
-
L-- ~
~
~
5 r- tPHL(S) 5
o I I
-75 -50 -25 0 25 50 75 100 125
o
-75 -50 -25 0 25 50 75 100 125
TA-Free-Air Temperature- C TA-Free-Air Temperature- C

FIGURE 8 FIGURE 9
tValues below ooe and above 70 0 e apply to SN55 Series only.
4-80 TEXAS
INSTRUMENTS
SN55107A, SN551078, SN551 DBA, SN5510B8
SN75107A, SN751078, SN7510BA, SN7510B8
DUAL LINE RECEIVERS
basic balanced-line transmission system-

The'1 07 A, , 107B, , 1DBA, and' 1OBB dual line circuits are designed specifically for use in high-speed data
transmission systems that utilize balanced, terminated transmission lines such. as twisted-pair lines. The
system operates in the balanced mode, so noise induced on one line is also induced on the other. The
noise appears common-mode at the receiver input terminals where it is rejected. The ground connection
between the line driver and receiver is not part of the signal circuit so that system performance is not
affected by circulating ground currents.
The unique driver-output circuit allows terminated transmission lines to be driven at normal line impedances.
High-speed system operation is ensured since line reflections are virtually eliminated when terminated lines
are used. Crosstalk is minimized by low signal amplitudes and low line impedances.
The typical data delay in a system is approximately (30 + 1.3 L) nanoseconds, where L is the distance
in feet separating the driver and receiver. This delay includes one gate delay in both the driver and receiver.
Data is impressed on the balanced-line system by unbalancing the line voltages with the driver output
current. The driven line is selected by appropriate driver-input logic levels. The voltage difference is
II
... en
approximately: Q)
:>
VDIFF ::::: 1/210(on) RT 'Ci)
CJ
High series line resistance will cause degradation of the signal. The receivers, however, will detect signals Q)
as low as 25 mV (or less). For normal line resistances, data may be recovered from lines of several thousand
feet in length. -...
a::
en
Q)
:>
Line-termination resistors (RT) are required only at the extreme ends of the line. For short lines, termination
'i:
resistors at the receiver only may prove adequate. The signal amplitude will then be approximately: C
VDIFF ::::: 10 (on) RT Q)
t:
:,::j
A _ ..... __ .. -....
DATA INPUT TRANSMISSION LINE HAVING
y
CHARACTERISTIC IMPEDANCE Zo
C _ . . r - -.... RT = Zo/2
INHIBIT
D -'"'1-_" ~I STROBES
DRIVER RECEIVER
SN55109A. SN55110A. '107A, '107B, '108A, '108B
SN75109A. SN75110A,
SN75112
FIGURE 10
data-bus or party-line system

The strobe feature of the receivers and the inhibit feature of the drivers allow these dual line circuits to
be used in data-bus or party-line systems. In these applications, several drivers and receivers may share
a common transmission line. An enabled driver transmits data to all enabled receivers on the line while
other drivers and receivers are disabled. Data is thus time-mUltiplexed on the transmission line. The device
specifications allow widely varying thermal and electrical environments at the various driver and receiver
locations. The data-bus system offers maximum performance at minimum cost.
TEXAS ~ 4-81
INSTRUMENTS
SN55107A, SN55107B, SN5510BA, SN5510BB
SN75107A, SN75107B, SN7510BA, SN7510BB
DUAL LINE RECEIVERS
RECEIVER 1 RECEIVER 2 RECEIVER 4

DRIVERS
SN55109A, SN55110A, y y
SN75109A, SN75110A,
SN75112
STROBES STROBES STROBES
RT RT
RT
LOCATION 2
RECEIVERS:
DRIVER 1 DRIVER 3 DRIVER 4
'107A, '107B,
A A
DATA INPUT B '10BA, '108B
B
C C
III
INHIBIT D
D
LOCATION 1 LOCATION 3 LOCATION 4
FIGURE 11
I"'"
:r
CD
unbalanced or single-line systems
..,o These dual line circuits may also be used in unbalanced or single-line systems, Although these systems
<"
..,CD do not offer the same performance as balanced systems for long lines, they are adequate for very short
UI lines where environmental noise is not severe.
iCD The receiver threshold level is established by applying a dc reference voltage to one receiver input terminal.
n The signal from the transmission line is applied to the remaining input. The reference voltage should be
CD. optimized so that signal swing is symmetrical about it for maximum noise margin. The reference voltage
<"
..,
CD should be in the range of - 3 volts to 3 volts. It can be provided by a voltage supply or by a voltage divider
UI from an available supply voltage.
A single-ended output from a driver may be used in single-line systems. Coaxial or shielded line is preferred
for minimum noise and crosstalk problems. For large signal swings, the high output current (typically 27 mAl
of the SN75112 is recommended. Drivers may be paralleled for higher current. When using only one channel
of the line drivers, the other channel should be inhibited and/or have its outputs grounded.
SN55109A, SN55110A
SN75109A, SN75110A
SN75112 '107A, '107B
A
OUTPUT INPUT~108A'
'108B
INPUT
B Vref OUTPUT
C
INHIBIT STROBES
o
FIGURE 12
4-82
TEXAS ~
INSTRUMENlS
POST OFFICi BOX 655012 DALLAS, TEXAS 76265
SN55107A, SN551078, SN5510BA, SN5510B8
SN75107A, SN751078, SN7510BA, SN7510B8
DUAL LINE RECEIVERS
'108A, '1088 dot-AND output connections

The '1 08A, '1088 line receivers feature an open-
collector-output circuit that can be connected in
the dot-AND logic configuration with other
similar open-collector Jutputs. This allows a level
of logic to be implemented without additional
logic delay. Oo-HH-OUTPUT
increasing common-mode input voltage range of receiver

FIGURE 13 II
.... t/)
Q,)
The common-mode voltage range or CMVR is defined as the range of voltage applied simultaneously to
both input terminals that i~ exceeded does not allow normal operation of the receiver.
om::-
(,)
Q,)
The recommended operating CMVR is 3 volts, making it useful in all but the noisiest environments. In
extremely noisy environments, common-mode voltage can easily reach 10 V to 15 V if some precautions
are not taken to reduce ground and power supply noise, as well as crosstalk problems. When the receiver
-...
a:
t /)
Q,)
must operate in such conditions, input attenuators should be used to decrease the system common-mode ::-
0a:;:
noise to a tolerable level at the receiver inputs. Differential noise is also reduced by the same ratio. C
These attenuators have been intentionally omitted from the receiver input terminals so the designer may Q,)
select resistors that will be compatible with his particular application or environment. Furthermore, the
c::
:::i
use of attenuators adversely affects the input sensitivity, the propagation delay time, the power dissipation,
and in some cas.es (depending on the selected resistor values) the input impedance, therefore reducing
the versatility of the receiver.
The ability of the receiver to operate with TABLE B. TYPICAL PROPAGATION DELAYS FOR
approximately 1 5 volts common-mode voltage RECEIVER WITH ATTENUATOR TEST CIRCUIT
at the inputs has been checked using the circuit SHOWN IN FIGURE 14
shown in Figure 14. The resistors R1 and R2
provide a voltage divider network. Dividers with INPUT TYPICAL
DEVICE PARAMETERS
three different values presenting a 5-to-1 ATTENUATOR Ins)
attenuation were used so as to operate the 1 20
differential inputs at approximately 3 volts tPLH 2 32
common-mode voltage. Careful matching of the 3 42
two attenuators is needed so as to balance the '107A, '107B
1 22
overdrive at the input stage. The resistors used tpHL 2 31
are shown in Table A. 3 33
TABLE A 1 36
tpLH 2 47
Attenuator 1: R1 = 2 krl, R2 = 0.5 krl 3 57
Attenuator 2: R1 = 6 krl, R2 = 1.5 krl '108A, '108B
1 29
Attenuator 3: R1 = 12 kO, R2 =3 kO
tpHl 2 38
3 41
Table 8 shows some of the typical switching
results obtained under such conditions.
TEXAS 4-83
INSTRUMENTS
POST OFFICE BOX 655012 OA~lAS, TeXAS 71i265
SN55107A, SN551078, SN5510BA, SN5510B8
SN75107A, SN751078, SN7510BA, SN7510B8
DUAL LINE RECEIVERS
ONE 5V
ATTENUATOR
+16V } ON EACH
+14 V
Cv
---.Jr RL - 390 fl
R1
-16 V - - - - . / R2
+15 V
OR ~-...-.....---'
-15 V R1
III
r-
FIGURE 14. COMMON-MODE CIRCUIT FOR TESTING INPUT ATTENUATORS,
WITH RESULTS SHOWN IN TABLE B
Two methods of terminating a transmission line to reduce reflections are:

:i'
CD
METHOD 2
~J::~ -t>(!r:
R1
...c
<'CD... 3 R2
-
C/l
::tJ
CD
C')
R3 - R1 +
R1
R2 - lO/2
3
_ e--JVI/Ir-_ .R_2.....
R1
R1 + R2 > > lO
CD
<'CD R3 - lO/2
...
til
FIGURE 15
The first method uses the resistors as the attenuation network and line termination. The second method
uses two additional resistors for the line terminations.
4-84 TEXAS -I!}

INSTRUMENTS
SN55107A, SN551078, SN55108A, SN551088
SN75107A, SN751078, SN75108A, SN751088
DUAL LINE RECEIVERS

For party-line operation, method 2 should be used as follows:
~_r
:3- mR~ __-zo~-.~-------.--r-~
2
FIGURE 16
To minimize the loading, the values of R1 and R2 should be fairly large. Examples of possible values are
II t/)
~
(1)
shown in Table A. ::-
'iii
(.)
-
furnace control using the SN75108A (1)
a:
The furnace control circuit in Figure 17 is an example of the possible use of the SN551 07 A Series in areas t /)
other than what would normally be considered electronic systems. Basically the operation of this control ~
(1)
is as follows. When the room temperature is below the desired level, the resistance of the room temperature ::-
sensor is high and channel 1 noninverting input is below (less positive than) the reference level set on 'i:
the input differential amplifier. This situation causes a low output, operating the "heat on" relay and turning C
(1)
on the heat. The channel 2 noninverting input is below the reference level when the bonnet temperature t:
of the furnace reaches the desired level. This causes a low output, thus operating the blower relay. Normally ::i
the furnace is shut down when the room temperature reaches the desired level and the channel 1 output
goes high, turning the heat off. The blower remains on as long as the bonnet temperature is high, even
after the "heat on" relay is off. There is also a safety switch in the bonnet that shuts the furnace down
if the temperature there exceeds desired limitations. The types of temperature-sensing devices and bias-
resistor values used are determined by the particular operating conditions encountered.
5V
BONNET UPPER
BONNET
LIMIT SWITCH
TEMP
SENSOR
~
-- ---,
TO "HEAT ON"
RELAY
RETURN
TO BLOWER
RELAY
RETURN
FIGURE 17. FURNACE CONTROL USING SN75108A
TEXAS ~ 4-85
INsrRUMENTS
SN55107A. SN551078. SN55108A. SN551088
SN75107A. SN751078. SN75108A. SN751088
DUAL LINE RECEIVERS

repeaters for long lines
In some cases, the driven line may be so long that the noise level on the line reaches the common-mode
limits or the attenuation becomes too large and results in poor reception. In such a case, a simple application
of a receivf.r and a driver as repeaters [shown in Figure 18(a)) restores the signal level and allows an adequate
signal level at the receiving end. If multichannel operation is desired, then proper gating for each channel
must be sent through the repeater station using another repeater set as in Figure 18(b).
REPEATERS
I
r-
1\ ,
D~~A 1""-D-R-IV-E-R--'~-~-R-E-C-EI-V-ER"""H""-D-R-IV-E-R-."'~~---.J-R-E-C-E-IV-E"""R DATA

OUT
P P
a. SINGLECHANNEL LINE
DATA DATA
IN OUT
CLOCK
IN
P P
b. MULTICHANNEL LINE WITH STROBE
FIGURE 18. RECEIVER-DRIVER REPEATERS
receiver as dual differential comparator

There are many applications for differential comparators, such as voltage comparison, threshold detection,
controlled Schmitt triggering, and pulse width control.
As a differential comparator, a ' 107 A or ' 108A may be connected so as to compare the noninverting input
terminal with the inverting input as shown in Figure 19. Thus the output will be high or low resulting from
the A input being greater or less than the reference. The strobe inputs allow additional control over the
circuit so that either output or both may be inhibited.
STROBE 1
REFERENCE 1 OUTPUT 1
STROBE 1,2
OUTPUT 2
REFERENCE 2
-= STROBE 2
FIGURE 19. SN55107A SERIES RECEIVER AS A DUAL DIFFERENTIAL COMPARATOR
4-86 TEXAS ~
INSTRUMENTS
SN55107A, SN55107~ SN5510B~ SN5510BB
SN75107A, SN75107B, SN7510BA, SN7510BB
DUAL LINE RECEIVERS

window detector
The window detector circuit in Figure 20 has a large number of applications in test equipment and in
determining upper limits, lower limits, or both at the same time - such as detecting whether a voltage
or signal has exceeded its limits or "window". Illumination of the upper-limit (lower-limit) indicator shows
that the input voltage is above (below) the selected upper (lower) limit. A mode selector is provided for
selecting the desired test. For window detecting, the "upper and lower limits" test position is used.
+5 v -5 V 5V
1 kfl
UPPER
SET k>-7-II--'VVI........,I-F~ LIMIT
UPPER INDICATOR
LIMIT
INPUT
FROM
TEST
LOWER
...rn
Q)
POINT INDICATOR >
'CU
(,)
Q)
MODE
-a:...
rn
Q)
SELECTOR 'i:
>
MODE SELECTOR LEGEND
C
Q)
POSITION CONDITION c::
1 OFF :J
2 TEST FOR UPPER LIMIT
3 TEST FOR LOWER LIMIT
4 TEST FOR UPPER AND LOWER LIMITS
FIGURE 20. WINDOW DETECTOR USING SN75108A
TEXAS ~ 4-87
INSTRUMENTS
SN55107A, SN55107B, SN5510BA, SN5510BB
SN75107A, SN75107B, SN7510BA, SN7510BB
DUAL LINE RECEIVERS
temperature controller with zero-voltage switching

The circuit in Figure 21 switches an electric resistive heater on or off by providing negative-going pulses
to the gate of a triac during the time interval when the line voltage is passing through zero. The pulse
generator is the 2N5447 and four diodes. This portion of the circuit provides negative-going pulses during
the short time (approximately 100 ~s) when the line voltage is near zero. These pulses are fed to the inverting
input of one channel of the' 108A. If the room temperature is below the desired level, the resistance of
the thermistor is high and the non inverting input of channel 2 is above the reference level determined by
the thermostat setting. This provides a high-level output from channel 2. This output is AND'ed with the
positive-going pulses from the output of channel 1, which are reinverted in the 2N5449.
II ro
120 V TO
220 V
60 Hz
HEATER
LOAD
FIGURE 2.1. ZERO-VOLTAGE SWITCHING TEMPERATURE CONTROLLER
4-88
TEXAS -I.!}
INSTRUMENTS
SN55109A, SN55110A,
SN75109A, SN75110A, SN75112
DUAL LINE DRIVERS
02106, DECEMBER 1975-REVISED SEPTEMBER 1986
Improved Stability over Supply Voltage and SN55109A. SN55110A . . . J PACKAGE

Temperature Ranges SN75109A. SN7511 OA. SN75112 .
D. J. OR N PACKAGE
o Constant-Current Outputs
(TOP VIEW)
High Speed
1A VCC+
Standard Supply Voltages 18 1Y
1C 1Z
High Output Impedance
2C VCC-
High Common-Mode Output Voltage Range 2A D
(-3 V to 10 V) 28 2Z
GND 2Y
TTL Input Compatibility
Inhibitor Available for Driver Selection SN55109A. SN55110A ... FK PACKAGE
II
(TOP VIEW)
-55 DC to 125 DC ODC to 70 D C OUTPUT +
J or FK PACKAGE J or N PACKAGE FUNCTION U
al <X: U U >-
6-mA Current .-Z>'-
SN55109A SN75109A rJ)
Switch 2019 ~
1 2-mA Current a>

SN55110A SN75110A 1C 18 1Z :>
Switch
NC 17 NC "Qi
27mA Current (,)
SN75112 2C 16 VCC- a>
description
Switch
NC
2A
9 1011 12 13
15
14
NC
D -
a::
rJ)
~
a>
:>
The SN55109A, SN55110A, SN75109A, alOU>-N ".:
SN75110A, and SN75112 have improved NZZNN C
c.!)
output current regulation with supply voltage a>
and temperature variations. In addition, the NC - No internal connection
c:
higher current of the SN75112 (27 mAl allows
:.:i
data to be transmitted over longer lines. These
drivers offer optimum performance when used
with the SN55107A, SN55108A, SN75107A,
and SN75108A line receivers.
(3) & lA 111

1C
1B (2)
ENl
1C (3)
o (10)
1A 1Y
lB lZ 2C (4)
2A -'-'-----t 2Y
2A (5)
2B -'-'----... 2Z
'------' 2B (6)
tThis symbol is in accordance. with ANSI/IEEE Std 91-1984 and

lED Publication 617-12.
~~~~~~~~i~ar~:I~~e ~!~:i~~ti~r fl~o::~:~:t:~~s not INSTRUMENTS
SN55109A, SN55110A
SN75109A, SN75110A, SN75112
DUAL LINE DRIVERS
These drivers feature independent channels with common voltage supply and ground terminals. The
significant difference between the three drivers is in the output current specification. The driver circuits
feature a constant output current that is switched to either of two output terminals by the appropriate
logic levels at the input terminals. The output current can be switched off (inhibited) by low logic levels
on the enable inputs. The output current is nominally 6 milliamperes for the' 1 OSA, 12 milliamperes for
the '110A, and 27 milliamperes for the SN75112.
The enablelinhibit feature is provided so the circuits can be used in party-line or data-bus applications.
A strobe or inhibitor (enable 0). common to both drivers, is included for increased driver-logic versatility.
The output current in the inhibited mode, IO(off), is specified so that minimum line loading is induced when
the driver is used in a party-line system with other drivers. The output impedance of the driver in the inhibited
mode is very high-the output impedance of a transistor biased to cutoff.
The driver outputs have a common-mode voltage range of - 3 volts to 10 volts, allowing common-mode
III voltage on the line without affecting driver performance.

All inputs are diode clamped and are designed to satisfy TTL-system requirements. The inputs are tested
at 2.0 volts for high-logic-level input conditions and 0.8 volt for low-logic-level input conditions. These
test guarantee 400 millivolts of noise margin when interfaced with Series 54/74 TTL.
The SN551 OSA and SN5511 OA are characterized for operation over the full military temperature range
of -55C to 125C. The SN7510SA, SN75110A, and SN75112 are characterized for operation from
OOC to 70C.
FUNCTION TABLE (EACH DRIVER)
LOGIC ENABLE
OUTPUTSt
INPUTS INPUTS
A B C D Y Z
X X L X OFF OFF
X X X L OFF OFF
L X H H ON OFF
X L H H ON OFF
H H H H OFF ON

t When using only one channel of the line drivers, the
other channel should be inhibited and/or have its
outputs grounded.
4-S0
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 DALlAS. TEXAS 75265
SN55109A, SN55110A
SN75109A, SN75110A, SN75112
DUAL LINE DRIVERS

VCC+~(1~4~)-.__- .__~
ENABLE C ...:...(3:.:.. ...:..;4)_ _- . f

E NAB LED ...:...(1:..:.0~)t---I1-4
INPUT A .;.,(1,.:....~5)___. J
INPUT B-,,(2=6'--4-~
II
...fA
GNDJ(7~)~t.~====~t--1 Q)
>
'0)
(.)
I
I
I
I
CoMMOkTOBDTH DRiVERs I
-...
Q)
a:
fA
Q)
>
'i:
VCC_~(1~1~)+-+-____~ C
Q)
c:
:.::i
9 ... VCC+bUS
9 ... vcc_ bUS

L _ _ _ _ _ _ _ _ _ _ .J
v
TO OTHER DRIVER
TEXAS . " 4-91

INSTRUMENTS
SN55109A, SN55110A
SN75109A, SN75110A, SN75112
DUAL LINE DRIVERS
SN55109A SN75109A
SN75112 UNIT
SN55110A SN75110A
VCC+ Supply voltage (see Note 1) 7 7 7 V
VCC- Supply voltage -7 -7 -7 V
VI Input voltage 5.5 5.5 5.5 V
Output voltage range - 5 to 12 -5 to 12 - 5 to 12 V
D package 950
mW
25C free-air temperature (see Note 2) J package 1375 1025 1025
N package 1150 1150
Operating free-air temperature range -55 to 125 o to 70 o to 70 C
Storage temperature range -65 to 150 -65 to 150 -65 to 150 C
III
r-
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds IIDN package
package
300 300
260
260
300
260
260
C
:i' NOTES: 1. Voltage values are with respect to network ground terminal.
2. For operation above 25C free-air temperature, refer to Dissipation Derating Table. In the J package, SN551 09A and SN5511 OA
CD
..c<' chips are alloy mounted, and SN75109A and SN75110A chips are glass mounted.
.
CD
en PACKAGE

iCD RATING FACTOR TA
C')
D 950 mW 7.6 mW/oC 25C
CD FK 1375 mW 11.0 mW/oC 25C
<'
..
CD
en
J (Alloy-mounted chip)
J (Glassmounted chip)
N
1375 mW
1025 mW
1150 mW
11.0 mW/oC
8.2 mW/oC
9.2 mW/oC
25C
25C
25C
4-92 TEXAS ~
INSTRUMENTS
SN75109A.
SN55109A.
SN75110A
SN55110A UNIT
SN75112
TA ~ ooe 4.5 5 5.5 4.75 5 5.25
Supply Voltage Vee + V
TA < ooe 4.75 5 5.5
TA ~ ooe -4.5 -5 -5.5 -4.75 -5 -5.25
Supply voltage Vee- V
TA < ooe -4.75 -5 -5.5
Positive common-mode output voltage 0 10 0 10 V
Negative common-mode output voltage 0 -3 0 -3 V !
High-level input voltage. VIH 2 2 V I
Low-level input voltage. VIL 0.8 0.8 V I
Operating free-air temperature. T A -55 125 0 70 e
z
~
AJ~
~~
Z
U1~
(I)
Z
.....
U1
C
u::a
l:II
'"(I)
(I) Z
CZU1
c: ..... U1
l:IIU1-
r--C
_u::a
!::cl:II
Z :1>'"
m'" en
C(l)Z
=ZU1
_ ..... U1
m--
<U1-
=_C
III
~
(l)Nl:II
cD
w
Line Drivers/Receivers
SN55109A, SN55110A
SN75109A, SN75110A, SN75112
DUAL LINE DRIVERS
switching characteristics, VCC+ ... 5 V, VCC- ... -5 V, TA - 25C

FROM TO
PARAMETERt TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tpLH 9 15 ns
A or B Y or Z CL = 40 pF,
tpHL 9 15 ns
RL = 50 n,
tPLH 16 25 ns
Cor D Y or Z See Figure 1
tpHL 13 25 ns
t tPLH = Propagation delay time, low-to-high-Ievel output.

tpHL = Propagation delay time, high-to-Iow-Ievel output.

INPUT
II
AOR B
OUTPUT
r::-"----=C-L- Y
PULSE
T 40 pF .
r- GENERATOR #1
~ (See Note B)
:i'
CD
(See Note A) OUTPUT
PULSE
...c
CL Z
GENERATOR #2 T40pF
<' INPUT ~ (See Note BI
...
CD
C/J
COR D
50 n
iCD TEST CIRCUIT
C')
CD 3V
~~
<' INPUT
...
CD
C/J
AOR B
OV
I ,
r-- t w1--j
i I ~tw2~
----~--------~----~.r-~ : ; 3V
ENABLE ,
50% 50%
COR 0
I
: '------~- ,- - - - - -- OV
tpLH~
I
I
--
,,
I
-+l ;-
,
tpLH . . . : - tpHL
- - - - - - off
OUTPUT
:
50%
Y
on
,
OUTPUT
Z
4 50%
LJ_O~7~
I"" C'_______________________ off
on
VOLTAGE WAVEFORMS
NOTES: A. The pulse generators have the following characteristics: Zout = 50 n, tr = tf = 10 5 ns, tw1 = 500 ns, PRR :5 1 MHz,
tw2 = 1 /ls, PRR :5 500 kHz.
C. For simplicity, only one channel and the enable connections are shown.
4-94 TEXAS "'-!}

INSTRUMENTS
SN55109A, SN55110A
SN75109A, SN75110A, SN75112
DUAL LINE DRIVERS
ONSTATE OUTPUT CURRENT
vs
NEGATIVE SUPPLY VOLTAGE
SN55109A.SN75109A SN55110A. SN75110A

7 14
Vcc+ = 4.5 V Vc~+ = 4~5 V
~
E 6
.!.
Vo =-3V
TA = 25C (l- - ~
E 12 Vo =-3V
.!.c TA = 2SoC
~
:; 5 ~
:5 10
/
u
...
:l
4 I u
...
:l
8 I
III
S- S-
:l
0
~ 3 I :l
0
~ 6 I
/
n:I n:I
t; II t;
c
9
c
4
... en
2 9 Q)
>
C
o
1 / C

0
2 I "Qi
(,)
o
-3
l/ -4 -5 -6 -7
o
-3
V -4 -5 -6 -7 -...
a:
Q)
en
Q)
VCc_-Negative Supply Voltage-V Vcc_-Negative Supply Voltage-V >
".::::
FIGURE 2 FIGURE 3 C
Q)
c
SN75112 ::::i
35
--
VCC+=4.5 V
~
E
.!.c
~
:;
u
...
:l
S-
30
25
20
Vo =:""3 V
TA = 25C
I
/
/-- -- h
:l
0
~ 15
!!
en
C 10
/
9
c0

5
/
/
o J
-3 -4 -5 -6 -7
Vcc_-Negative Supply Voltage-V
FIGURE 4
TEXAS 4-95
INSTRUMENTS
SN55109A, SN55110A
SN75109A, SN75110A, SN75112
DUAL LINE DRIVERS
special pulse-control circuit

Figure 5 shows a circuit that may be used as a pulse generator output or in many other testing applications.
INPUT OUTPUTS
A y z
HIGH OFF ON +5V
LOW ON OFF
--,
r-
5'
(1)
c...
<'
INPUT - - - f - - - 4
+2.5 V '-e--f---4
1/2'109A, j
Z I
I
\
2 \ 3
\
\
\
4
... Or~~~:112
-
(1) V--.JCC-
en L GROUND
~---
::tJ
(1)
(')
(1)
<' TO OTHER
LOGIC AND
-5 V OUTPUT
...en
(1)
STROBE
INPUTS
INPUT PULSE 'n

..J L ZERO VOLTS
SWITCH
2 3 4 5 6
POSITION 1
OUTPUTPUL~ JLLrl[-u n-
-.J L
ZERO
VOLTS
FIGURE 5. PULSE CONTROL CIRCUIT
4-96 TEXAS -I.!}

INSTRUMENTS
SN75111
Similar to a Dual Version of SN75109A line D. J. OR N

Driver DUALINLlNE PACKAGE
(TOP VIEW)
o Improved Stability Over Supply Voltage and
Temperature Ranges 1A VCC+
1Y 4A
o Constant-Current Outputs
1Z 4Y
High Output Impedance 2Z 4Z
2Y 3Z
G High Common-Mode Output Voltage Range
ENABLE 3Y
(-3 V to 10 VI 2A 3A
G Glitch-Free Power-Up/Power-Down GND '-t..:::""-_ _J - ' VCC-
Operation
FUNCTION TABLE

o TTL Input Compatibility
OUTPUT
G Common Enable Circuit LOGIC ENABLE
CURRENT
INPUT INPUT
Z
.
Y
description
H H ON OFF en
The SN75111 features four line drivers with a L H OFF ON Q)
common enable input. When the enable input is H L OFF OFF >
high, a constant output current is switched L L OFF OFF 'iii
(,)
between each pair of output terminals in
response to the logic level at that channel's
input. When the enable is low, all channel
outputs are non conductive (transistors biased to
cutoff). This minimizes loading in party-line
L = low logic level
H = high logic level
logic symbol t
-.
Q)
a:
en
Q)
>
'':
systems where a large number of drivers share C
the same line: Q)
c:
The driver outputs have a common-mode voltage ::J
range of - 3 volts to 10 volts, allowing common- lY
mode voltages on the line without affecting lZ
driver performance. 2Y
All inputs are diode clamped and are designed 2Z
to satisfy TTL-system requirements. The inputs 3Y

are tested at 2 volts for high-logic-level input 3Z
conditions and 0.8 volt for low-logic-level input 4Y
conditions. These tests guarantee 400 millivolts 4Z
of noise margin when interfaced with Series
54/74 TTL. t This symbol is in accordance with ANSI/lEEE Std 91-1984 and
ooe to 70 oe.
~~~~~:~~i~a{~:I~~~ ~!~~~~ti~r ~~o::~:~:t:~~s not INSTRUMENTS
POST OFFiCe BOX 655012 ' DALLAS. TeXAS 75265
SN75111
ENABLE
1Y
1A----t--l
1Z
2Y
2A----+--I
2Z
3Y
3Z
III
r-
5'
4A------I
4Y
4Z
CD schematics of inputs and outputs

C
.. EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS
<'
CD r - - - - - - OUTPUT
-
~
: 'l
CD
C')
VCC+---------.-----
CD
<'
CD
~ INPUT ---4t--....-l
'--,...------ OUTPUT
VCC-~------~~-----
--9----41,......----'-- VCC-
GNO_e_--
4-98 TEXAS . .
INSTRUMENTS
SN75111
Supply voltage, Vcc + (see Note 1) ............ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 7 V
Supply voltage, VCC - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7 V
Input voltage (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Output voltage range (any output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 5 V to 12 V
o package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950 mW
J package ...... '.' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package ......................................................... 11 50 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . . .. ooC to 70C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N package .......... 260C
2. For operation above 25C free-air temperature, derate the D package to 608 mW at 70C at the rate of 7.6 mW/oC, derate
the J package to 656 mW at 70C at the rate of 8.2 mW/oC, and the N package to 736 mW at 70C at the rate of 9.2
mW/oC. In the J package the SN75111 is glass mounted.
II CJ)
a..
Q)
>
recommended operating conditions 'Q)
CJ
Supply voltage, VCC +

Supply voltage, V CC-
MIN
4.75
-4.75
2
NOM
5
MAX
5.25
-5 -5.25
5.5
UNIT
V
V
V
-
a:
Q)
CJ)
a..
Q)
>
Low-level input voltage, VIL 0 0.8 V 'i:
! VOCR+ 0 10 V C
Common-mode .output voltage 'range Q)
!VOCR- 0 -3 V
t:
Operating free-air temperature, T A 0 70 c :.:::;
NOTE 3: All unused outputs must be grounded.
electrical characteristics over recommended operating free-air temperature range, Vee + 5.25V,
VIK Input clamp voltage II = -12 mA -0.9 -1.5 V
10 (on) On-state output current

VCC+ = 5.25 V, VCC- - -5.25 V 5.5 7
mA
VCC+ = 4.75 V, VCC- = - 4.75 V 3.5 5.5
10 (off) Off-state output current VCC+ = 4.75 V, VCC- = -4.75 V 100 /lA
VI = 2.4 V 40 /lA
VI = 5.25 V 1 mA
IlL Low-level input current VI = 0.4 V -1.6 mA
Enable at 2 V 28 40
ICC+ Supply current from VCC+ A inputs at 0.4 V mA
Enable at 0.4 V 27 40
Enable at 2 V -43 -55
ICC- Supply current from V CC- A inputs at 0.4 V mA
Enable at 0.4 V -25 -35
t All typical values are at VCC + 5 V, VCC-
TEXAS ~ 4-99
INSTRUMENTS
SN75111
switching characteristics, VCC+ = 5 V, VCC- -5 V, RL-= 500, CL = 40 pF, TA

FROM TO TEST
PARAMETER MIN TYP MAX UNIT
(INPUT) (OUTPUT) CONDITIONS
tpLH Propagation delay time, low-to-high-Ievel output A Y or Z 9 15 ns
tpHL Propagation delay time, high-to-Iow-Ievel output A Y or Z 7 15 ns
See Figure 1
tpLH Propagation delay time, low-to-high-Ievel output Enable Y or Z 14 25 ns
tpHL Propagation delay time, high-to-Iow-Ievel output Enable Y or Z 15 25 ns

AINPUT--------------~ ~------~----~~--- OUTPUTY
CL - 40 pF
III
r
ENABLE --------------~ D-------~.----- ....---- OUTPUT Z
CL - 40 pF
5'
CD
.<'
C
.
CD
en
=
TEST CIRCUIT
iCD
n
CD
<' A INPUT ~O% 50%
.
CD
en
I
I
I
I
I
I+- tw 1---+1
I
5---- o V-
I I
I I
I I
ENABLE 1 I
I I
I I OV
I ~tPHL
tPLH~
I I I
I off
I I
I
1 I
OUTPUT Y
I
I on
r--i'"f!F--------------- off
OUTPUT Z
I
-1--- - - - - - - - - - - - - - - on
k--+l--tPLH .
VOLTAGE WAVEFORMS
NOTES: A. The pulse generators have the following characteristics: Zo = 50 n, tr = tf = 10 5 ns, tw 1 = 200 ns, PRR :5 1 MHz,
tw2 = 1 p'S, PRR :5 500 kHz.
4-100 TEXAS
INSTRUMENlS
SN55113, SN75113
DUAL DIFFERENTIAL LINE DRIVERS
01315, SEPTEMBER 1973-REVISEO SEPTEMBER 1986
Choice of Open-Collector, Open-Emitter, or SN55113 ... J PACKAGE

3-State Outputs SN75113 ... D. J, OR N PACKAGE
(TOP VIEW)
High-Impedance Output State for Party-Line
Applications ' 1ZP VCC
1ZS 2ZP
Single-Ended or Differential AND/NAND 1YS 2ZS
Outputs 1YP 2YS
Single 5-V Supply 1A 2YP
1B 2A
Dual Channel Operation 1C 2C
Compatible with TTL GND CC
Short-Circuit Protection
SN55113 .. FK PACKAGE
High-Current Outputs (TOP VIEW)

Common and Individual Output Controls
Clamp Diodes at Inputs ,and Outputs
en ~ u t3~
N
3
,-Z>N
2 1 20 19
III
...
(I)
Easily Adaptable to SN55114 and SN75114 2ZS

Q)
1YS 4 18
>
Applications
1YP 5 17 2YS "Ci)
(,)
NC 6 16 NC
-...
Designed for Use with SN55115 and Q)
SN75115 1A 7 15 2YP a:
1B 8 14 2A ( I)
description 9 1011 12 13 Q)
>
The SN55113 and SN75113 dual differential line UOUUU
'-ZZUN
".::
drivers with three-state outputs are designed to l!) C
Q)
provide all the features of the SN55114 and
NC-No internal connection c
SN75114 line drivers with the added feature of :::i
driver output controls. Individual controls are
FUNCTION TABLE
provided for each output pair, as well as a
common control for both output pairs. If any INPUTS OUTPUTS
output is low, the associated output is in a high- OUTPUT CONTROL DATA AND NAND
impedance state and the output can neither drive C CC A Bt Y Z
nor load the bus. This permits many devices to L X X X Z Z
be connected together on the same transmission X L X X Z Z
line for party-line applications. H H L X L H
H H X L L H
The output stages are similar to TTL totem-pole
H H H H H L
outputs, but with the sink outputs,' YS and ZS,
and the corresponding active pull-up terminals, H = high level, L = low level. X = irrelevant,
YP and ZP, available on adjacent package pins. Z = high impedance (off)
tB input and 4th line of function table are applicable only
The SN55113 is characterized for operation over to driver number 1.
the full military temperature range of - 55C to
125C. The SN75113 is characterized for
operation over the temperature range of 0 C to
70C.
~
:~~~::~~i~ai~~I~~~ ~!=~:~ti:r ~~o::~:~:t:r~~s not INSTRUMENTS
SN55113. SN75113
logic symbolt logic diagram (positive logic)
&
lC (71
EN 1
CC
2C
1VP
lA
1VS
lZP 1A -=.:- .... r - -... <------'
18 lZS
lEe Publicatiori 617-12.

2YP
2YS
2ZP
2ZS
schematic
INPUT 1B INPUT 1A
(61 (51
(161 Vcc
AND 141 NAND

(11
PULL-UP PULL-UP
1YP 1ZP
NAND
AND
(21 SINK
SINK (31
OUTPUT
OUTPUT
1ZS
1YS
OUTPUT (71
CONTROL--------~
1C
W Vee bus
tThese components common to both drivers.
Resistor values shown are nominal and in ohms.
4-102 TEXAS ~
INSTRUMENTS
SN55113, SN75113
,absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Off-state voltage applied to open-collector outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 V
D package. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 950 mW
FK or J package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11 50 mW
Operating free-air temperature range: SN55113. . . . . . . . . . . . . . . . . . . . . . . . .. - 55C to 125C
SN75113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OOC to 70C
Storage temperature range ........... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65C to 150C
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds: D or N package. . . . . . . .. 260C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 260C

Lead temperature 1.6 mm (1/16 inch) from case for 60 seconds: J package ............. 300C
2. For operation above 25C freeair temperature, see Dissipation Derating Curves in Appendix A. In the J and FK packages, SN55113
chips are alloy mounted; SN75113 chips are glass mounted. In the N package, use the 9.2mW/oC curve for these devices.
...tn
Q)
>
SN55113 SN75113
'Q)
(J
UNIT
Q)
-a:...
Highlevel input voltage, VIH 2 2 V
tn
Q)
Lowlevel input voltage, VIL 0.8 0.8 V
Highlevel output current, IOH -40 -40 mA
>
'i:
Low-level output current, IOL 40 40 mA C
Operating freeair temperature, T A -55 125 0 70 C Q)
c
:.J
TEXAS ~ 4-103
INSTRUMENTS
SN55113, SN75113
noted)
SN55113 SN75113
PARAMETER TEST CONDITIONS t UNIT
VIK Input clamp voltage Vee = MIN. II = -12 mA -0.9 -1.5 -0.9 -1.5 V
Vee = MIN. VIH = 2 V. 10H = -10 mA 2.4 3.4 2.4 3.4
VOH Highlevel output voltage V
VIL = 0.8 V 10H = -40 mA 2 3.0 2 3.0
Vee = MIN. VIH = 2 V.
VOL Low-level output voltage 0.23 0.4 0.23 0.4 V
VIL = 0.8 V. 10L = 40 mA
VOK Output clamp voltage Vee = MAX. 10 = -40 mA -1.1 -1.5 -1.1 -1.5 V
TA = 25C 1 10
VOH = 12V
Off-state open-collector TA = 125C 200
1010f!) Vee = MAX I'A
output current TA = 25C 1 10
VOH = 5.25 V
= 70C
III
TA 20
TA = 25C. Vo = 0 to Vee 10 10
Off state Vee = MAX. Vo =0 -150 -20
10Z Ihigh-impedance-statel Output controls Vo = 0.4 V 80 20 I'A
r TA = MAX
output current at 0.8 V Vo = 2.4 V 80 20
:i'
CD Vo = Vee 80 20
..
c
c'
II
Input current
at maximum
A.B.e
Vee = MAX. VI = 5.5 V
1 1
mA
..
ee 2 2
input voltage
CD
-
High-level A.B.e 40 40
fI) IIH Vee = MAX. VI = 2.4 V I'A
input current ee 80 80
:D Lowlevel A.B.e -1.6 -1.6
CD IlL Vee = MAX. VI = 0.4 V mA
(') input current ee - 3.2 -3.2
CD Short-circuit
c'
..
CD
fI)
lOS
ICC
output current
Supply current
(both drivers)
Vee
TA =
= MAX.
All inputs at 0 V.
25C
Vo
No load.
= O. TA
Vee
Vee
=
=
=
25C
MAX
7 V
-40 -90
47
65
-120
65
85
-40 -90
47
65
-120
65
85
mA
mA
t All parameters with the exception of off-state open-collector output current are measured with the active pull-up connected to the sink output.
tAli typical values are at TA = 25C and Vee = 5 V. with the exception of ICC at 7 V.
Only one output should be shorted at a time. and duration of the short-circuit should not exceed one second.
switching characteristics, Vee - 5 V, eL ... 30 pF, TA = 25e

SN55113 SN75113
tpLH Propagation delay time. low-to-high-Ievel output 13 20 13 30 ns
See Figure 1
tpHL Propagation delay time. high-to-Iow-Ievel output 12 20 12 30 ns
tpZH Output enable time to high level RL = 180 n. See Figure 2 7 15 7 20 ns
tpZL Output enable time to low level RL = 250 n. See Figure 3 14 30 14 40 ns
tpHZ Output disable time from high level RL = 180 n. See Figure 2 10 20 10 30 ns
tpLZ Output disable time from low level RL = 250 n. See Figure 3 17 35 17 35 ns
4-104
INSTRUMENTS
TEXAS '1!1
SN55113, SN75113
1 kn
INPUT AND
~t---""'-OUTPUT
PULSE
GENERATOR
(See Note AI I NAND
so n I .....II---.....-OUTPUT
L ______ ~ ,...,.... CL=30pF
~ (See Note B)
TEST CIRCUIT
14- <;S ns
90%
-.I I+-..:S ns
;,.1_ _ _ _.....;I_L- ______
90% 1
3V IIIen
a-
I Q)
1\.,,;,10;;;,;%,;.,0_ _ _ _ _ 0 V >
"iii
--I~M--.PHL
...... v.,.t_ PL_H_ _ _ VOH
(.)
NAND
OUTPUT
-+_-J!~ ~ __
\\...s_V_ _ _ VOL
-Q)
a:
en
a-
Q)
>
"i:
tPLH----t.t----....1 ~--I.W-I- tpHL C
AND
OUTPUT ___-J'' 1.-S-V-----,,-= ~ ---::~ Q)
t:
:.:J
WAVEFORMS
FIGURE 1. tPLH and tPHL
NOTES: A. The pulse generator has the following characteristics: Zout = 50 n, PRR :s 500 kHz, tw = 100 ns.
TEXAS 4-105
INSTRUMENTS
SN55113, SN75113

INPUT
PULSE
GENERATOR
(See Note AI
AND
~----~----------OUTPUT
NAND
~----~----------OUTPUT
CL = 30 pF
1kO ~ (See Note B)
SV
TEST CIRCUIT
<S ns-+J 14-

~~--~~I-I- - - 3V
I
INPUT
I
I 10%
I """""'~--OV
I+----+f-tPZH
I '----T"__ -*- VOH
OUTPUT
i ~-Xv
______Y,5V tPHZ~
. ~ Voff""OV
WAVEFORMS
FIGURE 2. tPZH and tPHZ
NOTES: A. The pulse generator has the following characteristics: Zout = 50 O. PRR ::;; 500 kHz. tw = 100 ns.
B. CL includes probe and jig capacitance. '
4-106 TEXAS . .
INSTRUMENTS
SN55113, SN75113

INPUT
PULSE
GENERATOR 5V
(See Note AI
5V-"VV""",, ....I - - - e - - - - - - - - . A N O 250 n

1 kn UTPUT
OUTPUT
OUTPUT I
I
L J CL =30pF I
I - - - - - - I

~ (See Note B)
L ________________ J
TEST CIRCUIT
...rn
Q)
-.I 14-" 5 ns >
~~-~~I-t_-----3V '0)
I U
Q)
I
-...
INPUT
I II 10%
a:
OV rn
!+-tPZL -+I I Q)
I I >
I I ''::::
I I C
I I
tP_L_Z_-+l-,~
Q)
s::
::::i
OUTPUT
\L'5_v__ I+-
__ 5V
- - ,-VOL
WAVEFORMS
FIGURE 3. tpZL and tPLZ
NOTES: A. The pulse generator has the following characteristics: Zout = 50 0, PRR :s; 500 kHz, tw = 100 ns.
TEXAS ~ 4-107
INSTRUMENTS
post OFFICii BOX 655012 DALLA&. TEXAS 76266
SN55113, SN75113

vs vs
6 6 I I
Nolload I
Vee = 5 V
TA = 25e No load
5 5
=t& 4 Vee = 5.5 V >I TA = 125e

CIl
Cl
4
!9 Vee = 5 V !9
"0 "0 .. Jt
> Vee = 4.5 V >
... 3
; 3
~A = 25e
III
::::I
E- E- \
::::I ::::I
TA = -55e
9o 2 0
I 2
0
r > >
5'
CD
.c'
C
o o
.. o 2 3 4 o 2 3 4
-
CD
tn VI-Data Input Voltage-V VI-Data Input Voltage-V
:0 FIGURE 4 FIGURE 5
CD
n
CD
..C'
CD
tn
OUTPUT VOLTAGE
vs
OUTPUT CONTROL VOLTAGE
OUTPUT VOLTAGE
vs
OUTPUT CONTROL VOLTAGE
6 6 T J T T
Load = 500 n t~ ground Vee = 5 V
TA = 25e Load = 500 n to ground
5 5
I
TA = 125 (;
>I >I /
CIl 4 Vee=5.5V_ I - - - CIl 4
Cl Cl I'
!9 Vee = 5 V !9
"0 "0 I It.
....> 3 Vee = 4.5 V_ +-- >
... 3
::::I
E-
::::I
0
::::I
E-
::::I
0
1\ ~
T';\ = 25 e
I 2 I 2 TA = _55e .
0 0
> > I
DISABLED HIGH DISABLED HIGH
o o
o
I 4
o 2 3 4 2 3
VI-Input Voltage (Output eontroll-V VI-Input Voltage (Output eontroll-V
FIGURE 6 FIGURE 7
tO ata for temperatures below OOC and above 70C and for supply voltages below 4.75 V and above 5.25 V are applicable to SN55113
circuits only. These parameters were measured with the active pull-up connected to the sink output.
4-108 TEXAS
INSTRUMENTS
SN55113, SN75113
TYPICAL CHARACTERISTICSt
vs vs
OUTPUT CONTROL VOLTAGE OUTPUT CONTROL VOLTAGE
6 6
Vee=5.5V Load = 500 n to Vee Load = 500 n to Vee
TA = 25C Vee = 5 V
Vee = 5 V
5 5
Vee = 4.5 V
>I >I
Q)
CI
4 Q)
CI
4
~ ~ ,/"'"'TA = 25C
0 0 ~
>... 3
>... 3
::::I ::::I
e::::I e
0
0
>
I 2
DI~ABLfD LOW
I
">
::::I
0
2
TA = 125C
I I
TA = -55e
I
II
...
(/)
CD
J DIS~BLE~ LO~'j >

'4)
(J
o o
o 2
FIGURE 8
3
VI-Input Voltage (Output eontrol}-V
4 o 2
VI-Input Voltage (Output eontroJl-V
FIGURE 9
3 4
-...
CD
a:
( /)
CD
>
'i:
C
OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE CD
vs
s:::
vs
~
4.0 5
Vec=4.~V TA = 25C
3.6 I
Vee = 5.5 V
---
3.2 I-- 4
VOH(lOH = ~10 m!!-- I--- I---
=f
Q)
CI
~ 2.4
2.8
J-- ~ 1- I--- I---
I--
>I
Q)
CI
~
--..... r--....
t--..
IvJe=5V
--.....:~
o
>
;
Co
2.0
I--- ~VOH(lOH = -40 mAl "0
>...
::::I
e
3
~ t-- ~
t--."
l!-t--..... ,"
~ 1.6
0
::::I 2
\"
Vee = 4.5 V
6 1.2
>
I
:I:
0
0.8 >
0.4 f - - - I--VOL(lOL 40mA)
o o l\
~~~ 0 ~ ~ ~ 100 1~ o -20 -40 -60 -80 -100 -120
T A -Free-Air Temperature-e IOH-Output eurrent-mA
FIGURE 10 FIGURE 11
tOata for temperatures below OOC and above 70C and for supply voltages below 4.75 V and above 5.25 V are applicable to SN55113
TEXAS
INSTRUMENTS
-II 4-109
SN55113, SN75113
SUPPLY CURRENT
LOWLEVEL OUTPUT VOLTAGE (BOTH DRIVERS)
vs vs
OUTPUT CURRENT SUPPLY VOLTAGE
0.6 80 l
I NJload
TA= 25 C
0.5 ~ 70 f - TA = 25C
=t
Q) 0.4
VCC=4.5~
. '/' 87 <t 60
E
.!.I: bJ>g ~
A
~ <:'
Cl
~ 50
~
"0 VCC = 5.5 V ~ (:,<.0 Il-~
:; .... ..oq
~ 0.3 u 40 ,~q '"
# V
R ,~q
III
::I >
a-
::I
C.
c.
9 0.2
::I
'1
30
r- o
-l
V u
20 "If'
:r >
0.1 / :d
!
CD
V
.
c
c' o
10
./
V
.
CD
(f)
o W ~ ~ M
IOL -Output Current-rnA
100 1W
o
o 2 3 4 5 6
VCC-Supply Voltage-V
7 8
iCD FIGURE 12 FIGURE 13

C')
CD SUPPLY CURRENT SUPPL Y CURRENT
c'
..
CD
(f)
(BOTH DRIVERS)
vs
FREEAIR TEMPERATURE
(BOTH DRIVERS)
vs
FREQUENCY
56 100
VCC = 5 V VCC = 5 V
54 I nputs grounded RL = 00
No load CL = 30 pF
52 80
<t <t
Inputs: 3volt square wave
E E TA = 25C I)
--
50
.!.I: 2-I: II
/'
~ 48 ~ 60
::I
u ~ u
:; V
> 46 ......
~'"
Q. >
c. is.
::I 45 c. 40
"
::I
'1u t'-.
CI)
I
42 U
:d
40
38
" :d
20
36 o
-75 -50 -25 0 25 50 75 100 125 0.1 0.4 4 10 40 100
T A-FreeAir Temperature-oC f-Frequency-MHz
FIGURE 14 FIGURE 15
toata for temperature below 0 C and above 70CC and for supply voltages below 4.75 V and above 5.25 V are applicable to SN55113
circuits only. These parameters were measured with the active pullup connected to the sink output.
4-110
TEXAS -I!}
INSTRUMENTS
SN55113, SN75113
PROPAGATION DELAY TIMES

FROM DATA INPUTS OUTPUT ENABLE AND DISABLE TIMES
vs vs
20 30
Vee = 5 V Vee = 5 V
Z 18
:::I
eL = 30 pF See Figures 2 and 3
C. See Figure 1 i: 25
.: 16 ~
---
:s V CI
E '/
C 14
"" r- Vr-'" ~ /"
E
..
-tPLH
~ ------- :c
20
~
~
- -
12 ~
tpHL
L..-- l---
E
'" 10 C 15
"C
c
tPZL
~
-- II
---
~ 8
III I ~
~
CI
tPHZ _
III
a; :c
~
C
c
o
6 w
..
10
tP~H ...
U)
Q)
.;: 4 :::I
S- :>
III
CI :::I 5 'Q)
III
C. 2 o (,)
o Q)
ct o
-75 -50 -25 o 25 50
T A-Free-Air Temperature-e
75 100 125
o
-75 -50 -25 0 25 50 75
T A-Free-Air Temperature-oC
100 125 -...a::
U)
CD
:>
'':
FIGURE 16 FIGURE 17
C
tO ata for temperature below 0 ac and above 70 acc and for supply voltages below 4.75 V and above 5.25 V are applicable to SN55113 CD
circuits only. These parameters were measured with the active pull-up connected to the sink output. t:
:.::i
TWISTED
=a=
PAIR
SN75113 DRIVER
~ SN75115 RECEIVER
tRT = Z00 A capacitor may be connected in series with RT to reduce power dissipation.
FIGURE 18. BASIC PARTY-LINE OR DATA-BUS DIFFERENTIAL DATA TRANSMISSION
TEXAS ~ 4-111
INSTRUMENlS

r
:i"
CD
..
c
;r
..en
CD
l;
CD
n
CD
<'
.
CD
en
4-112
SN55114, SN75114
D1315, SEPTEMBER 1973 - REVISED SEPTEMBER 1986
Choice of Open-Collector, Open-Emitter, or SN55114 ... J PACKAGE

SN75114 ... D. J. OR N PACKAGE
Totem-Pole Outputs
(TOP VIEW)
Single-Ended or Differential AND/NAND
1ZP VCC
Outputs
1ZS 2ZP
Single 5-V Supply 1YS 2ZS
1YP 2YS
Dual Channel Operation
1A 2YP
TTL-Compatible 1B 2C
1C 2B
GND 2A
High-Current Outputs
SN55114 ... FK PACKAGE
Triple Inputs (TOP VIEW)

Clamp Diodes at Inputs and Outputs
Designed for Use with SN55115 and

SN75115 Differential Line Receivers
1YS 4
(/)
N
a..
N
2
U
Z>N
~~
2019
18 2ZS
II
... tn
Designed to be Interchangeable with Q)
1YP 5 17 2YS' :::-
Fairchild 9614 Line Driver
NC 6 16 NC 'Q)
15 (.)
1A 2YP
-...
7
description Q)
1B 8 14 2C a:
The SN55114 and SN75114 dual differential line 9 10 11 1213 tn
drivers are designed to provide differential output Q)
U OU<l:a:l
signals with the high-current capability for ZZNN :::-
t!J 'i:
driving balanced lines, such as twisted pair, at
C
normal line impedances without high power NC-No internal connection Q)
dissipation. The output stages are similar to TTL t:
totem-pole. outputs, but with the sink outputs, FUNCTION TABLE :::i
YS and ZS, and the corresponding active pull-
INPUTS OUTPUTS
up terminals, YP and ZP, available on adjacent
A B C Y Z
package pins. Since the output stages provide
H H H H L
TTL-compatible output levels, these devices may
ALL OTHER INPUT COMBINATIONS L H
also be used as TTL expanders or phase splitters.
The SN55114 is characterized for operation over

H = high level. L = low level
the full military temperature range of - 55 e to
125e. The SN75114 is characterized for logic diagram (positive logic)
operation from ooe to 70 oe.
1YP
1A
logic symbol t 1YS
18"':';:;:""'---1
&C> (4)
(5) 1YP 1ZP
1A (3)
(6)
1YS 1C
18 1ZS
(7) 1ZP
1C 1ZS
2YP
(9) 2YP 2YS
2A 2YS
(10)
28 2ZP
(11 ) 2ZP
2C 2ZS
2ZS
tThis symbol is in accordance with ANSI/!EEE Std 91-1984 and
lEe Publication 617-12. Pin numbers shown are for D, J. and N packages.
current as of publication date. ProductStConform to
~~~~~:~~i~ai~:1~1e ~!~~~~tigr :I~o::~:~:t~~~s not
TEXAS ~ 4-113
INSTRUMENTS
SN55114, SN75114

TO
OTHER
DRIVER
r--A-..
(16)
Vee
AND
PULL.~:{-,4.-,1.:c2.)_ ......_ _- ' (I. 151 NAND PULLUP
'----~---'--' ZP
AND (3.1l)
+-_-+_~ /_......_...:.{2=-:...:1.:::.:.4) ~I~~DOUTPUT
SINK OUTPUT
YS (8) ZS
III
GND
Pin numbers shown are for D, J. and N packages
tThese components are common to both drivers.
r
:i' absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
CD
SN55114 SN75114 UNIT
C Supply voltage. VCC (see Note 1) 7 7 V
<'"'CD" Input voltage 5.5 5.5 V
-
Off-state voltage applied to open-collector outputs 12 12 V
"'en" D package 950
:xJ Continuous total dissipation at (or below) FK package 1375
CD mW
(') 25C free-air temperature (see Note 2) J package 1375 1025
CD N package 1150
<'CD Operating free-air temperature range -55to 125 o to 70 C
"'"
(J) Storage temperature range -65 to 150 -65 to 150 C
Lead temperature 1.6 mm (1/16 inch) from case for 60 seconds: J package 300 c

2. For operation above 25C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the FK and J packages,
SN55114 chips are alloy mounted. In the J package, SN75114 chips are glass mounted.

SN55114 SN75114
UNIT
Supply voltage, VCC1 4.5 5 5.5 4.75 5 5.25 V
Highlevel input voltage, VIH 2 2 V
4-114 TEXAS ~
INSTRUMENTS
POST OFFICE BOX 866012 DALLAS. TEXAS 7626B
SN55114, SN75114
noted)
SN55114 SN75114
VIK Input clamp voltage Vee = MIN, II= -12 mA -0.9 -1.5 -0.9 -1.5 V
Vee = MIN, VIH = 2 V, 1i0H = -10 mA 2.4 3.4 2.4 3.4
VIL = 0.8 V, JIOH = -40 mA 2 3.0 2 3.0
Vee = MIN, VIH = 2 V,
VIL = 0.8 V, 10L = 40 mA
Vee = 5 V, 10 = 40 mA, TA = 25e 6.1 6.5 6.1 6.5
VOK Output clamp voltage V
Vee = MAX, 10 = -40 mA. TA = 25C -1.1 -1.5 -1.1 -1.5
TA -- 25e 1 100
VOH = 12 V
Off-state open-collector TA = 125e 200
10(off) output current
Vee = MAX p.A
TA = 25e 1 100
=
II
VOH 5.25 V
TA = 70 e 0
200
Input current at
II Vee = MAX, VI = 5.5 V 1 1 mA
maximum input voltage
IIH High-level input current Vee = MAX, VI = 2.4 V 40 40 p.A ... t/)
Q)
IlL Low-level input current Vee = MAX, VI = 0.4 V -1.1 -1.6 -1.1 -1.6 mA
>
Short-circuit '0)
lOS Vee. = MAX, Vo = 0, TA = 25C -40 -90 -120 -40 -90 -120 mA
tJ
output current
Q)
Supply current All inputs at 0 V, No load, Vee = MAX 37 50 37 50
mA a:
Ice
(i)
(both drivers) TA = 25C Vee = 7 V 47 65 47 70
...
Q)
t All parameters with the exception of off-state open-collector output current are measured with the active pullup connected to the sink
output. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions_
>
'i:
l: All typical values are at T A = 25e and Vee = 5 V, with the exception of-lee at 7 V. C
Only one output should be shorted at a time, and duration of the short-circuit should not exceed one second. Q)
r:::
switching characteristics, Vee 5 V, TA :.::i
SN55114 SN75114
tpLH Propagation delay time, low-to-high-Ievel output eL = 30 pF, 15 20 15 30 ns
tpHL Propagation delay time, high-to-Iow-Ievel output See Figure 1 11 20 11 30 ns
TEXAS ~ 4-115
INSTRUMENTS
PO lOT OFFICE BOX 65G012 DALLAS, teXAS ?S26B
SN55114, SN75114

14-<5 ns ~<5 ns
j,1_ _ _ _ _...y:-.-1- - - - 3V
INPUT VCC"5 V 90"10 I
1.5V I
I 10"10
y MlI4---tw--~~~1 ""110-""';'---0 V
AND OUTPUT
I I
filii ~I tPLH "14--.t~I--tPLH
Z
y
i _lr,r.5-V----~:--1.5~)t---VOH
NAND OUTPUT OUTPUT I /' I' "'---VOL
I I
z I '" tPLH 14 r~'. VOH
III
OUTPUT I 1.5 V 1.5 V
I I
tpHL ~ ------ - - VOL
~ TEST CIRCUIT VOLTAGE WAVEFORMS

5' NOTES: A. The pulse generator has the following characteristics: Zout = 500 n, PRR s 500 kHz, tw ~ 100 ns.
CD
.<'
C
8. CL includes probe and jig capacitance.

.
CD
en
~
CD
(') OUTPUT VOLTAGE OUTP.UT VOLTAGE
CD vs vs
<'CD
.
en 6
DATA INPUT VOLTAGE
No'load I
6 I
Vee =5 V
DATA INPUT VOLTAGE
I
TA = 25e No load
5 5
> > TA = 125e

Vee = 5.5 V
~ 4 ~ 4
:! Vee = 5 V :!
'0 '0 "I
> Vee = 4.5 V
; 3 ~::s 3 II:
& & \ ~A = 25e

::s ::s
9o 2
o TA = -55e
I 2
o
> >
o o
o 2 3 4 o 2 3 4
VI-Data Input Voltage-V VI-Data Input Voltage-V
FIGURE 2 FIGURE 3
t Data for temperatures below a DC and above 70 DC and for supply vOlt'ages below 4.75 V and above 5.25 V are applicable to SN55114
circuits only, These parameters were measured with the active pullup connected to the sink output.
4-116 . TEXAS ~
INSTRUMENlS
SN55114, SN75114
HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE

vs vs
5 0.4
TA = 25C I
TA = 25 C
Vee = 5.5 V VCC= 5.5 V

~
>
.!.
C>
~
~ 3
4
---
r---
...............
---- --- ----b--..'

1
r--..
Vec= 5 V
~
>
I
CI)
;
'0
>
0.3
/
~
~
IA
VCC= 4.5 V
>...
~
:::l
a.
I
2
--- T- vc~ =4.5 V
~,
,
; 0.2
So
:::l
9
...J ~
~V
o
:I:
~0.1 /
> '/ ...CD
C/)
/
V >
iii
o 1\ o CJ
o 10 20 30 40 50 60 70 80 CD
0
0 -20 -40 -60
IOH-Output Current-rnA
-80 -100 -120
IOL -O",tput Current-rnA
-...
ex:
C/)
CD
FIGURE 4 FIGURE 5 >
'a:::
OUTPUT VOLTAGE PROPAGATION DELAY TIMES C
vs vs CD
c
FREE-AIR TEMPERATURE :::i
4_0 40
VCC=4.5V VCC= 5 V
3.6 I-See Figure 1
3_2
VOHOOH = -;-10 rn!!,- I--- f..--
~ C
. l' 2_8
~
.!,
CI)
30
CI)
C>
~ 2.4
-I--- ~
1- I--- I--- E
j.:
o
> -f----- ~VOHOOH = -40 rnA) >
~
/
Ci 20
; 2.0 c
a. c
.g ~
V
tpLH
~ 1.6
>
I
01.2
~
C>
e
~
a.
10
- - ~
tpHL
-
c..
0.8
I
0.4 f - - - -VOLOOL - 40 rnA)
o o
-75 -50 -25 0 25 50 75 100 125 -75 -50 -25 0 25 50 75 100 125
TA-Free-Air Ternperature-OC T A-Free-Air Ternperature-oC
FIGURE 6 FIGURE 7
i Data for temperatures below OC and above 70C are applicable to SN55114 circuits only. These parameters were measured with the
active pullup connected to the sink output.
TEXAS . . 4-117
INSTRUMENlS
SN55114, SN75114
TYPICAL CHARACTERISTICS't
(BOTH DRIVERS) (BOTH DR IVERS)
vs vs
SUPPLY VOLTAGE FREEAIR TEMPERATURE
80 42
No load Vee = 5 V
=
70 TA 25e. I nputs grounded
40 Outputs open
60
E E
I
E 50
.!.c 38
r--....
/' ~
~ ~
:;
'""
:; ~~
u 40
~.....
(:,1,0
ff'~-
t--- c;. 36
III
r-
>
C.
g.
'7u
~ 20
30
\~~
\~~
~.....O C.
c..
~
:J
'7u 34 ~
'~
:i'
CD
10
( 32
o
... V
<' o ./ 30
o
... 2 3 5 6 8 ~75
-
CD 4 7 -50 -25 0 25 50 75 100 125
t/) TA-Free-Air Temperature-Oe
:CD:c
FIGURE 8 FIGURE 9
(')
CD
<' SUPPLY CURRENT
...
CD
t/)
(BOTH DRIVERS)
vs
FREQUENCY
100
Vee = 5 V
RL = 00
CL = 30 pF
80
Inputs: 3-volt square wave
E TA = 25C
.!.c I)
~ 60
:J [/1.1
U
>
C. V
c.. 40 ~
~-
u
u
- 20
o
0.1 0.4 4 10 40 100
f-Frequency-MHz
FIGURE 10
t Data for temperatures below OOC and above 70C are applicable to SN55114 circuits only. These parameters were measured with the
active pullup connected to the sink output.
4-118 TExAs ~
INSTRUMENTS
SN55114, SN75114
1/2SN75114 1/2 SN75115
DRIVER RECEIVER
TWISTED
PAIR
II
t RT = Z00 A capacitor may be connected in series with RT to reduce power dissipation.
FIGURE 11. BASIC PARTY-LINE OR DATA-BUS DIFFERENTIAL DATA TRANSMISSION
...
In
Q)
::-
'03
(,)
Q)
-...
a::
In
Q)
::-
"i:
C
Q)
c
:.:::i
. TEXAS-I!} 4-119
INSTRUMENTS
III
r
5'
CD
...C
<'
...
CD
(I)
iCD
o
CD
<'
...
CD
(I)
4-120
SN55115, SN75115
DUAL DIFFERENTIAL LINE RECEIVERS
D1315, SEPTEMBER 1973-REVISED OCTOBER 1986
Choice of Open-Collector or Active Pull-Up SN55115 ... J DUAL-IN-LiNE PACKAGE

(Totem-Pole) Outputs SN75115 ... D, J. OR N PACKAGE
(TOP VIEW)
Single 5-V Supply
lYS VCC
Differential Line Operation lYP 2YS
Dual-Channel Operation lSTRB 2YP
lRTC 2STRB
TTL Compatible lB 2RTC
15 V Common-Mode Input Voltage Range lRT 2B
lA 2RT
Optional-Use Built-In 130-0 Line-Terminating GND 2A
Resistor
Individual Frequency Response Controls SN55115 ... FK PACKAGE

Individual Channel Strobes
Designed for Use with SN55113, SN75113,
SN55114, and SN75114 Drivers
(TOP VIEW)
a. en Uen
>-UU>-
>- ...-Z>N
3 2 1 2019
II ...
rn
Q)
Fairchild 9615 Line Receivers lSTRB 4 18 2YP >
lRTC 5 17 2STRB "iii
CJ
-...
description NC 6 16 NC Q)
lB 7 15 2RTC a:
The SN55115 and SN75115 dual differential line lRT 8 14 2B rn
receivers are designed to sense small differential 9 1011 1213 Q)
signals in the presence of large common-mode >
".::
noise. These devices give TTL-compatible output <I: o U <I: I-
ZZNO: C
signals as a function of the differential input t!) N
Q)
voltage. The open-collector output configuration NC- No internal connection E:
permits the wire-ANDing of similar TTL :.::l
outputs (such as SN5401 /SN7401) or other FUNCTION TABLE
SN55115/SN75115 line receivers. This permits
a level of logic to be implemented without extra DIFF OUTPUT
STROBE
delay. The output stages are similar to TTL INPUT (YP AND YS TIED TOGETHER)
totem-pole outputs, but with sink outputs, 1 YS L X H
and 2YS, and the corresponding active pull-up H L H
terminals, 1YP and 2YP, available on adjacent H H L
package pins. The frequency response and noise

H = VI ~ VIH min or VID more positive than VTH max
immunity may be provided by a single external L = VI :$ VIL max or VID more negative than VTL max
capacitor. A strobe input is provided for each X = irrelevant
channel. With the strobe in the low level, the
receiver is disabled and the outputs are forced
to a high level.
the full military range of - 55C to 125C. The
SN75115 is characterized for operation from
ooe to 70C.
~
~~~~~~~~i~a{:~1~1e ~!~~~~ti~r :1~o::~:~:t::s~S not INSTRUMENTS
SN55115, SN75115
1B &C>
1A 1YP
1RT
1STRB 1YS
1RTC
2B
2A 2YP
2RT
2STRB 2YS
2RTe
III t This symbol is in accordance with ANSI/IEEE Std 91-1984 and


RESPONSE-
TIME
RT STROBE CONTROL
(6.101 (3.131 14.121
., k
lk
1.S k 1.64 k
20
'--_-1f--4-_....:2
.:..:.-'--'4.;.:. PULL-UP
YP
Sk
3 k
130
'.5 k
lS0
L -_ _~-~----~----~~-~18IGND
COMMON TO
r-------,I
I
BOTH RECEIVERS
I I
I I
I I
I I
I I Resistor values are nominal and in ohms.
I I
I _______ JI
L
4-122 TEXAS ~
INSTRUMENTS
POST OFFICE BOX 6560'2 DALLAl, TEXAS 1626'
SN55115, SN75115
, DUAL DIFFERENTIAL LINE RECEIVERS
Input voltage at A, B, and RT inputs 25 25 V
Input voltage at strobe input 5.5 5.5 V
Off-state voltage applied to open-collector outputs 14 14 V
D package 950
mW
25C free-air temperature (see Note 2) J package 1375 1025
N package 1150
Operating free-air temperature range -55t0125 o to 70 c
Storage temperature range -65 to 150 -65 to 150 c
Case temperature for 60 seconds: FK package 260 c
Lead temperature 1,6 mm (1116 inch) from case for 60 seconds: J package 300 c
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds: D or N package 260 c
NOTES: 1. All voltage values, except differential input voltage, are with respect to network ground terminal.
2. For operation above 25C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the FK and J packages,
(/)
SN55115 chips are alloy mounted and SN75115 chips are glass mounted. For these devices in the N package, use the 7.0-mW/oC ~
curve. For the D package, use the 8.2 mW/oC curve. (1)
>
'Q)
recommended operating conditions (J
Supply voltage, VCC

High-level (strobe) input voltage, VIH
MIN
4.5
2.4
SN55115
NOM
5
MAX
5.5
MIN
4.75
2.4
SN75115
NOM
5
MAX
5.25
UNIT
V
V
-
a:
(1)
( /)
~
(1)
>
'i:
Low-level (strobe) input voltage, VIL 0.4 0.4 V C
High-level output current, 10H -5 -5 mA (1)
Low-level output current, 10L 15 15 mA r:::
:.:J
TEXAS ~ 4-123
INSTRUMENTS
SN55115, SN75115
noted)
SN55115 SN75115
Differential input
VTH Vo = 0.4 V, 10L = 15 mA, VIC = 0 500 500 mV
high-threshold voltage
Differential input
VTL Vo = 2.4 V, 10H = -5 mA, VIC = 0 -500' -500' mV
low-threshold voltage
+15 +24 +15 +24
Common-mode
VICR VIC = 1 V to to to to V
input voltage range
-15 -19 -15 -19
TA = MIN 2.2 2.4
VCC = MIN, VIC = -0.5 V,
VOH High-level output voltage TA = 25C 2.4 3.4 2.4 3.4 V
10H = -5mA
TA = MAX 2.4 2.4
III
r-
S'
VOL
IlL
Lo)'V-level output voltage

VCC = MIN,
IOL=15mA
VCC = MAX,
VIC = 0.5 V,
VI = 0.4 V,
Other input at 5.5 V
TA = MIN
TA = 25C
0.22
-0.5
0.4
-0.9
-0.7
0.22
-0.5
0.45
-0.9
-0.7
V
mA
TA = MAX -0.7 -0.7
(I)
VCC = MIN, VIC = -0.5 V, TA = 25C
High-level strobe current
...C ISH
Vstrobe = 4.5 V TA = MAX 10
I'A
<' VCC = MAX, VIC = 0.5 V,
...tn ISL Low-level strobe current TA = 25C -1.15 -2.4 -1.15 -2.4 mA
-
(I)
Vstrobe = 0.4 V
Response-time-control VCC = MAX, VIC = 0.5 V,
I(RTC) TA = 25C -1.2 -3.4 -1.2 -3.4 mA
jJ current VRC = 0
(I)
(") VCC = MIN, VOH = 12 V, TA = 25C 100
(I)
Off-state open-collector VIC = -4.5 V TA = MAX 200
<' 10(0ft)
output current
I'A
...
(I)
tn
VCC = MIN,
VIC = -4.75 V
VOH = 5.25 V, TA = 25C
TA = MAX
100
200
Line-terminating
RT VCC = 5 V TA = 25C 77 130 167 74 130 179 {J
resistance
Short-circuit VCC = MAX, Vo = 0,
lOS TA = 25C -15 -40 -80 -14 -40 -100 mA
output current U VIC = -0.5 V
Supply current VCC = MAX, VIC = 0.5 V,
ICC TA = 25C 32 50 32 50 mA
(both receivers) VIC = 0
t Unless otherwise noted Vstrobe = 2.4 V. All parameters with the exception of off-state open-collector output current are measured with the active pull-up
connected to the sink output.-
t All typical values are at V CC = 5 V, TA = 25C, and VIC = O.
Differential voltages are at the B input terminal with respect to the A input terminal.
, The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold voltages only.
U Only one output should be shorted to ground at a time, and duration of the short-circuit should not exceed one second.
switching characteristics, V CC = 5 V, CL = 30 pF, TA == 25C

SN55115 SN75115
tpLH RL = 3.9 kO. See Figure 1 18 50 18 75 ns
tpHL RL = 390 0, See Figure 1 20 50 20 75 ns
4-124 TEXAS
INSTRUMENTS
SN55115, SN75115

OPEN 2.4 V
5V
:s 5 ns-+! I+- -+j I--:s 5 ns
DIFFERENTIA;J(olso% SO% 1- - - - - + 3 V
INPUT I 0V 0 ~:
10' I . j\.10% -3 V
I I
--.I 14- tpHL --.I j+- tpLH
~
I VOH
I I
OUTPUT 1.5 V 1.5 V
TIME CONTROL
OPEN -----VOL
TEST CIRCUIT WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zout = 50 n. PRR :5 500 kHz. tw = 100 ns. duty cycle = 50%.
II
FIGURE 1. PROPAGATION OELAY TIMES
TYPICAL CHARACTERISTICS ...rn

(1)
INPUT CURRENT >
'Ci)
VS (.)
INPUT VOLTAGE (1)
6
Vee - 5 V
Input not under test at 0 V V -...
a::
rn
(1)
4 TA - 25e L ,~
ct V C
E 2 (1)
2-t: V c:
::l
~
:; 0 V
V
()
....::I
C.
t: /
I -2
-4
VV
/
-6 /
- 25 - 20 - 15 - 10- 5 0 5 10 15 20 25
VI-Input Voltage-V
FIGURE 2
TEXAS . . 4-125
INSTRUMENTS
SN55115, SN75115

VS VS
FREE-AIR TEMPERATURE COMMON-MODE INPUT VOLTAGE
4.0 6
3.4
,
VCC - 4.5 V
, No Load
TA - 25C
Iii .I 1 I. .I.
3.2 VOH (VID - -0.5 V. IOH - -5 mA~ 5
> -~I---~ VC~ .. '5.5 V
I 2.8 >
I
CIl
CI .f....- 10- CIl
C)
4 VCC - 5 V
~ 2.4 ~
"0 VCC .. 4.5 V
"0
>
; 2.0 ..
>
::J
3
III
So Co ~ 1 .1 .I.
::J 1.6 ;
0
I
0
I 2
~ ~ VIO - -1 V
0 1.2
0
v
> >
r- 0.8
5'
(l) 0.4 f- VOLI(VID 1- 0.5 V. IOL - 15 mAI_
/VID - 1 V
...c o o I I I
<' -75 -50 -25 0 25 50 75' 100 125 -25-20-15-10-50 5 10 1520 25
...
-
(l)
TA - Fre~-Air Temperature - C Vlc-Common-Mode Input Voltage-V
en
jJ FIGURE 3 FIGURE 4
(l)
"<'
(l)
...
(l)
en
VS
OUTPUT CURRENT
VS
OUTPUT CURRENT
5 0.4 VID'" 0.5 V
VID ... -0.5 V
TA .. 25C TA .. 25C
> >
I I
4 '-
r-- V'
CIl CIl
CI
~
:\." ~V S 0.3r----+----~----r----+--7$4_--~
"0 "0
..
> r-- ~vr-- ..
>
::J
Co
;
0
3 "-
r-- r-.C '" 4 5 T'-
r--' V
r--
"" \\
"',
::J
Co
;
o 0.2 f-----+-----I-7fI'-~----_r_----r----_1
'" \\
Qi Qi
>
CIl 2 >
CIl
~\\
-I -I
.i:.C) ~
:f
I
Io 0.1
-I
>
:I:
0 \ o
>
o ~ OL-__- L_ _ _ _ ~_ _~_ _ _ _~_ _~_ _ _ _~
o -10 -20 -30 -40 -50 o 5 10 15 20 25 30

IOH-High-Level Output Current-rnA IOL -Low-Level Output Current-rnA
FIGURE 5 FIGURE 6
t Data for temperatures below OC and above 70C and for supply voltages below 4.75 V and above 5.25 V are applicable to SN55115
4-126 TEXAS . .
INSTRUMENTS
SN55115. SN75115

VS VS
6 6
Vee - 5 V Vee - 5.5 V
Load - 2 kfl to Vee
5 , 5
Vee - 5 V
Vee - 4.5 V
> >
I I
Q) 4 Q)
CD
4
CD
~
TA - 125e ~
"0
"0
>
...
::J
3 I I >
:; 3
-~
II
So TIA - 15 0e So
::J
::J
0 TA - -55e 0
I 2 I 2
0 0
> >
... tn
Q)
Load - 2 kfl to Vee >
0
TA ~ 25 e 'Q)
o o l I (,)
Q)
o
-...
o -0.2 -0.1 0.1 0.2
-0.2 -0.1 0.1 0.2 a:
VID-Differential Input Voltage-V VID-Differentiallnput Voltage-V tn
Q)
FIGURE 7 FIGURE 8 >
'i:
OUTPUT VOLTAGE OUTPUT VOLTAGE C
VS VS Q)
STROBE INPUT VOLTAGE STROBE INPUT VOLTAGE

c
:.::i
6 6
No Load Vee - 5 V
VID - 0.5 V No Load
5 TA - 25e 5 VID - 0.5 V
Vee" 5.5 V >
>
I
Q) 4 i\. Q)
I
4
r-----r-,. I
CD
J
~
CD ....... ~
~
"0 ~ "0
>
~
\ ~ / ' TA., - ,
125e ,
>
... 3 ~ ... 3
~
::J
So 1\ \ \ ::J
So \ TAl. _1550el
~\
::J ::J
0 vee;= 5 0
2 I 2
I
~ee
1
>
0 :... 4.5 V":!.
>
0
i-f- TA
1
J - 25e
o o
o 2 3 4 o 2 3 4
Vstrobe-Strobe Input Voltage-V V strobe - Strobe Input Voltage - V
FIGURE 9 FIGURE 10
t Data for temperatures below OC and above 70C and for supply voltages below 4.75 V and above 5.25 V are applicable to SN55115
circuits only. These parameters were measured with the active pull up connected to the sink output.
- TEXAS ~ 4-127
INSTRUMENTS
POST OFFice BOX 655012 ' OALLAS. TeXAS 75265
SN55115. SN75115

(BOTH RECEIVERS) (BOTH RECEIVERS)
VS vs
SUPPLY VOLTAGE FREE-AIR TEMPERATURE
60 40
No Load
<t
50
TA - 25C
35
- t---
E
.!.c 40
B INPUT AT VCC
A INPUT AT8
1/ <t
E
.!.c
30
~
~
V ~
~
25
c;. 30 u
III
20
~V >
~ INPUT AT 0 V
C. C.
Co
::I Co
~ 20
/ C/)
::I 15
A INPUT AT VCC
~
u I
r- u 10
5' 9
J/ 9
VCC'" 5.5 V
CD
...
C
10
l/V 5 B INPUT AT 5.5 V
A I~PUT tT 0 IV
<' o -'" o
...en
-
CD o 2 3 4 5 6 7 8 -75 -50 -25 0 25 50 75 100 125
VCC-Supply Voltage-V T A - Free-Air Temperature - C
:J:J
CD FIGURE 11 FIGURE 12
(')
CD
<'CD PROPAGATION DELAY TIMES MAXIMUM OPERATING FREQUENCY
...
en vs vs
FREE-AIR TEMPERATURE RESPONSE-TIME-CONTROL CAPACITANCE
30 10M ~~
N
Vcc - 5 V :I: ~~
I ~~
25
See Figure 1
~ >
u
1--1-"
(/)
c . I l./ c
CD
1M
~
~
I ::I
(/)
tPHL (RL - 390 0) t1'
CD I-- r.;
CD
E 20 u: I--f-
i= V----- en 100k 1;:;:;:::::;1=::
>
10
Gi 15
V ~10
Gi
c VtpLH (RL Co "-
.g
c
J,/ ... 3.9 kO) 0
E
::I
10k
10
en 10
10
E III
Co 'i( I'
0 10
11111111 11111111 11111111
Ii: ~ 1k
5 I VCC - 5 V
)(
10 INPUT: -0.5 V to 0.5 V SQUARE WAVE
o .E rTA .. 25C
100
-751-50 -25 0 25 50 75 100 125 0.001 0.01 0.1 10
T A - Free-Air Temperature Response-Time-Control Capacitance -ifF
FIGURE 13 FIGURE 14
t Data for temperatures below 0 DC and above 70 DC and for supply voltages below 4.75 V and above 5.25 V are applicable to SN55115
4-128 TEXAS
INSTRUMENTS
SN55115. SN75115
r - - -, LOCATION 5
L __-l
LOCATION 6
-
TWISTED
PAIR
=O:=SN75113 DRIVER
(I)
CD
=:{:::>-SN75115 RECEIVER >
'iii
(,)
CD
t A capacitor may be connected in series with Zo to reduce power dissipation.
FIGURE 15. BASIC PARTY-LINE OR DATA-BUS DIFFERENTIAL DATA TRANSMISSION --

a:
( I)
CD
'~
>
C
CD
c:
::J
TEXAS ~ 4-129
INSTRUMENTS

4-130
SN55116 THRU SN55119
SN75116 THRU SN75119
DIFFERENTIAL LINE TRANSCEIVERS
D~143, MAY 1976-REVISED SEPTEMBER 1986 ,
features common to all types additional features of the 5N55116/SN75116

Single 5-V Supply Independent Driver and Receiver
3-State Driver Output Circuitry Choice of Open-Collector or Totem-Pole
Outputs on Both Driver and Receiver
TTL-Compatible Driver Inputs
Dual Data Inputs on Driver
TTL-Compatible Receiver Output
Optional Line-Termination Resistor in
Differential Line Operation
Receiver
Receiver Output Strobe ('116, '117) or
Enable ('118; '119)
15-V Receiver Common-Mode Capability
Receiver Frequency Response Control
Designed for Party-Line (Data-Bus)
Applications additional features of the 5N55117/SN75117
Choice of Ceramic or Plastic Packages Driver Output Internally Connected to
Receiver Input
The SN551 18/SN75118 is an 5N55116/SN75116 with 3-5tate Receiver Output Circuitry

The SN55119/SN75119 is an SN55117/SN75117 with 3-State Receiver Output Circuitry
description
...en
Q)
:>
'Ci)
(,)
Q)
These integrated circuits are designed for use in interfacing between TTL-type digital systems and differential
data transmission lines. They are especially useful for party-line (data-bus) applications. Each of these circuit
types combine in one package a three-state differential line driver and a differential-input line receiver,
-...
IX:
en
Q)
:>
both of which operate from a single 5-volt power supply. The driver inputs and receiver outputs are TTL
'':
compatible. The driver employed is similar to the SN55113/SN75113 three-state line driver, and the receiver C
is similar to the SN55115/SN75115 line receiver. Q)
The '116 and '118 circuits offer all the features of the SN55113/SN75113 driver and the
c
:,:j
SN55115/SN75115 receiver combined. The driver performs the dual input AND and NAND functions when
enabled, or presents a high impedance to the load when in the disabled state. The driver output stages
are similar to TTL totem-pole outputs, but have the current-sink portion separated from the current-sourcing
portion and both are brought out to adjacent package pins. This feature allows the user the option of using
the driver in the open-collector output configuration, or, by connecting the adjacent source and sink pins
together, of using the driver in the normal totem-pole output configuration.
The receiver portion of the '116 and' 118 features a differential-input circuit having a common-mode voltage
range of ' 15 volts. An internal 130-ohm resistor is also provided, which may optionally be used for
terminating the transmission line. A frequency response control pin allows the user to reduce the speed
of the receiver or to improve differential noise immunity. The receiver of the' 116 also has an output strobe
and a split totem-pole output. The receiver of the' 118 has an output-enable for the three-state split totem-
pole output. The receiver section of either circuit is independent of the driver section except for the Vee
and ground pins.
The' 117 and' 119 circuits provide the basic driver and receiver functions of the' 116 and '118, but use
a package that is only half as ~arge. The '117 and '119 are intended primarily for party-line or bus-organized
systems as the driver outputs are internally connected to the receiver inputs. The driver has a single data
input and a single enable input, and the '117 receiver has an output strobe while the' 119 receiver has
a three-state-output enable. These devices do not, however, provide output connection options, line
termination resistors, or receiver frequency-response controls.
The SN55116, SN55117, SN55118, and SN55119 are characterized for operation over the full military
temperature range of -55e to 125e; the SN75116, SN75117, SN75118, and SN75119 are
characterized for operation from ooe to 70 oe.
~~~:~:~~i~ai~:1~1~ ~!:~~~ti:r :1~o::~:~:t::S~s not INSTRUMENTS
SN55116 THRU SN55119, SN75116 THRU SN75119
SN55116 ... J PACKAGE SN55118 ... J PACKAGE

SN75116 ... D. J. OR N PACKAGE SN75118 ... D. J. OR N PACKAGE
DZP [ 1 U16 VCC DZP 1 U16 VCC

DZS 2 15 DB DZS 2 15 DB
DYS 14 DA DYS 3 14 DA
DYP 13 DE DYP 4 13 DE
RA 12 RYP RA 5 12 RYP
RT 6 11 RYS RT 6 11 RYS
RB 10 RS RB 7 10 RE
GND 9 RTC GND [8 9 RTC
SN55116 SN55118
FK PACKAGE FK PACKAGE
III
r- DYS
Ulc" U
N N U UaJ
ClClZ>Cl
3 2 1 20 19
DA DYS
Ulc" U
NNUUaJ
ClClZ>Cl
3 2 1 2019
18 DA
5' DYP DE DYP 17 DE
CD 16
NC NC NC NC
...C RA RYP RA 15 RYP
<' RT RYS RT 14 RYS
...en 9 1011 12 13
-
CD
aJClUUUl aJClUUw
a:ZZI-a: a:ZZI-a:
(!) a: (!) a:
:JJ
CD
(')
CD SN55117 ... JG PACKAGE SN55119 ... JG PACKAGE
<'CD SN75117 ... D. JG. OR P PACKAGE SN75119 ... D. JG. OR P PACKAGE
...
en
D I [ ] 8 VCC D I [ ] 8 VCC
B 2 7 DE B 2 7 DE
A 3 6 RY A 3 6 RY
GND 4 5 RS GND 4 5 RE
SN55117 SN55119
FK PACKAGE FK PACKAGE
U U
U _ U UU U _ U uu
ZClZ>Z ZClZ>Z
3 2 1 20 19 3 2 1 2019
NC 4 18 NC 18 NC
B 5 17 DE 17 DE
NC 6 16 NC NC 16 NC
A 7 15 RY 15 RY
NC 8 14 NC 14 NC
9 1011 12 13 9 1011 1213
UClUUlU UClUwu
ZZZa:Z ZZza:z
(!) (!)
NC-No internal connection.
4-132 TEXAS
INSTRUMENTS
'116, '118 '117, '119

OF DRIVER OF DRIVER

DE DA DB DY DZ 01 DE A B
L X X Z Z H H H L
H L X L H L H L H
H X L L H X L Z Z
H H H H L
'116, '118 '117, '119

FUNCTION TABLE OF RECEIVER FUNCTION TABLE OF RECEIVER
DIFF OUTPUT RY INPUTS OUTPUT RY
II
RS/RE
INPUT '116 '118 A B RS/RE '117 '119
L X H Z H L H H H
H L H H L H H L L
H H L L X X L H Z ...U)
Q)
>
H = high level (VI 2: VIH min or VIO more positive than VTH max)
'iii
(,)
L = low level (VI :5 VIL max or VID more negative than VTL max) Q)
X = irrelevant
Z = high impedance (off) -a:...
U)
Q)
schematics of inputs and outputs >
'i:
C
Q)
EQUIVALENT OF EQUIVALENT OF TYPICAL OF ALL OUTPUTS
EACH DRIVER INPUT EACH RECEIVER INPUT
s:::
AND EACH RE AND RS INPUT (EXCLUDING ENABLES ::i
----~~-------.----VCC
AND STROBES)
VCC~---
vCc----------~-
4kU 1 pF NOM
NOM
I NPUT-._........~>--...-
INPUT
SkU
7kU
NOM
NOM
R
PULLUP
~---------',~~--OUTPUTt
~___
Y SINK
OUTPUT'
Driver output R - 9 n NOM

Receiver output R - 20 n NOM
t On 117 and '119, common outputs replace
the separate pullup and sink outputs.
TEXAS
INSTRUMENTS
-1!1 4-133
POST OFFICE BOX 655012 pALLAS. TEXAS 75265
SN55116 THRU SN55119, SI\I75116 THRU SN75119
logic symbols t logic diagrams (positive logic)

'116 '116 AND '118 DRIVER
&1> (4) OYP

(3) OYS
OZP
OZS
'116 RECEIVER
RT
RS
III
RTC
'118
r-
5'
(1)
'118 RECEIVER
...c
<'
...
(1)
en
i
(1)
(")
(1) RT
<' RE
...
(1)
en
RTC '117 DRIVER AND RECEIVER
RS (!::5~) _ _ _ _ _ _ _ _ _---,
'117
(7)
I>
(3) A
OE EN 'V
(1 )
. ;. :~. ;. : : }
(2) B
01 'V
&<3 L-_ _ _ _ _ +-...._ _ 8US
(5)
'119 DRIVER AND RECEIVER

'119
I>
OE (7) (3) A
EN 'V .Xl~......;.(6~) RY
01 (1) (2) B
<J
'V
L-_ _ _ _ _ +-+-___
(2) B
(3) A} BUS .
EN
Pin numbers shown for '116 and' 118 are for J and N packages; those shown for' 117. and '119 are for JG and P packages.
4-134 TEXAS
INSTRUMENTS
'116, '117,
UNIT
'118 '119
Supply voltage, VCC 7 7 V
IDA, DB, DE, 01, RE, RS 5.5 5.5
Input voltage, VI IRA, RB, RT 25 V
I A and B o to 6
Off-state voltage applied to open-collector outputs 12 V
SN55116 SN75116
THRU THRU UNIT
SN55119 SN75119
o package 950
FK package 1375
Continuous total dissipation at (or below) J package 1375 1025
mW
25 DC free-air temperature (see Note 2) JG package 1050 825
N package 1150
P package 1000 ...
fA
Q)
Operating free-air temperature range -55to 125 o to 70 DC
::-
DC
Storage temperature range -65 to 150 -65 to 150 'iii
Case temperature for 60 seconds: FK package 260 DC CJ
Q)
Lead temperature 1,6 mm (1116 inch) from case
for 60 seconds: J and JG packages
Lead temperature 1,6 mm (1/16 inch) from case
300 300
260
DC
DC
-...
a:
fA
Q)
for 10 seconds: 0, N, or P package ::-
'i:
NOTES: 1. All voltage values are with respect to network ground terminal. C
2. For operation above 25 DC free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the FK and J packages, Q)
SN55116 through SN55119 chips are alloy mounted and SN75116 through SN75119 chips are glass mounted. In the JG t:
package, SN55117 and SN55119 are alloy mounted and SN75117 and SN75119 chips are glass mounted. In the N package, :.::i
use the 9.2 mW/DC curve for these devices. In the P package, use the 8-mW/DC curve for these devices.

SNS5' SN7S'
PARAMETER UNIT
High-level input voltage, VIH All inputs except 2 2 V
Low-level input voltage, VIL differential inputs 0.8 0.8 V
Drivers -40 -40
High~level output current, IOH mA
Receivers -5 -5
Drivers 40 40
Receivers 15 15
'116, '1_18 15 15
Re'ceiver input voltage, VI V
'117, '119 0 6 0 6
Operating free-air temperature, T A -55 125 0 70 DC
TEXAS ~ 4-135
INSTRUMENTS
DIFFERENTIAL UNE TRANSCEIVERS
noted)
driver section
'116, '118 '117, '119
VIK Input clamp voltage Vee = MIN, II = -12 mA -0.9 -1.5 -0.9 -1.5 V
TA = 25e (SN55') 10H = -10 mA 2.4 3.4 2.4 3.4
Vee = MIN,
TA = ooe to 70 0 e (SN75') 10H = -40 mA 2 3 2 3
VOH High-level output voltage VIL = 0.8 V, V
TA = -55e to 125C 10H = -10 mA 2 2
VIH =2V
(SN55') 10H = -40 mA 1.8 1.8
Vee = MIN, VIH = 2 V,
VOL Low-level output voltage 0.4 0.4 V
VIL= 0.8 V, 10L = 40 mA
VOK Output clamp voltage Vee = MAX, 10 = -40 mA, DE at 0.8 V -1-5 -1.5 V
TA = 25C 1 10
Off-state open-collector Vee = MAX,
10(off) output current Vo = 12 V TA = MAX
I SN55' 200 "A
I SN75' 20
Vee = MAX, Vo =0 to Vee, DE at 0.8 V,
10
Off-state TA = 25C
10Z (high-impedance-state) Vee = MAX, Vo =0 I SN55' -300 "A
output current DE at 0.8 V, Vo = 0.4 V to Vee I SN55' 150
TA = MAX Vo = 0 to Vee I SN75' 20
Input current
II at maximum Vee = MAX, VI = 5.5 V 1 1 mA
input voltage Driver or
High-level enable
IIH Vee = MAX, VI = 2.4 V 40 40 I'A
input current input
Low-level
IlL Vee = MAX, VI = 0.4 V -1.6 -1.6 mA
input current
Short-circuit
lOS Vee = tJl AX , Vo = 0, TA = 25C -40 -120 -40 -120 mA
output current
Supply current (driver
ICC Vee = MAX, TA = 25C 42 60 42 60 mA
and receiver combined)
t All parameters with the exception of off-state open-collector output current are measured with the active pull-up connected to the sink output. For conditions
shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
* All typical values are at Vee = 5 V and TA = 25C.
Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
switching characteristics, Vee = 5 V, eL -= 30 pF, TA -= 25e

driver section
tpLH Propagation delay time, low-to-high-Ievel output 14 30
See Figure 13 ns
tpHL Propagation delay time, high-to-Iow-Ievel output 12 30
tpZH Output enable time to high level RL = 1800, See Figure 14 8 20 ns
tpZL Output enable time to low level RL = 2500, See Figure 15 17 40 ns
tpHZ Output disable time from high level RL = 1800, See Figure 14 16 30 ns
tpLZ Output disable time from low level RL = 2500, See Figure 15 20 35 ns
4-136 TEXAS
INSTRUMENTS
-111
electrical characteristics over recommended operating freeair temperature range (unless otherwise
noted)
receiver section
'116, '118 '117, '119
MIN TYP~ MAX MIN TYP~ MAX
Vee; MIN,
0.5 0.5
Differential input Vo ; 0.4 V, IOL ; 15 mA, See Note 4
VTH V
high-threshold voltage See Note 3 Vee; 5 V,
See Note 5
Vee; MIN,
-0.5' -0.5'
Differential input Vo ; 2.4 V, . IOH ; -5 mA, See Note 4
VTL V
low-threshold voltage See Note 3 Vee; 5 V,
-1' -1'
See Note 5
15
VI Input voltage range# Vee; 5 V, VID ; -1 Vorl V, See Note 3 to to V
III
-15 0
Vee '; MIN, VID ; -0.5 V,
2.4 2.4
IOH; -5 mA, See Note 4
See Note 3 Vee; 5 V, VID ; -1 V,
See Note 5
Vee; MIN, VID ; 0.5 V,
2.4 2.4
...
fA
Q)
0.4 0.4
IOL; 15 mA, See Note 4
V
>
VOL
See Note 3 Vee; 5 V, VID ; 1 V,
0.4 0.4
'iii
See Note 5 CJ
II(rec) Receiver input current
Input current at
maximum input
Strobe
Vee; MAX,
See Note 3
Vee; MIN,
Vstrobe ; 4.5 V
VI; 0 V,
VI; 0.4 V,
VI ; 2.4 V,
VID ; -0.5 V,
Other input at 0 V
other input at 2.4 V
Other input at 0.4 V
'116, '117
-0.5
-0.4
0.1
-0.9
-0.7
0.3
-0.5
-0.4
0.1
-1
-0.8
0.4
mA
I'A
-...
Q)
a::
fA
Q)
>
'i:
voltage Enable Vee; MAX, VI ; 5.5 V '118, '119 mA
High-level
C
IIH Enable Vee; MAX, VI ; 2.4 V '118, '119 40 40 I'A Q)
input current
t:
Low-level Strobe
Vee; MAX, VID ; 0.5 V,
Vstrobe ; 0.4 V, See Note 4
'116, '117 -2.4 -2.4
mA
::;
IlL
input current
Enable Vee; MAX, VI ; 0.4 V '118, '119 -1.6 -1.6
Response-time-control Vee - MAX, VID ; 0.5 V,
I(Re) TA ; 25e -1.2 mA
current (Pin 9) Re at 0 V, See Note 4
Vee; MAX, TA ; 25e 10
Off-state open-collector
IO(off) Vo; 12V, SN55' 200 I'A
output current TA ; MAX
VID; -lV SN75' 20
TA - 25e '118, '119 10 10
Off-state Vee; MAX, SN55118 150
10Z (high-impedance state) yo; OtoVee, SN55119 150 I'A
TA ; MAX
output current RE at 0.4 V SN75118 20
SN75119 20
RT line-terminating resistance Vee; 5 V TA ; 25C 77 167 0
Short-circuit Vee; MAX, Vo ; 0,
lOS TA ; 25C -15 -80 -15 -80 mA
output current! VID; -0.5 V, See Note 4
Supply current (driver Vee - MAX, VID - 0.5 V,
Ice TA ; 25e 42 60 42 60 mA
and receiver combined) See Note 4
t Unless otherwise noted Vstrobe ; 2.4 V. All parameters with the exception of off-state open-collector output current are measured with the active pull-up
connected to the sink output. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
* All typical values are at Vee; 5 V, TA ; 25e, and Vie; O.
Differential voltages are at the B input terminal with respect to the A input terminal. Neither receiver input of the '117 or '119 should be taken negative
with respect to GND.
, The algebraic convention, where the less positive (more negative) limit is designated'as minimum, is used in this data sheet for threshold voltages only.
#Input voltage range is the voltage range that, if exceeded at either input, will cause the receiver to cease functioning properly.
I Not more than one output should be shorted at a time.
NOTES: 3. Measurement of these characteristics on the '117 and '119 requires the driver to be disabled with the driver enable at 0.8 V.
4. This applies with the less positive receiver input grounded.
5. For '116 and '118, this applies with the more positive receiver input at 15 V or the more negative receiver input at - 15 V. For '117 and '119,
this applies with the more positive receiver input at 6 V.
TEXAS . . 4-137
INSTRUMENTS
DIFFERENTIAL LlN~ TRANSCEIVERS
switching characteristics, Vce

receiver section
tpLH Propagation delay time, low-to-high-Illltel output 20 75 ns
RL = 400 n, See Figure 16
tpHL Propagation delay time, high-to-Iow-Ievel output 17 75 ns
tpZH Output enable time to high level '118 RL = 480 n, See Figure 14 9 20 ns
tpZL Output enable time to low level and RL = 250 n, See Figure 1 5 16 35 ns
tpHZ Output disable time from high level '119 RL = 480 n, See Figure 14 12 30 ns
tpLZ Output disabie time from low level only RL = 250 n, See Figure 15 17 35 ns
III
r-
DRIVER OUTPUT VOLTAGE
vs
DRIVER INPUT VOLTAGE
DRIVER OUTPUT VOLTAGE
vs
DRIVER INPUT VOLTAGE
S'
(1)
6
No load
6
Vee =5 V
fA" 25e No load
C
5 5
<'"'"
-
(1)
>I Vee = 5.5 V >I
"'"
(II
Q) 4 4
CI Vee = 5 V Q)
jJ
(1)
~
"0 Vee = 4.5 V
N'
"0
("')
(1)
> >...
+' 3 3
<'
(1)
:I
S-
:I
:I
&
:I ~ TA = _55e
"'"
(II
0 0
I 2 I 1
0 0 2 0 -
> > ~- - TA = 25 e
. TA=125e -
I
o 2 .
o I
o 3 4 () 2 3 4
VI-Date Input Voltage-V VI-Data Input Voltage-V

FIGURE 1 FIGURE 2
4-138 TEXAS . .
INSTRUMENTS
TYPICAL CHARACTERISTics
DRIVER HIGH-LEVEL OUTPUT VOLTAGE DRIVER LOW-LEVEL OUTPUT VOLTAGE
vs vs
6r-----~----~----~-----,----~ 0.6
I D
TA = 25 C
~ 5~----+-----~-----+----~----~
~ 0.5
~
~ III
C) VCc=[/ ~
!9 !9
~ 4~"""""""-~- ~ 0.4
... ...
J~
:::I
Vce = 5.5 V
a-:::I :::I
Co
o 3~-=--+- 8 0.3
V
II
Q;
> Q;
III >
...I
t 2~----4_----~-----+----~r---~
...I
III
~ 0.2
/
J:
I ...I
o V ...
(/)
>
:t:
o ~ 0.1
I
...I / Q)
:>
V "a;
(,)
Q)
-20 -40 -60

IOH-High-Level Output Current-rnA
-80 -100
o
o 20 40 60. 80
IOL -Low Level Output Current-rnA
100 120
-...
a:
I I)
Q)
:>
FIGURE 3 FIGURE 4 "i:
DRIVER PROPAGATION DELAY TIMES DRIVER OUTPUT ENABLE AND DISABLE TIMES C
vs vs Q)
FREE-AIR TEMPERATUREt FREE-AIR TEMPERATUREt s:::::
:.:::i
20 30 I I
VCC= 5 V VCC = 5 V
18 CL = 30 pF See Note 6
See Figure 13 '"c: ./
-- -
/. 25 /'
~
'" 16
,.........,. , /
c:
- --""'" III
I
-----
tPLH I--- E
~ 14 i= 20
E
-~
I---
~~
III
i= 12 ::c tpZL
tpHL 51
~ tPHZ
is
~ 10 "'C 15
c: c:
.g '"
-
8 III
::c
'"g' '"c 10
g- 6 w
... tpZH
c: 4
:::I
a-:::I
0 5
2
o
-75 -50 -25 0 25 50 75 100 125 ':75 -50 -25 0 25 50 75 100 125
T A-Free-Air Temperature-DC TA-FreeAir Temperature-DC
FIGURE 5 FIGURE 6
t Data for temperatures below OOC and above 70 DC are applicable to SN55116 through SN55119 devices only.
NOTE 6: For tpZH and tpHZ: RL = 180 n, see Figure 14. For tpZL and tPLZ: RL = 250 n, see Figure 15.
TEXAS ~ 4-139
INSTRUMENTS
RECEIVER OUTPUT VOLTAGE RECEIVER OUTPUT VOLTAGE
vs vs
DIFFERENTIAL INPUT VOLTAGE DIFFERENTIAL INPUT VOLTAGE t
6 6
Vee = 5.5 V Load = 2 kn to Vee Vee= 5 V
Load = 2 kn to Vee
5
Vee = 5 V TA = 25e
5 , ,
Vee = 4.5 V
" >1 '"
'" ~
til
CI
4
t4-- TA = 125e
'0
>.... 1
::I
3
S- I
::I
0
+- -TA=25 e
1
0 2
> T A = -55e ---+
\. \
o
-0.1 o 0.1 0.2 -0.2 -0.1 o 0.1 0.2
VID-Differential Input Voltage-V VID-Differential Input Voltage-V
FIGURE 7 FIGURE 8
RECEIVER PROPAGATION DELAY TIMES RECEIVER OUTPUT ENABLE AND DISABLE TIMES
vs vs
FREE-AIR TEMPERATUREt FREE-AIR TEMPERATUREt
30 30
11-
Vee= 5 V
RL = 400 n / 25
Vee = 5 V
See Note 7
tvV
25 See Figure 16 c'"
'"c tP~
/' J.
til
J. ~
E
E 20 ./ i= 20
i=
>
co
~ 15
c
o
.;:
--- ~
~
-~~
tpHL
./' til
::c
~
is 15
'tI
c
"'
til
::c
- ---
-I---
-f.--- ~
~ f--.--
...-- VI tpZL
l.---+--
tPHZ
-
~ 10 I
10
co
c. c
w"'
o ....::I tPZH
Q:
5 S-
::I 5
0
o o
-75 -50 -25 0 25 50 75 100 125 -75 -50 -25 0 25 50 75 100 125
TA-Free-Air Temperature-Oe T A -Free-Air Temperature-e
FIGURE 9 FIGURE 10
t Data for temperatures below ooe and above 70 e are applicable to SN55116 through SN55119 devices only.
0
NOTE 7: For tpZH and tpHZ: RL = 480 {l, see Figure 14. For tpZL and tpLZ: RL = 250 {l, see Figure 15.
4-140 TEXAS
INSTRUMENTS
SUPPLY CURRENT (DRIVER AND RECEIVER) SUPPLY CURRENT (DRIVER & RECEIVER)
vs vs
SUPPLY VOLTAGE FREE-AIR TEMPERATUREt
80 I I.
50
No load
45
- r---
<t
E
.!.c:
70
60
50
TA = 25e
/V
/

E
.!.c:
40
35
30
~
-- r--
~
:;
u 40
/ ~
:;
u 25
>
Q.
Q,
:l
CIl
u
I
!:? 20
30
~/
V >
Q.
Q,
:l
CIl
I
u 15
!:?
20
III
... en
Q)
10
) 10
"Qi
>
5 I - Vee = 5V CJ
o
o
-Y 2 3 4 5 6 7 8
o 1 I
-75 -50 -25 0 25 50 75 100 125 -...
a:
Q)
en
Q)
vee-Supply Voltage-V T A -Free-Air Temperature-e
"i:
>
FIGURE 11 FIGURE 12
C
t Data for temperatures below OC and above 70C are applicable to SN55116 through SN55119 devices only. Q)
t:
:.::l
TEXAS ~ 4-141
INSTRUMENTS
POST OFFICE 80X 655012 OALLAS. TEXAS 752GS
FROM OUTPUT
UNDER TEST
PARAMETER
---ra---- TEST
POINT
CL = 30 pF
ME~SUREMENT INFORMATION
FROM OUTPUT
UNDER TEST - -....
r----41t-- TEST
POINT
CL = 30 pF -=RL
~ (See Note B) (See Note B) ~
LOAD CIRCUIT LOAD CIRCUIT
I+-""s ns -1 14-""S ns
.JI~___...;...-......~- 1- - - - - - -3 V
90% 90% I ,-"-""S ns
INPUT 1.SV I I
I ~10_o/,_._ _ _ _ 0V
I.---.t-
I
tpLH
I - - - - VOH
NAND
I
'-----.;.1_-' _____ VOL
OUTPUT
r
S
CD
AND
OUTPUT
_---I4_~1 tpHL
\~5:---
V
OH
"",----VOL
C
.... VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
C
-
CD FIGURE 13. tpLH and tpHL (DRIVERS ONLY) FIGURE 14. tPZH and tPHZ
....
(I)
:0 SV
CD
C')
~RL =2S0 n
CD FROM OUTPUT TEST
C UNDER TEST --+
....- ...--- POINT FROM OUTPUT_...._ ..._ .....................-___...---..
UNDER TEST
CD -LCL =30pF
....
(I) ~ (See Note B)
-.t \4-""s ns
--.r~- ......~-I- - - - - 3 V
I ~ l4-""s ns
INPUT 1.S V I 1
I 10% BINPUT 1
OV (See Note E) I SO%
I
10% I
I ~ -.I
I tPLZ~
---- I !~ Voff=SV VOH
OUTPUT ~.SV 1~:iV OUTPUT

"' VOL
FIGURE 15. tPZL and tPLZ FIGURE 16. tPLH and tPHL (RECEIVERS ONLY)
NOTES: A. Input pulses are supplied by generators having the following characteristics Zout = 50 n, PRR :s 500 kHz, tw = 100 ns.
D. When testing the '116 and '118 receiver sections, the response-time control and the termination resistor pins are left open.
E. For '116 and '118, VH = 3 V, VL = -3 V, the A input is at 0 V.
For '117 and '119, VH = 3 V, VL = 0 V, the A input is at 1.5 V ..
4-142 TEXAS . .
INSTRUMENTS
SN55121, SN75121
DUAL LINE DRIVERS
01334. SEPTEMBER 1973-REVISEO SEPTEMBER 1986
Designed for Digital Data Transmission over SN55121 .. J PACKAGE

50-n to 500-n Coaxial Cable, Strip Line, or SN75121 ... D. J. OR'N PACKAGE
Twisted Pair (TOP VIEW)
1A VCC
High-Speed. . . tpd - 20 ns Max at
18 2F
CL - 15 pF
1C 2E
TTL Compatible with Single 5-V Supply 10 20
1E 2C
2.4-V Output at IOH - - 75 rnA
1F 28
Uncommitted Emitter-Follower Output 1Y 2A
Structure for Party-Line Operation GNO 2Y
AND-OR Logic Configuration
II
(TOP VIEW)
Designed for Use with Triple Line Receivers U
SN55122, SN75122 co <l:: U Uu..
.-2>""
Signetics N8T13 1C 4
3 2 1 20 19
18 2E
...
CI)
Q)
10 5 17 20 :>
description 'iii
NC 6 16 NC (.)
TheSN55121 andSN75121 dual line drivers are

designed for digital data transmission over lines
having impedances from 50 to 500 n. They are
also compatible with standard TTL logic and
1E
1F
7
8
9 1011 12 13
>-OU>-<l::
15
14
2C
28
-...
a:
Q)
CI)
Q)
:>
supply voltage levels. '-22"""" 'i:
(!)
C
The low-impedance emitter-follower outputs of NC-No internal connection Q)
the SN55121 and SN75121 will drive c:
terminated lines such as coaxial cable or twisted ::i
pairs. Having the outputs uncommitted allows FUNCTION TABLE
wired-OR logic to be performed in party-line
INPUTS OUTPUT
applications. Output short-circuit protection is
A B C 0 E F Y
provided by an internal clamping network that
H H H H X X H
turns on when the output voltage drops below
X X X X H H H
approximately 1.5 volts. All of the inputs are in
All other input combinations L
conventional TTL configuration and the gating
can be used during power-up and power-down H = high level
sequences to ensure that no noise is introduced L= low level
to the line. X = irrelevant

operation from a C to 70 DC.
~~~~~:~~i~a{~:I~tl~ ~!~~~~ti~f :IIO::~:~:t::s~s not INSTRUMENTS
SN55121, SN75121
DUAL LINE DRIVERS

(1 ) & 1A~:-...,...-_
1A
(2) 1B
18
(3) 1C
1C (7) 1Y
(4) 10...:.;:.:..........- - "
10
(5) 1E
1E &
(6) 1F
1F
(10)
2A
(11) 2A~~_-_...
28
(12) 2B
2C (9) 2Y
(13) 2C
20 20.......:~......- - "
(14)
2E
(15) 2E
2F
2F
tThis symbol is in accordance with ANSIIIEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for J ~nd N packages.
r-
S'
CD schematic (each driver)
C
~ VCC-----.------.------.-----.------------._--~~----._------~~
<'CD TO OTHER
-
15.n
~ LINE DRIVER
en
::Jl
CD
n A----........., J
CD
<'
CD
B-----+--.
C ----t---I~
~
en o -----t---H-.
E----~~-r+_------------~ ~----+-~~--- y
F-----t---H-+----------------4-t
GNO----~~~~--------------~~~_.~--~~~~~~~-------J
TO OTHER
LINE DRIVER
Input voltage 6 6 V
Output voltage 6 6 V
D package 950
Continuous total dissipation at (or l:jelow) FK or J package 1375 mW
25C free air temperature (see Note 2) J package 1025
N package 1150
NOTES: 1. All voltage values are with respect to both ground terminals connected together.
2. For operation above 25C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the J package, SN55121
chips are alloy mounted and SN75121 chips are glass mounted. In the N package, use the 9.2 mW/oC curve for these devices.
4-144 TEXAS . .
INSTRUMENTS
1>0st OFFICE I30X 655012 DALLAS. TeXAs 15265
SN55121, SN75121
DUAL LINE DRIVERS

SN55121 SN75121
UNIT
low-level input voltage, Vil 0.8 0.8 V
High-level output current, 10H -75 -75 mA
Operating free-air temperature, T A -55 125 a 70 C
VIK Input clamp voltage VCC = 5 V, II = -12 mA -1.5 V
V(BR)I
VOH
10H
Input breakdown voltage
High-level output current

VCC = 5 V,
VIH = 2 V,
VCC = 5 V,
TA = 25C,
II = 10 mA
10H = -75 mA,
VIH = 4.5 V,
See Note 3
See Note 3
VOH = 2 V,
5.5
2.4
-100 -250
V
V
mA
II
'U)
...
10l low-level output current Vil = 0.8 V, VOL = 0.4 V, See Note 3 -800 JlA (1)
10(0ft) Off-state output current VCC = 3 V, Vo = 3 V 500 JlA

>
'iii
IIH High-level input current VI = 4.5 V 40 JlA (.)
(1)
-...
low-level input current VI = 0.4 V -0.1 -1.6 mA
III
Short-circuit output current T VCC = 5 V, TA = 25C -30 mA
a:
lOS U)
ICCH Supply current, outputs high VCC = 5.25 V, All inputs at 2 V, Outputs open 28 mA
(1)
ICCL Supply current, outputs low VCC = 5.25 V, All inputs at 0.8 V, Outputs open 60 mA >
'a:
tNot more than one output should be shorted at a time. C
NOTE 3. The output voltage and current limits are guaranteed for any appropriate combination of high and low inputs specified by the (1)
function table for the desired output. s::::::
:::l
switching characteristics, Vee = 5 V, T A
tplH Propagation delay time, low-to-high-Ievel output Rl = 37 n, Cl = 15 pF, 11 20
ns
tpHl Propagation delay time, high-to-Iow-Ievel output See Figure 1 8 20
tplH Propagation delay time, low-to-high-Ievel output Rl = 37 n, Cl = 1000 pF, 22 50
ns
tpHl Propagation delay time, high-to-Iow-Ievel output See Figure 1 20 50

...-" 5 ns --eoI 1--" 5 ns
3V -=-=-:-:-__~~'- -r - - - -
;,1 3V
90% I
PULSE
INPUT
1.5V I l
I 10% OV
I
)-I-e.....----e~ OUTPUT tpLH-foO----<.~1 I
I I tpH L -;.------.i
- --T.J I RL
~
CL
,So.N B) OUTPUT
_ _ _ _J
f.5V
I I
1.5.>L---
v ~VOL
V
OH

NOTES: A: The pulse generators have the following characteristics: Zout '" 50 n, tw = 200 ns, duty cycle s 50%.
B. Cl i~cludes probe and jig capacitance.
TEXAS ~ 4-145
INSTRUMENTS
SN55121. SN75121
DUAL LINE DRIVERS
OUTPUT CURRENT vs OUTPUT VOLTAGE
-300
Vee = 5 V
VIH = 2V
-250 TA = 25e-
oct
E I\.
}. -200
c '\
~
<3
...
6
:J
a-
-150
-100
"r\1\
III
I
9
-50
r-
:i'
CD
o
o 0.5 1 1.5 2 2.5 3
\
3.5 4 4.5 5
...c Vo-Output Voltage-V

<'CD FIGURE 2
...
VI
iCD TYPICAL APPLICATION DATA
C')
CD i -1/3 SNSS122- - i
<' I
...
CD
VI
I
I
I
L.!!~ ~~!3!" J
I
I
I
L_1L?J!~~~:d
FIGURE 3. SINGLE-ENDED PARTY LINE CIRCUITS
4-146 TEXAS
INSTRUMENlS
POST OFFICE BOX 85501 a DAL~AS, 'rEXA!> 15265
SN55122, SN75122
TRIPLE L1NERECEIVERS
01334, SEPTEMBER 1973-REVISED SEPTEMBER 1986
Designed for Digital Data Transmission Over SN55122 . J PACKAGE

Coaxial Cable, Strip Line, or Twisted Pair SN75122 . D. J. OR N PACKAGE
(TOP VIEW)
Designed for Operation with 50n to 500n
Transmission Lines 1A VCC
1B 15
TTL Compatible 2R 1R
Single 5-V Supply 25 1Y
2A 3A
Built-In Input Threshold Hysteresis 2B 35
High Speed . . . Typical Propagation 2Y 3R
Delay Time = 20 ns GND 3Y
Independent Channel Strobes

II
Input Gating Increases Application Flexibility (TOP VIEW)
U
Fanout to 10 Series 54/74 Standard Loads al~UUcn
.......... Z> .....
Can be Used with Dual Line-Drivers
SN55121 and SN75121 3 21 20 19 ... CI)
(1)
2R 4 18 1R
Interchangeable with Signetics N8T14 >
25 5 17 1Y 'iii
16 (.)
NC 6 NC
description
The SN55122 and SN75122 are triple line-
2A
2B
7
8
9 1011 12 13
>-OU>-a:
15
14
3A
35
-...
a:
(1)
CI)
(1)
>
receivers that are designed for digital data NZZMM 'iI:
transmission over lines having impedances from (!) C
50 to 500 ohms. They ar~ also compatible with Q)
standard TTL logic and supply voltage levels.

NC-No internal connection c:
:.J
The SN55122 and SN75122 have receiver inputs with puilt-in hysteresis to provide increased noise margin
for single-ended systems. The high impedance of this input presents a rninilTlum load to the driver and
allows termination of the transmission line in its characteristic impedance to minimize line reflection. An
open line will affect the rec;eiver input as would a 19w-level voltage. The receiver can withstand a level
of -0.15 volt with power on or off. The other inputs are in TTL cOllfiguratic)O. The S input must be high
to enable the receiver input. Two of the line receivers have A an~ Binputs that, if both are high, will hold
the output low, The third receiver has only an A input that, if high, will hold the output low.
The SN55122 is characterized for operation over the full military temperature range of - 55 ac to 125 ae.
The SN75122 is characterized for operation from oae to 70 ae.

nacaulrily include testing of III piralllaters.
TEXAS
INSTRUMENTS
-1!1 4-147
POST OFFICE BOX 655012 OALLAS. TEXAS '6265
SN55122, SN75122
TRIPLE LlNERECEIVERS
logic symbol t logic diagram
1R
1R 18----~~-----L __- ' (13)
XJ----1Y
18
1A~~--------~--'
1A
18 1B -------------1
2R 2R -----<1rr
28 2S--~~~----~--~ (7)
2A D-----2Y
28 2A ------------~
2B - - - - - - - - - - -....
3R
3R
38
III
3S---~~----~ __~ (9)
3A ]00----- 3Y
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and 3A -----------4

r- lEe Publication 617-12 ..
5' Pin numbers shown are for D. J. and N packages.
CD
FUNCTION TABLE
...C
<'CD INPUTS OUTPUT
...
-
en
~
CD
(')
CD
A
H
X
L
L
B*
H
X
X
X
R
X
L
H
X
S
X
H
X
L
Y
L
L
H
H
<' X L H X H
...enCD X L X L H
t B input lind last two lines of the

function table are applicable to
receivers 1 and 2 only.
H = high level
L = low level
X = irrelevant
TEXAS
INSTRUMENTS
SN55122, SN75122
schematic diagram (each receiver)
vcc~~.---~~~.--.----~~--e-----------~~----------~~~~-------------,
TO OTHER 4 kn 800 n 58 n
RECEIVERS
R (14.3.10)
(13.7.9)
,..-----V
III
...
(/)
CD
>
'a;
U
CD
-...
a:
(8)
GND~---'-4~~~--4
TO OTHER A (1.5.12) ( /)
RECEIVERS (2.6) CD
w ...
8-----
>
''::
VCC bus C
B input is provided on receivers 1 and 2 only. CD
Resistor values shown are nominal. c
::J
Supply voltage, VCC (see Note 1) .................. " . . . . . . . . . . . . . . . . . . . . . . . . . .. 6 V
Input voltage: R input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6 V
A, 8, or S input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6 V
Output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 mA
Continuous total power dissipation at (or below) 25C case temperature (see Note 2):
D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950 mW
J or FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . . . . . . .. 1375 mW
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 50 mW
SN75122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ooC to 70C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ........ 260C

2. For operation above 25C free-air temperature. refer to the Dissipation Derating Curves in Appendix A. In the FK and J package,
SN55122 chips are alloy mounted and in the J package, SN75122 chips are glass mounted. For derating the N package.
use the S.2-mW/oC curve and for the D package. use the 7.6-mW/oC curve.
TEXAS
INSTRUMENTS
-1!1 4-149
SN55122. SN75122

MIN NOM MAX UNIT
Supply voltage, Vee 4.75 5 5.25 V
High-level input voltage, VIH I A, B, R, or S 2 V
Low-level input voltage, VIL I A, B, R, or S 0.8 V
High-level output current, IOH -500 p.A
.
Operating free-air temperature, TA II SN55122
SN75122
-55
0
125
70
e
e
electrical characteristics over recommended operating free-air temperature, Vee"" 4.75 V to 5.25 V
VhYs* Hysteresis I R Vee == 5 V, TA == 25e 0.3 0.6 V
VIK Input clamp voltage I A,B, or S Vee == 5 V, II == -12 mA -1.5 V
VI(BR) Input breakdown voltage I A,B, or S Vee == 5 V, II == 10mA 5.5 V
r- VIH == 2 V, VIL == 0.8 V, IOH == -500 p.A 2.6
5' VI(A) == 0, VI(B) == 0, VI(S) == 2 V,
CD VOH High-level output voltage V
VI(R) == 1.45 V (see Note 3). 2.6
C
... IOH == -500 p.A
c' VIH == 2 V, VIL == 0.8 V, IOL == 16 mA 0.4
...VJ
CD
-
VI(A) == 0, VI(B) == 0, VI(S) == 2 V,
VI(R) == 1.45 V (see Note 4). 0.4
:IJ IOL == 16 mA
CD
(')
Highlevel input current
I A,B, or S VI == 4.5 V 40
p.A
CD IIH
c' I R VI == 3.8 V 170
I
...VJ
CD IlL
IOS
Short-circuit output current
A,B, or S VI == 0.4 V,
Vee == 5 V,
VIR == 0.8 V
TA == 25e
-0.1
-50
-1.6
-100
mA
mA
ICCH High-level supply current Vce == 5.25 V, All inputs at 0.8 V, Outputs open 72 mA
leCL Low-level supply current Vee == 5.25 V, All inputs at 2 V, Outputs open 10q mA
t All typical values are at Vee == 5 V and T A == 25e.

* Hysteresis is the difference between the positive-going input threshold voltage, VT +, and the negative-going input threshold voltage,
VT _. See Figure 4.
Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
NOTES: 3. The receiver input was high immediately before being reduced to 1.45 V.
4. The receiver input was low immediately before being increased to 1.45 V.
switching characteristics, Vee "" 5 V, T A ... 25e

tpLH Propagation delay time, low-to high-level output from R input See Figure 1 20 30
tpHL Propagation delay time, high-to-Iow-Ievel output from R input See Figure 1 20 30
4-150 TEXAS
INSTRUMENTS
-1!1
SN55122. SN75122
VCC 2.6 V 14-- s 5 ns ---+I t4- s 5 ns

:,.1...".,...,.,...._ _ _ _~I_+_---2.6V
90% 90% I
84.5 fl
I
1.5 V I
PULSE 1N3064 I : 10%
I
OV
GENERATOR I
(see Note Al 1O+.....--4t--. . .- OUTPUT ~tPLH I
I tPHL-I114-4-~.:
I
CL - 5 kfl
\i~.~VVOH
OU_T_PU_T_ _ .J}' V
~VOL
II
NOTES: A. The pulse generator has the following characteristics: Zout '" 50 fl, tw = 200 ns, duty cycle = 50%.
~. CL includes probe and jig capacitance.
FIGURE 1. SWITCHING TIMES ...(/)

(1)
:>
'iii
(,)
TYPICAL CHARACTERISTICS (1)
OUTPUT VOLTAGE
vs
-...
a::
( /)
(1)
:>
INPUT VOLTAGE 'i:
4.0 C
V~C !:
1
5 V (1)
3.5 -No load t:
TA -= 25C ::J
:> 3.0
I
Q)
Cl
!9 2.5
"0
:>
:; 2.0
Co VT- VT+
:; 1.5
0
I
0 1.0
:>
0.5
o
o 0.4 0.8 1 1.4 1.8 2
VI-Input Voltage-V
FIGURE 2
TEXAS ~ 4-151
INSTRUMENTS
SN55122. SN75122
TRIPLE L1NERECEIVERS
i- v3sN5s122--i
I
I
II
r-
S"
L...:!~~~~~J
I
I
CD
...C<"
...en
-
CD
:D
CD I
n
CD I
<" I
...
CD
en
L.2/~S~~1~1_J
FIGURE 3. SINGLEENDED PARTY LINE CIRCUITS
R
INPUT
OUTPUT
The high gain and built-in hysteresis of the

. SN55122 and SN751221ine receivers enable them
to be used as Schmitt triggers in squaring pulses.
FIGURE 4. PULSE SQUARING
4152 TEXAS
INSTRUMENTS
-111
POST OFFice BOX 655012 " DALLAS. TeXAS 75265
SN75123
DUAL LINE DRIVER
Meets IBM System 360 Input/Output D, J, OR N PACKAGE

Interface Specifications (TOP VIEW)
Operates from Single 5-V Supply 1A VCC

18 2F
TTL Compatible 1C 2E
3.11 V Output at IOH - - 59.3 rnA 10 20
1E 2C
Uncommitted Emitter-Follower Output 1F 28
Structure for Party-Line Operation 1Y 2A
Short-Circuit Protection GNO 2Y
AND-OR Logic Configuration

FUNCTION TABLE
Designed for Use with Triple Line Receiver
INPUTS OUTPUT
SN75124
Signetics N8T23
description
A
H
X
B
H
X
C
H
X
D
H
X
E F
X X
H H
All other input
V
H
H
L
II
..
CI)
Q)
combinations
>
The SN75123 dual line driver is specifically H = high level '0)
designed to meet the input/output interface CJ
-..
l = low level Q)
specifications for IBM System 360. It is also X = irrelevant a:
compatible with standard TTL logic and supply CI)
voltage levels. logic symbol t Q)
The low-impedance emitter-follower outputs of

>
'':
&
the SN75123 will drive terminated lines such as (1) 2:11> C
1A
coaxial cable or twisted pair. Having the outputs Q)
(2)
uncommitted allows wired-OR logic to be
1B c
1C
(3)
(71 1Y ~
performed in party-line applications. Output (4)
10
short-circuit protection is provided by an internal (5)
1E &
clamping network that turns on when the output (6)
1F
voltage drops below approximately 1 .5 volts. All (10)
the inputs are in conventional TTL configuration 2A
(11 )
and the gating can be used during power-up and 2B
(12)
power-down sequences to ensure that no noise 2C (9) 2Y
(13)
is introduced to the line. 20
(14)
2E
The SN7 5123 is characterized for operation from (15)
2F
ooe to 70C.
logic diagram, each driver (positive logic)

A_--.J--'"
B
C
D------.---
V
~~~~~:~~i~a{~~I~'J~ ~!~~~~ti:r lIlo::~:~:':rDs~S not
TEXAS -111 4-153
INSTRUMENTS
SN75123
DUAL LINE DRIVER
vee (16)
TO OTHER 4 kf! 4 kf! 15 f!

LINE DRIVER
A..;.....;~ .J
B-----+--..
e -'-'---+---+-.
D..:...;.:~'-t--Hr---.
(7,9) y
E~~~--~~4-------------------"
F~~~--~~-+-------------------~"
(S)
GND----~~~~------------------~e_~_.~~~~._~~._e_~~------~
TO OTHER
. LINE DRIVER
Resistor values shown are nominal.
Supply voltage, VCC (see Note 1) ................................ ; . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
D package ......................................................... 950 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package ....................................................... , 11 50 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 70C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............. 300C
2. For operation above 25e free-air temperature, derate the D package to 60S mW at 70 0 e at the rate of 7.6 mw/oe, the
J package to 656 mW at 70 0 e at the rate of S~2 mw/oe, and the N package to 736 mW at 70 0 e at the rate of 9.2 mw/oe.
In the J package, SN75123 chips are glass mounted.

MIN NOM MAX UNIT
Low-level input voltage, VIL O.S V
Operating free-air tempeature, T A 0 70 e
4-154 TEXAS.
INSTRUMENTs
POST O~FIC~ aOl< 655012 CALLAS, TEXAS 76265
SN75123
DUAL LINE DRIVER
electrical characteristics, vee 4.75 V to 5.25 V, TA o e to 70 0 e (unless otherwise noted)

VIK Input clamp voltage VCC = 5 V, II = -12 mA -1.5 V
V(BR)I Input breakdown voltage VCC = 5 V, II = 10 mA 5.5 V
VCC = 5 V, VIH = 2 V, ITA = 25C 3.11
10H = - 59.3 mAo See Note 3, ITA = ooC to 70C 2.9
VCC = 5 V, VIH = 4.5 V, VOH = 2 V,
10H High-level output current -100 -250 mA
TA = 25C, See Note 3
Val low-level output voltage VIL = 0.8 V, 10L = - 240 p.A, See Note 3 0.15 V
10(oft) Off-state output current VCC = 0, Va =3V 40 p.A
IIH High-level input current VI = 4.5 V 40 p.A
III low-level input current VI = 0.4 V -0.1 -1.6 mA
lOS Short-circuit output current t VCC = 5 V, TA = 25C -30 mA
VCC = 5.25 V,
II
All inputs at 2 V,
ICCH Supply current, outputs high 28 mA
Outputs open
VCC = 5.25 V, All inputs at 0.8 V,
ICCl Supply current, outputs low 60 mA
Outputs open
tNot more than one output should be shorted at a time.

...
tJ)
Q)
NOTE 3: The output voltage and current limits are guaranteed for any appropriate combination of high and low inputs specified by the ::>
function table for the desired output. 'iii
(.)
Q)
switching characteristics, Vee = 5 V, TA
-a:...
t J)
Q)
::>
tPL.H Propagation delay time, low-to-high-Ievel output RL = 50 fl. CL = 15 pF. 12 20
ns '':
tpHl Propagation delay time. high-to-Iow-Ievel output See Figure 1 12 20
C
tpLH Propagation delay time. low-to-high-Ievel output RL = 50 fl. Cl = 100 pF. 20 35
Q)
ns
tpHl Propagation delay time. high-to-Iow-Ievel output See Figure 1 15 25 t:
:.:::l
3 V VCC
~=:;5ns
r---- L -, INPUT
I 10%
~----OV
I
>-l~._--+_-OUTPUT tplH t4
=L----1-.J
I
I CL
(See Note B)
OUTPUT_ _ _ _
II
I
1.5 V
J
NOTES: A. The pulse generator has the following characteristics: Zout == 500; tw = 200 ns, duty cycle = 50%.
FIGURE 1. SN75123 SWITCHING TIMES
TEXAS ~ 4-155
INSTRUMENTS
SN75123
DUAL LINE DRIVER
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
-300
V~C .,.15 V I
All inputs at 2 V
-250 TA ... 25C

E
I\.
lc -200
~
'\
'" 1'\
:;
u
III ... -150

:::I
C.
:;
0 -100
I
r-
:i'
CD
9
-50 1\
...c
...<'
CD
o
o 2 3
1 4 5
f/)
VO-Output Voltage-V
iCD
(') FIGURE 2.
CD
<'
...
CD
f/) TYPICAL APPLICATION DATA
r------,
A -"-L-~-""
B --r---f
C
o
r-------. I
E -~--I"-' I I I
F --+---t._J I 95 n 95 n I y
L ___ ~2';N25~3 .J I A
I B---&.._,
L ____ -l3~N.::'~4.J
=
FIGURE 3. UNBALANCED LINE COMMUNICATION USING '123 AND '124
4-156 TEXAS ~
INSTRUMENTS
SN75124
TRIPLE LINE RECEIVER
Meets IBM System 360 Input/Output O. J .. OR N PACKAGE

Interface Specifications (TOP VIEW)
Operates from Single 5-V Supply 1A Vee

18 15
TTL Compatible 2R 1R
Built-In Input Threshold Hysteresis 25 1Y
2A 3A
High Speed ... Typical Propagation Delay 28 35
Time - 20 ns 2Y 3R
Independent Channel Strobes GND "'-t.:=--_-=..... 3Y
Input Gating Increases Application Flexibility
logic symbol t
Designed for Use with Dual Line Driver
SN75123 ' .LTC> & ~1
1R
15
Signetics N8T24
1A
description
1B
2R
...
CI)
Q)
The SN75124 triple line receiver is specifically >

25 'Q)
designed to meet the input/output interface 2A (.)
-...
Q)
specifications for IBM System 360. It is also
compatible with standard TTL logic and supply
2B a:
CI)
voltage levels. 3R Q)
The SN75124 has receiver inputs with built-in 35 >

''::::
3A
hysteresis to provide increased noise margin for C
single-ended systems. An open line will affect Q)
the receiver input as would a low-level input
tThis symbol is in accordance with ANSIIIEEE Std 91-1984 and c:
lEe Publication 617-12. :.:l
voltage and the receiver input can withstand a
level of -0.15 volt with power on or off. The
other inputs are in TTL configuration. The S input
must be high to enable the receiver input. Two
of the line receivers have A and 8 inputs that. 1R
if both are high. will hold the output low. The
15 ~~------~--~
third receiver has only an A input that. if high.
will hold the output low. 1A ....;..-------r-......
The SN75124 is characterized for operation from 1B ....!.::..:.....----I_...J
ooe to 70 oe.
2R
FUNCTION TABLE
25 ~~-----~--~
INPUTS OUTPUT
Bt y
A R 5 2A -----------~--~
H H X X L
28 ~------_L_~
X X L H L
L X H X H
L X X L H 3R
X L H X H
X L X L H 35 ~~---_L_~
*8 input and last two lines of the

function table are applicable to 3A ...:....~----I
receivers 1 and 2 only.
~~~~~:~~i~a{::I~l[~ ~!:~~~ti~r !J~o::~:~:t:r~~s not
TEXAS ~ 4-157
INSTRUMENTS
SN75124

(16)
VCC,---e~--e---~--~-----e---e----------~~----------~--e--------------.
TO OTHER 4 kn .800 n 58 n
RECEIVERS
R (14.3.10)
(13,7.9)
e-------y
II
r-
S (15. 4. 11)
:i"
CP
c
...
<' GND - -...... . - - . . - -.. A (1.5, lZ)
...
-
CP
(2.6)t
en B ------
: tI RECEIVERS
CP
(")
CP
<' W
'~ VCC bus
en tainput is provided on receivers 1 and 2 only.
absolute maximum ratings over operating free-air temperature range (unless other.wise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: R input with Vee applied. . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . . . . . ... 7 V
R input with Vee not applied ....................................... 6 V
A, 8, or S input ............................................... 5.5 V
Output voltage ............................................ .' . . . . . . . . . . . . . . .. 7 V
Output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 mA
eontinuous total dissipation at (or below) 25e free-air temperature (see Note 2):
D package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 950 mW
J package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1150 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 70 0 e
Storage temperature range ......................................... - 65 e to 150 e
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300 0 e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ........ 260 0 e

SN75124 chips are glass mounted. For these devices in the N package, use the 9.2-mW/oC curve.
4-158 TEXAS ~
INSTRUMENTS
SN75124

MIN NOM MAX UNIT
A, B, or S 2
R 1.7
A, B, or S O.B
R 0.7
High-level output current, IOH -800 p.A
Operating free-air temperature, T A 0 70 De
electrical characteristics, Vee 4.75 V to 5.25 V, TA o e to 70 0 e (unless otherwise noted)

Vhys Hysteresis (VT + - VT - ) R Vee = 5 V, TA = 25e 0.2 0.4 V
VIK Input clamp voltage A,B, or S Vee = 5 V, II = -12 mA -1.5 V
Input breakdown
A,B, or S Vee = 5 V, II = 10mA 5.5 V
V(BRlI
voltage
VIH = VIH min, VIL = VIL max, 10H = - 800 /lA,
...CD
tn

See Note 3
2.6 V >
'CU
VIH = VIH min, VIL = VIL max, IOL = 16 mA, (.)
-...
VOL Low-level output voltage 0.4 V CD
See Note 3
Input current at VI = 7 V 5
a:
II R mA tn
maximum input voltage VI = 6 V, Vee =0 5
CD
A,B, or S VI = 4.5 V 40 >
IIH /lA 'i:
R VI = 3.11 V 170
IlL Low-level input current A,B, or S VI = 0.4 V -0.1 -1.6 mA C
CD
lOS Short-circuit output current:!: Vee = 5 V, TA = 25e -50 -100 mA t:
lee Supply current Vee = 5.25 V 72 mA :.::i
t1ypical value is at Vee = 5 V, TA = 25e. ,
:I: Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 3: The output voltage and current limits are guaranteed for any appropriate combination of high and low inputs specified by the
function table for the desired output.
switching characteristics, Vee == 5 V, TA = 25e

tpLH Propagation delay time; low-to-high-Ievel output from R input 20 30
See Figure 1
tPHL Propagation delay time, high-to-Iow-Ievel output from R input 20 30
TEXAS -I!} 4-159

INSTRUMENTS
SN75124
~sSns -+t t+-sSns

VCC 2.6 V
84.S {}
;,.1__---~~~L+
90% 90% 1
-- ___ 2.6 V
I 1.SV 1.SV:
1 : 10% OV
1N3064
I I
~~~ __~~OUTPUT ~tPLH I
I tPHL~
S k{} I
OUTPUT f.5V \l.~~~ VOH

. LVOL
NOTES: A. The pulse generator has the following characteristics: Zout == SO {}. PRR s 5 MHz. duty cycle = 50%.
r- FIGURE 1. SN75124 SWITCHING TIMES

S'
(1)
.c<' TYPICAL CHARACTERISTICS

.
-
(1)
(f) OUTPUT VOLTAGE
vs
II
(1) RECEIVER INPUT VOLTAGE
n
(1) 4.0 1
<'
..
(1)
(f)
>
Vec':' 5 V
3.5 r-No load
TA - 25C
I 3.0
41
til
!9 2.5
"0
..
>
:l
2.0
VT- "VT+
So
:l
0 1.5
I
0 1.0
>
0.5
o
_..
o 0.20.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VI-Input Voltage-V
FIGURE 2
4-160 TEXAS . .
INSTRUMENTS
SN75124
I TYPICAL APPLICATION DATA
r------,
A -----.-'----'-_
B --r----I
C
o
E--.---r-, I I
I 95 fl 95 fl J Y
L ____ Y:..S~52:3.J I A
I B I
L ____ !. ':N~1!.4.J
=
FIGURE 3. UNBALANCED LINE COMMUN'ICATION USING SN75123 AND SN75124
III ...
t/)
CD
>
"Qi
(,)
-...
CD
a:
t /)
CD
>
"~
C
CD
c
:::i
TEXAS 4-161
INSTRUMENTS

4-162
SN75125, SN75127
SEVENCHANNEL LINE RECEIVERS
D2239. JANUARY 1977-REVISED SEPTEMBER 1986
Meets IBM 360/370 I/O Specification SN75125 ... D. J. OR N PACKAGE

Input Resistance ... 7 k!l to 20 k!l (TOP VIEWI
1A 1Y
Output Compatible with TTL
2A Vee
Schottky-Clamped Transistors 3A 3Y
4A 4Y
Operates from Single 5-V Supply
5A 5Y
High Speed ... Low Propagation Delay 6A 6Y
7A 7Y
Ratio Specification for Propagation Delay
GND 2Y
Time, Low-to-High/High-to-Low
Seven Channels in One 16-Pin Package SN75127 ... D. J. OR N PACKAGE
Standard VCC and Ground Positioning on (TOPVIEWI
II
SN75127 1A Vee
2A 1Y
description 3A 2Y
The SN75125 and SN75127 are monolithic 4A 3Y en
~
seven-channel line receivers designed to satisfy 5A 4Y Q)
the requirements of the IBM System 360/370 6A 5Y >

7A 6Y 'a:;
input/output interface specifications. Special (,J
low-power design and Schottky-clamped
transistors allow for low supply-current
requirements while maintaining fast switching
speeds and high-current TTL outputs.
GND 7Y
-Q)
a::
en
~
Q)
>
'i:
The SN75125 and SN75127 are characterized C
for operation from OOC to 70 o C. Q)
r:::
:i
logic symbols t
SN75125 SN75127
1A 1Y 1A 1Y
2A 2Y 2A 2Y
3A 3Y 3A 3Y
4A 4Y 4A 4Y
5A 5Y 5A 5Y
6A 6Y 6A 6Y
7A 7Y 7A 7Y
tThese symbols are in accordance with ANSIIIEEE Std 91-1984 and lEG Publicaiton 617-12.
~~~~~:~~i~ai~~1~1~ ~!~~~~tigr f,~o::~:~:t:r~~S not
TEXAS ~ 4-163
INSTRUMENTS
SN75125, SN75127
COMMON CIRCUITRY
VCC
r - - ~ - --, TO OTHER
CHANNELS
15011
NOM
A-_~,.........j
INPUT
Y
OUTPUT
12 kll
r- NOM
5'
CD
...c
<'
...
CD
(II
GND~.-t---~~---i~~--------~----~.-----+~~~-~~--+-~--~
'i
CD
L -_ _ _ _ _ _ _ _ _ _ _ _ _~~--------~_+- ..... TO OTHER
(')
CHANNELS
CD ~--------------~---~L--------~~~~
<'
...
CD
(II
Supply voltage, VCC (see Note 1) .' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage range: SN75125 ... " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.15 V to 7 V
SN75127 .......................................... -2 V to 7 V
D package ............................................ ',' . . . . . . . . . . . .. 950 mW
J package .. -. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1150 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooC to 70C
Storage temperature _range ......................................... - 65C to 1 50C
2. For operation above 25C free-air temperature; refer to the Dissipation Derating Curves in Appendix A. In the J package,
SN75125 and SN75127 chips are glass mounted. For these devices in the N package, use the 9.2-mW/oC curve.
4-164 TEXAS ~
INSTRUMENTS
SN75125, SN75127

MIN NOM MAX UNIT
High-level input voltage, VIH 1.7 V
High-level output current, IOH -0_4 V
noted) .
VOH High-level output voltage Vee = 4.5 V, VIL = 0.7 V, IOH = -0.4 mA 2.4 3.1 V
VOL
IIH
IlL
Vee = 4.5 V,
Vee = 5.5 V,
Vee = 5.5 V,
VIH = 1.7 V,
VI = 3.11 V
VI = 0.15 V
10L = 16mA 0.4
0.3
0.5
0.42
30
V
mA
p.A II
lOS
q
Short-circuit output current:!:
Input resistance
Vee = 5.5 V, Vo = 0
Vee = 4.5 V, 0 V. or open.
.:lVI = 0.15 V to 4.15 V
-18
7
-60
20
mA
kO
0Qi
-
(I)
(1)
::-
Vee = 5.5 V, 10H = -0.4 mA, (.)
15 25 mA (1)
--
All inputs at 0.7 V
lee Supply current
Vee = 5.5 V, 10L = 16 mA,
a:
28 47 mA ( I)
All inputs at 4 V
(1)
t All typical values are at Vee = 5 V, TA = 25C. ::-

0':::
:!: Not more than one output should be shorted at a time.
C
(1)
switching characteristics, Vee = 5 V, T A c:
::i
tpLH Propagation delay time, low-to-high-Ievel output 7 14 25 ns
tpHL Propagation delay time, high-to-Iow-Ievel output 10 18 30 ns
tpLH RL = 4000, eL = 50 pF,
Ratio of propagation delay times 0.5 0.8 1.3
tpHL See Figure 1
tTLH Transition time, low-to-high-Ievel output 1 7 12 ns
tTHL Transition time, high-to-Iow-Ievel output 1 3 12 ns
TEXAS . . 4-165
INSTRUMENTS
SN75125, SN75127
VCC
TEST CIRCUIT
I ~ 100 ns ~II
4 I '+--10 ns 10 ns --+I '+--
I III
lI
lf
INPUT ""'-SO-%------S-O%--ii[J"I - - - - - - - 3 V
I 0.7V 1.7V I
r- 10% I I 10%
5' ----------~~ I I OV
CD
I I
...C ~;P:L!\i
<' j+tPLHii- 2 - V - - - - - VOH
...
-
CD
(I) I :.5V 1.2V I
OUTPUT
:lJ I ._0.8V 0.8V 1-----vOL
CD
n
CD
--..l :.- tTHL -1 \.- tTLH
<' VOLTAGE WAVEFORMS

...
CD
(I) NOTES: A. The pulse generator has the following characteristics: Zout '" 50 n. PRR :5 5 MHz.
FIGURE 1
4-166 TEXAS
INSTRUMENTS
POST OFFice BOX 655012 ' DALLAS, TeXAS 75265
SN75125, SN75127
VOLTAGE TRANSFER CHARACTERISTICS VOLTAGE TRANSFER CHARACTERISTICS

5 5
1/f- TA lei 70C VCC - 5.5 V
~ VCC - 5 V
4 4
VCC - 4.5 V
> >
I I
CI) CI)
Cl Cl
~
3 ~ 3
"0 TA ... 25C- - "0
> >...
I
5 2 ::l
c. 2
So TA - ooC- -t 5
III
::l
0 0
I I
0 0
> I I >
I- VCC ... 5 V
No Load
No Load
TA ... 25C
... CI)
Q)
0 I I I o I I I >
'CD
o 2 o 2 (.)
VI-Input Voltage-V
FIGURE 2
VI-Input Voltage-V
FIGURE 3
-...
a:
Q)
CI)
Q)
>
LOW-LEVEL OUTPUT VOLTAGE '':
INPUT CURRENT C
vs vs
Q)
INPUT VOLTAGE OUTPUT CURRENT t:
0.4 0.6
I :::i
J '= ~
cc V /
V >
I
VCC - 5 V
f-- No Load / 0.5 _VI'" 5 V
CI)
Cl
TA ... 25C
TA ... 25C / ~
~
0.3 "0
E V > 0.4
I
/
~
E 5
/ So
~
:;
(.) 0.2
/ ::l
0 0.3 ~
Q; V
5c.
..5
/ >
CI)
...I
~
0.2
/
I
0.1 / 0
...I
V
I
/ >
...I 0.1
0
/
o o
o 2 3 4 5 o 5 10 15 20
VI-Input Voltage-V IO-Output Current-rnA
FIGURE 4 FIGURE 5
TEXAS 4-167
INSTRUMENTS
SN75125, SN75127
SUPPLY CURRENT
vs
SUPPLY VOLTAGE

E
lc: 20
f!
:;
0 15
>
C.
a.
::::I
en 10
I
r- 0
5' !:}
CD 5
C
'"l
<' 0
-
CD 2 3 4 5 6
'"l 0
en
::a vee-Supply Voltage-V
CD
n FIGURE 6
CD
<'CD
'"l
en
4-168 TEXAS
INSTRUMENTS
SN75128"SN75129
EIGHT,CHANNEL LINE RECEIVERS
D2305. JANUARY 1977-REVISED SEPTEMBER 19B6
Meets IBM 360/370 I/O Specification OW. J. OR N PACKAGE

(TOP VIEW)
Input Resistance . . . 7 kO to 20 kO
Output Compatible with TTL
1S/18* Vee
lA 'lY
Schottky-Clamped Transistors 2A 2Y
3A 3Y
Operates from a Single 5-Volt Supply
4A 4Y
High Speed . . . Low Propagation Delay 5A 5Y
6A 6Y
Ratio Specification . . . tPLH/tTHL 7Y
7A
Common Strobe for Each Group of Four BA BY
Receivers GND 2S/28*
SN75128 Active-High Strobes
*S and S for SN75128 and SN75129. respectively
II
SN75129 Active-Low Strobes
description
The SN75128 and SN75129 are eight-channel line receivers designed to satisfy the requirements of the ...
rn
Q)
input-output interface specification for IBM 360/370. Both devices feature common strobes for each group
:>
of four devices. The SN75128 has active-high strobes; the SN75129 has active-low strobes. Speciall,ow-
power design and Schottky-diode-clamped transistors allow low supply-current requirements while
'c(,)u
-...
Q)
maintaining fast switching speeds and high-current TTL outputs. a:
The SN75128 and SN75129 are characterized for operation from OOC to 70C, rn
Q)
:>
logic symbols t .~
C
SN75128 SN75129
Q)
c:
1S ::::i
2S 28
1A 1Y 1A 1Y
2A 2Y 2A 2Y
3A 3Y 3A
4A 4Y 4A
5A 5Y 5A
6A 6Y 6A
7A 7Y 7A
SA 8Y SA
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Pu'blication 617-12,

~~~~~:~~i~a{::1~1i ~~;~:~ti:r :I~o::~:~:t::s~s not
TEXAS ~ 4-169
INSTRUMENTS
SN75128, SN75129
EIGHTCHANNEL LINE RECEIVERS

SN75128 SN75129
III
r
:5"
CD
c
~
<"
-
CD
~
C/)
jJ
g schematic (each,driver)
CD r-----.-----------~~----~~~~r-VCC
<"
CD
~
C/)
INPUT~~ ______~~____________________+--;
A r__________-! y
12 k{J
NOM
TO THREE \ ...----..v..---....tl
OTHER TO SEVEN
CHANNELS OTHER CHANNELS
4-170 TEXAS
INSTRUMENTS
SN75128, SN75129
A input voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.15 V to 7 V
Strobe input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
DW package ........................................................ 1125 mW
J package ................. '.' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1150 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OoC to 70C
Stbrage temperature range ......................................... - 65C to 1 50 ~C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package. . . . . .. 260C
SN75128 amd SN75129 chips are glass mounted. For these devices in the N package, use the 9.2-mW/oC curve.

II
... CI)
MIN !'10M MAX UNIT Q)
Supply voltage, VCC 4.5 5 5.5 V :>
'4)
A 1.7 CJ
High-level output current, 10H

S
A
S
2
0.7
0.7
-0.4
V
mA
-...
a:
Q)
CI)
Q)'
:>
Low-level output current, 10L 16 mA 'i:
Operating free-air temperature, T A 0 70 C C
Q)
s::
:.:i
noted)
VOH High-level output voltage VCC = 4.5 V, VIL = 0.7 V, 10H = -0.4 mA 2.4 3.1 V
VOL Low-level output voltage Vee - 4.5 V, VIH-l.7V, 10L = 16 mA 0.4 0.5 V
VIK Input clamp voltage S Vee = 4.5 V, II= -18 mA -1.5 V
A Vee = 5.5 V, VI = 3.11 V 0.3 0.42 mA
S Vee = 5.5 V, VI = 2.7 V 20 p.A
A Vee - 5.5 V, VI = 0.15 V 30 p.A
S Vee = 5.5 V, VI = 0.4 V -0.4 mA
lOS Short-circuit output current+ Vee = 5.5 V, Vo = 0 -18 -60 mA
ri Input resistance Vee = 4.5 V, 0 V, or open; AVI = 0.15 V to 4.15 V 7 20 k!1
SN75128 Vee = 5.5 V, Strobe at 2.4 V, All A inputs at 0.7 V 19 31
SN75129 Vee = 5.5 V, Strobe at 0.4 V, All A inputs at 0.7 V 19 31
ICC Supply current mA
SN75128 Vee = 5.5 V, Strobe at 2.4 V, All A inputs at 4 V 32 53
SN75129 Vee = 5.5 V, Strobe at 0.4 V, All A irputs at 4 V 32 53
t All typical values are at Vee = 5 V, T A = 25C.

+ Not more than one output should be shorted at a time.
TEXAS 4-171
INSTRUMENTS
SN75128, SN75129
switching characteristics, vee == 5 V, TA == 25C

SN7S128 SN7S129
PARAMETER FROM TEST CONDITIONS UNIT
tpLH Propagation delay time, low-to-high-Ievel output 7 14 25 7 14 25 ns
A
tpHL Propagation delay time, high-to-Iow-Ievel output 10 18 30 10 18 30 ns
tpLH Propagation delay time, low-to-high-Ievel output 26 40 20 35 ns
S RL = 400 n,
tpHL Propagation delay time, high-to-Iow-Ievel output 22 35 16 30 ns
CL = 50 pF,
tpLH
Ratio of propagation delay times A See Figure 1 0.5 0.8 1.3 0.5 0.8 1.3
tpHL
tTLH Transition time, low-to-high-Ievel output 1 ,7 12 1 7 12 ns
tTHL Transition time, high-to-Iow-Ievel output 1 3 12 1 3 12 ns
III
r-
INPUT
(See Notes V re f1
I
I
t+-
:r
m
OUTPUT VCC A, D, and EI
I
100 ns
I
C
I I 10%
...
<0
I 1+-10 ns 10 ns-+!
I I
OV
~tpHL ~tPLH
~ FROMOUTPUT~.-__~-t.r~-i~-i~__IM--' I
-
--2~V"'" I 2 V VOH
CIl UNDER TEST I
I I I
:lJ I I I
m OUTPUT I I
(') I
m I
I
<0 I 0.8 V 0.8 V I
m
... --\- - - VOL
CIl ~tTHL tTLH -f4--.tI
LOAD CIRCUIT VOLTAGE WAVEFORMS
NOTES: A. Input pulses are supplied by a generator having the following characteristics: Zo = 50 n, PRR s 5 MHz.
B. Includes probe and jig capacitance.
D. The strobe inputs of SN75129 are in-phase with the output.
E. V re fl = 0.7 V and V re f2 = 1.7 V for testing data (AI inputs, V re fl = V re f2 = 1.3 V for strobe inputs.
FIGURE 1
4-172
TEXAS -II}
INSTRUMENTS
SN75128, SN75129
VOLTAGE TRANSFER CHARACTERISTICS
VOLTAGE TRANSFER CHARACTERISTICS FROM A INPUTS
5 5
I I I Vee - 5.5 V
TA - 70 oe -
Vee - 5 V
4 4
> Vee - 4.5 V
> I
I CD
CD 01
01
!9 3 !9 3
"0 "0
> TA - 25C f-- >...
:; ::s
So 2 I I So
::s 2
::s 0
III
0
I I
0 0
TA ~ ooe- f- >
>
I I No Load en
r-Vee - 5 V - ~
Q)
N~ Lo~d TA - 25C
o I
o I I I >
'CD
o 2 o 2 CJ
Q)
VI-Input Voltage-V
FIGURE 2
VI-Input Voltage-V
FIGURE 3 -
a::
en
~
Q)
INPUT CURRENT LOWLEVEL OUTPUT VOLTAGE >

'':
vs vs C
INPUT VOLTAGE OUTPUT CURRENT Q)
0.4 0.6 t:
I I I /
Vee -
1
5 V
::i
Vee - 5 V / >
r-- No Load I - VI - 5 V
V I 0.5
CD TA - 25C
~ _ TA - 25C / 01
~
E 0.3 !9
V "0
.!.c / > 0.4
...
!!?
:; V ::s
So ~
(.)
...::s 0.2 / ::s
0 0.3 ~
V
Qj
V
/
Co
c
/ >
.....CD
1 ~
0.2
17
0.1 / .....0
I
.....
/ >
0 0.1
/ o
o
o 2 3 4 5 o 5 10 15 20
VI-Input Voltage-V IO-Output Current-rnA
FIGURE 4 FIGURE 5
TEXAS 4173
INSTRUMENTS
r-
:r
(I)
c...
<'
.
-
(I)
en
:(I)a
o(I)
<'
.
(I)
en
4-174
SN75136
OUADRUPLE BUS TRANSCEIVER
WITH 3STATE OUTPUTS
D2291, JANUARY 1977-REVISED SEPTEM8ER 1986
P-N-P Inputs for Minimal Input Loading D. J, OR N PACKAGE

(200 p.A Maximum) . (TOP VIEW)
High-Speed Schottky Circuitry RE Vee

1R DE
3-State Outputs for Driver and Receiver 18 4R
10 48
Party-Line (Data-Bus) Operation
2R 40
Single 5V Supply 28 3R
20 38
Driver has 40-mA Current Sink Capability
GNO-......_---'-'r- 3D
Designed to be Functionally Interchangeable
with Signetics N8T26, also Called 8T26
logic symbol t
description
II
DE
The SN75136 is a quadruple transceiver utilizing RE
Schottky-diode-clamped transistors. Both the
driver and receiver have three-state outputs.
With p-n-p inputs, the input loading is
10
1R ...
tn
Q,)
reduced to a maximum input current of
200 microamperes.
20
2R 'm>
(,)
The SN7 5136 is characterized for operation from 3D Q,)
oDe to 70 o e.
FUNCTION TABLE (DRIVER)
3R
40
4R
-...
ex:
tn
Q,)
>
.~
INPUT OUTPUT
0 DE B
t This symbol is in accordance with ANSI/IEEE Std 911984 and C
lEe Publication 61712. Q,)
L H H c
H H L logic diagram (positive logic) :.:i
X L Z
FUNCTION TABLE (RECEIVER)
INPUT OUTPUT
(2)
B RE R 1R
(3)
L L H 1B
H L L (5)
X H Z 2R
(6)
2B
H = high level
L = low level
X = irrelevant 3D 3R
10)
Z = high impedance 3B
(12)
40 4R
131
48

~;Od;!!~~onl::~ut!:~:~ifi~::~~~~ger~~~::~~~ TEXAS -I.!} 4-175
Production processing does not necessariry
include testing of all parameters.
INSTRUMENTS
SN75136
OUADRUPLE BUS TRANSCEIVER

VCC------~~-------- ----------~--- VCC
5 kn NOM
INPUT
OUTPUT
II
r-
Drivers:
Receivers:
:i' absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
CD
...c Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
<' Continuous total dissipation at (or below) 25C free-air temperature (see Note 2):
...
CD
t/) D package ......................................................... 950 mW
J package .............................. '. . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
~ N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11 50 mW
CD
o Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooC to 70C
CD
<' Storage temperature range ......................................... - 65C to 150C
...
CD
t/)

2. For operation above 25C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the N package, use
the 9.2-mW/oC curve for these devices. In the J package, SN75136 chips are glass mounted, and use the B.25 mW/oC curve.

MIN NOM MAX UNIT
High-level input voltage, VIH B, D, DE, RE 2 V
Low-level input voltage, VIL B, D, DE, RE 0.B5 V
Driver, B -10
High-level output current, IOH mA
Receiver, R -2
Driver, B 40
Receiver, R 16
4-176 TEXAS ~
INSTRUMENlS
SN75136
electrical characteristics over recommended operating free-air temperature and supply voltage range
VIK Input clamp voltage B,D,DE,RE 11= -5 mA -1 V
B VIH = 2 V, VIL = 0.85 V, IOH = -10 mA 2.6 3.1
R VIL = 0.85 V, IOH = -2 mA 2.6 3.1
B VIH = 2 V, 10L = 40 mA 0.5
R VIH = 2 V, VIL = 0.85 V, 10L = 16 mA 0.5
Off-state (high-impedance B,R DE at 0.85 V, RE at 2 V, Va = 2.6 V 100
10Z I'A
state) output current R RE at 2 V, Va = 0.5 V -100
IIH High-level input current D,DE,RE VI = 5.25 V 25 I'A
IlL Low-level input current B,D,DE,RE VI = 0.4 V -200 I'A
B -50 -150
lOS Short-circuit output current t VCC = 5.25 V mA
II
R -30 -75
ICC Supply current VCC = 5.25 V, No load 87 mA

~.
PARAMETER FROM TO TEST CONDITIONS MIN TYP MAX UNIT Q)
:>
B R CL = 30 pF, See Figure 1 ns 'iii
tpHL Propagation delay time, high-to-Iow-Ievel output 7 14 CJ
tPLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay time, high-to-Iow-Ievel output
tpLZ Output disable time from low level
tpZL Output enable time to low level
D
RE
B
R
CL = 300 pF,See Figure 2

11
16
16
15
20
24
24
30
ns
ns
-...
a:
Q)
rn
Q)
:>
tpLZ Output disable time from low level 9 24 'i:
tpZL Output enable time to low level
DE B CL = 300 pF,See Figure 4
31 38
ns C
Q)
t All typical values are at T A = 25C and V CC = 5 V. :
tOnly one output should be shorted to ground at a time, and duration of the short circuit should not exceed one second. :.J
TEXAS 4-177
INSTRUMENTS
SN75136
WITH 3STATE OUTPUTS
PARAMETER IVIEASUREMENT INFORMATION

VCC 2.6V
TEST
POINT 92n
CIRCUIT (see Note D)

B R
UNDER
DE TEST
(see Note B) o (all) Cl = 30 pF
FiE 1.3kn
(see Note C)
OPEN
GND
TEST CIRCUIT
--., t--";5 ns ~ ~_';;:'n~ _ _ 2.6 V

90%~
I
I N P U T J 90%
I 1.5 V 1.5 V I
r- 10% ! : 10% 0V
:i' I4----*tPHl tplH~

CD
...c OUTPUT
i
~~1._5_V
vl._5JV~
-
________________
VOH
<' - VOL
...
-
CD VOLTAGE WAVEFORMS
en FIGURE 1. PROPAGATION DELAY TIMES FROM BUS TO RECEIVER OUTPUT
:xl
CD
(") 2.6V
2.6V VCC
CD
<'CD
...
en
TEST
POINT
30 n
CIRCUIT
DE B
UNDER
TEST
(See Note B) R (all)
OPEN
TEST CIRCUIT
~ ...-";5ns ~ ~";5ns
~
: 90% 90%~!---.-2.6V
INPUT I 1.5 V 1.5 V 1S..
10% I I ,,10% 0V
:..-.rtPHl tPlH~
---- I : V-- VOH
OUTPUT "'L1._5_V________________
1._5JV;r
- -VOL
VOLTAGE WAVEFORMS
FIGURE 2. PROPAGATION DELAY TIMES FROM DRIVER INPUT TO BUS

NOTES: A. The pulse generator in Figures 1 and 2 has the following characteristics: PRR ~ 10 MHz, duty cycle = 50%,.Zout == 50 n.
C. Cl includes probe and jig capacitance.
4-178 TEXAS ~
INSTRUMENlS
SN75136
WITH 3STATE OUTPUTS

2.6V Vcc
5V
TEST
POINT
CIRCUIT 240 n
RE UNDER R
TEST
(see Note B)
GND 5kn (see Note D)

CL = 30 pF
(Probe)
(see Note C)
TEST CIRCUIT
INPUT
~"5ns
I
I.
irl~----...:
I
2.6V
II
...t/)
Q)
14- tPL....Z_ _ _-..
>
O~7~UT ~ :
"(j)
(J
____-"',O% Q)
VOLTAGE WAVEFORMS
FIGURE 3. RECEIVER ENABLE AND DISABLE TIMES

-...
a:
t /)
Q)
"~
>
C
Q)
t:
:.::i
Isee Note D)
TEST CIRCUIT
~"5ns
~------:Ii:I- 1- ...... - - - - 2.6 V
I
INPUT I
I
I 10%
I I~----
----I-
......... ~.! tpZL ~V-I
tpLZ
OUTPUT 1.5 V I '

\"'._ _ _ _1....;.0.....;%~
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator in Figures 3 and 4 has the following characteristics: PRR =5 5 MHz, duty cycle = 50%, Zout :::: 50 fl.
TEXAS . . 4-179
INSTRUMENTS
POST OFi'ICE BOX 655012 DALLAS, TEXAS 75265
r-
S'
CD
...C;:-
...en
CD
iCD
(")
CD
<'
...enCD
4-180
SN55138. SN75138
01663. SEPTEMBER 1973-REVISED SEPTEMBER 19B6
Single 5-V Supply - SN55138 ... J PACKAGE

SN75138 ... D. J. OR N PACKAGE
High-Input-Impedance, High-Threshold (TOP VIEW)
Receivers
GND VCC
Common Driver Strobe 18 48
TTL-Compatible Driver and Strobe Inputs 1R 4R
with Clamp Diodes 10 40
2D S
High-Speed Operation 2R 3D
100-mA Open-Collector Driver Outputs 28 3R
GNO 38
Four Independent Channels
TTL-Compatible Receiver Output
(TOP VIEW)
description
The SN55138 and SN75138 quad bus
transceivers are designed for two-way data
communication over single-ended transmission 4
o U
mZUUm
.... t?Z>'<t
3 2 1 20 19
18 4R
II rJ)
a..
Q)
lines. Each of the four identical channels consists 5 17 40 >
of a driver with TTL inputs and a receiver with 6 16 NC "a;
CJ
-
a TTL output. The driver output is of the open- 7 15 S Q)
collector type, and is designed to handle loads 8 14 3D a:
r J)
of up to 100 milliamperes (50 ohms to 5 volts). 9 10 11 1213 a..
Q)
The receiver input is internally connected to the mouma:
driver output. and has a high impedance to NZZMM >
"i:
t?
minimize loading of the transmission line. C
8ecause of the high driver-output current and the NC-No internal connection Q)
s::::::
high receiver-input impedance, a very large
number (typically hundreds) of transceivers may FUNCTION TABLE FUNCTION TABLE :.::i
be connected to a single data bus. (TRANSMITTING) (RECEIVING)
The receiver design also features a threshold of INPUTS OUTPUTS INPUTS OUTPUT
2.3 volts (typical), providing a wider noise S 0 B R S B 0 R
margin than would be possible with a receiver L H L H H H X L
having the usual TTL threshold. A strobe turns L L H L H L X H
off all drivers (high impedance) but does not H = high level,. L = low level, X = irrelevant
affect receiver operation. These circuits are
designed for operation from a single five-volt logic symbol t
supply and include a provision to minimize
loading of the data bus when the power-supply
voltage is zero.
125C; the SN75138 is characterized for
operation from ooe to 70C.
t This symbol is in accordance with ANSI/IEEE Std 91- 1984 and

specifications per the terms of Texas Instruments TEXAS . .-
4-181
=~~~~:~~i~ai~~1~1~ ~!=~~~ti:; :I~o::~:~:t:~~s not INSTRUMENTS
SN55138, SN75138

(12)
S ...;....----<rl
(2) 1B
1D~(~4~)---------4---L__J
(3)
1R------------r-----~
(5) 171 2B
20 -----------+-~L~
2R (6)
(9) 3B
(11)
3D ------------t---L..~
(10)
3R-----------~----_<
(15) 4B
(13)
4D---------------L..~
(14)
4R--------------------C
Pin numbers showns are for 0, J, and N packages.
EQUIVALENT OF EACH EQUIVALENT OF TYPICAL OF ALL TYPICAL OF ALL

STROBE AND DRIVER INPUT EACH RECEIVER INPUT DRIVER OUTPUTS RECEIVER OUTPUTS
VCC
INPUT
---+----
vccz.::
,NPUT 1~M --q-0UTPUT
----r-VCC
13051 NOM
OUTPUT
4-182
. TEXAS"
INSTRUMENTS
SN55138. SN75138
Input voltage 5.5 5.5 V
Driver off-state output voltage 7 7 V
Low-level output current into the driver output 150 150 rnA
D package 950
Continuous total dissipation at (or below) FK or J package 1375
mW
25C free-air temperature (see Note 2) J package 1025
N package 1150
Operating free-air temperature range -55 to 125 o tr.o 70 c
Storage temperature range -65 to 150 -65 to 150 c
II...
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: Dar N package 260 c
Case temperature for 60 seconds: FK package 260 c
NOTES: 1. All voltage values arc with respect to both ground terminals connected together.
2. For operation above 25C free-air temperature, refer to the Dissipation Derating Curves in Appendix A. In the J package, tJ)
SN55138 chips are alloy mounted and SN75138 chips are glass mounted. In the N package, use the 9.2-mW/oC curve for Q)
these devices. >
"cu
(.)
-...
recommended operating conditions Q)
SN55138 SN75138
a:
UNIT t J)
Q)
".:
>
Driver or strobe 2 2
Receiver 3.2 2.9
V C
Q)
Driver or strobe 0.8 0.8
Low-level input voltage, VIL V c
Receiver 1.5 1.8 :.J
High-level output current, IOH Receiver output -400 -400 p.A
Driver output 100 100
Low-level output current, IOL rnA
Receiver output 16 16
TEXAS ~ 4-183
INSTRUMENTS
POST OFFICE BOX 655012 DALLAS. TEXAS 7526S
SN55138, SN75138
noted)
SN55138 SN75138
MIN TVpt MAX MIN TVpt MAX
Input clamp
VIK Driver or strobe Vee = MIN, II = -12 mA -1.5 -1.5 V
voltage
High-level Vee = MIN, VIH(S) = 2 V,
VOH Receiver 204 3.5 204 3.5 V
output voltage VIL(R) = VIL max, IOH = - 400 p.A
Vee MIN, VIH(D) = 2 V,
Driver 0045 0045
Low-level VIL(S) = 0.8 V, IOL = 100 mA
VOl V
output voltage Vee = MIN, VIH(R) = VIH min,
Receiver 004 0.4
VIH(S) = 2 V, 10L = 16 mA
Input current at
II
II maximum input Driver or strobe Vee = MAX, VI = Vee 1 1 mA
voltage
Driver or strobe Vee = MAX, VI = 204 V 40 40
High-level
IIH Vee = 5 V, VI(R) = 4.5 V, p.A
input current Receiver 25 300 25 300
VI(S) = 2 V
Driver or strobe Vee = MAX, VI = 0.4 V .:...1 -1.6 -1 -1.6 mA
Low-level
IlL Vee = MAX, VI(R) = 0045 V,
input current Receiver -50 -50 p.A
VI(S) = 2 V
Input current
Receiver Vee = 0, VI = 4.5 V 1.1 1.5 1.1 1.5 mA
with power off
Short-circuit
lOS Receiver Vee = MAX, -20 -55 -18 -55 mA
output current
All driver Vee = MAX, VI(D) = 2 V,
50 65 50 65
outputs low VI(S) = 0.8 V
lee Supply current Vee = MAX, VI(R) = 3.5 V, mA
All driver
VI(S) = 2 V, 42 55 42 55
outputs high'
Receiver outputs open
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. Parenthetical letters
D, R, and S used with VI refer to the driver input, receiver input, and strobe input, respectively.
tAli typical values are at Vee = 5 V, T A = 25e.
Not more than one output should be shorted at a time.

FROM TO
PARAMETERt TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tpLH 15 24
Driver Driver ns
tpHL eL = 50 pF, RL = 50 n, 14 24
tpLH See Figure 1 18 28
Strobe Driver ns
tpHL 22 32
tpLH eL = 15 pF, RL = 400 n, 7 15
Receiver Receiver ns
tpHL See Figure 2 8 15
ttPLH '" propagation delay time, low-to-high-Ievel output

tpHL '" propagation delay time, high-to-Iow-Ievel output
4-184 TEXAS
INSTRUMENTS
SN55138, SN75138

TEST
Vcc
POINT VCC
FROM OUTPUT
UNDER TEST ~ POINT
! RL TEST
/f'" CL
-4:- (See Note BI
DRIVER
--
INPUT
(See Note
STROBE
01
~r
../
1.5 V
I "'--_ _ _ _...J
~x"----3V
\
,,,-
1.5 V
~ .
~;pCUE~VER i\~2_.5_V ____ __

,.----4V
...JI"~ 0V
II
INPUT - I - - - 0V
,. '1 tPLH I
114'.-~'It- tPHL
..----..,ttll- tpLH
M l I
l'v, .
...
____..Jf.
t/)
DRIVER
OUTPUT 5V \ : VOH RECEIVER_ _ _ _.J V Q)
OUTPUT
'Q)
>
VOL
U
-...
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS Q)
a:
FIGURE 1. PROPAGATION DELAY TIMES FIGURE 2. PROPAGATION DELAY TIMES t /)
FROM DATA AND STROBE INPUTS FROM RECEIVER INPUT Q)
NOTES: A. Input pulses are supplied by generators having the following characteristics: tw = 100 ns, PRR :s 1 MHz, tr :S 10 ns, tf S 10 ns, 'i:
>
Zout ",,50 n. C
B. CL includes probe and jig capacitance. Q)
C. All diodes are 1N916 or 1N3064. c
D. When testing driver input (solid line) strobe must be low; when testing strobe input (dashed line) driver input must be high. :.:::J
TEXAS 4-185
INSTRUMENTS
SN55138, SN75138
STROBE TO-DRIVER OUTPUT
DRIVER TRANSFER CHARACTERISTICS DRIVER TRANSFER CHARACTERISTICS TRANSFER CHARACTERISTICS
-
Vee - 5 V Vee - 5.5 V VIIS) -O.B V
l'
VIIS)- O.B V
l'
Vee - 5 V TA -25"C
5 ~v"';e;;;e""--4."'5-v-Jt-+ Load' 50 II to VCC
I
ll
5 Loa 50 n to Vee
~
Z.
4
t
~ 4~~---+-j~-+-+--r--1~~
TA J12S"~
TA-25"e
~ TA - 25 e & 31---+----+~~-+-+-~---I-----1 i I
<3 3 <3
I
T~.-Je
TA -125"e
9o 2
Tl- _5 S"e
~ 21---+----+-~-+-+-~-I-----1
o
'0
> 1 ~ 1 1---+----+-If---+-+-~-I-----1 vel.5 V
VIID) -2 V
Load - 50 n to Vee
o o
o o
II
r-
Vt(D)-Driver Input Voltage-V
FIGURE 3
VIID)-D,i.e, Input Voltage-V
FIGURE 4
VIIS)-Strob. Input Voltage-V
FIGURE 5
5' STROBE-TO-DRIVER OUTPUT

CD
..<'
TRANSFER CHARACTERISTICS RECEIVER TRANSFER CHARACTERISTICS RECEIVER TRANSFER CHARACTERISTICS
C Vce - 5_5 V Vce - 5 V 5V
.. Vce - S V Load: >

l' =j 5~~-t-+--t- 400n I 51--+--+-+--r-
CD
t Vce - 4.5 V 8.
!l E
(f)
iCD
~ 4 t---t----1--tt--+-+---t---t---t
!
~ 4l--~-+-+--t-
i
'0
4 r----..---.____
(')
<3 31--t--j,---tt--t-+--t--t--1 ~ 3s=1~ o
CD 'il
<' 9 1--t--j--tt--t~~~)2~~eV ! ~ 21--+----+-1--+~+--r-r-~
..
CD
(f)
~ Load - 50 n to Vce
> 11---+----+-H--+-+-,-+---,-'I-----1
Vce - 5.5 V ,l
I
a:
~ ll---t-~-~-+-~~-I---t
a:
~ ll---t----+-4--+~~-+-I---t
0t::t~~~~Ve~C~-~4~.5~V_t-~J
o
Vl(s)-Strobe Input Voltage-V VI(R)-Receiver Input Voltage-V VI (R)-Receiver Input Voltage-V ,
FIGURE 6 FIGURE 7 FIGURE 8
HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE LOWLEVEL OUTPUT VOLTAGE

.,
OUTPUT CURRENT (RECEIVER' OUTPUT CURRENT (RECEIVER) OUTPUT CURRENT (RECEIVER)
1.2
Vce - 5 V
VIIR) - O.B V
VI(R) - 0.8 V
TA - 25C >I TA ~55C Tl-25"J'
5 1.0
~TA-125"C """"- '0
~TA-25"C > 0.8
~
"
........
'\
'\.'\... Vec = 5.5 V
~
o I~ V
~\1-"
TA-55"~
\..
'\."-." '\.
~ '\." '<'" Vee' 5 V
:: 0.6
:J
! 0.4
;;:; V
~ V
~
I
'\,'\ a:
!~
::; 0.2
,,,",1'\
""'
Vce - 4.5 V'\
\~
~ ~ VCC - 4.5 V
'0
o 5 10 15 20 25 30 35 40
o
o 10 15 20
""'1--. \l
25 30 35 40
o
o 10 20 30 40
VIIR) - 3.5 V
50 60
'OH(R)-HighL el Output eurrent-mA IOH(R)-Highlevel Output Current-rnA IOLIR)-Low-Level Output Currnet-r'nA
tOata for temperatures below OOC and above 70C is applicable to SN55138 circuits only.
4-186 TEXAS
INSTRUMENTS
SN55138, SN75138
LOWLEVEL OUTPUT VOLTAGE RECEIVER INPUT CURRENT RECEIVER INPUT CURRENT

vs
OUTPUT CURRENT IDRIVER OUTPUT) RECEIVER INPUT VOLTAGE RECEIVER INPUT VOLTAGE
1.6 1.6
1.2 VCC' 5 V
I I,
~ ~r;-
Vcc - 4.5 V VIIS)- 2 V
1.4 VIIS)-2 V
:rE 1.0 VIID)" 2 V
"t-
I!J TA-125.25 C

1.4 TA"25'C
VIIS)- 0.8 VI
;: ~ ~ 1.2
\ rv. E
~ 1.2 /
~
'0
> TA -55'C TA' -5S'C V
~ O.S
/ a
~
1.0 j 1.0
~ 0.6 A f 0.8 0.8 / >1-

3 A~/ > I~
~ 0.4
j 0.6 In
oi
(J
III
In
u

r---
51
~
I
~ ~
r)11)(-
(J
0.4 f--
C
~ 0.2 TA - 25C, _55C
~
0.2
~
o o
TA12s'C "J o
o 50 100 150 200
IOL(D}-Low-Level Output Current-mA
FIGURE 12
250 300 o
VI(R)-Receiver Input Voltage-V
FIGURE 13
o
VIIR)-Recoiver Input Voltage-V
FIGURE 14
II
...
rn
SUPPLY CURRENT
Q)
vs SUPPLY CURRENT PROPAGATION DELAY TIMES :::-
SUPPLY VOLTAGE
IALL DRIVER OUTPUTS LOW)
'iii
SUPPLY VOLTAGE FREEAIR TEMPERATURE (J
-...
80 Q)
VIIS)" 0.8 V 32 vee - 5 V
a:
::,:':O'd eL"5PF'RL~
Driver load: CL 50pF, Rl '" 50 n,See Figure 1
70 VIID)-2V
Driver loads = 1 In i v
to
~
70
rn
60
1:
r ITA _ ~5'C ~ ~
Q)
:::-
~ 50 f---+--+-t---' ~ 'I:
~
0e /":;'A -125'C
U
20
C
i 30f---+--4--~~--+-~--~
';. 40 40 f--;--'--r---r-~"7"". 16 _ -r-" tPLH{OOI-
Q.
$ Q)
i
12 - tPHUOOI
30
/J '/ T l- -55'C c:
~ 20 ~ 20 t---+---I--I+--+--+--+--'-+---1 8 - ~VL~ :::;
10
//V I
o ~~ I 0'---1--'---1..-'----'---"-
. L--JL--IL--IL.....J
o -60 -40 -20 0 20 40 60 80 100 120140
VCC-SupplyVoltage-V VCC-SupplyVoltage-V T A-free-Air Temperature-c
PROPAGATION DELAY TIMES DRIVER PROPAGATION DELAY TIMES RECEIVER PROPAGATION DELAY TIMES
SUPPLY VOLTAGE LOAD CAPACITANCE LOAD CAPACITANCE

30r---------------------, 16
Dn\ler load: Cl" 50 pF. RL = 50 n, See Figure 1 Vcc- SV
Receiver load: CL" 15 pF. RL 400 ~2. See Figure 2 14 RL - 400 n. See Figure 2
40 TA 25"e
f
25 f--t-+--+--+,-; TA"25'C
1
~
tPHLISD) 12
tV~\.
15t:t:t:~~=t=t=t~PL=H~IDED~)~
E 20!---'F-+-+-
>=
i;'
~ 15 t--+=.....""E::=-"""~
10
....... ........-: ~
--
~\I\.I\'
~~
r--
10r-~+-;_~~-+-tP~~-LI~1~D-)~ .~ 10 f-~+-+--+-+-+-+--t-~
tPHLIRR) il

o~~~~~~~_t~PI_H~li~R_)L--~ OL-~~J--L~~~~~~ o
4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 o 20 40 60 80 100 120 140 160 180 200 o 10 20 30 40 50 60 70 80
VCC-Supply Voltage-V CL -Load Capacitance-pF C L-load Capacitance-pF

tData for temperatures below Doe and above 70 0 e is applicable to SN55138 circuits only.
TEXAS 4-187
INSTRUMENTS
SN55138, SN75138

5V 5V
P
10051 r --j
50 ft Belden #8795
I
100-51 Telephone Cable I
@I>-"';"'I---+@
L.!/~5513~
--3V
---2V
-iI_--OV
III
r-
--------OV
5'
CD
...
C
TYPICAL VOLTAGE WAVEFORMS
<'CD
...
o
FIGURE 21. POINT-TO-POINT COMMUNICATION OVER 50 FEET OF TWISTED PAIR AT 5 MHz
'i
CD
5V 5V
(')
CD 10051 10051
<'
...o
CD
2V
OV
2V
OV
FIGURE 22. PARTY-LINE COMMUNICATION ON 500 FEET OF TWISTED PAIR AT 1 MHz
4-188 TEXAS
INSTRUMENTS
-1!1
SN55138, SN75138
OUADRUPLE BUS TRANSCEIVERS
1000 ft RG-53
or equivalent
-f_-~-
---L __ [ -t-2V+-
~ L - --
--lo_ _--'_'---_ _ _ _ _ _ _
3V
0V
0- -. 1--
--4V-- -----: 2V
---------oV
II
FIGURE 23. POINT-TO-POINT COMMUNICATION OVER 1000 FEET OF COAX AT 1 MHz
TEXAS. - 4-189
INSTRUMENTS
II
r-
5"
CD
.if
C
CD
-
U;
:Jl
CD
(")
CD
..<"
CD
th
4-190
SN7514D, SN75141
DUAL LINE RECEIVERS
02155. JANUARY 1977-REVISED OCTOBER 1986
Single 5-V Supply D. JG. OR P PACKAGE
100 mV Sensitivity ITOPVIEWI
For Application As:

Single-Ended Line Receiver eOMSTRB
1 0 U T [ ] 8 Vee
2 7 20UT
Gated Oscillator 1 LINE 3 6 eOMREF
level Comparator GND 4 5 2L1NE
Adjustable Reference Voltage

logic symbol t
TTL Outputs
COMSTRB EI2~1_ _ r-----'
TTL-Compatible Strobe
Designed for Party-Line

(Data-Bus) Applications
1 LINE ..:..;13~1_ _-I

Common Reference Pin
Common Strobe
' 141 Has Diode-Protected t This symbol is in accordance with ANSI/IEEE Std 91-1 984 and
II
...
(I)
Input Stage for Power-Off Q)

Condition >
"0)
logic diagram (positive logic) CJ
-...
Q)
description a:
121
COMSTRB ( I)
Each, of these devices consists of a dual _---lOUT
1LINE _13_1_ _...,...... Q)
single-ended line receiver with TTL-compatible
strobes and outputs. The reference voltage
161 >
COMREF ".:::
(switching threshold) is applied externally and C
can be adjusted from 1.5 volts to 3.5 volts, 2L1NE _15_1_ _-&.o~ Q)
making it possible to optimize noise immunity for c
a given system design. Due to their low input
::;
FUNCTION TABLE
current (less than 100 microamperes), they are
lEACH RECEIVERI
ideally suited for party-line (bus-organized)
LINE INPUT STROBE OUTPUT
systems.
oS Vref - 100 mV l H
The ' 140 has a common reference voltage pin ~ Vref + 100 mV X l
and a common strobe. The '141 is the same as X H l
the '140 except that the input stage is diode
protected. H = high level. l =low level. X = irrelevant

for operation from OOC to 70 o C.
~~~:~:~~i~a{:~1~1i ~!:~~~ti:r ~~o::~:~:t~~s~s not INSTRUMENTS
POST OFFiCe BOX 655012 " DALLAS. TeXAS 75265
SN75140, SN75141
DUAL LINE RECEIVERS
r-~~~--------~----~~----.-----'-------'-~--------~-'~--VCC
750 4000 4000 TO OTHER

LINE RECEIVER
LINE 1500
INPUT ILl
COM REF __..A,/\,..,....-+--~
470
t - - - - OUTPUT
TO OTHER
III LINE RECEIVER
LEGEND:
~----~~~-~~---~~--~~--~~---~~~.-~------GND
tttt++H++' 140 device only

:t
' - - __
TO OTHER LINE RECEIVER
, _ _ _ _ COMMON
STROBE
UNIT
Supply voltage, VCC (see Note 1) 7 V
Reference input voltage, Vref 5.5 V
Line input voltage with respect to ground -2 to 5.5 V
Line input voltage with respect to Vref 5 V
Strobe input voltage 5.5 V
Continuous total dissipation at (or belowl

I D package 725
25C free-air temperature Isee Note 21

I JG package 825 mW
I P package 1000
Operating free-air temperature range o to 70 C
Storage temperature range -65 to 150 C
Lead temperature 1,6 mm 11/16 inch) from case for 60 seconds: JG package 300 C
Lead temperature 1,6 mm 11/16 inch) from case for 10 seconds: D or P package 260 C
NOTES: 1. Unless otherwise specified, voltage values are with respect to network terminal.
2. For operation above 25C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the JG package, these
chips are glass mounted. For SN75140 and SN75141 devices in the P package, use the 8.0-mW/oC curve.

MIN NOM MAX UNIT
Reference input voltage, Vref 1.5 3.5 V
High-level line input voltage, VIH(L) V re f+ O.1 VCC-1 V
Low-level line input voltage, VILIL) 0 Vre f- O.1 V
High-level strobe input voltage, VIH(SI 2 5.5 V
Low-level strobe input voltage, VIL(S) 0 0.8 V
4-192 TEXAS . "

INSTRUMENTS
POST,OFFICE BOX 655012 DALLAS. TEXAS 75265
SN75140, SN75141
DUAL LINE RECEIVERS
electrical characteristics over recommended operating free-air temperature range, Vee - 5 V 10%,
Vref = 1.5 V to 3.5 V (unless otherwise noted)
VIK(S) Strobe input clamp voltage II(S) - -12 mA -1.5 V
VIL(L) = Vref - 100 mV, VIL(S) = 0.8 V,
VOH High-level output voltage 2.4 V
10H = -400 /lA
VIH(L) = Vref + 100 mV, VIL(S) = 0.8 V,
0.4
10L = 16mA
VIL(L) = Vref - 100 mV, VIH(S) = 2 V,
0.4
10L = 16 mA
Strobe input current
Strobe 1
II(S) at maximum VI(S) = 5.5 V mA
Com strb 2
input voltage
II
Strobe 40
VI(S) = 2.4 V
Com strb 80
High-level
IIH Line input VI(L) = 3.5 V, Vr!}f = 1.5 V 35 100 /lA
input current
Reference
Com ref
VI(L) = 0 V, Vref = 3.5 V
35
70
100
200
... t/)
CI)
Strobe -1.6 >

VI(S) = 0.4 V mA "Qi
Com strb -3.2 (.)
IlL
Low-level
input current
Line input
Reference
Com ref
VI(U
VI(U
=
=
0 V, Vref
1.5 V, Vref
= 1.5 V
=aV
-10
-10
-20
/lA -
a::
CI)
...
t /)
CI)
>
lOS Short-circuit output current; VCC = 5.5 V -18 -55 mA "i:
ICCH Supply current, output high VI(S) = 0 V, VI(L) = Vref - 100 mV 18 30 mA C
CI)
ICCL Supply current, output low VI(S) = 0 V, VI(L) = Vref + 100 mV 20 35 mA c
~
t All typical values are at VCC = 5 V, T A = 25 DC.
; Only one output should be shorted at a time.
switching characteristics, Vee = 5 V, Vref 2.5 V, TA

Propagation delay time, low-to- 22 35
tpLH(L)
high-level output from line input
ns
Propagation delay time, high-to-
tpHL(L) 22 30
low-level output from line input
CL = 15 pF, RL = 400 {}, See Figure 1
Propagation delay time, low-to-
tpLH(S) 12 22
high-level output from strobe input
ns
Propagation delay time, high-to-
tpHL(S) 8 15
low-level output from strobe input
TEXAS . . 4-193
INSTRUMENTS
SN75140, SN75141
DUAL LINE RECEIVERS
~10ns-+l /4- --./ j4-S10ns
~
2.5 V VCC OUTPUT
LINE 2.5 V
.90%
~-I":""2.5-V - - - - -- ---2.7V
RL - 4000 INPUT 10% 10% 2.3 V

LINE
I I ~ ~ w...-
S 10 ns--tl
1:-
E---
INPUT
I ~ r' S 10 ns
STROBE I
INPUT I
L - ""* - .-J STROBE I I ~ 90% 3.5V

(See NOTE B) INPUT I 1.5 V 10% 10% 1.5 V 0 V
I I
CL - 15 pF
(See Note C) tPHL(LI~ I -+I ~tPHL(SII
I ~tPLH(L) I ~ if-tPLH(S)
III
I'"'"
TEST CIRCUIT
OUTPUT
---'"
1.5 V
VOLTAGE WAVEFORMS
I VOH
:r
CD NOTES: A. Input pulses are supplied by generators having the following characteristics: PRR ~ 1 MHz, duty cycle ~ 50%, Zout = 50 O.
C B. Unused strobes are to be grounded.
... C. CL includes probe and jig capacitance.
:=:' D. All diodes are 1N3064.
-
CD
U; FIGURE 1
:x:J
CD
(')
CD TYPICAL CHARACTERISTICS
<'
CD
U; OUTPUT VOLTAGE
vs
LINE INPUT VOLTAGE
4 I I----r-
Vee" 5 V
Vref .. 2.5 V-
>
I
QI
3 " VIIS) .. 0
TA .. 25e -
Cl
5
,>
..S-
"0
::I
2
::I
0
I
0
>
\
o
o 2 3 4 5
VIIL)-Line Input Voltage-V
FIGURE 2
4-194 TEXAS
INSTRUMENlS
SN75140, SN75141
DUAL LINE RECEIVERS

line receiver
5 V STROBE
DATA
r - - - -, TWISTED PAIR LINE ----,
INPUT I I
I I OUTPUT
STROBE I RT
I
I I
I
I I
~ SN75361A I
Vref
I
~ SN75140/~ SN75141
high fan-out from standard TTL gate

STROBE
ANY N=1
SERIES 54/74 I - -....------I~--f'o.....
LOGIC ~-,-...".---...
...
t/)
Cl)
>
0Ci)
N = 2 ... ----:--+-........
CJ
N =74 ...- - - - ' - - -........

-...
a:
>
0'::
Cl)
t /)
Cl)
C
Cl)
N=75t~------+-~
c
:::J
t Although most Series 54/74 circuits have a guaranteed 2.4-V output at 400 p.A. they are typically capable of maintaining a 2.4-V
output level under a load of 7.5 mAo
dual bus transceiver +5 V
VCC = 5 V RT (50 to 100 {} depending
r ...L - - .,--,_..:........__D_A_T_A_B_U_S_...._ on line impedance)
DATA IN
DATA IN
I I
STROBE --""1._, I
.J
Vce = 5 V
r...J. ----.., +5V
DATA OUT I I
I I
I .~._~__~
DATA OUT
STROBE
I I Vref = 1.5V
I I II to 3.5 v
L __ ~_~.J
~ SN75140/~ SN75141
Using this arrangement. as many as 100 transceivers can be connected to a single data bus. The adjustable reference voltage
feature allows the noise margin to be optimized for a given system. The complete dual bus transceiver (SN75453B driver and
SN75140 receiver) can be assembled in approximately the same space required by a single 16-pin package and only one power
supply is required (+ 5 V). Data In and Data Out terminals are TTL compatible.
TEXAS ~ 4-195
INSTRUMENTS
SN75140. SN75141
DUAL LINE RECEIVERS
schmitt trigger
R1 vee = 5V
STROBE
SIGNAL
r ----,
lO-..;.I-tI~~~PUT
INPUT
_______
RT
I I I
-= L---lr---1
y, SN751401
-= Y, SN75141
III
r- 4
EXAMPLES OF TRANSFER CHARACTERISTICS
4
5'
CD 3.5 3.5
R1 - 6.2 kO R1 - 5.9 kO
...
C
3 RT - 3.9 kO 3 RT - 3.9 kO
<' > RF - 16 kO , > RF - 5 kO
...
- ..
CD I I
(I)
:::J:J
Q)
CD
!9
2.5 TA - 25C Q)
CD
!9
2.5 TA - 25C
.
CD
n
CD
'0
>
:l
So
2
4
..
'0
>
'Pt
2
<' :l 1.5 :l 1.5

...
CD'
(I)
0
I
0
0
0
I
> >
0.5 0.5
o o
o 0.5 1.5 -2 2.5 3 o 0.5 1.5 2 2.5 3
VI-Input Voltage-V VI-Input Voltage-V
Slowly changing input levels from data lines, optical detectors, and other types of transducers may be converted to standard TTL
signals with this Schmitt trigger circuit. R1, RF, and RT may be adjusted for the desired hysteresis and trigger levels.
4-196 TEXAS . "

INSTRUMENTS
SN75140, SN75141
DUAL LINE RECEIVERS
TYPICAL APPLICATION OAT A
gated oscillator
Vcc STROBE
STROBE
______r-
lO-..;-+-__- OUTPUT OUTPUT~
Vref --.ltW\.-
R
T
C
II
(I)
a-
OSCILLATOR FREQUENCY Q)
vs >
RC TIME CONSTANT
'Qi
(,)
-
40 Q)
a:
( I)
a-
Q)
20
---- ---- ..,.

>
N
J:
::?! ---- - ...... r-- fVref - 1.5 V
''::::
C
---
10 Q)
I "- :
>- .....
u
cCD 7
/ r--
~
::J
::J
C'
L Vref - 2.5 V
CD
u: 4 RF .. 15 kG
l
0.6
tw - -
2 f
VCC" 5 V
TA - 25C
1
0.1 0.2 0.4 0.7 1 2 4 7 10
RC Time Constant-its
TEXAS ~ 4-197
INSTRUMENTS
III
r-
S'
CD
...C
<'
...CD
-
t/)
:lJ
CD
(')
CD
<'
...
CD
t/)
4-198
SN75146
DUAL DIFFERENTIAL LINE RECEIVER
Meets EIA Standards RS-422-A and D. JG. OR P PACKAGE

RS-423-A (TOP VIEW)
Meets EIA Standards RS-232 and VCC[]8 11N+

CCITT V.28 with External Components 10UT 2 7 11N-
20UT 3 6 21N +
Meets Federal Standards 1020 and 1030 GND 4 5 21N-
Built-in 5-MHz Low-Pass Filter
. logic symbol t
Operates from Single 5-V Power Supply
Wide Common-Mode Voltage Range
(8)
..at>

High Input Impedance'
TTL-Compatible Outputs
11N+
11N-
(7)
(6)
] \J (2) 10UT
21N+
8-Pin Dual-In-Line Package (3) 20UT
(5)
21N-
Pinout Compatible with the I'A9637 and
I'A9639 t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
description
lEe Publication 617-12,
...
CI)
Q)
logic diagram >
The SN75146 is a dual differential line receiver 'iii
1IN+~8)
Co)
-...
designed to meet EIA standards RS-422-A and Q)
RS-423-A. The receiver is designed to have a . ..a (2) lOUT a:
constant impedance with input voltages of l1N- (7) CI)
3 volts to 25 volts allowing it to meet the Q)

requirements of EIA standard RS-232-C and >
CCITT recommendation V.28 with the addition 2IN+~6) 'i:
.r:r (3) 20UT C
of an external bias resistor. This receiver is 21N- (5) Q)
designed for low-speed operation below c:
355 kilohertz, and has a built-in 5-megahertz ::::i
low-pass filter to attenuate high-frequency
noise. The inputs are compatible with either a
single-ended or a differential line system and the
outputs are TTL compatible. This device
operates from a single 5-volt power supply and
is supplied in both the 8-pin dual-in-line and small
outline packages.
OOC to 70 o C.
~~~~~:~~i~ar~~1~1~ ~!~ti~~ti~r fl~o::~:~:t:~~$ not INSTRUMENTS
SN75146

vcc----------~---.~---
R1 ----------~----VCC
50 fl NOM
740 () NOM
7.4 R1
OUTPUT
7.4 k{) NOM
INPUT ---_'lNIt--.....
740 () NOM
r-
S'
CD
...C
cr Supply voltage, V CC (see Note 1) ...................................... - 0.5 V to 7 V
...
-
CD Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25 V
fA Differential input voltage (see Note 2) ......................................... 25 V
:0 Output voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.5 V to 5.5 V
CD
(") Low-level output current ................................................... 50 mA
CD Continuous total dissipation at (or below) 25C free-air temperature (see Note 3):
<' D package ................................................. " . . . . . .. 725 mW
...fACD JG package .................' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 825 mW
P package ......................... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1000 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OC to 70C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package ........... 300C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D and P package ....... 260C
NOTES: 1. All voltage values, except differential input voltage, are with respect to the network ground terminal.
2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.
3. For operation above 25 De free-air temperature, derate the JG package to 528 mW at 70 De at the rate of 6.6 mW/De, the
D package to 464 mW at 70 DC at the rate of 5.8 mW/DC, and the P package to 640 mW at 70 DC at the rate of 8 mW/DC.
The SN75146 chips are glass mounted in the JG package.

MIN NOM MAX UNIT
Common-mode input voltage, VIC 7 V
Operating free-air temperature, T A 0 25 70 DC
4-200 TEXAS -I.!}

INSTRUMENTS
SN75146
electrical characteristics over recommended ranges of supply voltage, common-mode input voltage,
-0.2+ 0.2
VT Threshold voltage (VT + and VT _ )
See Note 4 -O.4 t 0.4
V
Vhys Hysteresis (VT + - VT-) 70 mV
VIS Input bias voltage II - 0 2 2.4 V
VOH High-level output voltage VID = 0.2 V, 10 = -1 mA 2.5 3.5 V
VOL Low-level output voltage VID = -0.2 V, 10 = 20 mA 0.35 0.5 V
VI = 3 V to 25 V or
fj Input resistance See Note 5, 6 7.8 9.5 k{}
VI = -3 V to -25 V
II Input current
VCC = 0 to 5.5 V, I VI = 10 V 1.1 3.25
mA
'I VI = -10 V

See Note 6 -1.6 -3.25
lOS Short-circuit output current Vo = 0, VID = 0.2 V -40 -75 -100 mA

ICC Supply current VID = -0.5 V, No load 35 50 mA
t All typical values are at VCC = 5 V, TA = 25C. ,

t The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for
threshold levels only.
...en
Q)
Only one output should be shorted at a time, and duration of the short-circuit should not exceed one second. >
NOTES: 4. The expanded threshold parameter is tested with a SOO-{} resistor in series with each input.
'Ii)
CJ
-...
5. fj is defined by AVI/Ali. Q)
6. The input not under test is grounded. a:
en
switching characteristics, Vee = 5 V, T A Q)
PARAMETER TEST CONDITION MIN TYP MAX 'Ii:

>
tpLH Propagation delay time, low-to-high-Ievel output 100 150 300 C
Q)
tpHL Propagation delay time, high-to-Iow-Ievel output 100 150 300
t:
:.:::i
VCC+ OUTPUT
+o.s V r--------,
INPUT
392n INP~T
(see Note B) :
SO% soo/cl.
~I
0
51 n -0.5 V I ....- - - - -
~tpLH ~tPHl
Ir-__________--, V
3.92 kn
OUTPUT f.5V ,.5V'---- OH
_______J. ....-------VOL
TEST CIRCUIT VOLTAGE WAVEFORM

B. The input pulse is supplied by a generator having the following characteristics: tr S 5 ns, tf S 5 ns, PRR S 300 kHz,
duty cycle = 50%.
FIGURE 1. TRANSITION TIMES
TEXAS . . 4-201
INSTRUMENTS
SN75146 ,
OUTPUT yOLTAGE OUTPUT VOLTAGE

vs vs
4 4
vch= 4.~5
V VCC = 5.25 V
TA = 25C
-TA = 25C . I
I
I I
3 3
~ I >I I
VIC= 0
C1> I VIC=O I ~
~
C1>
C'I
I V'C = 7 V ~ I VIC = 7 V
"0 I "0 I
> 2 > I
,
'5 I ... 2
III
I I
:::I
fr
:::I
I fr V'C = 7 V:
o I
:::I
0 I
J
o VIC = 7 V: I I
V,C= 0
> 0 I
r- >
S'
CD
I
I ~IC=~
I
:
I i
...
C : I I
l
I
<'CD o o
... o 50 o
-
-100 -50 100 -100 -50 50 100
tn Vlb-Differential Input Voltage-mV VID-Differential Input Voltage-mV
:xl
n
CD
<'CD
...
tn
+12 V
>----JL
NOTE A: In order to meet the input-impedance and open-circuit-input voltage requirements of RS-232-C and CCITT V.2B and guarante~
open-circuit-input failsafe 'operation. R and V are selected to satisfy the following equations:
R
V = -1.1 - 3.3 - volts
q
FIGURE 4. RS-232-C SYSTEM APPLICATIONS
4-202 TEXAS -II}

INSTRUMENTS
SN75146
+5 V TWISTED PAIR +5 V
II (/)
~
Q)
>
'Q)
FIGURE 5. RS-422-A SYSTEM APPLICATIONS (,)
- Q)
a:
( /)
~
Q)
>
'i:
C
Q)
s::::
:.:i
TEXAS
INSTRUMENlS
-1!1 4-203

r-
S'
CD
C
'"<'
-
CD
o'"
:c
CD
(')
CD
<'
CD
'"o
4-204
SN55150, SN75150
DUAL LINE DRIVERS
D951. JANUARY 1971-REVISED SEPTEMBER 1986
Satisfies Requirements of EIA Standard SN55l50 ... JG PACKAGE

RS-232-C SN75150 ... D. JG. OR P PACKAGE
(TOP VIEW)
Withstands Sustained Output Short-Circuit
to any Low-Impedance Voltage Between S u 8 VCC+
-25 V and 25 V lA 2 7 lY
2A 3 6 2Y
2 p.s Max Transition Time Through the + 3 GND 4 5 VCC-
V to - 3 V Transition Region Under Full
2500-pF Load
Inputs Compatible with Most TTL Families (TOP VIEW)
Common Strobe Input +

U
U U UU
Inverting Output z (/)z>z

Slew Rate can be Controlled with an
External Capacitor at the Output
Standard Supply Voltages ... 12 V
description
The SN55150 and SN75150 are monolithic dual
line drivers designed to satisfy the requirements
NC
lA
NC
2A
NC
4
5
6
8
7
3 2
9 10111213
1 2019
18
17
16
15
14
NC
lY
NC
2Y
NC

'Q)
..
en
Q)
>
CJ
Q)
of the standard interface between data terminal
equipment and data communication equipment
as defined by EIA Standard RS-232-C. A rate of
U
Z
ClU
zz
(!) U
>
IU
U Z
-..
a::
en
Q)
20,000 bits per second can be transmitted with NC-No internal connection
'I:
>
a full 2500-pF load. Other applications are in C
data-transmission systems using relatively short logic symbol t Q)
single lines, in level translators, and for driving t:
MaS devices. The logic input is compatible with :J
most TTL families. Operation is from + 12-volt
and -12-volt power supplies.
the full military temperature range of - 55C to t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
125C. The SN75150 is characterized for IEC Publication 617-12.
operation from OC to 70C. Pin numbers shown are for D. JG. and P packages.
STROBE (1)
lY
1 A ...;.(2;...;)~-+-tL~
2A ...;..(3-')_ _-t_~
specifications p~r tho terms of Texas Instruments TEXAS 4-205
~!:.:~~~~~i~a{~~1~1~ ~!~~~~ti:fn fI~o::~:~Mros~s not INSTRUMENTS
SN55150, SN75150
DUAL LINE DRIVERS
schematic (each line driver)

vcc+--~~-- ______________ ~~ __________ ~~ ____________ ~
INPUT ________
STROBE __-'-M~~~~__~__~
S
TO OTHER
LINE DRIVER
r- 15 kO
OUTPUT
5' y
(1)
4:5 kO
C
""'II
<:'
(1) GND---.----~~--_.
""'II
en TO OTHER
~
(1)
LINE DRIVER.
n
(1)
<:'
(1)
""'II
en
TO OTHER
LINE DRIVER
VCC----4--------------------------~--------~~----~--~
4-206 TEXAS
INSTRUMENTS
SN55150, SN75150
DUAL LINE DRIVERS
c:'bsolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage VCC + (see Note 1) 15 15 V
Supply voltage VCC- -15 -15 V
Input voltage 15 15 V
Applied output voltage 25 25 V
D package 725
Continuous total dissipation at (or below) 25 DC FK package 1375
mW
free-air temperature (see Note 2) JG package 1050 825
P package j
1000
Operating free-air temperature range -55to125 o to 70 DC
Storage temperature range -65 to 150 -65 to 150 DC
Case temperature for 60 seconds: FK package 260 DC
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package 300 DC
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package

260 , DC
2. For operation above 25 DC free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the JG package, SN55150
chips are alloy mounted and SN75150 chips are glass mounted. In the P package use the 8.0-mW/ DC curve for these devices.
II... (I)
Q)
:>
recommended operating conditions 'iii
(.)
SN75150 Q)
-...
SN55150
UNIT a:
( I)
Supply voltage, VCC + 10.8 12 13.2 10.8 12 13.2 V
Q)
Supply voltage, VCC- -10.8 -12 -13.2 -10.8 -12 -13.2 V
:>
High-level input voltage, VIH 2 5.5 2 5.5 V 'i:
Low-level input voltage, VIL 0 0.8 0 0.8 V C
15 15 V Q)
Applied output voltage, Vo
DC
t:
Operating free-air temperature, TA - 55 125 0 70
:.:::i
. TEXAS ~ 4-207
INSTRUMENTS
SN55150. SN75150
DUAL LINE DRIVERS
noted)
Vec+ = 10.8 V, VCC- = -13.2 V,
RL = 3 k!1 to 7 k!1
5 8 .v
VIL = 0.8 V,
VCC+ = 10.8 V, Vec- = -10.8 V,
VOL Low-level output voltage (see Note 3) -8 -5 V
VIH = 2 V, RL = 3 kfl to 7 kfl
VCC+ = 13.2 V, Data input 1 10
IIH High-level input current Vec- = -13.2 V, p.A
Strobe input 2 20
VI = 2.4 V
VCC+ = 13.2 V, Data input -1 -1.6
IlL Low-level input current Vec- = -13.2 V, mA
Strobe input -2 -3.2
VI = 0.4 V
Vo = 25 V 2 8
II
r-
lOS Short-circuit output current;
Supply current from Vec +,

VCC+ =
VCC- = -13.2 V
13.2 V, Vo = -25 V
Vo = 0, VI = 3 V
Vo = 0, VI = 0
10
-10
-3
15
-15
-8
30
-30
mA
5' ICCH+
high-level output
VCC+ = 13.2 V, Vec- = -13.2 V, 10 22
CD VI = 0, RL = 3 kfl, mA
Supply current from Vec _,
...C ICCH-
high-level output
TA = 25C -1 -10
<' Supply current from Vee +,

...en
CD leeL+
low-level output
Vec+ = 13.2 V,
VI = 3 V,
Vec- = -13.2 V,
RL = 3 kfl,
8 17
mA
Supply current from Vee _,
~ leCL-
low-level output
TA = 25C -9 -20
CD
n
CD tAlitypicalvaluesareatVec+ = 12V,VCC- = -12V,TA = 25C.
<'CD :I: Not more than one output should be shorted at a time.
...
en
NOTE 3: The algebraic convention,
for logic levels only, e.g.,
in which the less positive (more negative) limit is designated as minimum, is used in this data sheet
when - 5 V is the maximum, the typical value is a more negative voltage.
switching characteristics, VCC+ = 12 V, VCC- = -12 V, TA = 25C (see Figure 1)

tTLH Transition time, low-to-high-Ievel output CL = 2500 pF, 0.2 1.4 2 p's
tTHL Transition time, high-to-Iow-Ievel output RL = 3 k!1 to 7 kfl 0.2 1.5 2 p's
tTLH Transition time, low-to-high-Ievel output CL = 15 pF, 40 ns
tTHL Transition time, high-to-Iow-Ievel output RL = 7 kfl 20 ns
tpLH Propagation delay time, low-to-high-Ievel output CL=15pF, 60 ns
tpHL Propagation delay time, high-to-Iow-Ievel output RL = 7 kfl 45 ns
4-208 TEXAS ~
INSTRUMENlS
SN55150, SN75150
DUAL LINE DRIVERS

3V
~+-~.--~..- OUTPUT
TEST CIRCUIT
!!f10ns--t+-~ 14 _I !!f10ns
:--~--~~.....t--.J.. - - - - - 3 V
INPUT 90% 90% I
10%
1 1 . SV
!+--
:.. tpHL
- - - - - - -..... 1
-+I
~3V
50 p.s
1.5V
---...,j
110
%
"------0 V
1+ tPLH-+!
I
~
V
. / + J V OH
II
...(I),
CD'
OUTPUT j' ~-3V -3vk'_L_vOL >
'iii
,tTHL --f4--I'I tTLH --\+--.I CJ
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the foliowing characteristics: duty cycle !!f 50%. Zout == 500.
-...
CD
a:
( I)
CD
>
'i:
FIGURE 1. SWITCHING CHARACTERISTICS C
CD
c
:.::i
TEXAS . . 4-209
INSTRUMENTS
SN55150, SN75150
DUAL LINE DRIVERS
OUTPUT CURRENT
vs
APPLIED OUTPUT VOLTAGE
20
Vcc+ - 12 V VI I.. 2~4 V
-12 V _
15 VCC- -
10
TA - 25C
f
I
5
'I-" , ,
'5
o
I--- ~
!.-L
-- ::::::::
...-....-
"
-
,
- :...--
-RL - 7 kfl
~
;- -5 'RL '" 3 kfl

o
I
,9-10
r-
:i'
(I)
-15
IJ
VI .. 0.4 V
t--
..c
c'
-20 I
-25-20-15-10-5 0
I I
5 10 15 20 25
.. Vo-Applied Output Voltage-V
-
(I)
In FIGURE 2
:0
(I)
(")
(I)
..c'
(I)
In
STROBE
I
I
CHANNEL 2 I ~I_-"""
DATA INPUT L ~~~O_-1
ALL DIODES ARE-'
1N752A
MIL-STO-188C _ _ _ _ _
INTERFACES
CHANNEL 2 STROBE
CHANNEL 2
DATA OUTPUT
HYSTERESIS~_ _ _~
CONTROL
CHANNEL 1 STROBE
FIGURE 3. DUAL-CHANNEL SINGLE-ENDED
INTERFACE CIRCUIT MEETING MIL-STD-'188C,
PARAGRAPH 7.2.
4-210 TEXAS -1.!1

INSTRUMENTS
SN75151, SN75153
QUAD DIFFERENTIAL LINE DRIVERS WITH 3STATE OUTPUTS
02453. DECEMBER 1978-REVISED OCTOBER 1986
Meets EIA Standard RS422-A SN75151

OW. J. OR N PACKAGE
High-Impedance Output State for Party-Line (TOP VIEW)
Operation
1A VCC
High Output Impedance in Power-Off
lY 4A
Condition
1Z 4Y
Low Input Current to Minimize Loading 1C 4Z
CC 4C
Single 5-V Supply 2C S
o '40-mA Sink- and Source-Current Capability 2Z 3C
2Y 3Z
2A 3Y
Low Power Requirements GND 3A
description
These line drivers are designed to provide
differential signals with high current capability
SN75153
J OR N DUAL-IN-LiNE PACKAGE
1A
(TOP VIEW)
VCC
II ...en
on balanced lines. These circuits provide strobe Q)
and enable inputs to control all four drivers, and 1Y 4A >

1Z 4Y CD
the SN75151 provides an :::<:iditional enable input CJ
CC 4Z Q)
-...
for each driver. The output circuits have active
pull-up and pull-down and are capable of sinking 2Z S a:
2Y 3Z en
or sourcing 40 milliamperes. Q)
2A 3Y
The SN75151 and SN75153 meet all GND 3A
>
.i:;
requirements of EIA Standard RS-422-A and C
Federal Standard 1020. They are characterized Q)
for operation from OC to 70C. s:::::
:.::i
FUNCTION TABLES
SN75151 SN75153

ENABLE ENABLE STROBE DATA ENABLE STROBE DATA
Y Z Y Z
CC C S A CC S A
L X X X Z Z L X X Z Z
X L X X Z Z H L X L H
H H L X L H H X L L H
H H X L L H H H H H L
H H H H H L
PRODUCTION DATA documents contain information Copyright 1978. Texas Instrum.ents Incorporated
~!:c~~~~~i~a{~~I~~e ~!~:i~~ti~; fl~o~:~:~M~s~s not
TEXAS -II} 4-211
INSTRUM,ENTS
POST OFFICE BOX 655012 DALLAS, TFlfA.S 75265
SN75151, SN75153
logic symbols t
SN75151 SN75153
1C (4) 1Y 1Y
1A (1) 1Z 1Z
2C (6) 2Y
2A (9)
3C (14) .
3A (11) 3A
3Z
4C (16) 4Y
4A (19) 4A
4Z
III
r-

S' SN75151 SN75153
CD
..
C S
(15)
(5)
S
(12)
.
:C:' CC
(4) CC
(4)
-
CD
1C
en (2)
1Y
(2)
1Y
:lJ (1) (3) 1A (1) (3)
CD 1A 1Z 1Z
(")
CD
..<'
CD
en
2C
2A
(6)
(9)
(8)
(7)
2Y
2Z 2A
(7)
(6)
(5)
2Y
2Z
(14)
3C
(12) (10)
3Y 3Y
(11) (13) (9) (11)
3A 3Z 3A 3Z
(16)
4C (18) (14)
4Y 4Y
(19) (17) (15) (13)
4A 4Z 4A 4Z
4-212 TEXAS . .
INSTRUMENTS
SN75151, SN75153
~UAD DIFFERENTIAL LINE DRIVERS WITH 3STATE OUTPUTS
schematic
STROBE S
TO THREE COMMON TO ONE
OTHER DRIVERS INPUT A OTHER CHANNEL
VCC~~~~____-+____~____~~__~~~__~r~-~l7-____~__~~__-+~
90
OUTPUT Y OUTPUT Z
III
. fA
Q)
'0)
>
CJ
ENABLE
CC
-..
a::
Q)
fA
Q)
>
TO THREE '~
OTHER DRIVERS C
Q)
All resistor values shown are nominal.
c
:.:J
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
OW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1125 mW
J package ...................................... ". . . . . . . . . . . . . . . . .. 1025 mW
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1150 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 70C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: OW or N package. . . . . .. 260C
NOTES: 1. All voltage values, except differential output voltage VOD, are with respect to network ground terminal.
2. For operation above 25C free-air temperature, derate the OW package at the rate of 9 mW/oC, the J package at the rate
of 8.2 mW/oC, and the N package at the rate of 9.2 mW/oC. In the J package, the chips are glass mounted.
TEXAS ~ 4-213
INSTRUMENTS
SN75151 r SN75153

MIN NOM MAX UNIT
Lowlevel input v.Jltage, VIL 0.8 V
Common-mode output voltage, Voe -0.25 6 V
High-level output current, 10H -40 mA
Low-level output current, 10L 40 mA
Operating free-air temperature, T A 0 70 DC
noted)
PARAMETER TEST CONDITIONSt MIN TYP* MAX UNIT
Vee = MIN, ee, S -2
VIK Input clamp voltage V
II = -12 mA All others -0.9 -1.5
Vee = MIN, 10H = -20 mA 2.5
r- VOH High-level output voltage VIL = MAX, V
10H = -40 mA 2.4
:i' VIH = 2 V
CD Vee = MIN, VIL = MAX,
.cC' VOL Low-level output voltage
I V OD11 Differential output voltage

VIH = 2 V,
Vee = MAX,
10L = 40 mA
10 = 0
0.5
3.4 2VOD2
V
.
CD
en
I V OD21 Differential output voltage
~IVODI
Vee = MIN
Vee = MIN
2 2.8
0.01 0.4
V
V
~ differential output voltage
RL = 100 fI,
CD
(")
. Common-mode output voltage'
Vee = MAX 1.8 3
Voe See Figure 1 V
CD Vee = MIN 1.6 3
..
C'
CD
en
~IVoel
common-mode output voltage
Vee = MIN or MAX
Vo = 0.5 V
0.02 0.4
-20
V
Off-state (high-impedance- Vee = MAX,

10Z
state) output current
Vo = 2.5 V 20 p.A
Enable at 0.8 V
Vo =
Vee 20
Vo =
6 V 0.1 100
10 Output current with power off Vee = 0 Vo = -0.25 V -0.1 -100 p.A
Vo = -0.25 V to 6 V 100
Input current at
II Vee = MAX, VI = 5.5 V 0.1 mA

Vee = MAX, e('151), A 20
IIH p.A
VI = 2.4 V ee,s 80

Vee = MAX, e ('151), A -0.36
IlL mA
VI = 0.4 V ee,s -1.6
lOS Short-circuit output current # Vee = MAX -50 -90 -150 mA
Vee = MAX, Outputs disabled 30 60
ICC Supply current (both drivers) mA
No load Outputs enabled 60 80
i All typical values are at T A = 25 DC and Vee = 5 V except for Voe, for which Vee is as stated under test conditions.
~ I VOD I and ~ I Voe I are the changes in magnitudes of VOD and Voe, respectively, that occur when the input is changed from a high
, In EIA Standard RS-422-A, Voe, which is the average of the two output voltages with respect to ground, is called output offset voltage, VOS.
#Only one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
4-214 TEXAS .-1}}

INSTRUMENTS
SN75151, SN75153
switching characteristics, Vee -= 5 V, T A -= Ooc to 70C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN Tvpt MAX UNIT
tpLH Propagation delay time, low-to-high-Ievel output CL = 30 pF, RL = 1000, See Figure 2, 15 30 ns
tpHL Propagation delay time, high-to-Iow-Ievel output Termination A 15 30 ns
tpLH Propagation delay time, low-to-high-Ievel output 13 25 ns
CL = 30 pF, See Figure 2, Termination B
tpHL Propagation delay time, high-to-Iow-Ievel output 13 25 ns
tTLH Transition time, low-to-high-Ievel output CL = 30 pF, RL = 1000, See Figure 2, 12 20 ns
tTHL Transition time, high-to-Iow-Ievel output Termination A 12 20 ns
tpZH Outut enable time to high level CL = 30 pF, RL = 600, See Figure 3 18 35 ns
tpZL Output enable time to low level CL = 30 pF, RL = 1110, See Figure 4 20 35 ns
tpHZ Output disable time from high level CL = 30 pF, RL = 600, See Figure 3 19 30 ns
tpLZ Output disable time from low level CL = 30 pF, RL = 111 0, See Figure 4 13 30 ns
Overshoot factor RL = 1000, See Figure 2, Termination C 10 %

II
... en
CI)
>
'0)
(.)
i
VOD2
500
500
~
VOC
-...
a:
CI)
en
CI)
>
'i:
I -=1- C
CI)
FIGURE 1. DIFFERENTIAL AND COMMON-MODE OUTPUT VOLTAGES c:
:::i
TEXAS 4-215
INSTRUMENTS
SN75151. SN75153
1 kn
5 V ------''\l1li"....,
L..-i--.......--~--f-- Y OUTPUT
t -........---::----tL_--J'P---:--- Z OUTPUT
II:
r-
5'
RL - 100 n
Y
Z
CD
TERMINATION A TERMINATION B TERMINATION C
C
"'<'" TEST CIRCUITS
CD
"'en"
l; 14 25ns~
CD
1 14- ~ ~ ns \4--~
on -+t --.! II 5 ns
CD 0
<'
CD
,II
1 I 90%
I 1
;:j I - - - 3 V
"'en" ~~T 1 1
14----.t--tpLH
~90"'%--"'-~~
Y OUTPUT
1
1 VOL
I I I I
1 -+t I+-tTLH 141 I+-tTHL
14 tpHL 14 ~I
I
90% 90%1
Z OUTPUT 1.5 V 1
10% 10% I
1- I-VOL
1
I+-tTHL -.I k-tTLH
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zout = 50 0, PRR ~ 10 MHz.
FIGURE 2. tPLH. tPHL. tTLH. tTHL. AND OVERSHOOT FACTOR
4-216 TEXAS
INSTRUMENTS
SN75151, SN75153
CL - 30 pF
~ (See Note B)
~I~----~--OUTPUT
I
I
I
I T (See Note B) I
L ____________ ~ ____ ~
5V
1 kG
TEST CIRCUIT
II
... II)
Q)
~ 5 ns~ 14- >
ir:-=-:-:-----=-::":':""\II- ~ - - - -3V
'iii
(J
-...
90% 90% I Q)
1.5V 1.5V I a:
I I I I)
14---100 ns----+l 10% 0 V
Q)
J+---* tpZH I
>
OUTPUT
il
!1.5V
i
I: R:--!:-VOH
0.5V
'i::
C
Q)
r::::
-----'. tPHzH Voff .. 0 V :::i
VOLTAGE WAVEFORMS
FIGURE 3. tpZH AND tPHZ
NOTES: A. The pulse generators have the following characteristics: Zout = 50 G, PRR ~ 500 kHz.
TEXAS ~ 4217
INSTRUMENTS
SN75151, SN75153
CL - 30 pF
~ (see Note B)
5V
5V RL - 111 0
1 kO ~I:-o-----e--OUTPUT
I
I
I CL - 30 pF I
I 'T' (see Note B) I
lL-------------~-----~
I
TEST CIRCUIT
I 10%
1.5V
,.--100 ns~ " - - - - - - 0 V

I+- tpZL -.I I
I I
I I
I I
I !f-tPLZ-+! V
OUTPUT \5V ~5
. - f-VOL
VOLTAGE WAVEFORMS
FIGURE 4. tpZL AND tpLZ

NOTES: A. The pulse generators have the following characteristics: Zout = 50 0, PRR :5 500 kHz.
4-218 TEXAS
INSfRUMENlS
-111
SN75151. SN75153
y OUTPUT VOLTAGE .
vs
DATA INPUT VOLTAGE
5
NoLo~d -
TA - 25e Vee - 5.5 V
4 I
> Vee - 15 V
I
CD
01 Vee - 4.5 V
S 3
>..So
"0

:I
:I 2
0
I
0
>
...en
Q)
:>
J 'Q)
(,)
o
o
FIGURE 5
2 3
-...
a::
Q)
en
Q)
:>
'':
Y OR Z OUTPUT VOLTAGE Y OR Z OUTPUT VOLTAGE C
Q)
vs vs
I:
ENABLE INPUT VOLTAGE ENABLE INPUT VOLTAGE ::l
4 l I 6
Load -470 b Vee" 5.5 V
Vee" 5.5 V Load .. 470 n to Vee
to Ground
l TA .. 25e
,
r- Vee .. 5 V
See Note 3 5 See Note 4
Vee - 5 V Vee - 4.5 V
> 3 -TA'" 25e >
I I
CD
01
Vee" 4.5 V CD
,01 4
S S
"0 "0
..
>
:I
2
>..
::J
3
So
:I
So
::J
0 0
I I 2
0 0
> >
1
o o
o 2 3 o 2 3
VI-Enable Input Voltage-V VI-Enable Input Voltage-V
FIGU~E 6 FIGURE 7
4. The A input is connected to ground during the testing of the Y outputs and to Vee during the testing of the Z outputs.
TEXAS 4-219
INSTRUMENTS
SN75151, SN75153
HIGHLEV~L OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE

vs vs
6
Vee - 5 V
1 4
--- r-- - ~ee I.. 5
II
TA - 25C
>
I
G)
5
See Note 3 >
I
II)
---r-- r-. ~
1..-:- See Note 3
;-.....
---
CI CI
S S 3 Vee .. 5 V
.. r-- -.. ~:r:J-

ee .. 45 ~~
"0 "0
>..:J
4 >
:J
-~
0
So
:J
3
IOH - -20mA
-40mA
;
0
C.
2
V
r-- ",1\
"\
II
Qj IOH - Qj
>
II)
>
G)
-' -'
.r.CI
2 .r.
CI
:f :f
r- I I
5' ::t:
0
::t:
0
CD > >
...
C
CE'
o o
o 10 20 30 40 50 60 70 80 o -20' -40 -60 -80 -100
...
-
(1)
(I) TA-Free-Air Temperature- C IOH-High-Level Output Current-mA
: lI
(')
(1)
LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
CE'
...
(1)
(I)
vs
vs
OUTPUT CURRENT
0.6 .----T""""-I--rl.---..---.----r--...----.---, 1.0 I
VCC - 5 V TA - 25e
> > 0.9 See Note 4
IOL- 40 mA
I 0.5 r-See Note 4 -t---t--+--t--t----i I
II) II)
CI CI 0.8
S S j
"0
>
;
0.4 ~--t---t--+--+--+---+---+---i
..
"0
>
:J
0.7
0.6
//
. ~
So
:J
So
:J ~~
0 0.3 ~--t---t--+--+--+---+---+---i 0 0.5 Cr
Qj
>
II)
-'
~ 0.2 I-----i:-----i--t--+--t---t---+---t
Qj
>
....
II)
~
0.4
~ ~CC
~CC
. ~.
~~
c 0.3
....c
-'
0
>
I
.... 0.1 I-----i:-----i--t--+--t---t---+---t
>
I
-'
0
0.2 , ~ 9'
0.1
o '-----''------'_---'-_--'-_--'-_--'-_-'-_..J o
.0 10 20 30 40 50 60 70 80 o 20 40 60 80 100 120
TA - Free-Air Temperature IOL -Low-Level Output Current-mA
FIGURE 10 FIGURE 11
4. The A input is connected to ground during the testing of the Y outputs and to Vee during the testing of the Z inputs.
4-220 TEXAS
INSTRUMENTS
SN75151, SN75153
QUAD DIFFERENTIAL LINE DRIVERS WITH 3"STATE OUTPUTS
vs vs
80 80 I I
70 ~ 70
No (oad I
A inputs open or grounded
<t A Inputs GrOUnde~V Outputs disabled
~
E 60 E 60 TA - 25e
1-c
~ 50 A'
V
lc:
l!? 50
:s
(J J A Inputs Open :;
(.) ./
40 >
40
~~
>-
Q. is.
V
II
Co
c. 30 :J 30
::J
r C/)
V
"
rJ)
I
I (.) /'
(J 20 9 20
,/
!:}
10 / No Load
Outputs enabled- 10 J ...
rJ)
Cl)
>
o / TA - 25e
I I I o /' "Qi
(,)
o 2 345
FIGURE 12
6 7 8 o 2 3 4 5
FIGURE 13
6 7 8
-...
CC
Cl)
r J)
Cl)
>
"i:
4. The A input is connected to ground during the testing of the Y outputs and to Vee during the testing of the Z inputs.
C
Cl)
c
::i
TEXAS . . 4-221
INSTRUMENTS
II
r-
5'
CD
..
C
..
<'
-
CD
VI
:CD:c
n
CD
..<'
CD
VI
4-222
SN55152. SN75152
DUAL LINE RECEIVERS
01114, AUGUST 1972-REVISEO SEPTEMBER 1986
Meets Specifications of EIA RS-232-C or SN55152 ... J PACKAGE

MIL-STD-188Ct SN75152 ... D, J, OR N PACKAGE
(TOP VIEWI
Dual Differential Receiver with Independent
Strobes HYST CONTt VCC+
lOUT 20UT
Common-Mode Input Voltage
lSTRB 2STRB
Range ... 25 V
lHYST ADJ 2HYST ADJ
Differential Input Capability with One Input llN- 21N-
Grounded . . . 25 V lRT 2RT
llN+ 21N+
Continuously Adjustable Hysteresis with
GND VCC-
External Resistors
Standard Supply Voltages ... + 12 V
(TOP VIEWI
and -12 V
Input Hysteresis (Double Thresholds)
Remain Approximately Fixed for Power
Supply and/or Temperature Variations 1-1-
:::::>
0+-
I-
Z
o
U
U)
+1-
u:::::>
III
... (/)
o >- u uo Q)
IZ>N
description
2 1 2019
om:>
The SN55152 and SN75152 are dual differential oQ)
-a:...
line receivers designed to meet the requirements lSTRB 4 18 2STRB
of EIA Standard RS-232-C or MIL-STD-188 lHYST ADJ 5 17 2HYST ADJ
( /)
interfaces. A single control, HYST CONT, sets NC 6 16 NC
Q)
the input hysteresis for the required operation. llN- 7 15 21N- :>
lRT 8 14 2RT a::::
An added feature is the capability of adjusting
9 10 11 1213 C
the hysteresis to any voltage between 0.3 volt
Q)
typical and 5 volts typical by means of the + 0 U 1+ t:
hysteresis adjust terminals, 1 HYST ADJ and Z
-
Z
(!)
Z UZ
U- ::;
2HYST ADJ, making the SN55152 and >N
SN75152 useful for a wide variety of line NC - No internal connection
receiver and Schmitt trigger applications. The
large common-mode input voltage range and
differential input voltage ( 25 volts) give the
circuit added versatility. The SN55152 and
SN75152 are designed for, operation from
standard 12-volt supplies with 10%
variation. Each receiver has an output strobe that
is TTL compatible.
t To meet the specifications of EIA Standard RS-232-C, connect the hysteresis control pin, HYST CaNT, to VCC _ . Also, connect termination
resistor pin 1RT to inverting input liN -, and termination resistor pin 2RT to inverting input 21N -. To meet the specifications of
MIL-STD-188, leave HYST CaNT, 1 RT, and 2RT open.
~~~~~:~~i~a[~~,~lJ~ ~!~~i~~ti~r :,~o::~:~:t:~s~s not INSTRUMENTS
SN55152, SN75152
DUAL LINE RECEIVERS
FUNCTION TABLE Definition of logic levels:

(EACH RECEIVER)
For the strobe: H (high) is any voltage between
LINE INPUT STROBE OUTPUT VIH min and Vee.
H H H L (low) is any voltage between
L H L ground and VIL max.
X L H For the line input: H (high) is any differential input
voltage (VID):t: more positive
than VT -. once the ~evel of
VT + has been reached.
L (low) is any differential input
voltage (VI D) :t: more negative
than VT +, once the level of
VT - has been reached.
X (irrelevant) is any input voltage
permitted by maximum ratings.
t Differential input voltages (VT and VIO) are at the noninverting

input terminal IN + with respect to the inverting input terminal
r-
:i'
CD
IN-.
..
c
<"
.. (3)
-
CD lSTRB
en lHYST ADJ
(4)
::Il l1N+
(7)
CD
n lRT
(6)
CD
<"
..
(5)
l1N-
CD (1)
HYST co NT
en (10)
21N+
1111
2RT
(121
21N-
(13)
2HYST ADJ
(14)
2STRB

lEe Pub.lication 617-12.
4-224 TEXAS
INSTRUMENTS
SN55152, SN75152
DUAL LINE RECEIVERS
;---11-; - - ,
STROBE OUTPUT I VCC+ :

13.141 12.151
I I
10 kll '----~~---
I I
I
I
I I
L _____ .J
H ....._ _ _ _.-""'8Nk0V--+_ _15_._12_1_:~~~~~~:
1 kO
r----T------J-:,~:~ II
r ---- --liiI-l
I GND
...
t/)
Q)
I I >
I I 'iii
(,)
I
I
I -...
Q)
a:
t /)
Q)
>
'i:
C
Q)
c:
5110 ::::i
511 Il 2 kO 511 Il 1.1 kll
t--_ _-+-___+_3_.3.-kll......,r-Il..;,.1 HYSTERESIS
I CONTROL
I 191
~ L ______V~=-__1
14. 13. TO OTHER
HYSTERESIS RECEIVER
ADJUST
Portions of circuit within dashed lines are common to both receivers.

TEXAS 4-225
INSTRUMENTS
SN55152, SN75152
DUAL LINE RECEIVERS
Supply voltage, VCC + (see Note 1) 15 15 V
Supply voltage, VCC _ (see Note 1) -15 -15 V
Voltage at any line input with respect to other line input, ground, ot RT 25 25 V
RT terminal voltage (see Note 1) 25 25 V
D package 950
mW
N. package 1150
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds J package 300 300
II
C
Lead temperature 1,6 mm (1/16 inch) from case for' 10 seconds D or N package 260 C
NOTES: 1. These voltage values are with respect to network ground terminal.
2. For operation above 25C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the J package, SN55152
r- chips are alloy mounted and SN75152 chips are glass mounted. In the N package, use the 9.2-mW/oC curve for these devices.
S'
..<'
CD
C
..
CD
tn Supply voltage, VCC +
MIN
10.8
SN55152
NOM
12
MAX
13.2
MIN
10.8
SN75152
NOM
12
MAX
13.2
UNIT
V
iCD Supply voltage, VCC- -10.8 -12 -13.2 -10.8 -12 -13.2 V
High-level input voltage at strobe, VIH(S) 2 2 V
n
CD Low-level input voltage at strobe, VIL(S) 0.8 0.8 V
..
<'
CD
tn
4-226
TEXAS -I.!}
INSTRUMENTS
electrical characteristics over operating free-air temperature range, VCC + 12V 10%, VCC- -12 V 10% (unless
otherwise noted)
TEST MIN Typt MAX
FIGURE (SEE NOTE 3)
'75152 0.1 0.3 0.5
VT+ Positive-going threshold voltage V
1 '55152 0.03 0.3 0.5
See MIL-STD-188 Conditions
'75152 -0.5 -0.3 -0.1
VT- Negative-going threshold voltage Figure 8 V
'55152 -0.5 -0.3 -0.03
VT+ Positive-going threshold voltage 1.5 2.2 3
2 EIA AS-232-C Conditions V
VT- Negative-going threshold voltage -3 -2.2 -1.5
VID = VT + max, Vl(strobe) = 2 V,
1 and 2 3 4.1 6
10H = -500/LA
VOH High,level output voltage V
VID = VT _ min, Vl(strobe) = 0.8 V,
1 and 2 3 4.1 6
10H = -500/LA
~
I
VID = VT _ min, Vl(strobe) = 2 V,

VOL Low-level output voltage 1 and 2 0 0.15 0.4 V
~-
10L :: 6.4 mA
~z Input current into strobe at
3
't5rn
X-i
II
maximum strobe voltage
Vl(strobe) = 5.5 V 0.1 1 mA
~;c~ IIH High-level strobe current 3 VI("trnh,,1 = 2.4 V 30 80 /LA
:~~
f?1TI
~z
IlL
q
Low-level strobe current
Input resistance
MIL-STO-188
EIA AS-232-C
3
4
4
Vl(strobe) = 0.4 V
IVlol = 0 V to 25 V,
IVlol =3Vt025V,
AT open, TA = 25C
AT connected to inverting line input,

6
3
-0.5
9
5
-1.5
7
mA
krl
~~~
~ Vl(ooen) Open-circuit input voltage 5
TA = 25C
+1 2 V
....
'"'" lOS Short-circuit output current 6 VID = 3 V -1.9 -4 mA
0>
ICC+ Supply current from VCC + 1 VID = -3V, V/(strobel = 2.4 V 10 16 mA
ICC- Supply current from VCC- 1 VID = -3V, VII"trnb,,1 = 2.4 V -7 -13 mA
t Oifferential input voltages (VT and VID) are at the noninverting line input terminal with respect to the inverting line input terminal.
tTypical values are at VCC+ = 12 V, VCC- = -12 V, TA = 25C.
NOTE 3: The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold levels only, e.g.,
when - 0.1 V is the maximum, the minimum limit is a more negative voltage.
c
c::
::c:a(/)
r-2
switching characteristics, VCC+ 12 V, VCC- -12 V, TA 25C r-U1
_U1
2-
mU1
TEST N
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ::a-
FIGURE
m(/)
tpLH Propagation delay time, low-to-high-Ievel output 40 n Z
7 CL = 15 pF ns !:!! .....
tpHL Propagation delay time, high-to-Iow-Ievel output 60
--- - - ----------- - -- -- c:: U1
m-
II
.p. :::JCI U1
(/) N
N
I\J
......
Line Drivers/Receivers
SN55152, SN75152
DUAL LINE RECEIVERS
III
r-
:l" NOTE: Output is open for testing ICC + and ICC-
CD
..c<" FIGURE 1. MIL-STD-188 CONDITION
..
-
CD
Ch Vcc+ VCC-
:c
CD
(')
CD
<"CD
r J---- ------
HYST
..
Ch
I
I NONINV
CONT TO OTHER
RECEIVER
I RT f1+
{ ; : JIOH '
'f}
I i II
I'NV HVST
AOJ S GNO.
I
L
---:EN-:':'~b:-I-"
FIGURE 2. EIA RS-232-C CONDITION
4-228
TEXAS -I/}
INSTRUMENTS
SN55152, SN75152
DUAL LINE RECEIVERS
Vcc+ Vcc-
OPEN
rJ---- _______ L,
I ~6~i TO OTHER I
I NON- RECEIVER I
OPENf-r-' ..,.IN\I'\V~ ;
OPEN
VI(strobe)
FIGURE 3
II
..CI)
Q)
>
Vcc+ VCC 'CD
1~
(.)
r -'---::
HYST
_____
CO NT
I
I
-..
a:
Q)
CI)
Q)
>
'a::::
I C
I Q)
I OPEN c:
I ::;
INV HYST I
L ADJ S GN~
_ AVID -~---------T,
q - AT! OPEN OPEN -=
FIGURE 4
Vcc+ VCC-
rJ------------,
HYST I
I NON CONT TO OTHER
I INV - RECEIVER I
I I
I
i
IRT
OPE_N__~____~~ I OPEN
Vl(open)
1 OPEN
FIGURE 5
OPEN
TEXAS . . 4-229
INSTRUMENTS
SN55152. SN75152
DUAL LINE RECEIVERS
III
I""
FIGURE 6
:5"
(I) Vcc+ OPEN VCC-
.,c
<' r -L---------1,I
-
.,
(I) HYST
til CONT I
:Xl I
(I) INPUT --+--~~.f".
o I
(I)
<' n---L---4......-
1
OUTPUT
.,
(I)
til AOJ S GNO!
OPEN - - : . . ~--r~
TEST CIRCUIT
:5 10 ns-+l I+- -+4 1f-:5 10 ns

l I I .
l i-o~---9-0-%S,-I- - --- 5 V
INPUT I
l OV I
:,.1_0_%~ __ -5 V
tpLH ~ ". ~I tpHL
I I V
OUTPUT '1.5V 1.5V\[-- OH
_ _ _..I. . "-- VOL
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR :5 1 MHz, duty cycle = 50%, Zout == 50 O.
4-230
TEXAS ~
INSTRUMENTS
SN55152, SN75152
DUAL LINE RECEIVERS
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
5
Vcc+ = 12 V EIA RS-232-C CONDITION
VCC- = -12 V (See Figure 2)
I \
> 4 TA = 25C
V \
I
CD
C'I I \
~
"0 3
>
....:l
0
Q.
5 2
VT- VT-
I
MIL-STD-1SS'
VT+ VT+
;--- II
,--- ..
I
CONDITION
0 en
>
--
(See Figure 1)
Q)
1\ >
'Q)
- (.)
o
-25 -4 -3 -2 -1 o
VIO-OIFFERENTIAL INPUT VOLTAGE-V

2 3 4
.1----
25
-..
a:
Q)
en
Q)
>
'i:
FIGURE S C
Q)
THRESHOLD VOLTAGE VARIATION

c:
:.:J
vs
POSITIVE SUPPLY VOLTAGE
> 20
E VCC- = -12 V
I TA = 25C
r:: 15
..g I I I, I
.!!! EIA RS-232-C CONDITION
10
n:; (See Figure 2)
> 1\
~
CD
C'I
5
o ~ ~ -
"0
>
"tl
"0
.r:.
-5
--V ~
V
II) MIL-STD-1SS CONDITION
.-~ -10 (See Figure 1)
>
I
.- -15
<I
-20
10.5" 11 11.5 12 12.5 13 13.5
VCC + - Positive Supply Voltage - V
FIGURE 9
TEXAS -Ij} 4-231

INSTRUMENTS
SN55152, SN75152
DUAL LINE RECEIVERS
THRESHOLD VOLTAGE VARIATION

vs
NEGATIVE POWER SUPPLY
> 20
E Vcc+ = 12V /
I
c 15 TA = 25C , I
/
.g
.~ 10
EIA RS-232-C_
CONDITION V
~
>=
CI) 5
(See Figure 2)/
Cl
S li-~
"0 0
>
-7
-----
MIL-S,b-188
~ -5 CONDITION
~
II)
/
/ (See Figure 1)
f? -10
r '~
:5"
CD ~ -15
/
>
...c <I -20 /
<" -10.5 -11 -11.~ -12 -12.5 -13 -13.5
...
-
CD
U) VCC - - Negative Supply Voltage - V
:x:J FIGURE 10
CD
o
CD THRESHOLD VOLTAGE
<" vs
...
CD
t/)
HYSTERESIS ADJUST RESISTANCE
6
VCC+ = 12 V
> 5
\ VCC- = -12 V
-
\ RT open
I
CI) TA = 25C
! 4
"0
>
~ 3 \
~
II)
CI) \ ~
~ 2
"'-...
...
> 1
I
'-- r---.
o
o 0.5 1.5 2 2.5 3
Radjt -HYSTERESIS ADJUST RESISTANCE-kD
t Radj is connected between Hysteresis Adjust terminal and Vee _.
FIGURE 11
4-232 TEXAS -Ij}

INSTRUMENTS
SN55152, SN75152
DUAL LINE RECEIVERS
PROPAGATION DELAY TIME

vs
80
1/1 70
tP~L
r:::
I
CD 60
E
j::
>- 50
IU
Ci tpLH
c 40
II
r-
r:::
.g 30
IU
C)
IU
C.
0
Ii:
20 VCC+ = 12 V ...
tJ)
(1)
VCC- = -12 V >
10 CL = 15 pF '0)
See Figure 7 I CJ
o
o 10 20 30 40 50
TA - Free-Air Temperature -
60
c
70 80
-...
a:
(1)
t J)
(1)
>
FIGURE 12 '':
C
(1)
c
:.:J
Some typical applications of the SN55152 and SN75152 are as follows:
MIL-STD-188 Interface Receiver
EIA RS-232-C Interface Receiver
Single-Ended Line Receiver
Differential Line Receiver
High-Noise-Immunity Line Receiver
Schmitt Trigger
High-Voltage-Logic-to-TTL Translator
MOS-to-TTL Converter
Pulse Generator
Threshold Detector
Pulse Shaper
TEXAS -Ij} 4-233

INSTRUMENTS
SN55152, SN75152
DUAL LINE RECEIVERS
;I__ :: _____-I,
VCC+
t NON-
HYST
CONT TO OTHER
j VCC- I
I
I INV RECEIVER I
INPUT
I
OPEN -+..JV'I.f'v-J I TTL-COMPATIBLE
I I OUTPUT
---
IINV HYST I
L ADJ S GND.
::-~T~:~-l-~
III FIGURE 13. MIL-STD-188 SINGLE-ENDED LINE RECEIVER
+12V -12V
,...J ___________,
IVCC+ HYST VCC-I
I NON- CONT TO OTHER
I INV RECEIVER I
INPUT --I---e......-f"'.J I
I
I TTL-COMPATIBLE
IINV OUTPUT
I HYST :
L
--- ADJ
:P:-:::~-r
S' GN'2.J
NORMAL OPERATION
+12 V OPEN -12 V
r: __ -' _______
VCC+ HYST
J_,
VCC- I
1kn
I _ CONT TO OTHER I
INPUT
! NON
INV RECEIVER I
I RT I
t I TTL-COMPATIBLE
f I OUTPUT
.
IINV HYST I
ADJ S GND.
200 n L
---:E:-:TR:-r~
FAIL-SAFE OPERATION
FIGURE 14. EIA RS-232-C SINGLE-ENDED RECEIVER
4-234 TEXAS
. INSTRUMENTS
SN55152, SN75152
DUAL LINE RECEIVERS
12 V
5V
HYSTERESIS
CONTROL
r-vk--,
__+--e
125 f! 3.9 f!
A rVCC:-- -"2SN75;S2- -j
I -
I NON
RG63B/U -e_I--...;..'_I_NV_......--f.......
TO OTHER
RECEIVER I
CABLE I
B I TTl-COMPA TlBlE
I I OUTPUT
I
L~~~1!....J
6.8 kf! . .__. . :~--~--I_N~ J II
...rJ)
-12 V Q)
>
FIGURE 15. SINGLE-ENDED TRANSMITTER WITH DRIVER "0R" CAPABILITY "(j)
(,)
AND RECEIVER WITH ADJUSTABLE NOISE IMMUNITY Q)
5V
12V -12V -...
a:
r J)
Q)
HY(~~;~NT
1 kf! >
560 f!
50 f! J "i:
C
Q)
r
50 f!
c:
::i
__-+--f+II-.+-e_-.r-..... +-. VcZ+- - - - - - - - VCC ~
INON- I
,INV I
I RT I
I
I TTLCOMPATIBlE
---S--IJ
I OUTPUT
TWISTED
PAIR
Frequency to 0.5 MHz

Common-Mode Voltage ... - 12 V to + 10 V
t The 1N4444 diodes are required only for negative common-mode protection at th~ driver outputs.
FIGURE 16. BALANCED LINE OPERATION WITH HIGH COMMON-MODE-VOLTAGE CAPABILITY
TEXAS ~ 4-235
INSTRUMENTS
post OFFICE SOX 865012 DALLAS, TEXAs 16265
III
r
5'
CD
...C
<'
...
CD
-
til
:a
CD
n
CD
<'
...
CD
til
4-236
SN55154. SN75154
QUADRUPLE LINE RECEIVERS
0899. NOVEMBER 1970-REVISEO SEPTEMBER 1986
Satisfies Requirements of EIA Standard SN55154 . J PACKAGE

RS-232-C SN75154 ... D. J. OR N PACKAGE
{TOP VIEW)
Input Resistance ... 3 kO to 7 kO over Full
3T VCC2
RS-232-C Voltage Range
2T VCC1
Input Threshold Adjustable to Meet 1T 4T
"Fail-Safe" Requirements Without Using 1A lY
External Components 2A 2Y
3A 3Y
Built-In Hysteresis for Increased Noise
4A 4Y
Immunity R1t
GND
Inverting Output Compatible with TTL
Output with Active Pull-Up for Symmetrical SN55154 ... FK PACKAGE
Switching Speeds {TOP VIEW) -
Standard Supply Voltages ... 5 V or 12 V
description 3
UU
I-I-UUU
N('t)Z
2
N..-
1 2019
II
...
en
Q)
The SN55154 and SN75154 are monolithic 1T 4 18 4T
1Y
>
Low-Power Schottky line receivers designed to 1A 5 17 '(i)
NC (.)
satisfy the requirements of the standard NC 6 16
Q)
interface between data terminal equipment and
data communication equipment as defined by
EIA standard RS-232-C. Other applications are
2A
3A 8
7
9 1011 1213
15
14
2Y
-...
a:
en
Q)
for relatively short, single-line, point-to-point <! DU+- >- >
'i:
data transmission and for level translators. <:t zz.-<:t
<.:J II: C
Operation is normally from a single five-volt Q)
supply; however, a built-in option allows NC No internal connection c:
operation from a 12-volt supply without the use t For function of R 1. see schematic :J
of additional components. The output is
compatible with most TTL circuits when either
supply voltage is used.
In normal operation, the threshold-control terminals are connected to the VCC1 terminal, even if power
is being supplied via the alternate VCC2 terminal. This provides a wide hysteresis loop, which is the
difference between the positive-going and negative-going threshold voltages. See typical characteristics.
In this mode of operation, if the input voltage goes to zero, the output voltage will remain at the low or
high level as determined by the previous input.
For fail-safe operation, the threshold-control terminals are open. This reduces the hysteresis loop by causing
the negative-going threshold voltage to be above zero. The positive-going threshold voltage remains above
zero as it is unaffected by the disposition of the threshold terminals. In the fail-safe mode, if the input
voltage goes to zero or an open-circuit condition, the output will go to the high level regardless of the
previous input condition.
The SN55154 is characterized for operation over the full military temperature range of - 55C to 125C.
The SN75154 is characterized for operation from OOC to 70C.
~:~~:~~i~ai~:1~1~ ~!:~~~ti~r :1~o::~:~M:s~s not
TEXAS ~ 4-237
. INSTRUMENTS
SN55154, SN75154
logic symbol t logic diagram
1A~. (13)1V
1T
~ V"
2A ~5)
..IT (12) 2V
(2)
2T
3A~3V
t This symbol is in accordance with ANSI/lEEE Std 91-1984 and
3T~ V-
Pin numbers shown are for D, J, and N packages.
4A ~7)
..IT (10) 4V
111
r- schematic
4T
(14) .
:r
CD COMMON TO 4 RECEIVERS
r-------,
.
c
<.
VCC2
(See Note 1)
I 3.2 kn I
CD
""II
t/) I I
iCD I I
o VCC1 ----....:..1--... I
CD
<. 1 I
..
CD
t/)
R1
GND
----------~--~__
5kn
L _______ ...JI
I
1 OF 4 RECEIVERS
r---- ----------l
THRESHOLD
CONTRO L -':--------------, I
5kn 1.6kn 1.6 kn 200 n I
I
9.9 kU
I
I
.---....:1,- OUTPUT
I
4.2 kn I
INPUT -.:..-----.----..-......~
2.7 kn
I
I
L ___________________ ~I
Component values shown are nominal.
ti? .. Substrate
NOTE 1: When VCC1 is used, VCC2 may be left open or shorted to VCC1. When VCC2 is used, VCC1 must be left open or connected
to the threshold control pins.
4-238 TEXAS ~
INSTRUMENTS
SN55154, SN75154
Normal supply voltage, VCCl (see Note 2) 7 7 V
Alternate supply voltage, VCC2 14 14 V
Input voltage 25 25 V
. D package 950
mW
N package 1150
Operating free-air temperature range -55to125 o to 70 C

SN55154 SN75154
II
... C/)
MIN NOM MAX MIN NOM MAX UNIT Q)
Normal supply voltage, VCCl 4.5 5 5.5 4.5 5 5.5 V >
10.8 13.2
'(jj
Alternate supply voltage, VCC2 10.8 12 13.2 12 V (,)
High-level input voltage, VIH (see Note 4)
Low-level input voltage, VIL (see Note 4)
High-level output current, IOH
Low-level output current, IOL
-15
-55
3 15
-3
-400
16
125
-15
3
0
15
-3
-400
16
70
V
V
p.A
mA
-...
a:
Q)
C/)
Q)
>
Operating free-air temperature, T A C 'i:
C
NOTES: 2. Voltage values are with respect to network ground terminal. Q)
3. For operation above 25C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the J package, SN55154 t:
chips are alloy mounted and SN75154 chips are glass mounted. In the N package, use the 9.2-mW/oC curve for these devices. :..J
4. The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet
for logic and threshold levels only, e.g., when 0 V is the maximum, the minimum limit is a more negative voltage.
TEXAS -II} 4-239

INSTRUMENTS
SN55154, SN75154
noted)
TEST MIN TYP~ MAX
FIGURE (SEE NOTE 4)
Positive-going Normal operation 0.8 2.2 3
VT+ 1 V
threshold voltage Fail-safe operation 0.8 2.2 3
Negative-going Normal operation -3 -1.1 0
VT- 1 V
threshold voltage Fail-safe operation 0.8 1.4 3
Normal operation 0.8 3.3 6
Vhys Hysteresis (VT + - VT _ ) 1 V
Fail-safe operation 0 0.8 2.2
VOH High-level output voltage 1 IOH = -400 p.A 2.4 3.5 V
VOL Low-level output voltage 1 10L = 16 rnA 0.29 0.4 V
AVI = -25Vto -14V 3 5 7
AVI = -14Vto -3V 3 5 7
III
r-
q Input resistance
Vl(openl Open-circuit input voltage

2
3
AVI = -3 V to 3 V
AVI = 3Vto 14V
AVI = 14Vt025V
II = 0
3
3
3
0
6
5
5
0.2
8
7
7
2
k!l
V
S Shortcircuit output current t 4
CD lOS VeC1 = 5.5 V, VI = -5 V -10 -20 -40 rnA
.
C
ct
ICCl
ICC2
Supply current from VCCl
5
VCCl = 5.5 V, TA = 25C
VCC2 = 13.2 V,TA = 25C
20
23
35
40
rnA
~ tNot more than one output should be shorted at a time.

~ tAli typical values are at VCC1 = 5 V, TA= 25C.
:xJ
gCD switching characteristics, VCC1 == 5 V, TA = 25C, N ... 10
<' PARAMETER
TEST
TEST CONDITIONS MIN TYP MAX UNIT
..,
CD FIGURE
til tpLH Propagation delay time, low-to-high-Ievel output 11 ns
tpHL Propagation delay time, high-to-Iow-Ievel output 8 ns
6 CL = 50 pF, RL = 390!l
tTHL Transition time, high-to-Iow-Ievel output 2.2 ns
OUTPUT VOLTAGE vs INPUT VOLTAGE

4 ----i :f--
VCC1 =5 V
~ po
TA = 25C
>I
G>
3 ;t--
NORMAL , .... FAILSAFE ...
E ----i OPERATION- OPERATI0 .r---
.e
"0
>
::J 2 ~
I,
See Note 5 j VT_
1
VT_ VT+
::J
0
-., ;r---
I
0 ----f
>
,
o =---1
-25 -4 -3 -2 -1 o 2 3 4
;~ 25
VI-Input Voltage-V
NOTE 5: For normal operation, the threshold controls are connectd to VCC1" For fail-safe operation, the threshold controls are open.
4-240 TEXAS ~
INSTRUMENTS
SN55154, SN75154
d-c test circuits t

TEST TABLE
VCC1 VCC2
TEST MEASURE A T Y
(PIN 15) (PIN 16)
Open-circuit input VOH Open Open IOH 4.5 V Open
(fail safe) VOH Open Open IOH Open 10.8 V
VT+ min, VOH 0.8 V Open IOH 5.5 V Open -
VT _ min (fail safe) VOH 0.8 V Open IOH Open 13.2 V
VOH Note A Pin 15 IOH 5.5 V and T Open
VT + min (normal)
VOH Note A Pin 15 IOH T 13.2 V
VIL max, VOH -3 V Pin 15 IOH 5.5 V and T Open
VT _ min (normal)
VIH min, VT + max,
VT _ max (fail safe)
VIH min, VT + max
VOH
VOL
VOL
VOL
-3 V
3V
3V
3V
Pin 15
Open
Open
Pin 15
IOH
IOL
IOL
IOL
T
4.5 V
Open
4.5 V and T
13.2 V
Open
10.8 V
Open
II
..(I)
(normal) VOL 3V Pin 15 IOL T 10.8 V Q)
VOL Note B Pin 15 IOL 5.5 V and T Open >
VT,- max (normal) 'Q)
VOL Note B Pin 15 IOL T 13.2 V (.)
Q)
NOTES: A. Momentarily apply - 5 V, then 0.8 V.
B. Momentarily apply 5 V, then ground.
-.
a:::
g
( I)
Q)
5.5 V 0 013.2 V
'':
>
OPEN 0 COPEN C
4.5 V 010.8 V
Q)
OPEN s:::
::l
- -VCC1- VCC2 - ~~ { ~OH
~OL
---r----.J li lI
GND
~
y
I ~-=-
V~L1- VOH
T""l
~
t Arrows indicate actual direction of current flow. Current into a terminal is a positive value.
TEXAS . . 4-241
INSTRUMENlS
SN55154, SN75154

d-c test circuits t (continued) TEST TABLE
VCCl VCC2
T
(PIN 15) (PIN 16)
Open 5V Open
Open GND Open
Open Open Open
Pin 15 T and 5 V Open
GND GND Open
.D-----'-~- OPEN Open Open 12 V
Open Open GND
Pin 15 T 12 V
Pin'15 T GND
III
r-
FIGURE 2. rj
Pin 15 T Open
5'
CD
...C
5.5 V ~O_ - -10--- 13.2 V
TEST TABLE
<'CD VCCl VCC2

...
en _____ .1..,
OPEN T
(PIN 15) (PIN 16)
Open 5.5 V Open
"i
CD
VCCl Rl I Pin 15 5.5 V Open
n ~---y:....t-- OPEN Open Open 13.2 V
m
<' L.
-----r---- J
Pin 15 T 13.2 V
Vl(open) GND
...
CD
en ~
FIGURE 3. Vl(open)
5.5 V j C C 1
1
-0---}1::-13.2 V
OPEN OPEN
r
T
--
VCC1
___
VCC2
J....,
R1
IA yl
-5V 5V IT OPEN
I GND I I
L... - - --.r----~
Each output is tested separately. All four line receivers are tested simultaneously.
FIGURE 4. lOS FIGURE 5. ICC

tArrows indicate actual direction of current flow. Current into a terminal is a positive value.
4-242 TEXAS
INSTRUMENTS
"bst O~FICl eox snal ~ DALLAS, tlxAII1S26B
SN55154, SN75154
INPUT SV OUTPUT
OPEN OPEN
r T - VCC1- VCC2 -
L J R1-'
RL=390n
PULSE IA yl
GENERATOR IT ~----~"-Mr4~r.r.~
(See Note A)
I GND I
'-- - --,------'
"* 1;
CL=SOpF
(See Note B)
II
TEST CIRCUIT
~ 10 2 ns let--.!-- 10 2 ns
I I I'
:ir~90~%~O------"!:'9~0%~O\ . - : - - - - - - - - - SV
... rn
OJ
>
INPUT "iii
a:"
10%}/
____.....-:r- I : 410%
I
ov
-s V OJ
I
~ tpHL I+- ---+\
I
tpLH l+- -... rn
OUTPUT
2V~
I
I
I 1.S V 1.S V
AI,..------
I
I
I :
2V
VOH
'0
OJ
>
"a:::
OJ
I O.sv os V I c
I !'-I-------.....;..;..---------VOL ::i
. I I I I
I I
tniL-.! ~ -*I ~tTLH
VOLTAGE WAVEI=ORMS
NOTES: A. The pulse generator has the following characteristics: Zout = 50 n, tw = 200 ns, duty cycle s 20%.
C. All diodes are 1N3064.
TEXAS . . 4-243
INSTRUMENTS
POST OFFICE. BOll 655012 DALLAS, TEXAS 75266
II
r-
5'
CD
...C
<'
...
CD
en
ii
CD
n
CD
<'
...
CD
en
4-244
ADVANCE SN75155
INFORMATION LINE DRIVER AND RECEIVER
02951. JULY 1986
D8
Meets EIA Standard RS-232-C D. JG. OR P PACKAGE
(TOP VIEW)
10-mA Current Limited Output
Wide Range of Supply Vee- Vee+
DA 2 7 DY
Voltage ... VCC = 4.5 V to 15 V
RY 3 6 RTe
Low Power ... 130 mW GND 4 5 RA
Built-In 5-Volt Regulator

logic symbol t
o Response Control Provides:
Input Threshold Shifting I>
Input Noise Filtering
DA' (2)
Power-Off Output Resistance ... 300 n Typ
Driver Input TTL Compatible
description
The SN75155 is a monolithic line driver and
receiver that is designed to satisfy the
RA (5)
RTC
I>
IIen
"-
(I)
requirements of the standard interface between
>
data terminal equipment and data 'iii
lEe Publication 617-12 u
communication equipment as defined by EIA (I)
standard RS-232-C. A Response Control input
is provided for the receiver. A resistor or a
resistor and a bias voltage can be connected
logic diagram
(1 )
-
a:
en
"-
(I)
between the response control input and ground VCC- - - - - - - - - - , >

'i:
to provide noise filtering. The driver used is VCC+~~----~-~ C
similar to the SN75188. The receiver used is (I)
similar to the SN75189A. DA ~~-----+--I c
:.:J
OOC to 70C. GND
RA
RTC
Z
0
i=
<t
:E
a:
0
LL
-w
Z
(.)
z
<t
>
c
<t
information on new IIroducts in the sampling or
IIreproduction phase of development. Charactenstic
ilata and other specifications are subject to change
TEXAS . . . 4-245
SN75155 ADVANCE
LINE DRIVER AND RECEIVER INFORMATION
schematic
DA~(~2)~ __________________________________________ ~
vcc+~(~8)~----~ ____~______________________________-r____~__~~__~
3.5 kG
RA (5)
III
r-
GND~(4~)~~--~~____~+-~__~~~-4~~__~~~
RTC~(~6)____________-+~
:i'
CD
...c
<'CD VCC_~(~l)------------~~--------*---__~__________~__~__~______4-~
...en (3) RY
iCD All resistor values shown are nominal.

(')
CD absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
<'CD
...
en
Supply voltage, VCC + (see Note 1) ............................................ 15 V
Supply voltage, VCC - (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -15 V
Input voltage range: Driver ................................. ,........ - 1 5 V to 15 V
Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 30 V to 30 V
Output voltage range (Driver) ......................................... - 15 V to 15 V
D package ......................................................... 725 mW

c
JG package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 825 mW
P package ........................................................ , 1000 mW
<

Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds, JG package ............ 300C
2 Case temperature for 60 seconds, FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260C
("')
m Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds, D or P package ......... 260C
-2 NOTES: 1. All voltage values are with respect to network ground terminal.
2. For operation above 25C freeair temperature, refer to Dissipation Derating Table. In the JG package, SN75155 chips are
"o . glass mounted.

:Jl
S TA - 25C TA - 70C
PACKAGE
POWER RATING
DERATING FACTOR ABOVE TA
POWER RATING
::! D 725 mW 5.8 mW/oC 25C 464 mW
o JG
P
825 mW
1000 mW
6.6 mW/oC
8.0 mW/oC
25C
25C
528 mW
640 mW
2
4-246 . TEXAS-li}
INSTRUMENTS
ADVANCE SN75155

PARAMETERS MIN NOM MAX UNIT
Supply voltage, Vcc + 4.5 12 15 V
Supply voltage, VCC- -4.5 -12 -15 V
Input voltage, driver, VI(O) 15 V
Input voltage, receiver, VI(R) -25 25 V
High-level input voltage, driver, VIH 2 V
Low-level input voltage, driver, VIL 0.8 V
Response control current 5.5 mA
Output current, receiver, IO(R) 24 mA
Operating free-air temperature, T A 0 70 DC
noted)
total device
PARAMETERS
VCC+ = 5 V,
TEST CONDITIONS
VCC- = -5 V, VI(O) = 2 V,
MIN Typt
6.3
MAX
8.1
UNIT
II
. t/)
Q)
ICCH+ High-level supply current VCC+ = 9 V, VCC- = -9 V, VI(R) = 2.3 V, 9.1 11.9 mA
>
VCC+ = 12 V, VCC- = -12 V, Output open 10.4 14 'iii
= 5 V, = -5 V, = 2.5 3.4 u
-.
VCC+ VCC- VI(O) 0.8 V, Q)
ICCL+ Low-level supply current VCC+ = 9 V, VCC- = -9 V, VI(R) = 0.6 V, 3.7 5.1 mA a:
VCC+ = 12 V, VCC- = -12 V, Output open 4.1 5.6 t /)
VCC+ = 5 V, VCC- = 0, VI(R) = 2.3 V, 4.8 6.4 Q)
ICC+ Supply current mA
VCC+ = 9 V, VCC- = 0, VI(O) =0 6.7 9.1
'i:
>
VCC+ = 5 V, VCC- = -5 V, VI(O) = 2 V, -2.4 -3.1 C
ICCH- High-level supply current VCC+ = 9 V, VCC- = -9 V, VI(R) = 2.3 V, -3.9 -4.9 mA Q)
VCC+ = 12 V, VCC- = -12 V, Output open -4.8 -6.1 c:
VCC+ = 5 V, VCC- = -5 V, VI(O) = 0.8 V, -0.2 -0.35 ::i
ICCL- Low-level supply current VCC+ = 9 V, VCC- = -9 V, VI(R) = 0.6 V, -0.25 -0.4 mA
VCC+ = 12 V, VCC- = -12 V, Output open -0.27 -0.45
t All typical values are at TA = 25 DC.
2:
o
i=
<C
~
a:
o
LL
-w
2:
(.)
2:
<C
>
c
<C
TEXAS 4-247
INSTRUMENTS
SN75155 ADVANCE
electrical characteristics over recommended operating free-air temperature range, Vee + == 12 V,

Vee- = -'12 V (unless otherwise noted)
driver section
Vcc+ = 5 V. Vcc- = -5 V 3.2 3.7
VOH High-level output voltage VIL = 0.8 V. RL = 3 kf! VCC+ = 9 V. VCC- = -9 V 6.5 7.2 V
VCC+ = 12 V. VCC- = -12 V 8.9 9.8
VCC+ = 5 V. VCC- = -5 V -3.6 -3.2
VOL VIH = 2 V. RL = 3 kf! VCC+ = 9 V. VCC- = -9 V -7.1 -6.4 V
(see Note 3)
VCC+ = 12 V. VCC- = -12 V -9.7 -8.8
IIH High-level input current VI = 7 V 5 /LA
IlL Low-level input current VI = 0 -0.73 -1.2 mA
High-level short-circuit
II
laSH VI = 0.8 V. Va = 0 -7 -12 -14.5 mA
output current
Low-level short-circuit
10SL VI = 2 V. Va = 0 6.5 11.5 15 mA
output current
r- RO
Output resistance
Va = -2 V to 2 V 300 n
5' with power off
CD
.ct
C receiver section
.
CD
en VT+
PARAMETER
Positive-going
threshold voltage
TEST CONDITIONS MIN
1.2
Typt
1.9
MAX
2.3
UNIT
V
"i
CD Negative-going
n VT- 0.6 0.95 1.2 V
threshold voltage
CD
<'CD
.
en
Vhys Hysteresis

VI = 0.6 V.
10H = 10/LA
VCC+ = 5 V.
VCC+ = 12 V.
VCC- = -5 V
VCC- = -12 V
0.6
3.7
4.4
4.1
4.7
4.5
5.2
V
V
VI = 0.6 V. VCC+ = 5 V. VCC- - -5 V 3.1 3.4 3.8
10H = 0.4 mA VCC+ =12 V. VCC- = -12 V 3.6 4 4.5
VOL Low-level output voltage VI = 2.3 V. 10L = 24 mA 0.2 0.3 V
VI = 25 V 3.6 6.7 10 mA
VI = 3 V 0.43 0.67 1 mA
c IlL Low-level input current

VI = -25 V
VI = -3 V
-3.6 -6.7
-0.43 -0.67
-10
-1
mA
mA
<
lOS Short-circuit output current

VI = 0.6 V -2.8 -3.7 mA
:2 NOTE 3: The algebraic limit system. in which the more positive (less negative) limit is designated as maximum. is used in this data sheet
for logic voltage levels only. e.g . if - 8.8 V is the maximum. the typical value is a more negative value.
("')
m
:-2
'TI
o
::JJ
S
::j
o
:2
4-248 TEXAS ~
INSTRUMENTS
ADVANCE SN75155
switching characteristics over recommended operating free-air temperature range, vee + ":' 5 V,
Vee - = - 5 V, eL = 50 pF (unless otherwise noted)
driver section (see Figure 2)
tPLH Propagation delay time, low-to-high-Ievel output 250 480
RL = 3 kO ns
tpHL Propagation delay time high-to-Iow-Ievel output 80 150
RL = 3 kO 67 180 ns
tr Output rise time
RL = 3 kO to 7 kO, CL = 2500 pF 2.4 3 /ls
Output fall time

RL = 3 kO 48 160 ns
tf
RL = 3 kO to 7 kO, CL = 2500 pF 1.9 3 /ls
receiver section (see Figure 3)

PARAMETER TEST CONDITIONS
II
MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-Ievel output 175 245
RL = 4000 ns
tr Output rise time RL = 4000 255 360 ns
tf Output fall time RL = 4000 23 50 ns ... en
CD
t All typical values are at T A = 25C. >
'Q)
CJ
VCC
-...
a:
CD
en
CD
>
'i:
C
CD
jlOH
t c:
:::i
t
jlOL
RESPONSE
CONTROL VOH
1
1\
ti VOL
z
T t-
11
OPEN
UNLESS
OTHERWISE
CC
iRC c'
o
SPECIFIED i=
vc +VC
':' -=
:!
t Arrows indicate actual direction of current flow. Current into a terminal is a positive value.
a:
FIGURE 1. RECEIVER SECTION TEST CIRCUIT (VT+, VT-, VOH, VoLl ou.
-w
Z
o
z

>
c

TEXAS -I./} 4-249
INSTRUMENTS
SN75155 ADVANCE
~5~---3V
-J: .
INPUT 1,.5 V
INPUT .x~~--.-- OUTPUT
(SEE NOTE BI I 0 V
RL - 3 kfl
I CL - 50 pF
(SEE NOTE AI
tpHL~
_ _...,.1
90%
t+-
I
-+I
OUTPUT
III

B.' The input waveform is supplied by a generator with the following characteristics: Zout '" 50 fl, tw = 1 p's, tr ~ 10 ns, tf ~ 10 ns.
r FIGURE 2. DRIVER SECTION SWITCHING TEST CIRCUIT AND VOLTAGE WAVEFORMS
:i'
(1)
...c OUTPUT 5V
<' RESPONSE
-'2 ~2 V
------4V
...
(1)
CONTROL INPUT V
en
i INPUT
---t': . (SEE NOTE BI l\ .0 V
(1)
I I
n tpHL --+I 1oII141---I+--
(1)
<' VOH
...en
(1)
10%

B. The input waveform is supplied by a generator with the following characteristics: Zout '" 50 fl, tw = 1 p's, tr ~ 10 ns, tf ~ 10 ns.
l>
c FIGURE 3. RECEIVER SECTION SWITCHING TEST CIRCUIT AND VOLTAGE WAVEFORMS
<
l>
:2
("')
m
:2
"TI
o::g
S
l>
~
o
:2
4-250 TEXAS ~
INSTRUMENTS
POST OFplc~ 1l0x ae~o12 OAl~AS, t&i<AS 15266
ADVANCE SN75155
(DRIVER)
OUTPUT CURRENT
vs
VOLTAGE TRANSFER CHARACTERISTICS OUTPUT VOLTAGE
10
V~C,- ~12y TA .. 25C
8 RL .. 3 kIl-
6 l - VCC - 9V
c:z:
>
I 4
I' I 1 1 E
CD
Cl VCC .. 5 V .!.c
!9 2 l!?
(5 :;
>...
:::I
So
0 u
..
:::I
:::I
o
-2 e
:::I
-4
o
>
6 -4 9
I -8
...CD
en
-6 -12 r-~--~~~~~~--+--+--+-~ :::-
'Q)
-8 - 16 ~....;e::,--++-+- (.)
-10
1 1.2 1.4 1.6
VI-Input Voltage-V
1.8 2
-20
-20
~~~~~~
- 12 - 4
__U-~_ _~~_ _~~
0 4
Va-Output Voltage-V
8 12 16 20
-... CD
a:
en
CD
:::-
FIGURE 4 FIGURE 5 'I:
C
CD
SHORT-CIRCUIT OUTPUT CURRENT SLEW RATE c:
vs vs ::J
FREE-AIR TEMPERATURE LOAD CAPACITANCE
15 1000
I t 1= FALL Vcc+ .. 12 V
c:z: IOS(L) = H
E --I--- 400 ... .c. . . . VCC- "" -12 V
.!.c 10
VCC+ .. 12 V
-........ I-Ris~
TA .. 25C
l!? VCC- "" -12 V
2:
:;
u
... 5 ~VO .. 0 ~ 100
:>
o
:::I
So !
I "-
i=
:::I 40
, <C
..
o
S
o co
a:
::CD 2
!::! a:
q
15
-5 iii 10
oLL
..c
(I'J 4 " 2:
In -10 IOS(H) ... L
'I .J.-- r--
9
r- w
-15
1
10 100 1000 10000
CJ
o 10 20 30 40 50 60 70 CL -Load Capacitance-pF 2:
TA - Free-Air Temperature - C <C
FIGURE 6
FIGURE 7
>
c
<C
TEXAS ~ 4-251
INSTRUMENTS
SN75155 ADVANCE
(RECEIVER)
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
5
RC - 3.9 kO I !
RC .. OPEN- -
RC - 20 kG
Vc - -5 V
Vc - 5 V
VCC+ - 12 V
> 4 VCC---12V
I
GJ TA - 25C
CI
III
~ 3
..
III
r-
>
:J
Q.
:; 2
o
I
VT+ VT+ VT+
:r
CD
o
> VT- VT- VT-
c...
<" o
...en
CD -5 -4 -3 -2 -1 0 2 3 4 5
VI-Input Voltage-V
iCD
(")
FIGURE 8
CD
<"CD OUTPUT VOLTAGE
...
en vs
INPUT VOLTAGE
RC - 10 kG - I L RC - 20 kOJ
RC .. OPEN- f - - -VC - -12 V
5 V .. 12 V
_ VCC+ _ 12 V
l>
o VCC- _ -12 V
<
l>
TA - 25C
2:
("')
..
:J
Q. VT+ VT+
, VT+
:; 2
-m
2:
i1
o
o
>
I
VT- VT- VT-
o
:rJ o
s: -5 -4 -3 -2 -1 0
VI-Input Voltage-V
2 3 4 5
l>
:::! FIGURE 9
o
2:
4-252 TEXAS -I.!}

INSTRUMENTS
POST OFFice BOX 655012 " OALLAS. TeXAS 75265
ADVANCE SN75155
(RECEIVER)
INPUT THRESHOLD VOLTAGE INPUT CURRENT

vs vs
FREE-AIR TEMPERATURE INPUT VOLTAGE
3 10
Vcc+ - 12 V TA = 25C
VCC- - -12 V 8 VCC+=12V
2.5 VCC- "" -12 V ./
6
>
- --
I
(I)

E 4 /
~ 2 r---VT+
____ I /V
"0 E 2
> r---I - - ~
V
~ 1.5
J:
CI)
(I)
..c
..
I- VT-
:;
U
~ -2
s::
I" -4
0
/V"
""V
V
II
... (I)
::l OJ
Co
-= -6
V
""V 'Q)
:>
0.5 (.)
o
o 10 20 30 40
T A - Free-Air Temperature - C
50 60 70
-8
-10
-25-20-15-10 -5 0 5
VI-Input Voltage-V
10 15 20 25 -...
"a:
OJ
( I)
OJ
:>
'':;:
FIGURE 10 FIGURE 11 C
OJ
t:
NOISE REJECTION :.J
9
\ \ \ 1VCC+ - 12 V
8 \ \ IvCC_ - -12 V
\
\ \ 1\ TA - 25C, , Lilt
~ 7 \ \ 1\ Cc .. 1000 pF
Ql
~6 \ \ 1\ Cc "" 500 pF z
"0 \
\
\
\
\ vl\ Cc - 300 pF o
~ 5 \ ~I\
k- Cc .. 100 pF
i=
"0
~ 4
\
X'
.v' ). . . . 1\
Cc - 10 pF

~
~
..
J:
I- 3 \/
"- ........
\.
~ I'\,. a:
::l
~2
r-..... r--..... o
. LL
o
10 100 1000 10000
-wZ
tw-Pulse Duration-ns U
z
FIGURE 12

c>

TEXAS 4-253
INSTRUMENlS
III
r-
:r
C'D
c
~.
..
<
C'D
-
(II
:D
C'D
~
C'D
::r
.
CD
(II
4-254
SN55157, SN75157
D2300, SEPTEMBER 19BO-REVISED SEPTEMBER 19B6
Meets EIA Standards RS-422-A and SN55157 ... JG PACKAGE

RS-423-A SN75157 ... 0, JG, OR P PACKAGE
u
ITOP VIEWI
Meets Federal Standards 1020 and 1030
11N+ 8 Vee
Operates from Single 5-V Power Supply 10UT 2 7 11N-
Wide Common-Mode Voltage Range 20UT 3 6 21N+
GND 4 5 21N-
High Input Impedance
.. TTL-Compatible Outputs logic symbol t
...crc>
8-Pin Dual-In-line Package
121 lOUT
Similar to uA9637 AC except for Corner
II
VCC and Ground Pin Positions 131 20UT
description
The SN75157 is a dual differential line receiver
designed to meet EIA standards RS-422-A and
...
CI)
Q)
RS-423-A and Federal Standards 1020 and logic diagram :>

'Q)
1030. It utilizes Schottky circuitry and has TTL- (,)
compatible outputs. The inputs are compatible
with either a single-ended or a differential-line
system. The device operates from a single 5-volt
power supply and is supplied in an 8-pin dual-in-
1IN+~11
11N- 171
.r:r 121 10UT
-...
Q)
a:
CI)
Q)
:>
'i:
line package and small outline package.
2IN+~61 C
IJ' 131 20UT
The SN55157 is characterized over the full Q)
21N- 151
military temperature range of - 55C to 125C. c:
The SN75157 is characterized for operation from ::i
ooe to 70C.
VCC
- - - - - -.....--VCC
50n NOM
INPUT--~--~~-e~.-----~
OUTPUT
CURRENT
SOURCE
~~~~~:~~i~ai~:I~"'~ ~!~~:~ti:r fI~o::::~~t:~~s not INSTRUMENTS
POST OFFiCe BOX 655012 ' DALLAS. TeXAS 75265
SN55157, SN75157
Supply voltage, Vcc (see Note 1) ...................................... -0.5 V to 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 5 V
Differential input voltage (see Note 2) ......................................... 1 5 V
Output voltage (see Note 1) '" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 5.5 V
Low-level output current ................................................... 50 mA
SN55157 JG package. '" ............................ '" '" ......... 1050 mW
SN75157 D package ................................................. 725 ~W
JG package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 825 mW
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1000 mW
SN75157 ............................. ooC to 70C
III
r-
S'
NOTES:
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds JG package ............ 300C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds D or P package ....... " 260C
1. All voltage values, except differential input voltage, are with respect to the network ground terminal.
2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.
CD 3. For operation above 25C free-air temperature, derate the SN55157 JG package to 672 mW at 70C at the rate of 8.4 mW/oC,
the SN75157 JG package to 528 mW at 70C at the rate of 6.6 mW/oC, the D package to 464 mW at 70C at the rate
C
... of 5.8 mW/oC, and the P package to 640 mW at 70C at the rate of B.O mW/oC. In the JG package, SN55157 chips are
<' alloy mounted and SN75157 chips are glass mounted.
...til
-
CD
Jl
CD MIN NOM MAX UNIT
(")
CD Supply voltage, VCC 4.75 5 5.25 V
<' Common-mode input voltage, VIC 7 V
...
CD
til Operating free-air temperature, T A I SN55157 -55 25 125
c
I SN75157 0 25 70
electrical characteristics over recommended ranges of supply voltage, common-mode input voltage,
MIN Typt MAX
See Note 4
-0.2 0.2
VT Threshold voltage (VT + and VT _ ) V
See Note 5 -0.4 0.4
V~s Hysteresis (VT + - VT _) 70 mV
VOH High-level output voltage VID = 0.2 V, 10 = -1 mA 2.5 3.5 V
VOL Low-level output voltage VID = -0.2 V, 10 = 20 mA 0.35 0.5 V
II Input current
Vee = Oto 5.5 V, I VI = 10 V 1.1 3.25
mA
See Note 6 I VI = -10 V -1.6 -3.25
lOS Short-circuit output current:!: Vo = 0, VID = 0.2 V -40 -75 -100 mA

lee Supply current VID = -0.5 V, No load 35 50 mA
tAli typical values are at Vee = 5 V, TA = 25e.

:l:Only one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTES: 4. The algebraic convention, where the less-positive (more-negative) limit is designated as minimum, is used in this data sheet
for threshold levels only.
5. The expanded threshold parameter is tested with a 500-0 resistor in series with each input.
6. The input not under test is grounded.
4-256
. TEXAS ~
INSTRUMENTS
SN55157, SN75157
switching characteristics, V CC = 5 V, T A
PARAMETER TEST CONDITION MIN TYP MAX

VCC+ OUTPUT VCC+
INPUT 50%
50%
I I
-0.5 V I
~tPLH ~tPHL
II
I
OUTPUT
;"5 V ,.5V\
... tn
Q)
>
"Q)
TEST CIRCUIT VOLTAGE WAVEFORMS CJ
Q)
B. The input pulse is supplied by a generator having the following characteristics: tr :5 5 ns, tf :5 5 ns, PRR :5 5 MHz,
duty cycle = 50%.
-...
a:
tn
Q)
FIGURE 1. TRANSITION TIMES >

"i:
C
TYPICAL CHARACTERISTICS Q)
c::
OUTPUT VO L T AG E OUTPUT VOLTAGE ::i
vs vs
4 4
I L VCC = 5.25 V
VCC = 4.75 V
TA = 25C
t-TA = 25C I
I
I I
>I
Q)
3
:
I VIC= 0
>I
3 I
~
VIC = 0
Cl i Q)
~
"0 I VIC = 7 V 3' I
I
VIC = 7 V
I "0
>.... 2 >.... 2 I
:::I
I II
I :::I
S- S- VIC = 7 V:
:::I
0
l 0
:::I
I
I I I I
0 VIC = 7 V ~ 0 I VIC=O I
> > I
I
VIC=O I
~ I I I
I I
l
o o
- 100 -50 o 50 100 -100 -50 o 50 100
VID-Ditferential Input Voltage-mV VID-Differentiallnput Voltage-mV
FIGURE 2 FIGURE 3
. TEXAS. 4-257
INSTRUMENTS
SN75157
vs vs
HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
5.0 0_6
I
VCC = 5 V _
l Il
VCC = 5 V
4.5
>I VID = 0.2 V >b 0.5
t- VID = -0.2 V
g, 4.0 TA = 25C -
CI
TA = 25C
~
~ /
...
3.5 ........ g... 0.4 ~
3.0 ~ V
:l
S-
:l
o 2.5 "'", <5
:l
S-
0.3 /"
V
III
~
'" "" V
Qj
>
j 2.0 Q)
i:
...J
~ 0.2 L
; 1.5 o
~
...J
r- I I
J: 1.0 ...J
5' o "f\.. o 0.1
C'D > 0.5 >
C
..,
<'
..,
C'D
til
o
o -10 -20 -30 -40 -50 -60 -70
IOH-HighLevel Output Current-rnA
" -80
o
o 5 10 15 20 25 30
IOL -Low Level Output Current-rnA
35 40
:0
C'D FIGURE 4 FIGURE 5
(')
C'D
<' SUPPLY CURRENT
..,
CD vs
til SUPPLY VOLTAGE
100
No1load I
90 f- Inputs open
80 _ TA = 25C
c:(
E 70
.!.c
~ 60
:;
()
50 /
>
ii
c. 40
/V
:l
CI)
I
() 30
/V
~
20
V
10
V
/
V
o
o 2 3 4 5 6 7 8
VCC-Supply Voltage-V
FIGURE 6
4-258 TEXAS ~
. INSTRUMENTS
SN75157
+5 V TWISTED PAIR +5 V
IIICI)
a-
Q)
FIGURE 7. RS-422-A SYSTEM APPLICATIONS >
"iii
C.)
Q)
-
a:
CI)
a-
Q)
>
"a;:
C
Q)
c:
::;
TEXAS ".!} 4-259

INSTRUMENlS
III
r-
:f
CD
..c<'
.
CD
en
iCD
n
CD
..<'
CD
en
4-260
SN55158. SN75158
02292. JANUARY 1977-REVISEO SEPTEMBER 1986
Meets EIA Standard RS-422-A SN55158 ... JG PACKAGE

SN75158 ... D. JG. OR P PACKAGE
Single 5-V Supply (TOP VIEW)

Balanced-Line Operation
TTL-Compatible
1Z[]8 Vee
1Y
1A
2
3
7
6
2Z
2Y
0 High Output Impedance in Power-Off GND 4 5 2A
Condition
0 High-Current Active-Pullup Outputs
Dual Channels
Input Clamp Diodes
description
The SN55158 and SN75158 are dual complementary-output line drivers designed to satisfy the
requirements set by the EIA Standard RS-422-A interface specifications. The outputs provide
II
...
rA
complementary signals with high-current capability for driving balanced lines, such as twisted pair, at normal Q)
line impedance without high power dissipation. The output stages are TTL totem-pole outputs providing >
a high-impedance state in the power-off condition.
"cu
(.)
The SN55158 is characterized for operation over the full military temperature range of - 55 OCto 125C.
The SN75158 is characterized for operation from OC to 70 DC.

-...
a:
Q)
rA
Q)
>
".::;
C
C> ~1Y Q)
(2) 1Y lA ~1Z s:::::
1A (3) ::i
1Z
2A (5)
2Y ~2Y
2Z 2A~2Z

:~~~~:~~i~ai~~I~lJ~ ~!~~~~ti:r ~~o::~:~:t:r~~S not INSTRUMENTS
SN55158, SN75158
VCC------~------~~ ------VCC
INPUT
9 flNOM
OUTPUT
GND---~----------~--
III
r- - - . - . - - - GND
:r
CD
...c
<' Supply voltage, VCC . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
...
CD
C/I
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Jj D package ............... ,........................................... 725 mW
CD JG package (alloy mount), SN55158 ..................................... 1050 mW
(')
CD JG package (glass mount), SN75158 ..................................... 825 mW
<' P package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1000 mW
...
CD
C/I
Operating free-air temperature range: SN55158........... . . . . . . . . . . . . . .. - 55C to 125C
SN75158 ............................. ooC to 70C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package ........... 300C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package. . . . . . . .. 260C
NOTES: 1. All voltage values except differential output voltage VOD are with respect to network ground terminal. VOD is at the Y output
with respect to the Z output.
2, For operation above 25C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the JG package, SN55158
chips are alloy mounted and SN75158 chips are glass mounted. In the P package, use the 8.0-mW/oC curve for these devices.

SN55158 SN75158
UNIT
SupplV voltage, VCC ,4.5 5 5.5 4.75 5 5.25 V
4-262 TEXAS . .
INSTRUMENTS
SN55158, SN75158
electrical characteristics over operating free-air temperature range (unless otherwise noted)
SN55158 SN75158
VIK Input clamp voltage Vee = MIN. II = -12 mA -0.9 -1.5 -0.9 -1.5 V
Vee = MIN. VIL = 0.8 V.
VOH High-level output voltage 2 3.0 2.4 3.0 V
VII-l = 2 V. 10H = -40 mA
Vee ~ MIN. VIL = 0.8 V.
VIH = 2 V. 10L = 40 mA
I V ODll Differential output voltage Vee = MAX. 10 =0 3.5 2VOD2 3.5 2VOD2 V
I V OD21 Differential output voltage Vee = MIN 2 3.0 2 3.0 V
~IVODI Vee = MIN 0.02 0.4 0.02 OA V
differential output voltage
RL= 100 n.
Vee = MAX 1.9 3 1.8 3
Voe Common-mode output voltage' See Figure 1 V
Vee = MIN 1.4 3 1.5 3
~IVoel Vee = MIN or MAX 0.01 0.4 0.01 0.4 V
common-mode output voltage
IVa = 6V 0.1 100 0.1 100
10 Output current with power off Vee = 0 Iva = -0.25 V -0.1 -100 -0.1 -100 JlA ...
CJ)
C1)
Iva = -0.25 to 6 V 100 100
:::-
Input current at maximum '(jj
II Vee = MAX. VI = 5.5 V 1 1 mA o
input voltage
C1)
IIH
IlL
lOS
Short-circuit output current 1/
Vee = MAX.
Vee = MAX.
Vee = MAX
VI = 2.4 V
VI = 0.4 V
-40
-1
-90
40
-1.6
-150 -40
-1
-90
40
-1.6
-150
p.A
mA
mA
-...
a:
CJ)
C1)
Vee = MAX. Inputs grounded. :::-
ICC Supply current (both drivers) 37 50 37 50 mA '~
No load. TA = 25C
C
t For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions. . C1)
s:::::
t All typical values are at Vee = 5 V and T A = 25C except for Voe. for which Vee is as stated under test conditions.
~ i VOD I and .11 Voe 1 are the changes in magnitudes of VOD and Voe. respectively, that occur when the input is changed from a high
:::i
, In EIA Standard RS-422-A. Voe. which is the average of the two output voltages with respect to ground. is called output offset voltage. Vas.
#Only one output should be shorted at a time. and duration of the short-circuit should not exceed one second.

TEST SN55158 SN75158
PARAMETER UNIT
CONDITIONS MIN TYP MAX MIN TYP MAX
tpLH Propagation delay time. low-to-high-Ievel output See Figure 2. 16 25 16 25 ns
tPHL Propagation delay time. high-to-Iow-Ievel output Termination A 10 20 10 20 ns
tPLH Propagation delay time. low-to-high-Ievel output See Figure 2. 13 20 13 20 ns
tpHL Propagation delay time. high-to-Iow-Ievel output Termination B 9 15 9 15 ns
tTLH Transition time. low-to-high-Ievel output See Figure 2. 4 20 4 20 ns
tTHL Transition time, high-to-Iow-Ievel output Termination A 4 20 4 20 ns
See Figure 2,
Overshoot factor 10 10 %
Termination C
TEXAS -I!} 4-263

INSTRUMENTS
POST OFF:CE BOX 655012 ' OALLAS. TEXAS 75265
SN55158, SN75158
INPUT
Y OUTPUT
Z OUTPUT
r-
:r
CD
...c
y
Y--------------~
CL - 15 pF--L
(see Note Bl T
<'
...enCD
z
100 n CL - 30 pF
(see Note Bl
TERMINATION A
Z
CL - 15
(see Note Bl
TERMINATION B
*'
PFl
-=
TERMINATION C
~
CD TEST CIRCUIT
(")
CD
<'
...en
CD OVERSHOOT
-..-,1..;.0.;.;110_ _ _
0
V
100%~=~\
DIFFERENTIAL
OUTPUT 10% 10%
) O%!=~
f--
I I
I I OVERSHOOT
tTLH-+t If-tTHL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zout = 50 n, tw = 25 ns, PRR :5 10 MHz.
4-264 TEXAS ~
INSTRUMENTS
SN55158, SN75158

vs vs
6 6
No load I
t
ve6 ... 5 V
TA - 25C No load
5 5
> >, TA = 125C

VCC'" 5.5 V
~ 4
Cl
CI)
Cl
4 /
~ S
'0 '0 "i
VCC = 5 V
> 3 > 3
; Vee c 4.5 V 5c.
III
c.
; 5 \ T f ' " roc
~ 2 ~ 2
a o TA .. -55C
> >
... III
Q)
>
"(i)
o o CJ
o 2
FIGURE 3
3 4 o 2
FIGURE 4
3 4
-...
a::
Q)
I II
Q)
>
"a:::
C
HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE Q)
vs vs c:
OUTPUT CURRENT OUTPUT CURRENT ~
5 0.4
TA = 25C TA '= 25'Oe
.I _I , ,
Vec c 5.5 V
Vee'" 5',5 ~ ~
---
4
>,
CI)
Cl
S 3
--- --- I
~
vice'" 5 V
---':'7(..,
>,
S
CI)
Cl
0.3
/
~
Ir'Vee = 4.5 V
----
'0 '0
...> r--... ~
r-...,.' ..
>
0.2
V
:I :I
E:-
:I
i)-- r-.... '\ e-
:I
a, 2 0
,
Vee'" 4.5 V \\
:I:
a \
..J
0 0.1
/V
> > /
/
V
o l\ o
o 10 20 30 40 50 60 70 80
o - 20 - 40 - 60 - 80 - 100 - 120
IOL -Output Current-rnA
IOH-Output Current"':"'rnA
FIGURE 5 FIGURE 6
tO ata for temperatures below oDe and above 70 De are applicable to SN55158 circuits only.
TEXAS 4-265
INSTRUMENTS
SN55158, SN75158
OUTPUT VOLTAGE PROPAGATION DELAY TIMES

vs vs
4.0 30 1
Ve~'" 5V I~\ I.
_20 m
Ve~ .. 5 V
3.5 -= See figure 2
~\
- --
.-
_40 m
\lO\-\l\OH'" _ . - ' -
.- I/)
c::
25 I--Termination A
> 3.0 I
--
I I/)
Gl
S 2.5
E 20
--
i=
"0
>5 2.0
>
CtI
a;
o
15
tpLH ~
~
-----
III
r-
S-
:::l
o
o
>
I
1.5
1.0
c::
.g
~
CtI
c.
o
a:
10
tPHI:-- ~ ~
f...--
:r
(I)
5
0.5
VoLiloL - 40 mAl
o I I I I
""I
<' o o
(I) -75 -50 -25 0 25 50 75 100 125 -75 -50 -25 0 25 50 75 100 125
""I
(f) T A - free-Air Temperature; e T A - free-Air Temperature - e
l;
(I) FIGURE 7 FIGURE 8
(')
(I)
<'
(I)
SUPPLY CURRENT
(BOTH DRIVERS)
SUPPLY CURRENT
(BOTH DRIVERS)
""I
(f)
vs vs
SUPPLY VOLTAGE FREE-AIR TEMPERATURE
80 42
No load I 1 I.
Vee" 5 V
70 - TA ... 25e Input grounded
40 Outputs open
60 oCt
oCt E
~ ~c:: 38
E
~
50
~:::l -........
~
:;
u
> 40 G~o
.;)~
"
u 36 ~
O~0 >
""-
.;)\.<;
C. C.
\"~
/'
C. .;)\.<; C.
\"~
:::l :::l
(J) 30 !/J
I I 34
u u
'"
S; 20 S;
10
V
/ 32
./ 30
2 3 4 5 6 7 8 -75 -50 -25 0 25 50 75 100 125
vee-Supply Voltage-V TA-free-Air Temperature- e
FIGURE 9 FIGURE 10
tOata for temperatures below OC and above 70C are applicable to SN55158 circuits only.
4-266 TEXAS
INSTRUMENlS
l.!1
SN55158, SN75158
SUPPLY CURRENT
(BOTH DRIVERS)
vs
FREQUENCY
100
Vee = 5 V
RL = 00
eL = 30 pF
80
E TA = 25e
~t:
IJ
~ 60
:; VV
II
u
>-
C. V
g. 40
en
I C/)
u ~
(1)
9 20 :>
'iii
(J
o
0.1 0.4 4
f - Frequency - MHz
10 40 100 -(1)
a:
C/)
~
(1)
:::-
'i:
FIGURE 11 C
(1)
E:
:.J
TEXAS
INSTRUMENTS
l.!.J 4-267
r
S'
(1)
.c'c
.
(1)
(I)
li
(1)
CO)
(1)
c'
.
(1)
(I)
4-268
SN75159
DUAL DIFFERENTIAL LINE DRIVER
D2325. JANUARY 1977 - REVISED SEPTEMBER 1986
Meets EIA Standard RS-422-A D. J, OR N PACKAGE

(TOP VIEW)
Single 5-V Supply
NC VCC
Balanced Line Operation 1Z 2Z
TTL-Compatible 1Y 2Y
1A 28
High-Impedance Output State for Party-Line 18 2A
Applications 1EN 2EN
High-Current Active-Pull-Up Outputs GND NC
Short-Circuit Protection NC-No internal connection
Dual Channels
Clamp Diodes at Inputs
description
The SN75159 dual differential line driver with three-state outputs is designed to provide all the features
of the SN751 58 line driver with the added feature of driver output controls. There is an individual control
III
...
CI)
Q)
for each driver. When the output control is low, the associated outputs are in a high-impedance state and
the outputs can neither drive nor load the bus. This permits many devices to be connected together on
>
'CD
the same transmission line for party-line applications. (J
-...
Q)
The SN75159 is characterized for operation from OC to 70 o e. a::

CI)
Q)
>
-i:
&[>
C
lEN Q)
(6)
lEN
(4)
EN
'Q (3) 1Y
(3)
c:
1A
1Z
lA
(2)
lY :::i
1B lB lZ
2EN
2Y
2A
2Z 2EN
28
(12)
2A 2Y
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and (13)
IEC Publication 617-12. 2B 22
specifications per the terms of Texas Instruments TEXAS . " 4-269
~~~~~:~~i~a{::I~~e ~!~~~~ti:r :1~o::~:~:t:~s~S not INSTRUMENTS
SN75159
WITH 3STATE OUTPUTS
INPUT B INPUT A
(141 (5.111 (4.101
VCC-.-------.--~-, r -__--.-~~~-r----~----_.~--~~,
4 kO
90 90
(3.12) (2.131
OUTPUT OUTPUT
y Z
(6.91
OUTPUT
CONTROL
(71
GND----~~------~~~~
w.,. VCC bus
4-270 TEXAS ~
INSTRUMENlS
SN75159
WITH 3STATE OUTPUTS
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Off-state voltage applied to open-collector outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 V
D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11,50 mW
NOTES: 1. All voltage values except differential output voltage VOD are with respect to the network ground terminal. VOD is at the Y
output with respect to the Z output.
2. For operation above 25C free-air temperature, derate the D package to 608 mW at 70 0 e at the rate of 7.6 mw/oe, the
J package to 656 mW at 70 0 e at the rate of 8.2 mw/oe, and the N package to 736 mW at 70 De at the rate of 9.2 mW/ De.
In the J package, SN75159 chips are glass mounted.
II
...
U)
Q)
recommended operating conditions :>
.ii)
MIN NOM MAX UNIT C,,)
Supply voltage, Vee 4.75 5 5.25 V Q)

High-level output voltage, 10H
2
0.8
-40
V
V
mA
-...
a::
U)
Q)
:>
Low-level output current, IOL 40 mA 'i:
Operating free-air temperature, T A 0 70 e C
Q)
t:
:.J
TEXAS ~ 4-271
INSTRUMENTS
SN75159
electrical characteristics over operating free-air temperature range (unless otherwise noted)
VIK Input clamp voltage Vee ~ 4.75 V, II ~ -12 mA -0.9 -1.5 V
Vee ~ 4.75 V, VIL ~ 0.8 V,
VOH High-level output voltage 2.4 3.0 V
VIH = 2 V, IOH = -40 mA
Vee = 4.75 V, VIL = 0.8 V,
VOL Low-level output voltage 0.25 0.4 V
VIH = 2 V, 10L = 40 mA
VOK Output clamp voltage Vee ~ 5.25 V, 10 = -40 mA -1.1 -1.5 V
Vo Output voltage Vee = 4.75 V to 5.25 V, 10 ~ 0 0 6 V
I V ODll Differential output voltage Vee ~ 5.25 V, 10 = 0 3.5 2VOD2 V
I V OD21 Differential output voltage Vee = 4.75 V 2 3.0 V
ehange in magnitude of
t.lVODI Vee ~ 4.75 V 0.02 0.4 V
differential output voltage ~
Vee ~ 5.25 V RL ~ loon, See Figure 1 1.8 3
III
r-
Voe
t.lVoel
eommon-mode output voltage
ehange in magnitude of
common-mode output voltage~
Vee - 4.75 V
Vee ~ 4.75 V
to 5.25 V
Vo = 6 V
1.5
0.01
0.1
3
0.4
100
V
5' 10 Output current with power off Vee ~ 0 Va = -0.25 V -0.1 -100 p.A
CD
..<'
C
Va
TA
=
=
-0.25 V to 6 V
25 De, Va ~ 0 to Vee
100
10
..
CD
(I)
10Z
Off-state (high impedance-
state) output current
Vee ~ 5.25 V,
Output controls
at 0.8 V
TA = 70 De
Va
Va
Va
~
=
~
0
0.4 V
2.4 V
-20
20
20
p.A
iCD Va = Vee 20
(') Input current at
CD II Vee ~ 5.25 V, VI = 5.5 V 1 mA
<'CD
..
IIH High-level input current Vee = 5.25 V, VI = 2.4 V 40 p.A
(I) IlL Low-level input current Vee = 5.25 V, VI ~ 0.4 V -1 -1.6 mA
lOS Short-circuit output current' Vee ~ 5.25 V -40 -90 -150 mA
VC;:C;: = 5.25 V, Inputs grounded, No load,
lee Supply current (both drivers) 47 65 mA
TA = 25e
t All typical values are at Vee ~ 5 V and T A = 25 De except for Voe, for which Vee is as stated under test conditions.
~ .11 VOD 1 and .11 Voe 1 are the changes in magnitudes of VOD and Voe, respectively, that occur when the input is changed from a high
level to a low level. .
In EIA Standard RS-422-A, Voe, which is the average of the two output voltages with respect to ground, is called output offset voltage, Vas.
, Only one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
4-272 TEXAS
INSTRUMENTS
SN75159
switching characteristics over operating free-air temperature range, Vee = 5 V (unless otherwise noted)
tpLH Propagation delay time. low-to-high-Ievel output CL = 30 pF. RL = 100 fl. See Figure 2. 16 25 ns
tpHL Propagation delay time. high-to-Iow-Ievel output Termination A 11 20 ns
tpLH Propagation delay time. low-to-high-Ievel output 13 20 ns
CL=15pF. See Figure 2. Termination B
tpHL Propagation delay time. high-to-Iow-Ievel output 9 15 ns
tTLH Transition time. low-to-high-Ievel output CL = 30 pF. RL = 100 fl. See Figure 2. 4 20 ns
tTHL Transition time. high-to-Iow-Ievel output Termination A 4 20 ns
tpZH Output enable time to high level CL = 30 pF. RL = 180 fl. See Figure 3 7 20 ns
tpZL Output enable time to low level CL = 30 pF. RL = 250 fl. See Figure 4 14 40 ns
tpHZ Output disable time from high level CL = 30 pF. RL = 180 fl. See Figure 3 10 30 ns
tPLZ Output disable time from low level CL = 30 pF. RL = 250 fl. See Figure 4 17 35 ns
Overshoot factor RL = 100 fl. See Figure 2. Terminatfon C 10 %
II tn
~
Q)
SYMBOL EQUIVALENTS
'>
DATA SHEET PARAMETER RS-422-A "Qi
CJ
Vo
!YOD11
I V OD21
~IVODI
Voa. Vob
Vo
Vt
I IVtl - IVtl I
-
a:
>
Q)
tn
~
Q)
VOC IVosl "i:

~IVocl I Vos - Vos I C
lOS Iisal. IIsbl Q)
10 Ilxa I. Ilxbl
c
::l
TEXAS
INSTRUMENlS
-1!1 4-273
SN75159
WITH 3STATE OUTPUTS
1 kfl
5V--------~~----~ ,----""1
I I
I
-I
PULSE ~--,..----V OUTPUT
1
GENERATOR ...-... --4...----=-----I.._""""'J-- - - - Z OUTPUT
(See Note AI __ .J
III v
CL - RL - 100 fl V--------l' CL
~
- 15 pF Y f
*
30 pF Z .:;;- (See Note BI RL - 100 fl
Z _______J
(See
r- Note BI
CL - 15 pF l Z
5' (See Note BI
m
TERMINATION A TERM INAnON B TERMINATION C
...
C
<'m TEST CIRCUITS
...
-
CJl
:0
m
(")
~25 ns-----+j
-+j I j+-:S5 ns ~ 1 ~:S5 ns
II
m +1- - - - - - 3 V
<'m 90% 90%
...
CJl
INPUT 1
I
1.5V 1.5V
I
1
10% 0V
OVERSHOOT
100%~=~\ .
tPLH..w----.I !+--+t-tPHL
V :- OJ 90% I~I- - - - -VOH
OUTPUT I 1.5 V 1 I 1.5 V
) O%t=~
_ _1_0_%..Jt 1 : I ""I _10_o/c_o- - VOL
Z
1 -
~tPHL
90%
\++tTLH I
1414-~1-
~tTHL
il-90-01c-o- - VOH
,-- OVERSHOOT
OUTPUT
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zout = 50 fl, PRR :s 10 MHz.
FIGURE 2. tPLH, tPHL. tTLH, tTHL. AND OVERSHOOT FACTOR
4-274 TEXAS
INSTRUMENTS
POST OFFICE BOX 656012 DALLAS. tExAs 75265
SN75159
WITH 3STATE OUTPUTS
INPUT
PULSE
GENERATORI--~----4i~-~
(See Note Al
Cl -
30 PF
T-= (See
Note Bl
I n--~--OUTPUT
I
Rl - 180 ()
I
I I
II
'--------C-l-_---I
I (See
II T 3 0 PF
-= Note Bl
1 kn L __________ --.J
I
...
C/)
(1)
5V :>
'Q)
TEST CIRCUIT (.)
-...
(1)
a:
C/)
(1)
:>
''::
INPUT 1.5 V 1.5 V C
~100 ns~ ~10;;.;,;%:...-_ C1,)
&:
~tpZH I OV
:.::i
I I _*- VOH
OUTPUT
_ _ _--J
Y,sv tPHZ~
i kJv
~VOff '" 0 V
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zout = 50 n, PRR oS 500 kHz.
B. Cl includes probe and jig capacitance.
FIGURE 3. tpZH AND tPHZ
TEXAS ~ 4-275
INSTRUMENTS
POST OFFICE sox 655012 ' OA~lAS, TEXAS 75265
SN75159
WITH 3STATE OUTPUTS
INPUT
PULSE
GENERATOR
5V
(See Note A)
CL -
-= T-= 30pF
(See
Note B)
RL - 250 fl
5V "0---41>--- OUTPUT
, kfl I
'--------Cl~---' II
III
r- 1
I
L - - - - - - - -
T-=
-
30 pF
(see
Note B)
__ J
I
I
:r
CD
C TEST CIRCUIT
""I
<'
-
CD
""I
o
:c
CD INPUT
(')
CD
<'
I
14-----'00 ns ----+t
I
.-'_O'Yc_o_ _ _ _ V
CD ~tpZL-+I I
""I I I
o I I
I I
I I
: I4-'PLZ: v
OUTPUT
\.v. l-L-"lv_
- l- vOL
VOLTAGE WAVEFORMS
NOTES: A. The pulse gener'ator has the following characteristics: Zout = 50 fl, PRR:s 500 kHz.
FIGURE 4. tpZL AND tPLZ
4276 TEXAS ~
INSTRUMENTS
SN75159
WITH 3STATE OUTPUTS

vs vs
6 6 I
No load VCC - 5 V
TA ... 25C No load
5 5
> jVCC - 5.25 V > i r T A - 70C
I I
~ 4 t/. ~ 4
~ ( ~
tt
"0 "0
>
; 3
'{
\
\ ~:l 3 ""\ ~TA
"\
P:
II
Co
; \..VCC - 5 V - 25C
o
I 2
1\ "I
:l
o
I 2
\ I
~vccl- 4.75 V '\-~TA .Iooc
o
>
o
> . til
Q)
>
"Qi
CJ
o o
-..
Q)
o 2 3 4 o 2 3' 4 a:
t il
VI-Data Input Voltage-V VI-Data Input Voltage-V
Q)
FIGURE 5 FIGURE 6 >
.i:
C
OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE Q)
vs vs t:
FREE-AIR TEMPERATURE OUTPUT CURRENT :::i
4.0 I
5 r---.----.----.---.----.--~
3.5
VCC - 5 V
I
VOH (lOH - -20 mA)_
VOH (lOH .. -40 rnA) 4 ~--~--_+----~--~--_+--~
> 3.0 >
I I
G)
CD
CI CI
~
2.5 ~ 3~-=-_....I.:::_--.:::~IL_=-..~--__+_--_+--~
"0
..
>
:l
2.0 ..
>
:l
Co
P:
:l ~ 21----+---_+----+----W---+---j
0 1.5
I I
0 ::J:
> 1.0 o
>
0.5
VOL (lOL .. 40 rnA)
o
o 25 50 75 -20 -40 -60 -80 -100 -120
T A - Free-Air Temperature - C IOH-Output Current-rnA
FIGURE 7 FIGURE 8
TEXAS 4-277
INSTRUMENTS
SN75159
WITH 3STATE OUTPUTS
SUPPLY CURRENT
LOW-LEVEL OUTPUT VOLTAGE (BOTH DRIVERS)
vs vs
OUTPUT CURRENT SUPPLY VOLTAGE
0.6 80
I No1load I
TA - 25 De
0.5 ~ 70 r- TA - 25 De
> Vee - 4.75 ~ {/

E 60
~
I
8, 0.4 2-c:: l>~ ~
!9 ~ 50 ~
~..o 0~
~
~
"0 :; ~~ ... oq
lIIi
(.J
0.3 40 ,~q ~...~
# V
>
Vee - 5.25 V C.
Co
;;- ,~q
::l 30
C/)
r- ....I
0.2
I ~
o / (.J
5'
CI)
>
0.1 / 9 20
/"
V 10
/
o o /
o 20 40 60 80 100 120 o 2 3 4 5 6 7 8
IOL -Output Current-rnA vee-Supply Voltage-V
FIGURE 9 FIGURE 10

(BOTH DRIVERS) (BOTH DRIVERS)
vs vs
FREE-AIR TEMPERATURE FREQUENCY
56 100
Vee - 5 V Vee - 5 V
54 Inputs grounded RL - ex>
No load eL - 30 pF
52 80
------- ----
E 50 E TA - 25C I
2- 2-c:: I
e:; 48 ~
:;
60
/
./
(.J 46 (.J
> > .......
C. C.
Co 44 Co 40
::l ::l
C/) C/)
I 42 I
(.J (.J
9 40 9 20
38
36 o
o 25 50 75 0.1 0.4 4 10 40 100.
T A -Free-Air Ternperature- DC
f-Freque.ncy-MHz
FIGURE 11 FIGURE 12
4-278 TEXAS -1.!1

INSTRUMENTS
SN75159
WITH 3STATE OUTPUTS
PROPAGATION DELAY TIMES OUTPUT ENABLE AND DISABLE TIMES

FROM DATA INPUTS vs
vs FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE 30
Vee - 5 V
c 20
Ul
--
Ul
c See Figures 3 and 4
I
~ 18 I 25
-
:::I Ul
c. tpLH Q)
.E 16 E
~
ra 14
C
- j::
Q)
:is
20
tpLZ
~
- -~
ra
E 12
~
Ul
i:3
"0
15
- tpZL
II
Ul C
10 ra
-
Q)
E tpHL Q)
tpHZ
j::
8 :is 10
r::I
>
ra
Gi
c 6 ..
C
W
:::I
tpZH
... en
c S- 5 Q)
-.g 4
Vee" 5 V
:::I
o >
ra 'iii
~ 2 eL .. 30 pF (.)
o
-...
c. Q)
o RL .. 100 n o a:
c: 0 25 50 75
o 25 50 75 en
T A - Free-Air Temperature - C Q)
T A - Free-Air Temperature - e >
FIGURE 14 'i:
FIGURE 13 C
Q)
r::::
:.:i
TEXAS -II} 4-279

INSTRUMENTS
II
r-
5'
CD
C
""I
<'
CD
""I
en
iCD
(')
CD
<'
CD
""I
en
4-280
SN75160B
OCTAL GENERALPURPOSE
INTERFACE BUS TRANSCEIVER
D2525, OCTOBER 19B5
MEETS IEEE STANDARD 488-1978 (GPIB)

a-Channel Bidirectional Transceiver
OW. J, OR N DUAL-IN-L1NE PACKAGE
Power-Up/Power-Down Protection (Glitch- (TOP VIEW)
Free)
TE Vee
o High-Speed, Low-Power Schottky Circuitry 81 01
82 02
Low-Power Dissipation ... 72 mW Max per
83 03
Channel GPI8
84 04 TERMINAL
)/0
o Fast Propagation Times ... 22 ns Max PORTS 85 05 1/0 PORTS
86 06
High-Impedance P-N-P Inputs
87 07
Receiver Hysteresis ... 650 mV Typ 88 08
GNO PE
II
Open-Collector Driver Output Option
No Loading of Bus When Device is Powered FUNCTION TABLES
..
Down (VCC = 0)
EACH DRIVER EACH RECEIVER rJ)
description INPUTS OUTPUT INPUTS OUTPUT
Q)
>
The SN75160B 8-channel general-purpose 0 TE PE B B TE PE 0 'iii
interface bus transceiver is a monolithic, high- H H H H L L X L u
speed, low-power Schottky device designed for
two-way data communications over single-
ended transmission lines. It is designed to meet
the requirements of IEEE Standard 488-1978.
L
H
X
X
H
L
X
L
X
L
zt
zt
H
X H
L X
X
H
Z
H = high level, L = low level, X = irrelevant. Z = High-impedance

-.
a::
Q)
rJ)
Q)
>
state. '':::
The transceiver features driver outputs that can C
be operated in either the passive-pullup or three- t This is the high-impedance state of a normal 3-state output
Q)
modified by the internal resistors to Vee and ground.
state mode. If Talk Enable (TE) is high, these t:
. ports have the characteristics of passive-pull up :.:J
outputs when Pullup Enable (PEl is low, and of
three-state outputs when PE is high. Taking TE
low places these ports in the high-impedance
state. The driver outputs are designed to handle
loads up to 48 milliamperes of sink current.
Output glitches during power-up and power-
down are eliminated by an internal circuit that
disables both the bus and receiver outputs. The
outputs do not load the bus when Vee = 0
volts. When combined with the SN75161 B or
SN75162B management bus transceivers, the
pair provides the complete 16-wire interface for
the IEEE 488 bus.
The SN75160B is characterized for operation
from ooe to 70 oe.
~~~~~:~~i~ai~:I~~~ ~!~~~~ti:f :llo~:~:~:t:~~S not INSTRUMENTS
SN75160B
OCTAL GENERALPURPOSE INTERFACE BUS TRANSCEIVER
TE
Bl
02 (18)
B2
B3
03 (17)
B4
B5
B6
III
04 (16)
B7
B8 TERMINAL
GPIB
05 (15)
r- t This symbol is in accordance with ANSIIIEEE Std 91-1984 and
I/O
S' lEe Publication 617- 12.
PORTS
CD 'iJ Designates 3state outputs.
06 (14)
~ Designates passive-pullup outputs .
.,C
<'.,CD (13)
CJI 07------~~~----~
~
CD
n 08 (12)
CD
<'.,CD
CJI
EaUIVALENT OF ALL CONTROL INPUTS EaUIVALENT OF ALL INPUT/OUTPUT PORTS
r----,
VCC---------.---------
9kn 10kn
NOM NOM
INPUT
L ___ _
GNO--~----~~----~-
INPUT/OUTPUT
PORT
Driver output Req = 30 n NOM

Receiver output Req = 110 n NOM
Circuit inside dashed lines is on the driver outputs only.
4-282 TEXAS.
INSTRUMENTS
pbST OFFICE BOX 655012 CALLAS. TExAS 75265
SN75160B
OCTAL GENERALPURPOSEINTERFACE BUS TRANSCEIVER
Supply voltage, VCC (see Note 1) ................ : . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 5.5 V
Low-level driver output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 mA
OW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1125 mW
J package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375 mW
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1150 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 DC to 70C
Lead temperature 1,6 mm (1/16 inch) from the case for 60 seconds: J package. . . . . . . . .. 300C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: OW or N package. . .. 260C
II
2. For operation above 25 e free-air temper.ature, derate the OW package at the rate of 9.0 mw/oe, the N package at the rate
of 9.2 mw/oe, and the J package at the rate of 11.0 mw/oe. In the J package, SN75160B chips are alloy mounted.

MIN NOM MAX UNIT ...CI)
Q)
Supply voltage, Vee 4.75 5 5.25 V :>
High-level input voltage, VIH 2 V 'iii
(.)
-...
Low-level input voltage, VIL 0.8 V Q)
High-level output current, IOH

Bus ports with pull ups active -5.2 mA c:
Terminal ports -800 p.A CI)
Bus ports 48 Q)
Terminal ports 16
mA :>
'i:
Operating free-air temperature, T A 0 70 e C
Q)
c:
:::i
TEXAS ~ 4-283
INSTRUMENTS
SN75160B
VIK Input clamp voltage II = -18 rnA -0.8 - 1.5 V
Hysteresis
Vhys Bus 0.4 0.65 V
(VT+ - VT-)
High-level Terminal 10H = - 800 p.A. TE at 0.8 V 2.7 3.5
VOH V
output voltage Bus IOH = - 5.2 rnA. PE and TE at 2 V 2.5 3.3
Low-level Terminal IOL = 16 rnA. TE at 0.8 V 0.3 0.5
VOL V
output voltage Bus IOL = 48 rnA. TE at 2 V 0.35 0.5
Input current at
II Terminal VI = 5.5 V 0.2 100 p.A
IIH . High-level input current Terminal VI = 2.7 V 0.1 20 p.A
Low-level input current Terminal VI = 0.5 V -10 -100 p.A
II:,-
IlL
Il(bus) = 0 2.5 3.0 3.7
VI/O(bus) Voltage at bus port Driver disabled V
Il(bus) = - 1 2 rnA - 1.5
VI(bus) = -1.5 V to 0.4 V -1.3
r- Vl(bus) = 0.4 V to 2.5 V 0 -3.2
(1) +2.5
VI(bus) =2.5Vt03.7V
Current into bus port Power on Driver disabled -3.2 rnA
...c 11/0(bus)
Vl(bus) = 3.7 V to 5 V 0 2.5
<' Vl(bus) = 5 V to 5.5 V 0.7 2.5
...
-
(1)
Power off VCC =0. Vl(bus) = 0 V to 2.5 V -40 p.A
tJ)
Short-circuit Terminal -15 -35 -75
:lJ lOS rnA
(1) output current Bus -25 -50 -125
o(1) Receivers low and enabled 70 90
ICC Supply current No load rnA
<' Drivers low and enabled 85 110
...
(1)
tJ)
Ci/o(bus) Bus-port capacitance
VCC = 5 V to 0 V.
f = 1 MHz
VI/O = 0 to 2 V.
30 pF
t All typical values are at VCC = 5 V. T A = 25C.
switching chara.cteristics, Vee = 5 V, eL 15 pF, TA 25e (unless otherwise noted)

PARAMETER FROM TO TEST CONDITIONS MIN TYP MAX UNIT
tpLH 14 20
low-to-high-Ievel output CL = 30 pF.
Terminal Bus ns
Propagation delay time. See Figure 1
tpHL 14 20
tpLH 10 20
Bus Terminal ns
tpHL 15 22
tpZH Output enable time to high level 25 35
tpHZ Output disable time from high level 13 22
TE Bus See Figure 3 ns
tpZL Output enable time to low level 22 35
tpLZ Output disable time from low level 22 32
TE Terminal See Figure 4 ns
ten Output pull-Up enable time 15 22
PE Bus See Figure 5 ns
tdis Output pull-up disable time 13 20
4-284 TEXAS
INSTRUMENTS
SN75160B
200n D'''", f.v \,~ ---,v

----'1~_,
tpLH~ tpHL~
~-------ov
- -VOH
I
B OUTPUT
'-------..~I-
2.2 V . I
480n 1.0V
VOH
3V
II
FIGURE 1. TERMINALTOBUS PROPAGATION DELAY TIMES
TE r ---- --l ...

(I)
Q)
>
"""' {..v \.~---"
I '0)
I 4.3V
,, --Ii" CJ
Q)
10
I
240 n
tplH~
II _------_.J-tpHl~
I'
,OH
--V
OV
-...
a:
( I)
Q)
I
3kn
o OUTPUT >
'':
I I C
I
L- _ _ _ _ _ _ JI Q)
r:
TEST CIRCUIT VOLTAGE WAVEFORMS :::i
FIGURE 2. BUSTOTERMINAL PROPAGATION DELAY TIMES
S2
::j.v 'X.~----"
tpZH~ 14- tpHZ----' 0V
B OUTPUTI I, _ - - - - - -.....2-
SI to3V I
480n
O.BV
3.5 V
BOUTPUT
SI toGNO
S2ClOSEO
FIGURE 3. TETOBUS ENABLE AND DISABLE TIMES

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR s 1 MHz, 50% duty cycle, tr :56 ns,
tf sns, Zout = 50 n. .
TEXAS ~
INSTRUMENTS
SN75160B
\._
TE INPUT~L5,"_V
tpZH~
______
r:
-,i':.
tpHZ---t
n
,...
nO<
3V
D OUTPUT I I -90% - - -VOH

51 to3V I 1.5V
52 OPEN'
OV
tpZL --i
4V
DOUTPUT
51 toGND
S2 CLOSED
II
r-
FIGURE 4. TETOTERMINAL ENABLE AND DISABLE TIMES
S'
~,~--::
CD
...C
<' >-.....~-....-~.--OUTPUT tdis~ ~
...
CD
t/)
_-------"L 900/.,- - VOH
iCD
(') VOL ~ 0.8 V
CD
<'
...
CD
t/)
FIGURE 5. PE TOBUS PULLUP ENABLE AND DISABLE TIMES

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR :5 1 MHz, 50% duty cycle, tr :5 6 ns, '
tf :5 ns, Zout = 50 n.
4-286 TEXAS . .
INSTRUMENTS
SN75160B
TERMINAL HIGHLEVEL OUTPUT VOLTAGE TERMINAL LOWLEVEL OUTPUT VOLTAGE

vs vs
HIGHLEVEL OUTPUT CURRENT LOWLEVEl OUTPUT CURRENT
4.0 0.6
I .1. /
>I
e
Q)
3.5
-..... , VCC= 5 V
TA = 25C-
l'
Q)
CI
0.5 ~TA=25C
.I. .I.
VCC = 5 V
V
/
"0
..
>
e
::I
3.0
2.5 ",'\ !!
.e
"0
>
::I
0.4
V
0
::I
2.0
::I
0 0.3 /
-~ V
-a;
"2
II
>
Q)
/
Q)
..J 1.5 ..J
~
.i:.CI ~ 0.2
:i:
I 1.0
0
..J
I / (I)
"
J: ..J a-
0 0 0.1 Cl)
> 0.5 > >
'\~ '4)
o o (J
o -5. -10 -15 -20 -25 -30 -35 -40.
IOH-Highlevel Output Current-mA
FIGURE 6
o 10 20 30 40 50
IOl-lowlevel Output Current-mA
FIGURE 7
60
-
Cl)
a:
( I)
a-
Cl)
>
'i:
TERM INAL OUTPUT VOLTAGE C
vs Cl)
I:
BUS INPUT VOLTAGE
4.0 :.J
VCC = 5 V
3.5 No load
TA = 25C
3.0
>I
Q)
CI
!! 2.5
..e
"0
>
::I
2.0
VT-
::I
VT+
0 1.5
I
0
> 1.0
0.5
o
o 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VI-Input Voltage-V
FIGURE 8
TEXAS . . 4-287
. INSTRUMENTS
SN75160B
BUS HIGH-LEVEL OUTPUT VOLTAGE BUS LOW-LEVEL OUTPUT VOLTAGE

vs vs
BUS HIGH-LEVEL OUTPUT CURRENT BUS LOW-LEVEL OUTPUT CURRENT
4 0.6
I
Vee = 5 V
VC'C = V 5
>I TA = 2SoC >I TA = 25e
/'
/
0.5
~
Cl> CI>
CI
:3 3
CI
!3 V""
~
'0
'0
>... >... 0.4 /'
::I ::I ,/'
So So
::I
o 2 '\. ::I
0
a;
0.3
V "'v
'\
1111 V
>
Cl>
..J'
/'
~'\
~ 0.2
0
r- ~
..J
I
..J
V
5 0
>
0 0.1
(1) >
.,C
<0
.,
-
(1)
til
: ll
(1)
(')
(1)
<0
o
o -10 -20 -30
""
-40
FIGURE 9
BUS OUTPUT VOLTAGE

-50 -60
o
o 10 20 30 40 50 60
IOL -Low-Level Output Current-rnA
FIGURE 10
BUS CURRENT
vs
70 80 90 100
vs
.,(1) TERMINAL INPUT VOLTAGE BUS VOLTAGE
til
4
_"
VCC = 5 V
2
No load
TA = 2Soe
3 <t
>I E
Cl>
CI
.!.c
!3 ~ -1~~~~~-+~~--~~~~~~
'0 ::I
>
... 2
CJ
II>
::I ::I
So co
0
I
::I
-k
::I
.c
0
> g
o~~~~ __~__~__~__~__~~
0.9 1.0 1.1 1.2 1.3 1.4 1.S 1.6 1.7 -1 0 2 3 4 5 6
VI-Input Voltage-V VI/O(bus)-Bus Voltage-V
FIGURE 11 FIGURE 12
4-288 TEXAS ~
INSTRUMENTS
SN75161B, SN75162B
OCTAL GENERALPURPOSE INTERFACE BUS TRANSCEIVERS
02618. OCTOBER 1980-REVISED OCTOBER 1985
MEETS IEEE STANDARD 4881978 (GPIB)

o 8Channel Bidirectional Transceiver SN75161B ... OW, J, OR N DUAL-IN-L1NE PACKAGE
(TOP VIEW)
o Power-Up/Power-Down Protection
(Glitch-Freel TE VCC
REN REN
o Designed to Implement Control Bus
IFC IFe
Interface
NDAC NDAC
GPIB
o SN75161 B Designed for Single Controller NRFD NRFD TERMINAL
I/O
DAV DAV 1/0 PORTS
o SN75162B Designed for Multi-Controllers PORTS
EOI EOI
o High-Speed, Low-Power Schottky Circuitry ATN ATN
SRO SRO
o Low-Power Dissipation ... 72 mW Max Per
GND DC
Channel
o
o
Fast Propagation Times ... 22 ns Max
High-Impedance PN-P Inputs
SN75162B ... OW DUAl-IN-L1NE PACKAGE
(TOP VIEW)
SC VCC
III
...
rJ)
o Receiver Hysteresis ... 650 mV Typ Q)
TE NC :::-
o Bus-Terminating Resistors Provided on REN REN .iii
Driver Outputs (,)
IFC IFC Q)
o No Loading of Bus When Device is Powered
Down (VCC = 0)
GPIB
1/0
PORTS
NDAC
NRFD
DAV
NDAC
NRFD
DAV
TERMINAL
I/O PORTS
-...
a:
r J)
Q)
:::-
EOI EOI
description 'a::
ATN ATN C
The SN75161 Band SN75162B eight-channel SRO SRO Q)
general-purpose interface bus transceivers are NC NC c::
monolithic, high-speed, low-power Schottky GND DC :.J
devices designed to meet the requirements of
IEEE Standard 488-1978. Each transceiver is SN75162B ... N DUAL-IN-L1NE PACKAGE
designed to provide the bus-management and (TOP VIEW)
data-transfer signals between operating units of
SC VCC
a single- or multiple-controller instrumentation
TE NC
system. When combined with the SN75160B
REN REN
octal bus transceiver, the SN751.61 B or
IFC IFC
SN75162B provides the complete 16-wire
NDAC NDAC
interface for the IEEE 488 bus. GPIB
NRFD NRFD TERMINAL
I/O
The SN75161B and SN75162B each features DAV DAV 110 PORTS
PORTS
eight driver-receiver pairs connected in a front- EOI EOI
to-back configuration to form input/output (liD) ATN ATN
ports at both the bus and terminal sides. A power SRO SRO
up/down disable circuit is included on all bus and GND DC
receiver outputs. This provides glitch-free
operation during VCC power-up and power- NC - No internal connection.
down. The direction of data through these driver-
receiver pairs is determined by the DC, TE, and
SC (on SN75162B) enable 3ignals. The SC input
on the SN75162B allows the REN and IFC
transceivers to be controlled independently.
specifications per tho terms of Texas Instruments TEXAS -I!}
~~~~~~~~i~ar~:I~lJe ~!~~~~ti~r :I~o~:~:~:t~~s~s not INSTRUMENTS
4-289
SN75161B, SN75162B
The driver outputs (GPIB 110 ports) feature active bus-terminating resistor circuits designed to provide a
high impedance to the bus when supply voltage Vee is O. The drivers are designed to handle loads up
to 48 milliamperes of sink current. Each receiver features p-n-p transistor inputs for high input impedance
and a guaranteed hysteresis of 400 millivolts for increased noise immunity. All receivers have 3-state outputs
to present a high impedance to the terminal when disabled.
The SN75161B and SN75162B are characterized for operation from ooe to 70C.
CHANNEL IDENTIFICATION TABLE.
NAME IDENTITY CLASS

DC Direction Control
TE Talk Enable Control
SC System Control (SN75162B only)
ATN Attention
III
SRQ Service Request Bus
REN Remote Enable Management
IFC Interface Clear
EOI End or Identify
DAV Data Valid
Data
NDAC Not Data Accepted
Transfer
NRFD Not Ready for Data
4290 TEXAS . .
INSTRUMENTS
SN75161B
SN75161B logic symbol t SN75161 B logic diagram (positive logic)
DC(ll) EN1/G4
TE ( 1) EN2/G5
ATN(13)
(131 (81 ATN

EOI(14) ATN
(141
EOI (]I EOI
REN~(1~9)r---~____~__~~
IFC(18)
DAV~(1~5)t---1-~__~~__~~
SRO (121 (9)
SRO II
... en
Q)
(191 (2) >
NDAC(~17~)I----I REN REN 'a;
1--------------1 0
Q)
NRFD(~1~6)t---1-____~~__~~
IFe (181 (3) IFe -...
a:
rn
Q)
t This symbol is in accordance with IEEE Std 91-1984 and lEe 'i:
>
publication 617-12. (6) C
(151
Qdesignates 3-state output, ~designates passive-pullup outputs. DAV DAV Q)
s:::
::J
(17)
NDAC (4) NDAC
(161 (51 NRFD

NRFD
TEXAS -II} 4-291

INSTRUMENTS
SN75162B
SN751628 logic symbol t SN751628 logic diagram (positive logic)
oc [13) (12) EN1/G4

TE (2) (21 EN2/G5
sc [1) (11 EN3
t---.,
TE
ATN [9)
(9) ATN
EOI
(17) [8)
EOI (15) (81
EOI
III
r
REN
IFC
[15)
SRO (13)
[10)
(10)
SRO
:r
CD
DAV [22) (3)
(31
REN (201 REN
C NDAC
<.
~
[21) [4)
-
CD (41
~ NRFD IFC (191
IFC
til
l'
CD [18) [7)
0 tThis symbol is in accordance with IEEE Std 91-1984 and lEe (161 (7)
CD DAV
<. publication 617-12.
Qdesignates 3-state output. ~designates passive-pullup outputs.
DAV
CD
~
til [20) [5)
(18) (5) NDAC
NDAC
[19) [6)
(17) (6)
NRFD NRFD
) Denotes pin numbers for DW package.

) Denotes pin numbers for N package.
4-292
TEXAS
INSTRUMENTS
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SN75161B
RECEIVE/TRANSMIT FUNCTION TABLE
CONTROLS BUS-MANAGEMENT CHANNELS DATA-TRANSFER CHANNELS
DC TE ATNt ATNt SRQ REN IFC EOI DAV NDAC NRFD
(Controlled by DC) (Controlled by TE)
H H H T
R T R R T R R
H H L ~
L L H R
L L L
T R T T
r-:r R T T
H L X R T R R R R T T
L H X T R T T T T R R
SN75162B
III
DAV NDAC NRFD

(Controlled by TE) ...
en
Q)
T R R >
0Ci)
(,)
-...
Q)
a::
en
Q)
>
0'::::
C
Q)
H = high level, L = low level, R = receive, T = transmit, X = irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the
c:
bus side to the terminal side. Data transfer is noninverting in both directions.
::::i
t ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC
and TE inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only.
TEXAS ~ 4-293
INSTRUMENTS
SN75161 B, SN75162B

EOUIVALENT OF ALL TYPICAL OF SRO: NDAC, and NRFD
CONTROL INPUTS GPIB I/O PORT
-+---r~-_---~'~----+---_r-vcc
vcc --_0------
9kn
I
I
1.7 kll
NOM
10 kll
NOM
NOM
INPUT
GND _--'-411'---_-
~--~~~---~~--~--------GND
INPUT/OUTPUT
III
PORT
~ Circuit inside dashed lines is on the driver outputs only.
L . . . - -_ _ _ _----'----~------'
TYPICAL OF ALL I/O PORTS
r- EXCEPT SRO, NDAC, and NRFD GPIB I/O PORTS
:i'
CD ~r----'------~r---~----~r-----~vcc
.C'
c
..
CD
(I)
iCD
(')
CD
..C'
CD
(I)
----~~~--~_T4---~~----4--------GND
INPUT/OUTPUT
PORT
Circuit inside dashed lines is on the driver outputs only.
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Low-level driver output current. . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 mA
Continuous total dissipation at (or below) 25 DC free-air temperature (see Note 2):
DW package (20 pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1125 mW
DW package (24 pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1350 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1375 mW
N package (20 pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150 mW
N package (22 pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 DC to 70 DC
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 DC to 150 DC
Lead temperature 1,6 mm (1/16) inch from the case for 60 seconds: J package. . . . . . . . .. 300 DC
Lead temperature 1,6 mm (1/16) inch from the case for 10 seconds: OW or N package .... 260 DC
2. For operation above 25C free-air temperature, derate the 20-pin DW package at the rate of 9.0 mW/oC, the 24-pin DW
package at the rate of 10.8 mW/oC, the 20-pin N package at the rate of 9.2 mW/oC, the 22-pin N package at the rate of
13.6 mW/oC, and the J package at the rate of 11.0 mW/oC. In the J package, SN75161 B chips are alloy mounted.
4-294 TEXAS . .
INSTRUMENlS
SN75161 B, SN75162B

MIN NOM MAX UNIT
Bus ports with 3-state outputs -5.2 mA
High-level output current, 10H
Terminal ports -800 J1.A
Bus ports 48
Low-level output current, 10L mA
Terminal ports 16
Operating free-air temperature, T A a 70 e
(unless otherwise noted) .
VIK
Vhys
VOHt
PARAMETER
Input clamp voltage
Hysteresis (VT + - VT-)
High-level
Bus
Terminal
II
10H
=
TEST CONDITIONS
-18 mA
= -800 J1.A
MIN Typt
0.4
2.7
-0.8
0.65
3.5
MAX
- 1.5
UNIT
V
V
V
II ...en
output voltage Bus 10H = -5.2 mA 2.5 3.3 Q)
Low-level Terminal 10L = 16 mA 0.3 0.5
'Q)
>
VOL V
output voltage Bus 10L = 48 mA 0.35 0.5 (.)
II
IIH
Input current at
High-level
input current
Terminal
Terminal
and
VI
VI
=
=
5.5 V
2.7 V
0.2
0.1
100
20
J1.A
J1.A
-...
a:
Q)
en
Q)
>
Low-level control 'i:
IlL VI = 0.5 V -10 -100 J1.A C
input current inputs
Q)
VI/O(bus) Voltage at bus port Driver disabled
Illbus) = 0 2.5 3.0 3.7
V r:::::
Il(bus) = -12 mA -1.5 :J
VI (bus) - -1.5 V to 0.4 V -1.3
VI (bus) = 0.4 V to 2.5 V 0 -3.2
+2.5
eurrent into bus port Power on Driver disabled
VI(bus) = 2.5Vt03.7V
-3.2 mA
11/0(bus)
VI(bus) = 3.7 V to 5 V 0 2.5
VI(bus) = 5 V to 5.5 V 0.7 2.5
Power off Vee = 0, VI(bus) = 0 V to 2.5 V -40 ItA
Short-circuit Terminal -15 -35 -75
lOS mA
output current Bus -25 -50 -125
ICC Supply current No load, TE, DC, and SC low 110 mA
Vee = 5 V to 0 V,
Ci/o(bus) Bus-port capacitance 30 pF
VI/O = 0 to 2 V, f = 1 MHz
t All typical values are at Vec = 5 V, T A = 25C.

tVOH applies for three-state outputs only.
TEXAS l./} 4-295

INSTRUMENTS
SN75161B, SN75162B
switching characteristics, V CC 5 V, CL 15 pF, TA 25C (unless otherwise noted)

TEST
PARAMETER FROM TO MIN TYP MAX UNIT
CONDITIONS
tpLH 14 20
low-to-high-Ievel output CL = 30 pF, ns
Terminal Bus
Propagation delay time, See Figure 1
tpHL 14 20
Bus
Propagation delay time, CL = 30 pF,
tpLH Terminal (SRQ, NDAC 29 35 ns
low-to-high-Ievel output See Figure 1
NRFD)
tpLH 10 20
low-to-high-Ievel output CL = 30 pF,
Bus Terminal ns
tpHL 15 22
III tpZH
tpHZ
tpZL
tpLZ
Output enable time to high level
Output disable time from high level
Output enable time to low level
Output disable time from low level
TE, DC,
or
SC
BUS
(ATTN, EOI,
REN,IFC,
and DAV)
See Figure 3
60
45
60
55
ns
tpZH Output enable time to high level 55

TE, DC,
tpHZ Output disable time from high level 50
or Terminal See Figure 4 ns
tpZL Output enable time to low level 45
SC
tpLZ Output disable time from low level 55

5V 4_3V
200 n 240n
FROM (BUS) FROM (TERMINAL)

OUTPUT UNDER-~t----"~'--TEST POINT
TEST
OUTPUT UNDER
TEST
--.----+-...-TEST POINT
l' CL = 30 pF
(See Note A) ":'
480 n
l' CL = 30 pF
(See Note A)
3kS1
r_----------.----- 3V
~I ;.~
3V
BUS
INPUT 1.5 V 1,.5 V U
INPUT
"----0 V
J , . (See Note B) :\
0v
tPHL~ tPLH-f4+/ tPHL-14-+!
BUS
------"'-I---
2.2V
VOH
TERMINAL
, _-----_;----VOH
OUTPUT OUTPUT 1.5V

VOL
FIGURE 1. TERMINAL TO-BUS FIGURE 2. BUS-TO-TERMINAL

PROPAGATION DELAY TIMES PROPAGATION DELAY TIMES
B_ The input pulse is supplied by a generator having the following characteristics: PRR ~ 1 MHz, 50% duty cycle, tr ~ 6 ns,
tf 56 ns, Zout = 5011.
4-296 TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 DALLAS. TEXAS '75265
SN75161 Br SN75162B
S1 S1
o--5V 0--4.3 V
200n 240n
OUTPUT UNDER---It_-....-_i_TEST POINT OUTPUT --41--"'---4~ TEST POINT
TEST UNDER TEST
CL = 15 pF
JIsee Note A)
480n
J CL = 15 pF
(See Note A)
3kn
--, r-------, r---- 3V --,V,--------""\ r----- 3V

CONTROL
INPUT
BUS,
--j
tPZH-+l
'i'~ ~-------JI~----OV
I
1.5 V
14-
I
it;
(See Note B)
' " 1.5 V
tPHZ--+l t+-
- - - - - VOH
CONTROL
INPUT
tpZH--..!
TERMINAL I
i\ .
15
~
I
V
__ J I '- _____ ___ J

(See Note B)
tPHZ-+!
~
' " 1.5 V
1'-- ---- OV
,.-
-- ---- VOH
II
... U)
I I I OUTPUT I I 90%
OUTPUT
S1 OPEN I 2V I
90%
0V S10PEN I 1.5V I Q)
>
'Q)
OV
tpZL --+t-+I tPLz--l..t tPZL--.j j4- tPLZ~ C
Q)
BUS
OUTPUT
I
\!1.0 V
y . : - I I .",,3.5 V
S1 C L O S E D " \'---_ _ _ _ _--J 0.5

- -V - VOL
TERMINAL
OUTPUT
S1 CLOSED
I
1.0 V
-...
a:
U)
Q)
'~
>
FIGURE 3. BUS ENABLE AND FIGURE 4. TERMINAL ENABLE C
DISABLE TIMES AND DISABLE TIMES Q)
c:
NOTES: A. CL includes probe and jig capacitance. ~
B. The input pulse is supplied by a generator having the following characteristics: PRR $ 1 MHz, 50% duty cycle, tr $ 6 ns,
tf $6 ns, Zout = 5011.
TEXAS . . 4-297
INSTRUMENTS
SN75161B, SN75162B
TERMINAL HIGHLEVEL OUTPUT VOLTAGE TERMINAL LOWLEVEL OUTPUT VOLTAGE

vs vs
HIGHLEVEL OUTPUT CURRENT LOWLEVEL OUTPUT CURRENT
4.0 0.6
Jcc =15 V Vcc = 5 V ./
l' 3.5 TA = 25C- >I TA = 25C
/
""" \. 0.5
V
CIl CIl
en en
~
'0
>
3.0
'\ , ~
'0
>... 0.4
:;
S-
::I
2.5
'\ ::I
S-
::I
./
/
o 2.0 0 0.3
/
'"'"
iii iii
III
> >
CIl
.!l 1.5 ...J
/
1:.
en ~ 0.2
~ 1.0
0
...J
I /
"
:I: ...J
0 0.1
~ 0.5 '\ >
o '\.
o -5 -10 -15 -20 -25 -30 -35 -40 10 20 30 40 50 60
IOH-HighLevel Output Current-mA IOL -LowLevel Output Current-mA
FIGURE 5 FIGURE 6
TERMINAL OUTPUT VOLTAGE

vs
BUS INPUT VOLTAGE
4.0
Vcc = 5 V
3.5 No load
TA = 25C
3.0
>I
CIl
en 2.5
19
'0
>
... 2.0
::I
S- VT- VT+
::I
0 1.5
I
0
> 1.0
0.5
o
o 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VI-Input Voltage-V
FIGURE 7
4-298 TEXAS -I.!}

INSTRUMENTS
SN75161B, SN75162B
BUS HIGH-LEVEL OUTPUT VOLTAGE BUS-LOW LEVEL OUTPUT VOLTAGE

vs vs
4 l 0.6
Vee = 5 V Vee = 5 V
>I
TA = 25e
>I TA = 25C
/'
V
~ <11
0.5
<11
Cl
~
3 ~
Cl
V
~
"0
>
"0
>
....
0.4 L
....:l :l V
So
:l
2 ~
S-
:l
0 0.3
/V
0
'\ VV
Ci
>
<11
~<11
..J
/'
II
'"
..J
J::. ~ 0:2
~
I
Cl
:z:
"\
0
..J
I
..J
V en
a..
~
0 0.1 Cl)
.0
> > :>
aa;
o o (.)
o ...:10 -20 -40 -30 -50 -60
'OH-High-Level Output Current-rnA
FIGURE 8
o 10 20 30 40 50 60 70 80 90 100
IOL - Low-Level Output Current-rnA
FIGURE 9
-
a::
ai:
Cl)
en
a..
Cl)
:>
BUS OUTPUT VOLTAGE BUS CURRENT C
vs vs Q)
TERMINAL INPUT VOLTAGE BUS VOLTAGE t:
4 :J
VC~ = 5 V
No load 2
TA = 25e
>I 3
E 0
~
<11
Cl .!.c
~
-1
'0
>.... I :;
:l
2 () -2
Co :;
:; to -3
0 .!...
0
I :; -4
.c
>
g -5
-6
o
0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 -1 0 2 3 4 5 6
VI-Input Voltage-V VI/Olbus)-Bus Voltage-V
FIGURE 10 FIGURE 11
TEXAS ~ 4-299
INSTRUMENTS
POST OFFICE BOX 655012 a DALLAS. TEXAS 75265
III
r-
5'
CI)
c...
<'
...
CI)
o
Jj
CI)
(')
CI)
<'
...
CI)
4-300
SN75163B
02611, OCTOBER 1985
8-Channel Bidirectional Transceivers DW, J, OR N DUAL-IN-liNE PACKAGE

(TOP VIEW)
Power-Up/Power-Down Protection
(Glitch-Free) TE
B1
High-Speed Low-Power Schottky Circuitry
B2 02
Low Power Dissipation ... 66 mW Max per B3 03
Channel BUS B4 04 TERMINAL
1/0 PORTS B5 05 1/0 PORTS
B6 06
Receiver Hysteresis ... 650 mV Typ B7 07
B8 08
Open-Collector Driver Output Option
GNO PE
No Loading of Bus When Device is Powered
Down (V CC = 0)
II
FUNCTION TABLES
description EACH DRIVER EACH RECEIVER

INPUTS OUTPUT INPUTS OUTPUT
The SN75163B octal general-purpose interface
bus transceiver is a monolithic, high-speed,
D
H
TE
H
PE
H
B
H
B
L
TE
L
PE
X
D
L
... tJ)
CD
low-power Schottky device. It is designed for L H H L H L X H
>
.iii
two-way data communications over single-ended H X L Z X H X Z (,)
transmission lines. The transceiver features
driver outputs that can be operated in either the
open-collector or three-state modes. If Talk
Enable (TEl is high, these outputs have the
characteristics of open-collector outputs when
L
X
state.
H
L
H = high level, L
L
X
L
Z
= low level, X = irrelevant, Z = high-impedance

-...
CD
c:
t J)
CD
>
'i:
Pullup Enable (PEl is low and of three-state C
outputs when PE is high. Taking TE low places CD
the outputs in the high-impedance state. The c:
driver outputs are designed to handle loads of
::l
up to 48 milliamperes of sink current. Each
receiver features p-n-p transistor inputs for high
input impedance and 400 millivolts of
guaranteed hysteresis for increased noise
immunity.
Output glitches during power-up and power-
down are eliminated by an internal circuit that
disables both the bus and receiver outputs. The
outputs do not load the bus when Vee ,,; 0
volts.
The SN75163B is characterized fpr operation
from ooe to 70 oe.
~~~~~:~~i~at~:I~~~ ~!~~~~ti~; ~Io~:~:~:t::s~s not
TEXAS -II; 4-301
INSTRUMENTS
POST OFFICE BOX 655012 , OALLAS, TEXAS 75265
SN75163B
TE
01 ------~~ >----~
Bl 02 (181
B2
B3 03 (171
B4
III
B5
B6 04 (161
B7
TERMINAL
B8
r 05 (151
:r
CD
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and BUS
..,c 'V Designates 3-state outputs.
~ Designates open-collector outputs. 06 (141
;2"
..,
CD
B6
Ul
(131
J:i
CD
07------~4~----_.
()
CD
<' 08 (121
..,
CD
Ul
EQUIVALENT OF ALL CONTROL INPUTS EQUIVALENT OF ALL INPUT/OUTPUT PORTS
---.------~------------------.-------~~VCC
Vcc --------.---------- Req 10kn NOM

9 kn NOM
INPUT
GND~~----~----~~--
------~--~----~--+---._----._----------GND
INPUT/OUTPUT
PORT
4-302 TEXAS -1.!1

INSTRUMENTS
SN75163B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Low-level driver output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 rnA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1125 mW
J package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375 mW
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1150 mW
Lead temperature 1,6 mm (1/16) inch from the case for 60 seconds: J package. . . . . . . . .. 300C
Lead temperature 1.6 mm (1/16 inch) from the case for 10 seconds: N package. . . . . . . . .. 260C
2. For operation above 25 e free-air temperature, derate the OW package at the rate of 9.0 mW/oe, the N package at the rate __
of 9.2 mW/oe, and the J package at the rate of 11.0 mW/oe. In the J package, SN75163B chips are alloy mounted. ~
Supply voltage, Vee

MIN
4.75
NOM
5
MAX
5.25
UNIT
V
>
-iii
-
VJ
Q)
2 V (,)
Q)
--
Bus ports with pullups active -10 mA
a:
High-level output current, IOH VJ
Terminal ports -800 p.A
Q)
Bus ports 48
mA 'i:
>
Terminal ports 16
Operating free-air temperature range, T A a 70 e
C
Q)
c:
:::i
TEXAS -I.!} 4-303

INSTRUMENTS
POST OFFICE BOX 655012 - DALLAS, TEXAS 75265
SN75163B
electrical characteristics over recommended ranges of supply voltage and operating freeair temperature
VIK Input clamp voltage 11= -18 mA -0.8 -1.5 V
Vhys Hysteresis (VT + - VT _I; Bus 0.4 0.65 V
High level Terminal 10H = - 800 p.A, TE at 0.8 V 2.7 3.5
VOH V
output voltage Bus 10H = -10 mA, PE and TE at 2 V 2.5 3.3
Low-level Terminal 10L = 16 rnA, TE at 0.8 V 0.3 0.5
VOL V
output voltage Bus 10L = 48 rnA, PE and TE at 2 V 0.4 0.5
High-level output current Vo = 5.5 V, PE at 0.8 V,
10H Bus 100 p.A
(open-collector mode) D and TE at 2 V
Off-state output current PE at 2 V, IVo = 2.7 V 20
10Z Bus p.A
(3state mode) TE at 0.8 V IVo = 0.4 V -20
Input current at
II Terminal VI = 5.5 V 0.2 100 p.A
High-level
IIH Terminal VI = 2.7 V 0.1 20 p.A
input current
r- Low-level
:i" IlL
input current
Terminal VI = 0.5 V -10 -100 p.A
CD
.cC' lOS
Short-circuit
output current
Terminal
Bus
-15
-25
-35
-50
-75
-125
mA
..
CD
t/)
ICC Supply current No load
I Receivers low and enabled
I Drivers low and enabled
VCC = 5 V or 0 V, VI/O = 0 to 2 V,
80
100
mA
l; Cilo(bus) Bus-port capacitance

f = 1 MHz
30 pF
CD
o
CD t All typical values are at VCC = 5, T A = 25C.
C'
.
CD
t/)
;Hysteresis is the difference between the positive-going input threshold voltage, VT +, and the negative-going input threshold voltage, VT _ .
switching characteristics, V CC = 5 V, CL = 15 pF, T A = 25C (unless otherwise noted)

PARAMETER FROM TO TEST CONDITIONS MIN TYP MAX UNIT
tpLH 14 20
low-tohigh-Ievel output CL = 30 pF,
Terminal Bus ns
tpHL 14 20
tpLH 10 20
low-to-high-Ievel output CL = 30 pF,
Bus Terminal ns
tpHL 15 22
tpZH Output enable time to higb level 25 35
TE Bus See Figure 3 ns
TE Terminal See Figure 4 ns
ten Output pull-up enable time 15 22
PE Terminal See Figure 5 ns
tdis Output pull-up disable time 13 20
4-304
TEXAS
INSTRUMENTS
-1!1
SN75163B
,,'"u,
.-J!'
f.'" X'~
\. ----0
---"
'
V
tpLH~ tPHL~
,----------"'\~I,
- - -V OH
B OUTPUT
I
,
2.2 V
1.0 V
V OH
3V
II
FIGURE 1. TERMINALTOBUS PROPAGATION DELAY TIMES
....
CI)
Q)
"""' f"v \: ---" >

'iii
--J:' ,. (J
240 l!
tpLH~
o OUTPUT
I, _-------~JI
tpHL~
- --V
OV
OH
-
a:
Q)
....Q)CI)
>
3kfl '':
C
Q)
c:
TEST CIRCUIT VOLTAGE WAVEFORMS ::i
FIGURE 2. BUSTOTERMINAL PROPAGATION DELAY TIMES
S2
=J'v
tpZH~ ~
\,~----'v
tpHz-.I 0V
B OUTPUTI ',-------+~
Sl to 3 V j
480n
0.8 V
tpZL
3.5 V
B OUTPUT
Sl to GND
1.0 V
S2 CLOSED
FIGURE 3. TETOBUS ENABLE AND DISABLE TIMES

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR s 1 MHz. 50% duty cycle, tr s 6 ns,
tf s ns, Zout = 50 fl.
TEXAS 4305
INSTRUMENTS
SN75163B
~.
INPUT~"",~5_V ...Jt':.
3V
52 TE ______ n nO'
240n
tpZH~
DDUTPUTI
r:
I
tpHZ---t r--
-900/,- - -VOH
51 to 3 V I 1.5 V
52 OPEN I
OV
3kn tpZL ---i 4V
DOUTPUT
51 to GND
52 CLOSED
III
r
FIGURE 4. TETOTERMINAL ENABLE AND DISABLE TIMES
5"
~,~--::
(\)
.
o
<" >---.~- ......--_+-OUTPUT
..
(\)
o
_-------~L 90%- -
tdis~ t4-
VOH
ii
(\) VOL> O.BV
(')
(\)
..<"
(\)
o TEST CIRCUIT VOLTAGE WAVEFORMS
FIGURE 5. PETOBUS PULLUP ENABLE AND DISABLE TIMES

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ~ 1 MHz, 50% duty cycle, tr ~ 6 ns,
tf ~ ns, Zout = 50 fl.
4-306 TEXAS
INSTRUMENTS
-1!1
POST OFFICE BOX aSS012 " DALLAS, TEXAS 75265
SN75163B
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE TERMINAL LOW-LEVEL OUTPUT VOLTAGE

vs vs
HIGHLEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
4.0 0.6
II .1.. .I. '/
> 3.5
............
VCC = 5 V
TA = 25C- >I VCC = 5 V /
i 0.5 ~TA=25C
V
"
<I>
Cl
3.0 ~
"0
>.... '\ "0
>.... 0.4
'-
0
:l
e-
:l
2.5
2.0
'\ 0
:l
e-
:l
0.3 /
V
V
'"'"
-;;;
II
-;;;
~ ~
...J
.,
1.5 ...J
3:0 0.2 L
J:
I
:I:
0
1.0
~
...J
0
I
...J
0.1
V ...
tn
Cl)
> 0.5 > >
'CU
o i "r'\ o
(.)
Cl)
o -5 -10 -15 -20 -25 -30 -35 -40
10H-High-Level Output Current-rnA
o 10 20 30 40 50
10L -LowLevel Output Current-rnA
60
-a:...
tn
Cl)
FIGURE 6 FIGURE 7 >
'i:
TERMINAL OUTPUT VOLTAGE
C
Cl)
vs r:::
BUS INPUT VOLTAGE :.:J
4.0
VCC = 5 V
3.5 No load
TA = 25C
3.0
>
~
5
"0
2.5
> 2.0
;
Co
; VT- VT+
0 1.5
I
0
> 1.0
0.5
o
o 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VI-Input Voltage-V
FIGURE 8
TEXAS . " 4-307

INSTRUMENTS
SN751638

vs vs
BUS HIGH-LEVEL OUTPUT CURRENT BUS LOW-LEVEL OUTPUT CURRENT
4 , 0.6
vdc = V 5
>I
VCC = 5 V
TA = 2SoC ->I TA = 2SDC
,- V
./
8.
~ 3 ~
Q)
!
O.S ------
VV
~ i\..
~...
"0
>... 0.4 1/
:s
e:s e
:s V
o 2
:s
0 0.3
V
VV
Ill~ i '"
Gi Gi
>
Q)
....I
/'
~
~ 0.2
0
r ~
....I
I
....I
V
:5"
CD
C
.,
0
>
o
""", >
0 0.1
o I
.rCD o -10 -20 -30 -40 -SO -60 o 10 20 30 40 SO 60 70 80 90 100
., IOH-High-Level Output Current-rnA IOL -Low-Level Output Current-rnA
en
iCD FIGURE 9 FIGURE 10
n
CD BUS OUTPUT VOLTAGE
<' vs
.,
CD
TERMINAL INPUT VOLTAGE
en
4'--'1---T1--~--~--~~~~--~
Vce= S V
No load
TA = 2Soe
> 3~-4---+--~--~--+-~~-+--~
I
8.
~
o
>; 2~-4---+--~--~--+-~~-+--~
e:s
9o
>
OL-~ __~__-L__~__~__L-~__~
0.9 1.0 1.1 1.2 1.3 1.4 1.S 1~6 1.7
VI-Input Voltage-V
FIGURE 11
4-308 TEXAS . .
INSTRUMENTS
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
02908. OCT08ER 1985
8-Channel Bidirectional Transceiver DW SMALL OUTLINE PACKAGE

(TOP VIEW)
Power-Up/Power-Down Protection
SC VCC
(Glitch-Free)
TE ATN+EOI
ATN + EOI (OR Function) Output to Simplify REN REN
Board Layout IFC IFC
NDAC NDAC
GPIB
Designed to Implement Control Bus NRFD NRFD TERMINAL
I/O
Interface for Multi-Controllers DAV DAV I/O PORTS
PORTS
EOI EOI
Low-Power Dissipation ... 72 mW Max Per ATN ATN
Channel SRQ SRQ
NC NC
Fast Propagation Times ... 22 ns Max
GND DC

Receiver Hysteresis ... 650 mV Typ

SC
(TOP VIEW)
II
...(/)
Bus-Terminating Resistors Provided on VCC Q)
Driver Outputs TE ATN+EOI >
REN REN 'Q)
CJ
-...
No Loading of Bus When Device is Powered IFC IFC Q)
Down (V CC = 0)
GPIB
NDAC NDAC a::
NRFD NRFD TERMINAL ( /)
I/O Q)
DAV DAV I/O PORTS
description PORTS >
EOI EOI 'a::::
The SN75164B eight-channel general-purpose ATN ATN C
interface bus transceiver is a monolithic. high- SRQ SRQ Q)
speed. low-power Schottky device designed to GND DC C
meet the requirements of IEEE Standard :::l
488-1978. Each transceiver is designed to NC-No internal connection.
provide the bus-management and data-transfer
signals between operating units of a multiple- CHANNEL IDENTIFICATION TABLE
controller instrumentation system. When
NAME IDENTITY CLASS
combined with the SN75160B octal bus
DC Direction Control
transceiver. the SN75164B provides the TE Talk Enable Control
complete 16-wire interface for the IEEE 488 bus. SC System Control
ATN Attention
The SN75164B features eight driver-receiver
SRQ Service Request Bus
pairs connected in a front-to-back configuration REN Remote Enable Management
to form input/output (110) ports at both the bus IFC Interface Clear
and terminal sides. All outputs are disabled (at EOI End or Identify
a high-impedance state) during Vee power-up ATN+EOI ATN logical OR EOI Logic
and power-down transitions for glitch-free DAV Data Valid
Data
operation. The direction of data flow through NDAC Not Data Accepted
Transfer
these driver-receiver pairs is determined by the NRFD Not Ready for Data
De. TE. and se enable signals. The SN75164B

is identical to the SN75162B with the addition
of an OR gate to help simplify board layouts in
several popular applications. The ATN and EOI
signals are ORed to pin 21. which is a standard
totem-pole output.
specifications per the terms of Texas Instruments TEXAS -II} 4-309
~~~~~:~~i~ar::1~7.; ~!~~:~ti~; lI~o~:~:~:t::s~s not INSTRUMENTS
SN75164B
The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a
high impedance to the bus when supply voltage VCC is O. The drivers are designed to handle loads up
to 48 milliamperes of sink current. Each receiver features p-n-p transistor inputs for high input impedance
and a guaranteed hysteresis of 400 millivolts for increased noise immunity. All receivers have 3-state outputs
to present a high impedance to the terminal when disabled.
The SN-/5164B is manufactured in a 22-pin dual-in-line and 24-pin Small Outline package. The SN75164B
is characterized for operation from 0 DC to 70 DC.
DC [13)(12) EN1/G4
TE [2) (2) EN2/G5
Sc[1)(1)
III
r-
5'
[9)
(9) ATN
CD
...
C
<'
...en
CD (23)
(21) ATN+EOI
iCD [17) [8]

(") (8) EOI
EOI (15)
CD
<'
...
CD
en (15] [10]
SRQ (13) (10) SRQ
(22] [3]
REN (20) (3) REN

lEG Publication 617-12. (21] [4]
IFC (19) (4) IFC
[181 [71
DAV (16) (7) DAV
[20] [5]
NDAC (18) (5) NDAC
[191 [6]
NRFO(17) (6) NRFD
[ ) Denotes pin numbers for OW package.

( ) Denotes pin numbers for N package.
4-310
TEXAS . .
INSTRUMENTS
SN75164B
H ~ high level. L = low level. R = receive. T = transmit. X = irrelevant

Direction of data transmission is from the terminal side to the bus side. and the direction of data receiving is from the
bus side to the terminal side. Data transfer is noninverting in both directions.
t ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC II
-
and TE Inputs arc in the same state. When DC and TE are in opposite states. the ATN channel functions as an independent transceiver only.
en
Q)
ATN+EOI FUNCTION TABLE :>
'Q)
INPUTS OUTPUT CJ
--
ATN EOI ATN+EOI Q)
H X H
a:
X H H en
L L L Q)
:>
'':
C
Q)
c::
:.:::i
TEXAS -I!} 4-311

INSTRUMENTS
SN75164B
EQUIVALENT OF ALL TYPICAL OF SRQ, NDAC, and NRFD

CONTROL INPUTS GPIB 1/0 PORT
~---~-~~--~----~~vcc
vcc - - - - . , - - - - -
9kn 1.7 k!! 10 k!!
NOM NOM NOM
INPUT
GND ~----41'"__ _ _-
~--~~L~_~_-_-_~J~~--~--------GND
III
~
r-
S"
1-------+---------1
TYPICAL OF ALL 1/0 PORTS
EXCEPT SRQ, NDAC, and NRFD GPIB 1/0 PORTS
INPUT/OUTPUT'
PORT
Circuit inside dashed lines is on GPIB 1/0 ports only.
ATN+EOIOUTPUT
~~---------~vcc
CD
.<"
C
.
CD
C/I
iCD OUTPUT
(')
CD
<"CD
.
C/I
----~~~--~r+~--~~~-+-------GND
INPUT/OUTPUT
PORT
Driver output Req = 30 [} NOM -----~--~~GND
Receiver output Req = 110 [} NOM
Circuit inside dashed lines is on GPIB 1/0 ports only.
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " 5.5 V
Low-level driver output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 mA
OW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1350 mW
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 700 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooC to 70C
Lead temperature 1,6 mm (1/16) inch from the case for 10 seconds: OW or N package .... 260C
2. For operation above 25C free-air temperature, derate the OW package at the rate of 10.B mWloC, the N package at the
rate of 13.6 mW/oC.
4-312 TEXAS -Ij}

INSTRUMENTS
SN75164B

MIN NOM MAX UNIT
Supply voltage, Vee1 4.75 5 5.25 V
Bus ports with 3-state outputs -5_2 mA
High-level output current, 10H Terminal ports -800
p.A
ATN+EOI -400
Bus ports' 48
Low-level output current, 10L Terminal ports 16 mA
ATN+EOI 4
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature _ _
(unless otherwise noted) __
VIK
Vhys
Input clamp voltage
Hysteresis (VT + - VT - ) Bus
11= -18 mA
0.4
-1.5 V
V
...
t/)
Q)
Terminal 10H = -800 p.A 2.7 >
'CD
VOH~ High-level output voltage Bus IOH = -5.2 mA 2.5 V (J
-...
Q)
ATN+EOI IOH = -400 p.A 2.7
Terminal 10L = 16 mA 0.5
a:
t /)
VOL Low-level output voltage Bus 10L = 48 mA 0.5 V
Q)
ATN+EOI 10L = 4 mA 0.4
''::
>
Input current at Terminal 9 VI = 5.5 V 100
II p.A C
maximum input voltage ATN, EOI VI = 5.5 V 200
Terminal, Q)
VI = 2.7 V 20 c:
High-level input current control p.A
IIH
~
ATN, EOI VI = 2.7 V 40
Terminal,
VI = 0.5 V -100
IlL Low-level input current control p.A
ATN, EOI VI = 0.5 V -500
Il(bus) = 0 2.5 3.7

VI/O(bus) Voltage at bus port Driver disabled V
Il(bus) = -12 mA -1.5
Vl(bus) = -1.5 V to 0.4 V -1.3
Vl(bus) = 0.4 V to 2.5 V 0 -3.2
+2.5
IIIO(bus) Current into bus port Power on Driver disabled VI(bus) = 2.5Vt03.7V mA
-3.2
Vl(bus) =3.7Vt05V 0 2.5
Vl(bus) = 5 V to 5.5 V 0.7 2.5
Power off Vee = 0, VI(bus) = 0 V to 2.5 V -40 p.A
Terminal -15 -75
lOS Short-circuit output current Bus -25 -125 mA
ATN+EOI -10 -100
lee Supply current No load, TE, De, and se low 120 mA
Vee = 5 V to 0 V,
ei/o(bus) Bus-port capacitance 30 pF
VI/O = 0 to 2 V, f = 1 MHz
t All typical values are at Vee = 5 V, TA = 25e.

*VOH applies for three-state outputs only.
Except ATN and EOI terminal pins.
TEXAS . . 4-313
INSTRUMENTS
SN75164B
switching characteristics, Vee 5 V, eL == 15 pF, T A == 25e (unless otherwise noted)

TEST
PARAMETER FROM TO MIN TYP MAX UNIT
CONDITIONS
tpLH 14 20
low-to-high-Ievel output CL = 30 pF. ns
Terminal Bus
tpHL 14 20
Bus
Propagation delay time, CL = 30 pF,
tpLH Terminal (SRQ, NDAC 29 35 ns
low-to-high-Ievel output See Figure 1
NRFD)
Propagation delay time
tpLH 10 20
Bus Terminal ns
tpHL 15 22
III tpLH

Terminal ATN
or
Terminal EOI
Terminal ATN
ATN+EOI See Figure 3 14 ns
tpHL or ATN+EOI See Figure 3 14 ns

Terminal EOI
tpZH Output enable time to high level BUS 60
TE, DC.
tpHZ Output disable time from high level (ATTN. EOI. 45
or See Figure 4 ns
tpZL Output enable time to low level REN.IFC. 60
SC
tpLZ Output disable time from low level and DAV) 55
tpZH Output enable time to high level 55
TE. DC.
tpHZ Output disable time from high level 50
or Terminal See Figure 5 ns
tpZL Output enable time to low level 45
SC
tpLZ Output disable time from low level 55
4-314 TEXAS
INSTRUMENTS
-1!1
POST OFFice BOX 655012 DALLAS. TexAs 75265
SN75164B

5V 4.3V
20051 24051

OUTPUT UNDER-~""'---4~~.......-TEST POINT OUTPUT UNDER - .....- - - - - - 4......-4I...-TEST POINT
TEST TEST
J CL = 30 pF
(See Note A) -=
48051
J CL = 30 pF
(See Note A)
3k51

_------,.- - ---3V
TERMINAL
INPUT 1.5V 1.5V
BUS
-L...5V \-1 ;:~ - -'oVv
(See Note B) ----0 V
INPUT
--I: . (See Note B) .
tPHL~ tPL H -f4+I tpH L--J4--+I
BUS ------"'-I---
2.2V
VOH
TERMINAL
I_-----_-t---VOH CI)
~
1.5 V 1.5 V Q)
OUTPUT OUTPUT
>
VOH 'Q)
(.)
-
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS Q)
c:
FIGURE 1. TERMINAL TOBUS FIGURE 2. BUSTOTERMINAl CI)
~
PROPAGATION DELAY TIMES PROPAGATION DELAY TIMES Q)
>
.~
TEST
POINT VCC C
(l)
c::
2k51 :J
FROM
ATN+EOI
CL VOLTAGE WAVEFORMS
(See Note C)
I'S".O""
LOAD CIRCUIT
FIGURE 3. ATN+EOI PROPAGATION DELAY TIMES

B. The input pulse is supplied by a generator having the following characteristics: PRR :s 1 MHz, 50% duty cycle, tr :s 6 ns,
tf s6 ns, Zout = 5011.
C. All diodes are 1 N916 or 1 N3064.
TEXAS ~ 4-315
INSTRUMENTS
SN75164B

S1
0--4.3 V
200n 240n
FROM (BUSI FROM (TERMINALI
OUTPUT UNDER ~""-"'---4f-- TEST POINT OUTPUT - - - 4 t - - - -.....- - -....-TEST POINT
TEST UNDER TEST
CL ~ 15 pF
J(see Note AI-=-
480 n CL = 15 pF
ISee Note AI J 3kn
--""'\ r------- """"'\ r- - - -- 3V --,V,--------"\ r----- 3V
III
r-
5'
CONTROL
BUS
~15 V
I
I
'1"
INPUT __ ..J '- _______
tpZH-+I
(See Note BI
14-
I
~15V
JI'-. ____ OV
tpHZ--.I
I
j4-
---- - VOH
CONTROL
INPUT
OUTPUT
__ J j1\'
tPZH-.!
TERMINAL I
I
15V
I
_____ J Ii'
(See Note BI
I '- ___
r--
1.5 V
tPHZ-.(
~
1 ' - - - ___ OV
I
j4-
-- - ---
90%
VOH
CD
OUTPUT
S10PEN I
I
2V
I
90%
0V
S10PEN I 1.5V I
..<'
C
BUS
tpZL~
I
tPLZ~
y . : - I I .. 3.5 V
tPZL-.! I'-
I
tpLZ---! 14-
I
OV
... 4V
..
TERMINAL I
OUTPUT \!1.0 V OUTPUT 1.0 V I
CD
0.7 V
tn
S1 C L O S E D " \' - - _ _ _ _ _- . J 0.5
- -V - VOL S1 CLOSED
'---------1'..----- VOL
iCD VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
(')
CD FIGURE 4. BUS ENABLE AND FIGURE 5. TERMINAL ENABLE
<'
..
CD
tn
DISABLE TIMES
AND DISABLE TIMES
B. The input pulse is supplied by a generator having the following characteristics: PRR :5 1 MHz, 50% duty cycle, tr :56 ns,
tf :5 6 ns, Zout = 50 O.
4-316 TEXAS
INSTRUMENTS
SN75164B
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE TERMINAL LOW-LEVEL OUTPUT VOLTAGE

vs vs
HIGHLEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
4.0 0.6
It /'
>
~
3.5
...........
VCC = 5 V
TA = 25C- >I Jcc=5V
0.5 t------ T A = 25C
1
/
r\.
V
C) CI>
C)
~ 3.0 ~
'0
> '-r\. '0
>... 0.4
:;
e-
:l
0
2.5
2.0
'\ :l
C.
:;
0 0.3 L
V
V
"'"
~CI>
..J
1:.
C)
:I:
I
1.5
1.0
~CI>
..J
~
0
..J
I
0.2
V
/ II
. tn
>
::t:
0
0.5
r\. '\
..J
0
>
0.1 (1)
:>
"(jj
o ~ o
(,)
(1)
o -5 -10 -15 -20 -25 -30 -35 -40
FIGURE 6
o 10 20 30 40 50
IOL -Low-Level Output Current-rnA
FIGURE 7
60
-.
a:
tn
(1)
:>
".::
TERMINAL OUTPUT VOLTAGE C
(1)
vs c
BUS INPUT VOLTAGE :,:j
4.0
VCC = V 5
3.5 No load
TA = 25C
3.0
>
~
C)
~
2.5
'0
>... 2.0
:l
e-
:l
VT- VT+
0 1.5
I
0
> 1.0
0.5
o
o 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VI-Input Voltage-V
FIGURE 8
TEXAS 4-317
INSTRUMENTS
SN75164B

vs vs
4 0.6
I Ve'e = V 5
VCC = 5 V
TA = 25C >I
O.S
TA = 2Soe V
./
"~
II)
01
~ V
'0
>... 0.4 L
::l
S- V
I\. 0
::l
0.3
LV
V
"\ Qj
>
II)
...J
./
V
~'\
3:0 0.2
...J
I
...J
0
V
~
0.1
>
o
-10 -20 -30 -40 -50 -60 o 10 20 30 40 SO 60 70 80 90 100
IOH-HighLevel Output Current-mA IOL -Low-Level Output Current-mA
FIGURE 9 FIGURE 10
BUS OUTPUT VOLTAGE BUS CURRENT

vs vs
TERMINAL INPUT VOLTAGE BUS VOLTAGE
4 I I
Vee = 5 V
No load
TA = 2Soe
3

>I E
II) .!.r: 0
01
~ ~ -1
'0 :;
>... 2
u
::l
en
::l
-2
S-
::l
a:l
I
0 :;
I ~
0 -4
> Q
o
. 0.9 1.0 1.1 1.2 1.3 1.4 1.S 1.6 1.7
VI-Input Voltage-V VI/O(bus)-Bus Voltage-V
FIGURE 11 FIGURE 12
4-318 TEXAS ~
INSTRUMENTS
SN75172
02596, OCTOBER 1980-REVISED SEPTEMBER 1986
Meets EIA Standards RS-422-A and RS-485 J OR N DUAL-IN-LiNE PACKAGE

(TOP VIEW)
Meets CCITT Recommendations V. 11 and
X.27 1A Vee
1Y 4A
Designed for Multipoint Transmission on 1Z 4Y
Long Bus Lines in Noisy Environments ENABLE G 4Z
3-State Outputs 2Z ENABLE G
2Y 3Z
o Common-Mode Output Voltage Range of 2A 3Y
-7 V to 12 V GND 3A
Active-High and Active-Low Enables
Thermal Shutdown Protection
Positive- and Negative-Current Limiting

o
Operates from Single 5-V Supply
Low Power Requirements
II
...
en
Functionally Interchangeable with Q)
AM26LS31 >
'Qi
(J
description
-...
Q)
CC
The SN75172 is a monolithic quadruple differential line driver with three-state outputs. It is designed to en
meet the requirements of EIA Standards RS-422-A and RS-485 and eelTT Recommendations V.11 and Q)
X.27. The device is optimized for balanced multipoint bus transmission at rates of up to 4 megabaud. >
'i:
Each driver features wide positive and negative common-mode output voltage ranges making it suitable
C
for party-line applications in noisy environments. Q)
The SN75172 provides positive- and negative-current limiting and thermal shutdown for protection from
c:
line fault coriditions on the transmission bus line. Shutdown occurs at a junction temperature of
:.J
approximately 150 oe. This device offers optimum performance when used with the SN75173 or SN75175
quadruple differential line receivers.
The SN75172 is characterized for operation from ooe to 70 oe.
logic symbol t FUNCTION TABLE (EACH DRIVER)
INPUT ENABLES OUTPUTS

A G G Y Z
G (4) EN H H X H L
G L H X l H
H X l H l
1Y l X l l H
1Z X l H Z Z
H = high level, l = low level

2Y
2A X = irrelevant, Z = high impedance (off)
2Z
3'(
3A
3Z
4Y
4A
4Z
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and'

lEe Publication 61 7 -12.
specifications per the terms of Texas Instruments . TEXAS. 4-319
~~~~~:~~i~a{~:,~1e ~~~g~~tigr f1~o~:~:~:t:r~~s not INSTRUMENTS
POST OFfiCE BOX 655012 ' OALLAS. TEXAS 75265
SN75172

G 141
G 1121
121
1V
1A 111
131
1Z
161
2V
2A 171
151
2Z
(10)
3V
3A -.,;...19..;.,1_ _ _--1
1111
III
3Z
1141
4V
4A ....;..11_5.;".1_ _ _-I
1131
r- 4Z
:i"
CD
...c EQUIVALENT OF EACH INPUT TVPICAL OF ALL OUTPUTS
<"
...oCD Vce - - - - - - -....- - - --------~-----Vee
li
CD - - - - ___---I
()
CD INPUT --._--11---4
<"CD OUTPUT
...
o
-- - - - -....--~...-..--- GND
Data inputs: Req - 3 kO NOM
Enable ~nputs: Req - 8 kO NOM
4-320 TEXAS ~
INSTRUMENTS
POST OFFICE BOX B55012 DALLAS. TEXAS 75265
SN75172
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, Vcc ........................................................ , 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '. . .. 5.5 V
Continuous total dissipation at (or below)
25C free-air temperature (see Note 2): J package . . . . . . . . . . . . .. . . . . . . . . . . . .. 1375 mW
N package .................. ' ....... " 1150 mW
Operating free-air temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooC to 70C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,. - 65C to 150C
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. For operation above 25C freeair temperature, derate the J package to 880 mW at 70C at the rate of 11.0 mw/oe and
the N package to 736 mW at 70C at the rate of 9.2 mW/oe. In the J package, SN75172 chips are alloy mounted.
Supply voltage, Vee

MIN
4.75
NOM
5
MAX
5.25
UNIT
V
III
...tn
Highlevel input voltage, VIH 2 V Q)
Low-level input voltage, VIL 0.8

:>
V '0)
Common-mode output voltage, Voe -7 to 12 V (.)
-...
Q)
High-level output current, IOH -60
Low-level output current, IOL 60
mA
rnA
a::
tn
Operating free-air temperature, T A 0 70 e Q)
:>
'':::;
C
Q)
r:::
:.:J
TEXAS -I!} 4-321

INSTRUMENTS
SN75172
(unless otherwise noted) .
VIK Input clamp voltage 11=-18mA -1.5 V
Vo Output voltage 10 = 0 0 6 V
IV OD11 Differential output voltage 10 = 0 1.5 6 V
Y, VOD1
RL = 100 n. See Figure 1
I V OD21 Differential output voltage 2 V
RL = 54 n. See Figure 1 1.5 2.5 5 V
VOD3 Differential output voltage See Note 3 1.5 5 V
AIVODI 0.2 V
differential output voltage t
+3
VOC Common-mode output voltage RL = 54 n or 100 n. See Figure 1
-1
V
III
r-
AIVocl
10
10Z
common-mode output voltage t
Output current with power off
High-impedance-state output current
VCC = o.
VO=-7Vt012V
Va = -7 V to 12 V
0.2
100
.100
V
p.A
p.A
S' IIH High-level input current VI = 2.7 V 20 p.A
CD
IlL Low-level input current VI = 0.5 V -360 p.A
...o Va = -7 V -180
<' lOS Short-circuit output current Va = Vcc 180 mA

...rn
CD Va = 12 V
I Outputs enabled 38
500
60
iCD ICC Supply current (all drivers) No load
I Outputs disabled 18 40
mA
g t All typical values are at VCC = 5 V and T A = 25C.

<'
CD
t AIVODI and AIVoci are the changes in magnitude of VOD and VOC. respectively. that occur when the input is changed from a high
C;; In EIA Standard RS-422-A. Voc. which is the average of the two output voltages with respect to ground. is called output offset voltage. Vas.
NOTE 3: See EIA Standard RS-485 Figure 3-5. Test Termination Measurement 2.
SYMBOL EQUIVALENTS
DATA SHEET PARAMETER RS-422-A RS-485

Va Voa. Vab Voa. Vab
IVODil Vo Vo
I V OD21 V t (RL = 100 m V t (RL = 54 m
Vt (Test Termination
I V OD31 Measurement 2)
AIVODI I IVtl-IVtl I I IVtl-IVtl I
VOC IVasl IVasl
AIVocl I Vos - Vos I I Vos - Vos I
lOS lisal. Ilsbl
10 Ilxal. Ilxbl lia. lib
4-322
TEXAS . .
INSTRUMENlS
POST OFFICE sox 655012 ' DALLAS. TEXAS 75265
SN75172

PARAMETER TEST CONDITIONS MIN TVP MAX UNIT
too Differential-output delay time 45 65 ns
RL = 54 fl, See Figure 2
tTD Differential-output transition time 80 120 ns
tpZH Output enable time to high level RL = 110 fl, See Figure 3 80 120 ns
tpZL Output enable time to low level RL = 110 fl, See Figure 4 45 80 ns
tpHZ Output disable time from high level RL - 110 fI, See Figure 3 78 115 ns
tpLZ Output disable time from low level RL - 110 fl, See Figure 4 1.8 30 ns
III
...en
Q)
>
'CD
(.)
'NPUT /.'.'V . \;.-;: 3V

-...
a::
Q)
en
Q)
>
I : OV "t:
: I C
GENERATOR
too ~ k-t+- too Q)
50 n I I :
(See Note AI I T- "'2.5 V
OUTPUT 50%
::J
3V
"'-2.5 V
"tTD
TEST CIRCUIT VOL TAGE WAVEFORMS
FIGURE 2. DRIVER DIFFERENTIAL-OUTPUT DELAY AND TRANSITION TIMES
NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr oS 5 ns, tf oS 5 ns, PRR oS 1 MHz, duty
cycle = 50%. Zo = 50 fl.
TEXAS ~ 4-323
INSTRUMENTS
SN75172
INPUT ~~5~- 3V
S1
:....!1 .. ~. ~OV
o V or 3 V -1----1 OUTPUT ~ tpZH I ,0 5 V
I I - ~- ~OH
OUTPUT
2.3 V
I l"l-
GENERATOR 50 n I RL - 110 II
I
I
I
I
Vff"'OV
p~
(SEE NOTE Al 0
- - - - J CL - 50 ~ I4-tPHZ
(SEE NOTE Bl
3V
-= (SEE NOTE Cl -
III
FIGURE 3. tPZH AND tPHZ
5V
.NPU'-.t5V \-.;- - 3V
RL - 110 II
S1 I I 0V
o V or 3 V-+----4 OUTPUT ~tPZL I
I I4---+t- tpLZ
GENERATOR
(SEE NOTE Al
-=
50 II
3V
IL - -
(SEE NOTE Cl
CL - 50 pF
I
--J(SEE NOTE Bl 1-=
OUTPU-T--~~3V k:
'------' f - VOL
5V
FIGURE 4. tpZL AND tpLZ
NOTES: A. The input pulse is supplied by a generator having the following characteristics: tt :5 5 ns, tf :5 5 ns, PRR :5 1 MHz, duty
cycle = 50%, Zout = 50 n.
B. CL include probe and jig capacitance.
C. To test the activelow enable G, ground G and apply an inverted waveform to G.
4-324 TEXAS
INSTRUMENTS
"'!1
SN75172

vs vs
5 5
I
VCC'" 5 V_
> 4.5 > 4.5 I
TA a 25C
---
I I I- VCC .. 5 V
~ 4 ~ 4
TA .= 25C
!S
g 3.5 r-.... co
-a 3.5 I
~
~, >
I
3 ~ 3
:i ...............
:i I
02.5
Qj
~
...I
J::.
2 ""
\
02.5
Qj
~
-I
2
II
III
~ J
--
.~ 1.5 1.5
:I:
:ko 1
-I
~ 1
~
~
...
en
Q)
o / >
> 0.5 > 0.5 'n;
CJ
-...
Q)
o o a::
o - 20 - 40 - 60 - 80 - 100 - 120 o 20 40 60 80 100 120
High-Level Output Current-rnA IOL -Low-Level Output Current-rnA
en
Q)
FIGURE 5 FIGURE 6 >
'i:
C
DIFFERENTIAL OUTPUT VOLTAGE OUTPUT CURRENT Q)
vs vs I:
OUTPUT CURRENT OUTPUT VOLTAGE :.:;
4 50
I I Ou~put 'oisabled
VCC = 5 V 40 f-TA _ 25C
~ 3.5 TA = 25C
I---
Q)
-....... 30
S
C)
3
"'-..
"0 ........... :I. 20
> "'-.. ...... l
:i 2.5
Co
~ 10
:i "':----....... ~
o 2 r--.....
..
() 0
, VCe - 0 V
t1~JCC
~
~ 1.5
1\ ::J
So
::J
o
-10
I. 5 V
U
\ I -20
i:5 o
- -30 ~
I
c
$l0.5
\\ -40
-50
o -25-20-15-10-5 0 5 10 1520 25
o 10 20 30 40 50 60 70 80 90 100
'O-Output Current-rnA YO-Output Vo.'tage-V
FIGURE 7 FIGURE 8
TEXAS . . 4-325
INSTRUMENTS
SN75172

vs vs
100 30
I I I I I I
90 I-- No Load No Load. V
Outputs Enabled 25 I-- Inputs Open /

E 70
80 I-- TA a 25 0 e

E
Output Disabled
TA .. 25e
/
/
~c: j ~c: 20
f:! 60 CII
V
:;
u 50 INPUTS ~ /
u 15
>
>
Q.
c. 40
OPEN
\ ../;'NPUTS
Q.
c.
/
::::J
II)
I
) r- GROUNDED
::::J
~ 10 /
u 30 u V
E
20
/-~ E
/
5
10 V V
o ~~ o ~
o 2 3 4 5 6 7 8 o 2 3 4 5 6 7 8
Vee-Supply Voltage-V vee-Supply Voltage-V
FIGURE 9 FIGURE 10
TYPICAL APPLICATION
1/4 SN75173 1/4 SN75174
1/4 SN75173 1/4 SN75175
1/4 SN75172 1/4 SN75173 1/4 SN75173 1/4 SN75174
NOTE A: The line length should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept
as short as possible. .
FIGURE 11
4-326
TEXAS -1./1"
INSTRUMENTS
SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVER
D2600. OCTOBER 1980-SEPTEMBER 1986
Meets EIA Standards RS-422-A, RS-423-A, D. J. OR N

and RS-485 DUAL-IN-L1NE PACKAGE
(TOP VIEW)
o Meets CCITT Recommendations V.10,
V .11, X.26, and X.27 18 Vee
1A 48
o Designed for Multipoint Bus Transmission on 1Y 4A
long Bus lines in Noisy Environments G 4Y
3-State Outputs 2Y G
2A 3Y
Common-Mode Input Voltage 28 3A
Range . . . - 12 to 12 V GND 38
Input Sensitivity ... 200 mV
logic symbol

o Input Hysteresis ... 50 mV Typ
o High Input Impedance ... 12 kn Min
G
o Operates from Single 5-Volt Supply G
o low Power Requirements
o Plug-In Replacement for AM26lS32 1A (3) 1Y
18
description 2A (5) 2Y
The SN75173 is a monolithic quadruple 28
differential line receiver with three-state outputs. 3A
(11) 3Y
It is designed to meet the requirements of EIA 38
Standards RS-422-A, RS-423-A, and RS-485 4A (13) 4Y
and several CCITT recommendations. The.
48
device is optimized for balanced multipoint bus
transmission at rates up to 10 megabits per
second. Each of the two pairs of receivers has logic diagram (positive logic)
a common active-high enable. The device
features high input impedance, input hysteresis
for increased noise immunity, and input
sensitivity of 200 millivolts over a common-
mode input voltage range of - 12 to 12 volts.
The SN75173 is designed for optimum >--+~(3-,-) 1 Y
performance when used with the. SN75172 or
SN75174 quadruple differential line drivers.
OC to 70C.
1'11) 3Y
(13) 4Y
specifications per the terms of Texas Instruments TEXAS -I/} 4-327
~~~~~:~~i~ai~~I~~e ~!~~~~tigr ~~o::~:~~t:r~~s not INSTRUMENTS
SN75173
FUNCTION TABLE (EACH RECEIVER)
DIFFERENTIAL ENABLES OUTPUT

A-B G G Y
H X H
VID ;:: 0.2 V
X L H
H X 7
-0.2 V < VIO < 0.2 V
X L 7
H X L
VIO:5 -0.2 V
X L L
X L H Z
H = high level
L = low level
X = irrelevant
7 = indeterminate
Z = high-impedance (off)

r-
S' EQUIVALENT OF A OR B INPUT EQUIVALENT OF G OR G INPUT TYPICAL OF ALL OUTPUTS
CD VCC-------.----.---
...C'
C
VCC-------.---
...en
CD 8.3 kO
NOM
16.8 kO
i; NOM
CD INPUT_IIIY---a..:.=.4_
(')
INPUT-.-....---t
CD
C'
...enCD
4-328 TEXAS
INSTRUMENTS
-1!1
SN75173
Supply voltage. Vcc (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage, A or B inputs . . . . . . . . . . . . . . . . . . . . . . . . . . ; . . . . . . . . . . . . . . . . . . . . .. 25 V
Differential input voltage (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
Enable input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Low-level output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
D Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 950 mW
J Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1150 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , OOC to 70C
Lead temperature 1.6 mm (1/16 inch) from case for 60 seconds: J package ............ 300C
2. Differential-input voltage is measured at the noninverting input with respect to the corresponding inverting input.
3. For operation above 25 De free-air temperature, derate the D package to 608 mW at 70 DC at the rate of 7.6 mW/DC, the
J package to 656 mW at 70 DC at the rate of 8.2 mW/DC, and the N package to 736 mW at 70 De at the rate of 9.2 mW/DC.
III
. f/)
In the J package, SN75173 chips are glass mounted. Q)
>
recommended operating conditions '4)
(.)
Supply voltage, VCC

Common-mode input voltage, VIC
Differential input voltage, VID
MIN
4.75
NOM
5
MAX
5.25
12
12
UNIT
V
V
V
-..
a:
Q)
f /)
Q)
>
'i:

Interface Circuits 1987

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Interface Circuits 1987

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SLYD002

Data Acquisition and Conversion, Display Drivers,

Copyright 1987, Texas Instruments Incorporated

This data book provides information on the following types of products:

Texas Instruments Incorporated

Data Acquisition Circuits

Memory Interface Circuits

Speech. Synthesis. Circuits

Appendix A Power Derating Curves

Appendix B Mechanical Data

DEVICE PAGE NO, DEVICE P.AGE NO,

II DEVICE PAGE NO. DEVICE PAGE NO.

DEVICE PAGE NO. DEVICE PAGE NO.

TEXAS -II} 1-5

Single-Slope and Dual-Slope AID Converters

DIA Converters (5 to 15 Volts)

TEXAS -I!} 1-7

~ Successive-Approximation AID Converters

t Includes access time.

Analog Switches and Multiplexers

TYPICAL VOLTAGE POWER CO

Switched-Capacitor Filter ICs

Electroluminescent Display Drivers

3 Extremely low steady state power

o Left side (SNXX551) and right side

80-V totem-pole BIDFET output structures SN65559

1 5-mA sink or source output capability

Energy recovery system compatible

to 5.5 V 15-mA sink or source output capability SN65568

LED Display Drivers

Vacuum Fluorescent Display Drivers

Serial-in. parallel-out architecture

20 Drives up to 20 lines TL5812

DC Plasma Display Drivers

180-V open drain parallel output

:::J 32 CMOS outputs FT

AC Plasma Display Drivers

1-12 TEXAS -II}

Line Receivers (Continued)

AND DIFFERENTIAL 1 SN751778 D,JG,P

General Purpose Drivers and Actuators

General Purpose Drivers and Actuators (Continuedf

55 70 300 2 NO TTL AND 28 SN55471 FK,JG 5-109

60 100 350 7 YES TTL,CMOS,PMOS INVERT 250 SN75466 D,N 1

Motor Drivers and Power Actuators

Core-Memory Sense Amplifiers

tPD - Propagation Delay Time

MOS-Memory Sense Amplifiers

tpD - Propagation Delay Time

PROCESS DESCRIPTION PACKAGE DEVICE TYPE PAGE

Data Acquisition Circuits

aBit Resolution N DUAL-IN-LiNE PACKAGE

135 ns Access Time WR

OnChip Clock Generator DGTl GND DB7 (MSB)

Designed to be Interchangeable with

functional block diagram (positive logic)

L..-_ _ _ _ _ -I l~-r;~: ~ DB4

ADe080_e ............................. ooe to 70 0 e

Operating free-air temperature, T A

electrical characteristics over recommended operating freeair temperature range, Vee 5 V,

operating characteristics over recommended operating free-air temperature, Vee = 5 V,

Total unadjusted error ADC0805

-t All typic~1 values are at T A = 25C.

PARAMETER MEASUREMENT INFORMATION

~: : (24) ADDRESS