Experiment 3

To design and simulate a 2:4 Decoder

with clock?
Source Code
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity decoder2_4 is

Port ( I : in STD_LOGIC_VECTOR (1 downto 0);

D : out STD_LOGIC_VECTOR (3 downto 0));

end decoder2_4;

architecture Behavioral of decoder2_4 is

begin

process(I)

begin

case I is

when "00"=>D<="0001";

when "01"=>D<="0010";

when "10"=>D<="0100";

when "11"=>D<="1000";
when others=>NULL;

end case;

end process;

end Behavioral;

output
When Input is 00

When Input is 01

When Input is 10

When Input is 11
Experiment 4
To design and simulate a binary to gray
code converter?
Source Code
entity B2G is

Port ( din : in STD_LOGIC_VECTOR (3 downto 0);

dout : out STD_LOGIC_VECTOR (3 downto 0));

end B2G;

architecture Behavioral of B2G is

begin

dout(3)<=din(3);

dout(2)<=din(3) xor din(2);

dout(1)<=din(2) xor din(1);

dout(0)<=din(1) xor din(0);

end Behavioral;

Output
Gray code of binary 0000 is
Gray code of binary 0010 is

Gray code of binary 0011 is