A brief view to the ECU hw

Massimo Violante
Politecnico di Torino
Dip. Automatica e Informatica
Torino, Italy
 Outline
n The reference architecture
n Processor families
 Outline
n The reference architecture
n Processor families
Reference architecture internals
ARM, PowerPC, Intel,
NOR flash

ECU

Boot Flash
CPU
RAM
Memory Mass
Memory
I/O Flash

Custom device (e.g., ADC, PWM, ) NAND flash

4
 Reference architecture internals
n CPU is connected to other components via Address,
Data, and Control buses
Address
Bus decoder
Data
enIO enMMF enBF
CPU enRAM

Boot Flash
I/O Mass
RAM Memory
Memory Flash

Read/Write*/
STB*/ACK*
5
 Outline
n The reference architecture
n Processor families
 Processor families
2 GHz
Hybrid
Performance

Microprocessor

Digital Signal Processor

1 GHz

120 MHz
Microcontroller
50 MHz

1$ 10 $ 20 $ 500 $
Cost 7
 Processor families
n Microcontroller
n Embeds SRAM/Flash/Peripherals/Real-time Clock
n Needs only oscillator and power supply
n Suitable for low-cost bill of material
n Microprocessor
n Needs external RAM/Flash
n May include peripherals and memory interface
n May require bridge (more later)

8
 Processor families
n Digital signal processor
n Same as microprocessor
n Optimize for specific applications
n Hybrid
n Microprocessor + Microcontroller
n Microprocessor + Microcontroller + DSP
n Microprocessor + FPGA
n Microprocessor + GPU

9
 Processor families

Instruction Set Market

ARM Consumer, Industrial, Automotive
AVR Consumer, Automotive
Intel x86 Consumer, Industrial, Mil & Aero
MIPS Consumer
PowerPC Automotive, Industrial, Mil &
Aero, Telecom
Sparc Consumer, Mil & Aero

10
 Microcontroller
n Embeds SRAM/Flash/Peripherals/Real-time Clock
n Needs only oscillator and power supply
n Suitable for low-cost bill of material

PCB
Power
Supply
MCU

Oscillator

11
An example

12
ST STM32F7

13
5LFKFRQQHFWLYLW\DQG+0,HQDEOHG0&8ZLWKDQWLWDPSHUFDSDEL

Kinetis
Kinetis K70
K70 Family
Family Freescale Kinetis K70
Core System Memories Clocks
Internal and Program Flash SRAM Phase-Locked
ARM Cortex-M4 External (512 KB to 1 MB) (128 KB) Loop
120/150 MHz Watchdogs
FlexMemory External Frequency-
Debug Memory (512 KB) Bus Interface Locked Loop
DSP Protection Unit
Interfaces (16 KB EE) (FlexBus)
(MPU) Low/High-
Interrupt Floating Point Serial Cache Frequency
Controller Unit (FPU) Programming Oscillators
DMA Interface
(EzPort) DDR Controller Internal
Low-Leakage Reference
Wake-Up Unit NAND Flash Clocks
Controller

Security Analog Timers Communication Interfaces HMI

and Integrity
16-bit FlexTimer I2C I2S GPIO
ADC
Cyclic
Redundancy Carrier
Check (CRC) Secure Xtrinsic
PGA Modulator Digital Host Low-Power
UART
Transmitter (ISO 7816) Controller Touch-Sensing
Random Analog (SDHC) Interface
Number Comparator Programmable
Generator Delay Block USB OTG Graphic
SPI LCD Controller
6-bit (LS/FS/HS)
Cryptographic DAC Periodic
Acceleration Interrupt USB Device
Unit (CAU) Timers CAN Charger Detect
12-bit
DAC
H/W Tamper Low-Power IEEE 1588 USB Voltage
Detection Timer Ethernet MAC Regulator
Voltage
Unit Reference
Independent
Real-Time
Clock (RTC)

IEEE 1588
Timer

STandard Feature Optional

14
7KH.0&8IDPLO\LVDKLJKO\LQWHUJUDWHG  86%FRPSOLDQW27*PRGXOHZLWKLQWHJUDWHG
*HQHUDOSXUSRVHORZSRZHUPL[HGVLJQDO0&8

KinetisK10
Kinetis K10 Family
Entry Level Baseline MCUs Freescale K10 T
7
Core System Memories Clocks
Internal and Program Flash SRAM Phase-Locked I
ARM Cortex-M4 Loop
External (32 to 128 KB) (8 or 16 KB)
50 MHz
Watchdogs Frequency-Locked
M
FlexMemory Serial Programming Loop
Debug
Interfaces
DSP DMA (Up to 32 KB) Interface (EzPort)
Low/High-Frequency
S
(2 KB EE) Oscillators
Interrupt Low-Leakage p
Controller Wake Up Unit Internal Reference
Clocks f
Security Analog Timers Communication Interfaces HMI D
and Integrity

Cyclic
16-bit ADC FlexTimer I2C I2S GPIO c
Redundancy Analog Comparators
Check (CRC) Carrier Modulator
UART
Xtrinsic
Low Power
c
Transmitter SPI
6-bit DAC (ISO 7816 + LON) Touch-Sensing
Programmable Interface Q
Voltage Reference Delay Block
Periodic Interrupt K
Timers

Low-Power
Timer
Independent
Real-Time
Clock (RTC)


Optional

7KH.0&8IDPLO\LVWKHHQWU\SRLQWLQWR Features
15
WKH.LQHWLVSRUWIROLR'HYLFHVVWDUWIURP  8SWR0+]$50&RUWH[0FRUH
2. Overview

2.1 Block Diagram

Figure 2-1. Atmel AVR

Block Diagram
MCKO
MDO[5..0] LOCAL BUS LOCAL BUS

MEMORY INTERFACE
MSEO[1..0] INTERFACE
EVTI_N
AVR32UC CPU
EVTO_N NEXUS
TCK CLASS 2+
MEMORY PROTECTION UNIT
TDO JTAG OCD 32/16 KB
TDI INTERFACE INSTR DATA SRAM
TMS
DATAOUT INTERFACE INTERFACE
RESET_N aWire

M M M S

CONTROLLER
S/M
SAU
256/128/64

FLASH
HIGH SPEED KB
BUS MATRIX S FLASH
DP USB 2.0 S
Interface M
8EP
S S
DM

CONFIGURATION REGISTERS BUS

PERIPHERAL
HSB-PB HSB-PB
DMA
BRIDGE B BRIDGE A
CONTROLLER

GENERALPURPOSE I/Os
DIS
POWER MANAGER VDIVEN
CAPACITIVE TOUCH

DMA
CSA[16:0]
CLOCK MODULE CSB[16:0]
PA SMP
PB
CONTROLLER SYNC

SLEEP USART0
CONTROLLER USART1 RXD

DMA
TXD
USART2 CLK
RESET USART3 RTS, CTS
CONTROLLER
SCK

DMA
MISO, MOSI
GCLK_IN[2..0] SPI
GCLK[9..0] NPCS[3..0]

GENERAL PURPOSE I/Os

RCSYS
RC32OUT RC32K TWCK
TWI MASTER 0

DMA
TWD PA
RC120M TWI MASTER 1 PB
SYSTEM CONTROL TWALM
XIN32
XOUT32 OSC32K INTERFACE
TWCK
XIN0
OSC0 TWI SLAVE 0

DMA
XOUT0 TWD
TWI SLAVE 1
DFLL TWALM

PLL ADP[1..0]
8-CHANNEL ADC

DMA
TRIGGER
INTERFACE AD[8..0]
ADVREFP
ISCK
IWS
INTER-IC SOUND
DMA ISDI
INTERRUPT CONTROLLER ISDO
IMCK
CONTROLLER
CLK
EXTERNAL INTERRUPT AUDIO BITSTREAM
DMA

EXTINT[5..1] DAC0, DAC1

NMI CONTROLLER DAC DACN0, DACN1

ACBP[3..0]
PWMA[35..0] PWM CONTROLLER ACBN[3..0]
AC INTERFACE ACAP[3..0]
ACAN[3..0]
ASYNCHRONOUS ACREFN
TIMER
GLUE LOGIC OUT[1..0]
WATCHDOG IN[7..0]
CONTROLLER
TIMER

FREQUENCY METER A[2..0]

TIMER/COUNTER 0
B[2..0]
TIMER/COUNTER 1 CLK[2..0]

16
Freescale MPC564xL

17
Freescale MPC5777M

18
 Microprocessor/DSP
n Needs external RAM/Flash
n May include peripherals and memory interface
n May require bridge to interface microprocessor/DSP
with external memory
PCB
Power
Supply
CPU/DSP Bridge Memory

Oscillator

19
 An example
Memory

Processor

20
 standard x8 DDR3 devices.

The SoC also features a 512 Kbyte on-die embedded SRAM (eSRAM) that can be

Intel Quark x1000

configured to overlay regions of DRAM to provide low latency access to critical portions
of system memory. For robustness, the contents of this on-die eSRAM are also ECC
protected.
Figure 1. Block Diagram

CPU Core

Clock

eSRAM
JTAG Host Bridge
DDR3
Memory
Controller

AMBA Fabric Legacy Bridge

PCIe*
USB 2.0
10/100 ETH
I2C*/GPIO

UART

HPET
GPIO
SDIO

APIC

ROM
PMC

8254
8259
RTC
SPI

SPI

I/O

I/O
I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O
21
Introduction

Intel Atom E3800

Figure 1. SoC Block Diagram

IO JTAG

OOE Intel OOE Intel OOE Intel OOE Intel

AtomTM AtomTM AtomTM AtomTM
Processor Core Processor Core Processor Core Processor Core

1MiB L2 1MiB L2

Video P-Unit

IO
3D Graphics SVID

DDI SoC

Display
IO 2
Channel

Controller
Transaction

Memory
IO
0
IO VGA Router
Channel IO
1
MIPI-CSI

Camera
IO 3

ISP
IO GPIO Integrated Clock O

IO HD Audio APIC
8259

Platform Control Unit

HPET
LPE
IO 3 I2S/PCM

ILB
8254 O

RTC IO
O 2 PWM
GPIO IO
IO 2 HSUART
SIO

LPC IO
IO SPI
PMC IO
IO 7 I2C I/O
SPI IO
Fabric
UART IO
IO 4 PCIe*
SMB IO

IO 2 SATA 3.0 (SS) IO

1/2/3
USB

1/2.0 (HS/FS) 4 IO

2.0 (HSIC) 2 IO

3.0 (SS) IO
USB
Dev

IO 3 SD/MMC ULPI (HS/FS) IO 22

Intel Core i7

23
 Freescale PowerPC 7448
2

Overview
Additional Features 128-Bit (4 Instructions)
Instruction Unit Instruction Queue Instruction MMU
Time Base Counter/Decrementer
Clock Multiplier (12-Word) SRs 128-Entry
Branch Processing Unit Fetcher
JTAG/COP Interface (Shadow) ITLB 32-Kbyte
Thermal/Power Management BTIC (128-Entry) CTR Tags
I Cache
Performance Monitor IBAT Array
Out-of-Order Issue of AltiVec Instr. BHT (2048-Entry) LR
Dispatch
Unit Data MMU
32-Kbyte
Completion Unit 96-Bit (3 Instructions) Tags
SRs 128-Entry D Cache
Completion Queue (Original) DTLB
(16-Entry) VR Issue GPR Issue FPR Issue
(4-Entry/2-Issue) (6-Entry/3-Issue) (2-Entry/1-Issue) DBAT Array
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

Reservation
Stations (2-Entry)
EA
Figure 1. MPC7448 Block Diagram

Completes up Vector
to three Touch Load/Store Unit
instructions Queue PA
per clock Reservation Reservation
Reservation Vector Touch Engine Reservation
Reservation
Stations (2) Station
Station
Station + (EA Calculation) Stations (2)
VR File GPR File FPR File

16 Rename 16 Rename Finished L1 Castout 16 Rename

Buffers Buffers Stores Buffers
Reservation Reservation Reservation Reservation Integer Integer
Integer
Integer Floating-
Station Station Station Station Unit 2 Unit
Unit
Unit122 Point Unit
(3)
L1 Push + x
x +++
Vector Vector Vector Completed FPSCR
Vector
Permute Integer Integer Stores Load Miss
FPU 32-Bit 32-Bit 32-Bit 64-Bit 64-Bit
Unit Unit 2 Unit 1
128-Bit
128-Bit

Memory Subsystem
L1 Store Queue
1-Mbyte Unified L2 Cache Controller System Bus Interface
(LSQ)
L1 Service Line Block 0 (32-Byte) Load
Block 1 (32-Byte)
Queues Tags Status Queue (11) Bus Store Queue
L1 Load Queue (LLQ) Status
Castout
Queue (5) /
L1 Load Miss (5)
Freescale Semiconductor

Push
L2 Store Queue (L2SQ) Queue (6)1
L2 Prefetch (3) L1 Castouts Snoop Push/
(4) Interventions
Instruction Fetch (2)
Bus Accumulator
Cacheable Store Miss (2)
36-Bit 64-Bit
Notes: The Castout Queue and Push Queue share resources such for a combined total of 6 entries.
The Castout Queue itself is limited to 5 entries, ensuring 1 entry will be available for a push.
Address Bus Data Bus 24
Freescale QorIQ P1010

25
Freescale P2040

26
Freescale T4240

27
Freescale i.MX6

28
www.ti.com SPRS717G OCTOBER 2011 REVISED JUNE 2014

TI AM335x
1.4 Functional Block Diagram
Figure 1-1 shows the AM335x microprocessor functional block diagram.

Graphics Display
ARM
Cortex-A8 PowerVR 24-bit LCD controller
Up to 1 GHz SGX
3D GFX Touch screen controller

Crypto PRU-ICSS
32K and 32K L1 + SED
256K L2 + ECC EtherCAT, PROFINET,
64K EtherNet/IP,
176K ROM 64K RAM shared and more
RAM

L3 and L4 interconnect

Serial System Parallel

eCAP x3
UART x6 eDMA MMC, SD and
ADC (8 channel) SDIO x3
SPI x2 Timers x8 12-bit SAR
2
I C x3 WDT GPIO
McASP x2 RTC JTAG
(4 channel)
eHRPWM x3
CAN x2 Crystal
eQEP x3 Oscillator x2
(Ver. 2 A and B)
PRCM
USB 2.0 HS Memory interface
OTG + PHY x2
mDDR(LPDDR), DDR2,
EMAC (2-port) 10M, 100M, 1G DDR3, DDR3L
IEEE 1588v2, and switch (16-bit; 200, 266, 400, 400 MHz)
(MII, RMII, RGMII) NAND and NOR (16-bit ECC)

29
Figure 1-1. AM335x Functional Block Diagram
 AM5K2E04, AM5K2E02
Multicore ARM KeyStone II System-on-Chip (SoC)
SPRS864CAugust 2014

1.6 Functional Block Diagram

TI AM5K2E04
The figures below show the functional block diagrams of the AM5K2E04/02 devices.
Figure 1-1 AM5K2E04 Functional Block Diagram
AM5K2E04
Memory Subsystem
2MB
72-Bit MSM
DDR3 EMIF SRAM
MSMC

Debug & Trace

PRODUCT PREVIEW

Boot ROM
32KB L1 32KB L1 32KB L1 32KB L1
Semaphore P-Cache D-Cache P-Cache D-Cache

Secure Mode ARM ARM

A15 A15
Power 4MB L2 Cache
Management
ARM ARM
PLL
A15 A15
3! 32KB L1 32KB L1 32KB L1 32KB L1
P-Cache D-Cache P-Cache D-Cache
EDMA
5! 4 ARM Cores @ up to 1.4 GHz

HyperLink TeraNet
Multicore Navigator
Queue Packet
Manager DMA

Network Coprocessor
3-Port 9-Port Security
Ethernet Ethernet Accelerator
2! USB 3.0

2! PCIe !2
GPIO !32

2! UART
EMIF16

3! SPI

Switch Switch
3! I2C
USIM

TSIP

Packet
Accelerator
10GBE
10GBE

10GBE

1GBE

1GBE

1GBE

1GBE

1GBE

1GBE

1GBE

1GBE
30
TMS320C6655/57
Fixed and Floating-Point Digital Signal Processor
SPRS814AAugust 2012

TI TMS320C6655/57
www.ti.com

1.3 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the device.
Figure 1-1 Functional Block Diagram

TCI6655/57
Memory Subsystem
1MB
32-Bit MSM
DDR3 EMIF SRAM
MSMC

Debug & Trace

Boot ROM
2nd core, C6657 only
Semaphore

Timers
C66x
Security /
Key Manager
CorePac
Coprocessors
Power
Management
32KB L1 32KB L1
P-Cache D-Cache TCP3d
PLL
!2 1024KB L2 Cache
VCP2 !2
EDMA
1 or 2 Cores @ up to 1.25 GHz

HyperLink TeraNet

Multicore Navigator
Queue Packet
Manager DMA
McBSP !2
UART !2

SRIO !4
PCIe !2
Ethernet
EMIF16

GPIO

UPP

SPI
I2C

MAC

SGMII

31
 Hybrid
n Microprocessor + Microcontroller
n Microprocessor + Microcontroller + DSP
n Microprocessor + FPGA/
n Microprocessor + GPU
PCB
Power
Supply
Hybrid Bridge Memory

Oscillator
32
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS866ENovember 2013

1.6 Functional Block Diagram

Figure 1-1 TI 66AK2H14

The following figures show the functional block diagrams of the devices.

Functional Block Diagram for 66AK2H14

66AK2H14
Memory Subsystem C66x
C66x
C66x
C66x
6MB C66x
C66x
C66x
C66x
CorePac
72-Bit
MSM CorePac
CorePac
CorePac
CorePac
DDR3 EMIF
SRAM CorePac
CorePac
CorePac
72-Bit 32KBL1
32KB L1 32KB
32KBL1 L1
MSMC 32KB
32KB
32KB
L1 32KB
L1
L1
P-Cache
32KBL1
32KB
L1
L1
D-Cache
DDR3 EMIF 32KB
32KB L1
P-Cache
L1
P-Cache 32KB
32KB L1
D-Cache
L1
D-Cache
32KB L1
P-Cache 32KB
P-Cache D-Cache L1
D-Cache
D-Cache
P-Cache
P-Cache D-Cache
P-Cache 1024KB D-Cache
L2Cache
Cache
1024KB
1024KB L2
L2 Cache
Debug & Trace 1024KBL2
1024KB L2Cache
Cache
1024KB
1024KB L2 L2 Cache
L2 Cache
Cache
1024KB

Boot ROM 32KB L1 32KB L1 32KB L1 32KB L1 8!

P-Cache D-Cache P-Cache D-Cache
Semaphore ARM ARM
A15 A15
Power
Management 4MB L2 Cache

ARM ARM
PLL
A15 A15
5! 32KB L1 32KB L1 32KB L1 32KB L1
P-Cache D-Cache P-Cache D-Cache
EDMA
8 C66x DSP Cores @ up to 1.2 GHz
5! 4 ARM Cores @ up to 1.4 GHz
2! HyperLink TeraNet

Multicore Navigator
Queue Packet
Manager DMA

3-Port 5-Port Security

Ethernet Ethernet Accelerator
GPIO !32

2! UART

SRIO !4

Switch
PCIe !2

Switch
USB 3.0
EMIF16

3! SPI
3! I2C

Packet
Accelerator
10GBE
10GBE

10GBE

1GBE

1GBE

1GBE

1GBE
Network
Coprocessor

33
 Zynq-7000 All Programmable SoC Overview

Xilinx Zynq 7000

Figure 1 illustrates the functional blocks of the Zynq-7000 All Programmable SoC. For more information on the functional
blocks, see UG585, Zynq-7000 AP SoC Technical Reference Manual.
X-Ref Target - Figure 1

Zynq-7000 All Programmable SoC

I/O
Processing System
Peripherals Clock Application Processor Unit
Reset SWDT
USB Generation
FPU and NEON Engine FPU and NEON Engine
2x USB TTC
USB ARM Cortex-A9 ARM Cortex-A9
MMU MMU
GigE 2x GigE System- CPU CPU
GigE 2x SD Level 32 KB 32 KB 32 KB 32 KB
SD Control I-Cache D-Cache I-Cache D-Cache
SDIO Regs
IRQ
SD GIC Snoop Controller, AWDT, Timer
SDIO
GPIO DMA 8 512 KB L2 Cache & Controller
Channel
MIO

UART
UART
CAN
OCM 256K
CAN
Interconnect SRAM
I2C
I2C Memory
SPI Central Interfaces
SPI Interconnect DDR2/3,
CoreSight DDR3L,
Memory
Interfaces Components LPDDR2
Controller
SRAM/
NOR
DAP
ONFI 1.0
NAND DevC Programmable Logic to
Q-SPI Memory Interconnect
CTRL

EMIO General-Purpose DMA IRQ Config High-Performance Ports ACP

XADC
Ports Sync AES/
12-Bit ADC Programmable Logic
SHA
SelectIO
Notes: Resources
1) Arrow direction shows control (master to slave)
2) Data flows in both directions: AXI 32-Bit/64-Bit, AXI 64-Bit, AXI 32-Bit, AHB 32-Bit, APB 32-Bit, Custom
34
DS190_01_030113
nVidia Tegra K1

35