SHELLCASE-TYPE WAFER-LEVEL PACKAGING SOLUTIONS:
RF CHARACTERIZATION AND MODELING
M. Bartek1, S. M. Sinaga1, G. Zilber2, D. Teomin2, A. Polyakov1, J. N. Burghartz1
1
Delft University of Technology, Lab. of High-Frequency Technology and Components / DIMES
Mekelweg 4, 2628 CD Delft, the Netherlands, e-mail: m.bartek@ewi.tudelft.nl
2
Shellcase Ltd, Manhat Technology Park, PO Box 48328, Jerusalem 96251, Israel
ABSTRACT
In this paper, Shellcase WLCSP technology is analyzed for
electrical performance and its potential in RF packaging. An
equivalent circuit model is developed using parameter
extraction from a physical model representing typical
package geometries (3.1 x 3.1 mm2, 48 I/Os). Analysis of
the results indicates that due to its comparably low electrical
parasitics (L = 0.3-1.1 nH), this package is suitable for low-
power RF/microwave applications. Moreover, intrinsic
flexibility of this packaging technology provides novel
opportunities for RF enhancements. As the Si substrate
when bonded to a glass carrier is mechanically stabilized, it
can be thinned or selectively removed to any extent. Full
through-substrate trenches provide an effective way of
substrate crosstalk suppression. Selective removal of lossy
silicon substrate below spiral inductors provides high
quality passives. Possibility to implement cavities makes
this package type also an attractive option for RF MEMS
applications.
Key words: wafer-level packaging, RF packaging, crosstalk
suppression, electrical modeling.
INTRODUCTION
As the demand for ever-smaller electronic systems grows,
manufacturers are seeking ways to increase IC integration
levels and to reduce the size and weight of IC packages. The
explosive expansion of mobile electronic terminals
generates strong demand for high-performance, cost-
effective and miniaturized RF modules providing desired
wireless connectivity. Ideally, they should be realized as a
single-chip solution and could easily be embedded into any
electronic system. Such System-on-Chip (SoC) RF ICs have
set a challenge for packaging, especially at the low-end
market segment where low-cost solutions are required. The
chip size package (CSP) and wafer-level packaging (WLP)
resulting from this effort, have been introduced into
manufacturing at an unprecedented rate.
The driving force behind is not only the reduced size and
weight, but primarily the fact that the wafer-level chip-scale
packaging (WLCSP) technology has potential of electrical
performance improvement at a comparable or even reduced
manufacturing cost and thus providing an improved
performance-to-price ratio. Moreover, the same processing
steps that are used to achieve the WLP technology basic
packaging goal, can also be adopted for implementation of
an additional functionality at no or very limited additional
cost. As an example, packaging of RF silicon ICs with
simultaneous integration of high-quality passives, antennas
or isolation structures [1] or protection of MEMS structures
[2] can be mentioned. The emerging WLCSP technology
and related integrated passive devices (IPDs) have proven to
have capabilities of significant size reduction at a
comparable cost and an improved electrical performance
[3], [4].
In this paper, results of our work on electrical modeling of
Shellcase-type WLP solutions that was performed in the
frame of the Blue Whale project [5], [6], are presented. Next
to that, the capabilities and added value for packaging of RF
ICs are analyzed.
SHELLCASE-TYPE WLP SOLUTIONS
The ShellCase-type WLCSP approach [7] is based on
sandwiching of a thinned silicon substrate between two
glass plates and redistribution of the electrical contacts from
the die periphery into an area-array of solder bumps on the
bottom glass plate. Adhesive bonding of glass and silicon
wafers using optical quality adhesives makes this
technology highly suitable for optical sensors. The ShellOP
package is currently the technology of choice for miniature
image sensors, e.g. VGA CMOS image sensor shown in
Fig. 1.
(a) (b)
Figure 1. A VGA CMOS image sensor packaged using
Shellcase WLP technology: (a) front side; (b) back side.
This approach is highly flexible and allows variety of
modifications as shown in Fig. 2. The silicon substrate can
be packaged with its active side up or down and the
adhesive bonding can be performed selectively allowing for
optical cavity implementation. The latest package for image
sensors is the ShellOC, a cavity type package which can,
due to its high flexibility, be used for (RF) MEMS as well.
ShellOC package enables incorporating of single or double
cavity either from one side or from both sides of the
substrate. It can be used for optical or non-optical
applications. It allows incorporating of optional optical
filters and selective removal of various areas in the silicon of pre-formed solder spheres. The process is completed by
die as part of the packaging process. Later we will discus singulation into individual dies using dicing.
how this features can be used for enhancements in RF
applications. pad extensions adhesive
glass
silicon

glass

trenches thinned silicon

glass

adhesive bottom glass

glass

trenches exposed pads

glass

solder balls
glass

Figure 2. Overview of basic Shellcase packaging solutions

[8]. singulation

Fig. 3 shows schematically a typical WLP fabrication
sequence used. The processed silicon IC wafer with bonding
pad extensions into scribe lanes is adhesively bonded to a
glass wafer. If required by application, an adhesive with
optical quality in this step is used. The glass substrate serves
subsequently as a mechanical carrier allowing silicon
substrate thinning down to 50-100 m and trench forming
beneath the pad extensions. Then a second glass substrate is
adhesively bonded resulting in silicon islands fully
encapsulated by the adhesive. At this stage, a compliant
polymer layer beneath the future solder bumps is formed
(not shown in Fig. 3) enhancing the package mechanical
reliability. A V-shaped dicing blade is subsequently used to
perform notching within the scribe lane regions. The
exposed pad extensions at each die periphery are then
redistributed to the area array of solder balls on the bottom
glass substrate. This is done by sputtering and patterning of
an Al layer, followed by solder mask deposition and solder
bump forming using solder paste deposition or attachment
Figure 3. Schematic WLCSP fabrication sequence used by
Shellcase.
EQUIVALENT CIRCUIT MODEL OF PACKAGE
INTERCONNECT
High device speeds require accurate package models to
assure the signal integrity of the die within the package and
of the packaged die within the system. For this purpose, an
equivalent circuit model has been developed based on
physical modeling of the package 3D structure. Although a
full validation of the achieved results would require
frequency domain measurements on properly prepared
samples, the modeling results can be considered as a good
indication of the expected package performance. The
parameter (R, L, and C) extraction was done using Q3D
Extractor from Ansoft [9]. Q3D extractor is a software
package that electrically characterizes three-dimensional
interconnect structures, where lumped equivalent circuit
models can be generated.
Fig. 4 shows the 3D physical model of a 48 I/O package Table 1. Extracted capacitance values (in fF) for selected
used in the extraction process. The equivalent lumped package I/Os (see Fig. 4). Note: the diagonal elements are
circuit model is shown in Fig. 5. The input data for the the capacitances between the n-th I/O and the reference
extraction process are, next to the package geometry, also ground at the backside of Si substrate.
the material properties. These were estimated from literature I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6
data or where required, own measurements have been 46 23 4.6 1.7 0.79 0.48
I/O 1
performed [10].
I/O 2 23 84 27 25 4.4 4.4
I/O 3 4.6 27 44 22 4.3 1.5
I/O 4 1.7 25 22 110 27 21
I/O 5 0.79 4.4 4.3 27 45 23
I/O 6 0.48 4.4 1.5 21 23 73

I/O 1 Table 2. Extracted self- and mutual inductances (in pH) of

I/O 2 selected package I/Os at 1 GHz.
I/O 3 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6
I/O 4 I/O 1 240 85 35 45 18 24
I/O 5 I/O 2 85 840 85 260 38 89
I/O 6 I/O 3 35 85 230 90 35 37
I/O 4 45 260 90 1100 93 220
I/O 5 15 38 35 93 240 84
I/O 1 I/O 6 24 89 37 220 84 590
Figure 4. Physical model of a 3.1x3.1 mm2, 48 I/O package
used to extract electrical parameters of the equivalent circuit Table 3. Extracted resistances (m) of selected I/Os as
model. function of the frequency.
Rtotal
In 1 R/2,L/2 R/2,L/2 Out 1 RDC
0.1GHz 1GHz 5GHz 10GHz
C10 I/O 1 66 82 120 180 220
C12 I/O 2 205 270 270 580 730
I/O 3 64 80 110 170 220
In 2 R/2,L/2 R/2,L/2 Out 2
I/O 4 262 330 470 730 920
C20
I/O 5 66 82 120 180 230
. I/O 6 152 190 270 420 530
.
When Q3D Extractor calculates the AC resistance, it fixes
. the reference frequency at a default value of 100 MHz. A
reasonable estimate of resistance at any frequency f is then
In N R/2,L/2 R/2,L/2 Out N obtained by adding the AC and the DC resistance values:
C N0

Figure 5. Circuit topology of the equivalent lumped circuit
model used by Q3D Extractor.
Simulation results for selected package I/Os (see Fig. 4) are
summarized in Tables 1, 2 and 3. These data includes the
shortest (I/O 1 or 3) and the longest (I/O 4) package I/O
traces. Table 1 lists the extracted capacitances in fF. The
capacitance to ground (Table 1 diagonal elements) was
calculated as the capacitance between a particular I/O trace
and a reference ground within the package positioned at the
backside of the Si substrate. Table 2 shows self- and mutual
inductances in pH. Table 3 lists the resistances in mOhm at
various frequencies (considering the skin effect).
f
R( f ) = RDC + R AC ,
fs
where RDC is the DC resistance component, RAC the AC
component and fs is the reference frequency. For the
convenience, the values listed in Table 3 are the total
resistance values.
For illustration, the simulated S-parameters of the shortest
and the longest package I/O traces are shown in Fig. 6 up to
10 GHz. These results together with the data in the tables
above indicate that the analyzed package has favorable
high-frequency properties and is suitable for RF applications
as a low-cost packaging solution.
 Frequency (GHz)
0 2 4 6 8 10
0.0 Noise transmitter Noise receiver

-0.2
port 1 port 2

-0.4
s21 (dB)

-0.6
I/O 1
substrate coupling ~100 m
-0.8
I/O 4 Silicon substrate
-1.0

-1.2

(a) Figure 7. Schematic illustration of a crosstalk through

silicon substrate. Two single-ended front-side substrate
Frequency (GHz) contacts separated by 100 m and a backside ground
0 2 4 6 8 10
0
terminal are considered.

-10

R2=1382
s11 (dB)

-20
port 1 port 2
I/O 1
-30
I/O 4
-40 C2=0.0052 pF
C2=0.022 pF
R2=234 R2=234
-50

(b) C2=0.022 pF
Figure 6. Simulated S-parameters comparing the shortest
(I/O 1) and the longest (I/O 4) traces of the package from
Fig. 4.

EFFECTS ON SUBSTRATE COUPLING Figure 8. An equivalent RC network circuit model of

To see the how much effect the parasitics produced by the substrate coupling from Fig. 7.
package interconnect may bring, a substrate coupling
problem is employed as an example. Substrate coupling is a
very common problem in mixed-signal integrated circuit. port 2
port 1
Noise generated by the noisy digital circuit (e.g. inverter)
can couple through the substrate into the analog/RF part
(e.g. Low Noise Amplifier) and deteriorates its signal
integrity. In our previous work [11], capabilities of this
package for crosstalk suppression using substrate thinning
and trenching has been explored.

Figure 7 shows an illustration of substrate coupling for a

specific case, which consists of two rectangular substrate substrate model
contacts on a 100 m thick, 5 cm silicon substrate where
the backside is grounded. Its equivalent RC network circuit
model is shown in Fig. 8. To investigate influence of
Internal ground
parasitics contributed by the package traces, these were
added to the equivalent circuit model as shown
schematically in Fig. 9. Then some illustrative cases were
ground connection I/O
selected and analysed using circuit simulator. Overview of
all cases is listed in Table 4. Cases 1-4 represent influence
of the internal ground connection. Cases 5 and 6 represent
influence of short, not-coupled input/output traces. And Figure 9. Lumped circuit model used to investigate
Cases 7 and 8 show the influence of coupled input/output influence of package parasitics on crosstalk between two
traces. circuit terminals.
Table 4. Overview of various cases compared in this study Frequency (GHz)
for their influence on substrate coupling. For the lumped 0.01 0.1 1 10 100

circuit model and I/O assignment, see Fig. 9 and Fig. 4, 0

respectively. -5
case 1 (ideal)
Port 1 Port 2 Ground connection case 2 (short I/O)
I/O

Isolation (dB)
-10
I/O I/O case 3 (medium I/O)
case 4 (long I/O)
Case 1 - - - -15
Case 2 - - I/O 1 (short)
-20
Case 3 - - I/O 6 (medium)
Case 4 - - I/O 4 (long) -25
Case 5 I/O 1 I/O 1 -
-30
Case 6 I/O 1 I/O 1 I/O 4 (long)
Case 7 I/O 1 I/O 2 - (a)
Case 8 I/O 1 I/O 2 I/O 6 (medium)
Frequency (GHz)
0.01 0.1 1 10 100
The results for all cases summarized in Table 4 are shown in 0
Figures 10a-c. Case 1 (without any additional package
-5
traces) is used as a reference.
case 1

Isolation (dB)
-10
Figure 10a compares the cases where the noise signal is case 5
-15
injected directly into the substrate, without any influence of case 6
package interconnect. The internal package ground is -20

connected through one of the package traces: the shortest, a

-25
medium-length and the longest trace are compared. The
results show that the impedance caused by the ground -30

interconnect worsens the isolation and a proper grounding (b)

scheme is very important. The longer the connecting trace,
the higher is the crosstalk between the input and output
Frequency (GHz)
ports. Each case in Fig. 10a uses a single independent 0.01 0.1 1 10 100
interconnect, therefore, coupling with other interconnects is 0

not considered. -5

case 1
Isolation (dB)

In Figure 10b, the isolations achieved from structure using -10

case 7
Case 5 and Case 6 are shown. In these cases the signal is -15 case 8
injected via the shortest package traces (I/O 1 and I/O 1).
Optionally a long ground connection (Case 6) is used. In all -20

cases, the coupling between the package traces is neglected -25

since the distance between them is considerably large. The
results indicate that the short, uncoupled input/output traces
have only a small influence and that proper grounding
scheme is of outmost importance.
In Fig. 10c, isolations achieved for Case 7 and Case 8 are
shown. Here, the interconnects taken for input and output
(I/Os 1 and 2) are next to each other, therefore, the
capacitive and inductive coupling between them is taken
into account (not shown in the lumped circuit model in
Fig. 9). Since the ground interconnect is considerably far,
the coupling to it is neglected. The results indicate that
coupled input/output traces for critical signals should be
avoided.
In summary, the results of above evaluation clearly illustrate
that for the critical signal paths the shortest package I/Os
having low parasitics and no mutual coupling have to be
selected. Particular attention is required to realize the
connection of the internal package ground.
-30
(c)
Figure 10. Influence of package I/O parasitics on crosstalk
between two substrate single-ended contacts (for the lumped
circuit model and the description of the cases under
investigation see Fig. 9 and Table 4, respectively).
(a) Influence of internal ground connection I/O trace length.
(b) Influence of short, not coupled traces and a long ground
connection.
(c) Influence of coupled input/output traces and medium-
length ground connection.
POSSIBLE RF ENHANCEMENTS
Due to its intrinsic fabrication flexibility, the Shellcase
packaging solutions can easily be modified or extended to
provide additional RF enhancements. Some basic
possibilities are shown in Fig. 11. The silicon substrate after
its bonding to one of the glass substrates, is mechanically
stabilized and can be structured from the backside as needed
(thinned, trenched, selectively removed). As already
mentioned, the through-substrate trenches are an effective
way of substrate crosstalk suppression at low and medium
frequencies. Further improvement is possible by using
shielding in the form of metallized and grounded trenches
[11].
Figure 11. Schematic illustration of possible RF
enhancements that at a minimum additional cost will
significantly improve the package RF performance.
Silicon integrated planar inductors suffer from the substrate
losses [12]. Selective substrate removal of lossy silicon
substrate beneath integrated spiral inductors can
significantly improve their quality factor.
CONCLUSIONS
In this work, suitability of a Shellcase-type WLCSP
package for RF packaging has been analyzed and its
potential for implementation of RF enhancements is shown.
The Shellcase-type WLP solutions, which is based on
sandwiching of an IC silicon substrate between two glass
plates, provide high fabrication flexibility and many
optional features (e.g. one or two-side cavities for packaging
of MEMS applications). In the fabrication sequence, the Si
substrate is mechanically supported by a glass plate and can
therefore be 3D structured allowing e.g. its thinning and
partitioning by through-substrate trenches or its selective
removal. These features can be used for crosstalk
suppression between various circuit blocks or integration of
high-quality passives (spiral inductors). Although this
package type has rather limited thermal dissipation
capabilities, due to its high flexibility and low electrical
interconnect parasitics, it is highly suitable for low-power
RF applications including RF MEMS devices.
ACKNOWLEDGMENT
The authors wish to acknowledge the technical staff of
Dimes Technology Center for their technical assistance, and
the Blue Whale project partners for technical support and
input. This work is supported by European Commission
(project Blue Whale, IST-2000-30006).
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