NEHRU INSTITUTE OF ENGINEERING AND TECHNOLOGY

(Approved by AICTE & Affiliated to Anna University)

Nehru Gardens, T.M.Palayam, Coimbatore - 641 105.

AE-6713 FLIGHT INTEGRATION SYSTEMS AND CONTROL

LABORATORY

DEPARTMENT OF AERONAUTICAL ENGINEERING

NAME :
REG.NO :
YEAR/SEMESTER : IV / VII

COURSE : B.E - AERONAUTICAL ENGINEERING

ANNA UNIVERSITY, CHENNAI.

1
 NEHRU INSTITUTE OF ENGINEERING AND TECHNOLOGY
(Approved by AICTE & Affiliated to Anna University)
Nehru Gardens, T.M.Palayam, Coimbatore - 641 105.

DEPARTMENT OF AERONAUTICAL ENGINEERING

Certified that this is the bonafide work done

by.. in the Flight Integration Systems and Control
Laboratory for this institution as prescribed by the Anna University, Chennai for the VII
semester during the academic year 2017-18.

Staff In-Charge Head of the Department

University Register Number submitted for

the practical examination of the Anna University conducted on ..

INTERNAL EXAMINER EXTERNAL EXAMINER

2
SI. DATE EXPERIMENTS PAGE. SIGNATURE
NO NO.
1 8 BIT DATA ADDITION 04

2 8 BIT DATA SUBTRACTION 08

3 16 BIT DATA ADDITION 12

4 16 BIT DATA SUBTRACTION 16

5 SUM OF NUMBERS IN A SERIES 20

WITHOUT CARRY TO IDENTIFY
THE FLAP DATA
6 SUM OF NUMBERS IN A SERIES 24
WITH CARRY TO IDENTIFY THE
FLAP DATA
7 SORTING OF NUMBERS IN 29
ASCENDING ORDER
8 SORTING OF NUMBERS IN 34
DECENDING ORDER
9 GREATEST NUMBER IN AN ARRAY 39

10 MULTI BYTE ADDITION IN BCD 43

MODE
11 STUDY OF LOGIC GATES 46

12 IMPLEMENTATION OF HALF 54
SUBTRACTOR AND FULL
SUBTRACTOR
13 IMPLEMENTATION OF HALF 58
ADDER AND FULL ADDER
14 DESIGN & IMPLEMENTATION OF 62
MULTIPLEXER AND
DE-MULTIPLEXER
15 DESIGN & IMPLEMENTATION OF 67
ENCODER AND DECODER

3
 Ex.no: 1
8 BIT DATA ADDITION

AIM:

To add two 8 bit numbers stored at consecutive memory locations using 8085
microprocessor.

ALGORITHM:

1. Initialize memory pointer to data location.

2. Get the first number from memory in accumulator.
3. Get the second number and add it to the value in accumulator.
4. Store the answer at another memory location.

4
FLOW CHART:
START

[C] 00H

[HL] 3500H

[A] [M]

[HL] [HL]+1

[A]YES [A]+[M]

NO
Is there a
Carry ?

YES

[C] [C]+1

[HL] [HL]+1

[M] [A]

[HL] [HL]+1

[M] [C]

STOP

5
PROGRAM:

ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENT

3100 0E START MVI C, 00 Clear C reg.
3101 00
3102 21 LXI H, 3500 Initialize HL reg. to
3103 00 3500

3104 35
3105 7E MOV A, M Transfer first data to
accumulator

3106 23 INX H Increment HL reg. to

point next memory
Location.

3107 86 ADD M Add first number to

acc. Content.

3108 D2 JNC L1 Jump to location if

3109 0C result does not yield
carry.
310A 31

310B 0C INR C Increment C reg.

310C 23 L1 INX H Increment HL reg. to
point next memory
Location.

310D 77 MOV M, A Transfer the result from

acc. to memory.

310E 23 INX H Increment HL reg. to

point next memory
Location.

310F 71 MOV M, C Move carry to memory

3110 76 HLT Stop the program

6
OBSERVATION:

INPUT OUTPUT
3500 3502
3501 3503

RESULT:

Thus the 8 bit numbers stored at 3500 & 3501 are added and the result is stored at 3502 &
3503.

7
 Ex.no: 2
8 BIT DATA SUBTRACTION

AIM:

To subtract two 8 bit numbers stored at consecutive memory locations using 8085
microprocessor.

ALGORITHM:

1. Initialize memory pointer to data location.

2. Get the first number from memory in accumulator.
3. Get the second number and subtract from the value in accumulator.
4. If the result yields a borrow, the content of the accumulator is complemented and 01H
is added to it (2s complement). A register is cleared and the content of that reg. is
incremented in case there is a borrow. If there is no borrow the content of the acc. is
directly taken as the result.
5. Store the answer at next memory location.

8
FLOW CHART:
START

[C] 00H

[HL] 3500H

[A] [M]

[HL] [HL]+1

[A] [A]-[M]

Is there a
Borrow ? NO

YES
Complement [A]
Add 01H to [A]

[C] [C]+1

[HL] [HL]+1

[M] [A]

[HL] [HL]+1

[M] [C]

STOP

9
PROGRAM:

ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENT

3100 0E START MVI C, 00 Clear C reg.
3101 00
3102 21 LXI H, 3500 Initialize HL reg. to
3103 00 3500
3104 35
3105 7E MOV A, M Transfer first data to
accumulator
3106 23 INX H Increment HL reg. to
point next mem.
Location.
3107 96 SUB M Subtract first number
from acc. Content.
3108 D2 JNC L1 Jump to location if
3109 0F result does not yield
310A 31 borrow.

310B 0C INR C Increment C reg.

310C 2F CMA Complement the Acc.
content
310D C6 ADI 01H Add 01H to content of
310E 01 acc.
310F 23 L1 INX H Increment HL reg. to
point next mem.
Location.
3110 77 MOV M, A Transfer the result from
acc. to memory.
3111 23 INX H Increment HL reg. to
point next mem.
Location.
3112 71 MOV M, C Move carry to mem.
3113 76 HLT Stop the program

10
OBSERVATION:

INPUT OUTPUT
3500 3502
3501 3503

RESULT:

Thus the 8 bit numbers stored at 3500 &3501 are subtracted and the result is stored at 3502 &
3503.

11
Ex.no: 3
16 BIT DATA ADDITION

AIM:

To add two 16-bit numbers stored at consecutive memory locations.

ALGORITHM:

1. Initialize memory pointer to data location.

2. Get the first number from memory and store in Register pair.
3. Get the second number in memory and add it to the Register pair.
4. Store the sum & carry in separate memory locations.

12
FLOW CHART:
START

[L] [3050 H]
[H] [3051 H]

[DE] [HL]

[L] [3052H]
[H] [3053H]

[A] 00H

[HL] [HL]+[DE]
NO

NO
Is there a
Carry?

YES

[A] [A]+1

[3054] [ L]

[3055] [H]

[3056] [A]

STOP

13
PROGRAM:

ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENT

3000 2A START LHLD 3050H Load the augends in DE
pair through HL pair.
3001 50
3002 30
3003 EB XCHG
3004 2A LHLD 3052H Load the addend in HL
pair.
3005 52
3006 30
3007 3E MVI A, 00H Initialize reg. A for
carry
3008 00
3009 19 DAD D Add the contents of HL
Pair with that of DE
pair.

300A D2 JNC LOOP If there is no carry, go

to the instruction
300B 0E
labeled LOOP.
300C 30
300D 3C INR A Otherwise increment
reg. A

300E 22 LOOP SHLD 3054H Store the content of HL

Pair in 3054H
300F 54
(LSB of sum)
3010 30
3011 32 STA 3056H Store the carry in
3056H through Acc.
3012 56 (MSB of sum).
3013 30
3014 76 HLT Stop the program.

14
OBSERVATION:

INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
3050H 3054H
3051H 3055H
3052H 3056H
3053H

RESULT:

Thus an ALP program for 16-bit addition was written and executed in 8085
microprocessor using special instructions.

15
Ex.no: 4
16 BIT DATA SUBTRACTION

AIM:

To subtract two 16-bit numbers stored at consecutive memory locations using 8085
microprocessor.

ALGORITHM:

1. Initialize memory pointer to data location.

2. Get the subtrahend from memory and transfer it to register pair.
3. Get the minuend from memory and store it in another register pair.
4. Subtract subtrahend from minuend.
5. Store the difference and borrow in different memory locations.

16
FLOW CHART:

START

[L] [3050 H]
[H] [3051 H]

[DE] [HL]

[L] [3052H]
[H] [3053H]

[HL] [HL]-[DE]

NO
Is there a
borrow?
YES

YES

[C] [C]+1

[3054] [ L]

[3055] [H]

[3056] [C]

STOP

17
PROGRAM:

ADDRESS OPCODE LABEL MNEMO OPER COMMENTS

NICS AND
3000 0E START MVI C, 00 Initialize C reg.
3001 00
3002 2A LHLD 3050H Load the subtrahend in DE reg.
3003 50 Pair through HL reg. pair.
3004 30
3005 EB XCHG
3006 2A LHLD 3052H Load the minuend in HL reg.
3007 52 Pair.
3008 30
3009 7D MOV A, L Move the content of reg. L to
Acc.
300A 93 SUB E Subtract the content of reg. E
from that of acc.
300B 6F MOV L, A Move the content of Acc. to
reg. L
300C 7C MOV A, H Move the content of reg. H to
Acc.
300D 9A SBB D Subtract content of reg. D with
that of Acc.
300E 67 MOV H, A Transfer content of acc. to reg.
H
300F 22 SHLD 3054H Store the content of HL pair in
3010 54 memory location 3054H.
3011 30
3012 D2 JNC NEXT If there is borrow, go to the
3013 16 instruction labeled NEXT.
3014 20
3015 0C INR C Increment reg. C
3016 79 NEXT MOV A, C Transfer the content of reg. C to
Acc.
3017 32 STA 3056H Store the content of acc. to the
3018 56 memory location 3056H
3019 30
301A 76 HLT Stop the program execution.

18
OBSERVATION:

INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
3050H 3054H
3051H 3055H
3052H 3056H
3053H

RESULT:

Thus an ALP program for subtracting two 16-bit numbers was written and executed.

19
Ex.no: 5
SUM OF NUMBERS IN A SERIES WITHOUT CARRY TO IDENTIFY
THE FLAP DATA

AIM:

To find sum of a series of numbers without carry using 8085 microprocessor.

ALGORITHM:

1. Load the counter value to the accumulator and initialize it

2. Clear the accumulator.
3. Get the first number from memory and store in accumulator.
4. Get the second number in memory and add it to the accumulator.
5. Repeat till counter becomes zero
6. Store the sum in separate memory locations.

20
FLOW CHART:

START

[A] 4200H

[C] [A]

[A] [A]-[A]

[HL] 4201H

[A] [A]+[M]

[HL] [HL]+1

[C] [C]-1

NO

Is [C] = 0?

YES

[4301H] [A]

STOP

21
PROGRAM:

ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENT

3000 3A START LDA 3200H Load data immediately
to the accumulator
3001 00
3002 32
3003 4F MOV C, A Initialize Counter
3004 97 SUB A Subtract the value in
the accumulator
3005 21 LXI H, 3201H Intialize Pointer
3006 01
3007 32
3008 86 LOOP ADD M Add first number to
accumulator content.
3009 23 INX H Increment Pointer
300A 0D DCR C Decrement Counter
300B C2 JNZ LOOP If Counter 0 Repeat
300C 32 STA 3300H Store sum
300D 00
300E 33
300F 76 HLT Stops the program

22
OBSERVATION:

INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
3200H 3300H
3201H
3202H
3203H
3204H

RESULT:

Thus an ALP program for sum of numbers in a series without carry is executed in 8085
microprocessor using special instructions.

23
Ex.no: 6
SUM OF NUMBERS IN A SERIES WITH CARRY TO
IDENTIFY THE FLAP DATA

AIM:

To find sum of a series of numbers without carry using 8085 microprocessor.

ALGORITHM:

1. Load the counter value to the accumulator and initialize it

2. Clear the accumulator.
3. Get the first number from memory and store in accumulator.
4. Get the second number in memory and add it to the accumulator.
5. Repeat till counter becomes zero
6. Store the sum in separate memory locations.

24
FLOW CHART

START

[A] 4200H

[C] [A]

[HL] 4201H

[A] [A]-[A]

[B] [A]

[A] [A]+[M]

NO
Is there a
Carry ?

YES
[B] [B]+1

[HL] [HL]+1

[C] [C]-1

25
 A

NO
Is [C] = 0?

YES

[4300H] [B]

[4301H] [A]

STOP

26
PROGRAM:

ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENT

3000 3A START LDA 3200H Load data immediately
to the accumulator
3001 00
3002 32
3003 4F MOV C, A Initialize Counter
3004 21 LXI H, 3201H Initialize Pointer
3005 01
3006 32
3007 97 SUB A Subtract the value in
the accumulator
3008 47 MOV B, A Move the value from
the accumulator to the
register
3009 8E LOOP1 ADD M Add first number to
accumulator content.
300A D2 JNC LOOP2
300B 04 INR B Adds the carry to the
MSB
300C 23 LOOP2 INX H Increment Pointer
300D 0D DCR C Decrement Counter
300E C2 JNZ LOOP1 If Counter 0 Repeat
300F 32 STA 3300H Store carry
3010 00
3011 33
3012 32 STA 3301H Store sum
3013 01
3014 33
3015 76 HLT Stops the program

27
OBSERVATION:

INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
3200H 3300H
3201H 3301H
3202H
3203H
3204H

RESULT:

Thus an ALP program for sum of numbers in a series without carry is executed in 8085
microprocessor using special instructions.

28
 Ex.no: 7
SORTING OF NUMBERS IN ASCENDING ORDER

AIM:
To sort the given numbers in the ascending order using 8085 microprocessor.

ALGORITHM:

1. Get the numbers to be sorted from the memory locations.

2. Compare the first two numbers and if the first number is larger than second number then
interchange the numbers.
3. If the first number is smaller, go to step 4.
4. Repeat steps 2 and 3 until the numbers are in required order

29
FLOWCHART:

START

[B] 04H

[HL] [3100H]

[C] 04H

[A] [HL]

[HL [HL] + 1

IS
YES [A] < [HL] ?

YES
[D] [HL]

[HL] [A]

[HL] [HL] - 1

[HL] [D]

[HL] [HL] + 1

[C] [C] 01 H

30
 A

NO
IS[C] = 0?

YES

YES

[B] [B]-1

IS NO
[B] = 0?

YES

STOP

31
PROGRAM:

ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENTS

3000 06 MVI B,04 Initialize B reg with
3001 04 number of comparisons
(n-1)
3002 21 LOOP 3 LXI H,3100 Initialize HL reg. to
3003 00 3100H
3004 31
3005 0E MVI C,04 Initialize C reg with no.
3006 04 of comparisons(n-1)
3007 7E LOOP2 MOV A,M Transfer first data to acc.
3008 23 INX H Increment HL reg. to
point next memory
location
3009 BE CMP M Compare M & A
300A DA JC LOOP1 If A is less than M then
300B 12 go to loop1
300C 30
300D 56 MOV D,M Transfer data from M to
D reg
300E 77 MOV M,A Transfer data from acc
to M
300F 2B DCX H Decrement HL pair
3010 72 MOV M,D Transfer data from D to
M
3011 23 INX H Increment HL pair
3012 0D LOOP1 DCR C Decrement C reg
3013 C2 JNZ LOOP2 If C is not zero go to
3014 07 loop2
3015 30
3016 05 DCR B Decrement B reg
3017 C2 JNZ LOOP3 If B is not Zero go to
3018 02 loop3
3019 30
301A 76 HLT Stop the program

32
OBSERVATION:

INPUT OUTPUT
MEMORY DATA MEMORY DATA
LOCATION LOCATION
3100 3100
3101 3101
3102 3102
3103 3103
3104 3104

RESULT:

Thus the ascending order program was executed and the given numbers are arranged
in ascending order.

33
Ex.no: 8
SORTING OF NUMBERS IN DESCENDING ORDER

AIM:

To sort the given numbers in the descending order using 8085 microprocessor.

ALGORITHM:

1. Get the numbers to be sorted from the memory locations.

2. Compare the first two numbers and if the first number is smaller than second number then
interchange the number.
3. If the first number is larger, go to step 4
4. Repeat steps 2 and 3 until the numbers are in required order

34
FLOWCHART:
START

[B] 04H

[HL] [3100H]

[C] 04H

[A] [HL]

[HL [HL] + 1

IS
[A] < [HL] ?

NO YES
[D] [HL]

YES
[HL] [A]

[HL] [HL] - 1

[HL] [D]

[HL] [HL] + 1

[C] [C] 01 H

35
 A

NO
IS
[C] = 0?

YES

[B] [B]-1

no
IS
[B] = 0 ?

yes

STOP

36
PROGRAM:

ADDRESS OPCODE LABEL MNEMONIS OPERAND COMMENTS

3000 06 MVI B,04 Initialize B reg with
3001 04 number of
comparisons (n-1)
3002 21 LOOP 3 LXI H,3100 Initialize HL reg. to
3003 00 3100H
3004 31
3005 0E MVI C,04 Initialize C reg with
3006 04 no. of comparisons
(n-1)
3007 7E LOOP2 MOV A,M Transfer first data to
acc.
3004 23 INX H Increment HL reg. to
point next memory
location
3009 BE CMP M Compare M & A
300A D2 JNC LOOP1 If A is greater than M
300B 12 then go to loop1
300C 30
300D 56 MOV D,M Transfer data from M
to D reg
300E 77 MOV M,A Transfer data from acc
to M
300F 2B DCX H Decrement HL pair
3010 72 MOV M,D Transfer data from D
to M
3011 23 INX H Increment HL pair
3012 0D LOOP1 DCR C Decrement C reg
3013 C2 JNZ LOOP2 If C is not zero go to
3014 07 loop2
3015 30
3016 05 DCR B Decrement B reg
3017 C2 JNZ LOOP3 If B is not Zero go to
3014 02 loop3
3019 30
301A 76 HLT Stop the program

37
OBSERVATION:

INPUT OUTPUT
MEMORY DATA MEMORY DATA
LOCATION LOCATION
3100 3100
3101 3101
3102 3102
3103 3103
3104 3104

RESULT:

Thus the descending order program was executed and the given numbers are arranged
in descending order.

38
Ex.no: 9 GREATEST ELEMENT IN A GIVEN SERIES

AIM:
To find the greatest element in a given series.

ALGORITHM:
1. Place all the elements of a series in the consecutive memory locations.
2. Fetch the first element from the memory location and load it in the accumulator.
3. Initialize a counter (register) with the total number of elements in an array.
4. Decrement the counter by 1.
5. Increment the memory pointer to point to the next element.
6. Compare the accumulator content with the memory content
7. If the accumulator content is smaller, then move the memory content to the
accumulator. Else continue.
8. Decrement the counter by 1.
9. Repeat steps 5 to 8 until the counter reaches zero
10. Store the result (accumulator content) in the specified memory location.

39
FLOW CHART:

START

[HL] [3100H]

[B] 04H

[A] [HL]

NO
[HL [HL] + 1

IS YES
[A] < [HL]?

[A] [HL]

[B] [B]-1 NO

YES
IS
[B] = 0?

[3105] [A]

STOP

40
PROGRAM:

ADDRESS OPCODE LABEL MNEMONCS OPERAND COMMENTS

3001 21 LXI H,4100 Initialize HL reg. to
3100H
3002 00
3003 31
3004 06 MVI B,04 Initialize B reg with
3005 04 no. of comparisons
(n-1)
3006 7E MOV A,M Transfer first data to
acc.
3007 23 LOOP1 INX H Increment HL reg. to
point next memory
location
3008 BE CMP M Compare M & A
3009 D2 JNC LOOP If A is greater than M
then go to loop

300A 0D
300B 30
300C 7E MOV A,M Transfer data from M
to A reg

300D 05 LOOP DCR B Decrement B reg

300E C2 JNZ LOOP1 If B is not Zero go to

300F 07 loop1
3010 30
3011 32 STA 3105 Store the result in a
3012 05 memory location.
3013 31
3014 76 HLT Stop the program

41
OBSERVATION:

INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
3100 3105
3101
3102
3103
3104

RESULT:
Thus the program is executed and largest number in the given series was identified.

42
Ex.no: 10 MULTI BYTE ADDITION IN BCD MODE

AIM :
To perform Multi-Byte addition in BCD mode using 8085
microprocessor.

ALGORITHM:

1. Start the Program

2. Load a number from first memory block to be added into any
register.
3. Load the corresponding number to be added from the second
memory block into the accumulator.
4. Add both register and store the value in the same location of the
first memory block.
5. If there is no carry, go to step 7.
6. Increase the value of any register by 1 to store carry.
7. Loop the step 3 until there is no next number.
8. Store the value of Accumulator or sum and register use in step 6 as
carry.
9. If there was no carry display carry as 0.
10.Stop the program.

43
PROGRAM:
ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENTS
3000 21 LXJ,H 3100h Incialize HL

3001 00 register to 3100

3002 31
3003 4E MOV C,M Copies the Counter
of M to C to be
used as Counter.
3004 3E MVI A,00 Clear the

3005 00 accumulator.

3006 11 LXI D 3500 Intialize DE pair to

3500 H
3007 00
3008 35
3009 21 LXI H 3600 Incialize HL
register to 3600
300A 00
300B 36

300C 1A Loop L1 LDA X D Load data to

accumulator
300D 86 ADD M Add value with M

300E 77 MOV M,A Copy the content

from A to M.
300F 23 INX HL Increase the value
of HL
3010 13 INX D Increase the value
of DE

44
3011 0D DCR C Decrease the value
of DE
3012 C2 JNZ C If c is not zero go
to loop L1
3013 0C
3014 30
3015 76 HLT

Observation:

3100 03
3500
3501
3502
3600
3601
3602

RESULT:
Thus the multi-byte addition in BCD mode is executed & result is
obtained.

45
Ex.no: 11
STUDY OF LOGIC GATES

AIM:

To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-OR
gates.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1
2. Resistor 330 1
3. AND gate IC 7408 1
4. OR gate IC 7432 1
5. NOT gate IC 7404 1
6. NAND gate IC 7400 1
7. NOR gate IC 7402 1
8. EX-OR gate IC 7486 1
9 Connecting wires As required
10 Power supply 1

THEORY:

a. AND gate:

An AND gate is the physical realization of logical multiplication operation. It

is an electronic circuit which generates an output signal of 1 only if all the input
signals are 1.

b. OR gate:

An OR gate is the physical realization of the logical addition operation. It is

an electronic circuit which generates an output signal of 1 if any of the input signals
is 1.

c. NOT gate:

A NOT gate is the physical realization of the complementation operation. It is

an electronic circuit which generates an output signal which is the reverse of the input
signal. A NOT gate is also known as an inverter because it inverts the input.

d. NAND gate:

46
 A NAND gate is a complemented AND gate. The output of the NAND gate
will be 0 if all the input signals are 1 and will be 1 if any one of the input signal
is 0.

f. NOR gate:

A NOR gate is a complemented OR gate. The output of the OR gate will be 1 if

all the inputs are 0 and will be 0 if any one of the input signal is 1.

f. EX-OR gate:

An Ex-OR gate performs the following Boolean function,

A B = (A. B) + (A. B)

It is similar to OR gate but excludes the combination of both A and B being

equal to one. The exclusive OR is a function that give an output signal 0 when the
two input signals are equal either 0 or 1.

PROCEDURE:

1. Connections are given as per the circuit diagram.

2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and verify the truth table for all gates.

47
AND GATE

CIRCUIT DIAGRAM:

Symbol of IC 7408:

PIN DIAGRAM
TRUTH TABLE:

INPUT OUTPUT
S.No
A B Y = A. B
1. 0 0 0
2. 0 1 0
3. 1 0 0
4. 1 1 1

48
OR GATE

CIRCUIT DIAGRAM:
Symbol of IC 7432:

INPUT OUTPUT
S.No
A B Y=A+B

1. 0 0 0

2. 0 1 1

3. 1 0 1
TRUTH TABLE
PIN DIAGRAM
4. 1 1 1

49
NOT GATE

CIRCUIT DIAGRAM:
SYMBOL OF IC 7404:

TRUTH TABLE

INPUT OUTPUT
S.No
A Y = A

1. 0 1

2. 1 0

NAND GATE

CIRCUIT DIAGRAM:
SYMBOL OF IC 7400: PIN DIARAM:

50
 TRUTH TABLE:

INPUT OUTPUT
S.No
A B Y = (A. B)
1. 0 0 1
2. 0 1 1
3. 1 0 1
4. 1 1 0

NOR GATE

CIRCUIT DIAGRAM:
SYMBOL OF IC 7402:

PIN DIAGRAM:

TRUTH TABLE:

INPUT OUTPUT
S.No
A B Y = (A + B)
1. 0 0 1
2. 0 1 0
3. 1 0 0
4. 1 1 0

51
EX-OR GATE

CIRCUIT DIAGRAM
SYMBOL OF IC 7486:

PIN DIAGRAM:

TRUTH TABLE:

INPUT OUTPUT
S.No
A B Y=A B
1. 0 0 0
2. 0 1 1
3. 1 0 1
4. 1 1 0

52
RESULT:

Thus the truth table of all the basic digital ICs are verified.

53
Ex.no: 12
IMPLEMENTATION OF HALF SUBTRACTOR AND FULL
SUBTRACTOR

AIM:

To design and verify the truth table of the Half Subtractor & Full Subtractor
circuits.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required

THEORY:

The arithmetic operation, subtraction of two binary digits has four possible
elementary operations, namely,

0-0=0
0 - 1 = 1 with 1 borrow
1-0=1
1-1=0

In all operations, each subtrahend bit is subtracted from the minuend bit. In
case of the second operation the minuend bit is smaller than the subtrahend bit, hence
1 is borrowed.

HALF SUBTRACTOR:

A combinational circuit which performs the subtraction of two bits is called half
subtractor. The input variables designate the minuend and the subtrahend bit, whereas the
output variables produce the difference and borrow bits.

54
FULL SUBTRACTOR:

A combinational circuit which performs the subtraction of three input bits is called
full subtractor. The three input bits include two significant bits and a previous borrow bit. A
full subtractor circuit can be implemented with two half subtractors and one OR gate.

PROCEDURE:

1. Connections are given as per the circuit diagrams.

2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half subtractor and full subtractor
circuits.

HALF SUBTRACTOR

CIRCUIT DIAGRAM:

B = A.B

TRUTH TABLE:

INPUT OUTPUT
S.No
A B DIFF BORR
1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0

55
FULL SUBTRACTOR

CIRCUIT DIAGRAM:

DIFFERENCE

BORROW

TRUTH TABLE:

INPUT OUTPUT
S.No
A B C DIFF BORR
1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1

56
RESULT:

The design of the half subtractor and full subtractor circuits was done and their truth
tables are verified.

57
Ex.no: 13
IMPLEMENTATION
OF HALF ADDER & FULL ADDER

AIM:

To design and verify the truth table of the Half Adder & Full Adder circuits.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. EX-OR gate IC 7486 1
6. Connecting wires As required

THEORY:

The most basic arithmetic operation is the addition of two binary digits. There
are four possible elementary operations, namely,

0+0=0
0+1=1
1+0=1
1 + 1 = 102

The first three operations produce a sum of whose length is one digit, but
when the last operation is performed the sum is two digits. The higher significant bit
of this result is called a carry and lower significant bit is called the sum.

HALF ADDER:

A combinational circuit which performs the addition of two bits is called half
adder. The input variables designate the augends and the addend bit, whereas the
output variables produce the sum and carry bits.

58
FULL ADDER:

A combinational circuit which performs the arithmetic sum of three input bits
is called full adder. The three input bits include two significant bits and a previous
carry bit. A full adder circuit can be implemented with two half adders and one OR
gate.

PROCEDURE:

1. Connections are given as per the circuit diagrams.

2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder
circuits.

59
 HALF ADDER

CIRCUIT DIAGRAM:

TRUTH TABLE:

INPUT OUTPUT
S.No
A B S C
1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0
4. 1 1 0 1

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 FULL ADDER

CIRCUIT DIAGRAM:

TRUTH TABLE:

INPUT OUTPUT
S.No
A B C SUM CARRY
1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1

RESULT:

The design of the half adder and full adder circuits was done and their truth
tables are verified.

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Ex.no: 14
DESIGN & IMPLEMENTATION OF MULTIPLEXER AND
DE-MULTIPLEXER

AIM:

To design and verify the truth table of a 4 X 1 Multiplexer & 1 X 4 Demultiplexer

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1
2. OR gate IC 7432
3. NOT gate IC 7404
4. AND gate ( three input ) IC 7411
5. Connecting wires As required

THEORY:

Multiplexer is a digital switch which allows digital information from several

sources to be routed onto a single output line. The basic multiplexer has several data
input lines and a single output line. The selection of a particular input line is
controlled by a set of selection lines. Normally, there are 2n input lines and n selector
lines whose bit combinations determine which input is selected. Therefore,
multiplexer is many into one and it provides the digital equivalent of an analog
selector switch.

A Demultiplexer is a circuit that receives information on a single line and

transmits this information on one of 2n possible output lines. The selection of specific
output line is controlled by the values of n selection lines.

PROCEDURE:

1. Connections are given as per the circuit diagrams.

2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the multiplexer & demultiplexer.

62
 4 X 1 MULTIPLEXER

LOGIC SYMBOL:

PIN DIAGRAM OF IC 7411:

63
CIRCUIT DIAGRAM:

TRUTH TABLE:

SELECTION INPUT OUTPUT

S.No
S1 S2 Y

1. 0 0 D0

2. 0 1 D1

3. 1 0 D2

4. 1 1 D3

64
 1X4 DEMULTIPLEXER

LOGIC SYMBOL:

CIRCUIT DIAGRAM:

65
TRUTH TABLE:

INPUT OUTPUT
S.No
S1 S2 Din Y0 Y1 Y2 Y3

1. 0 0 0 0 0 0 0

2. 0 0 1 1 0 0 0

3. 0 1 0 0 0 0 0

4. 0 1 1 0 1 0 0

5. 1 0 0 0 0 0 0

6. 1 0 1 0 0 1 0

7. 1 1 0 0 0 0 0

8. 1 1 1 0 0 0 1

RESULT:

The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their
truth tables were verified.

66
Ex.no: 15
DESIGN & IMPLEMENTATION OF ENCODER AND DECODER

AIM:
To design and implement encoder and decoder circuits using logic gates.

APPARATUS REQUIRED:

S.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P NAND GATE IC 7410 2
2. OR GATE IC 7432 3
3. NOT GATE IC 7404 1
4. IC TRAINER KIT - 1
5. PATCH CORDS - 27

THEORY:

ENCODER:
An encoder is a digital circuit that perform inverse operation of a decoder. An encoder
has 2n input lines and n output lines. In encoder the output lines generates the binary code
corresponding to the input value. In octal to binary encoder it has eight inputs, one for each
octal digit and three output that generate the corresponding binary code. In encoder it is
assumed that only one input has a value of one at any given time otherwise the circuit is
meaningless. It has an ambiguila that when all inputs are zero the outputs are zero. The zero
outputs can also be generated when D0 = 1.

DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded input
into coded output where input and output codes are different. The input code generally has
fewer bits than the output code. Each input code word produces a different output code word
i.e there is one to one mapping can be expressed in truth table. In the block diagram of
decoder circuit the encoded information is present as n input producing 2n possible outputs.
2n output values are from 0 through out 2n 1.

67
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

LOGIC DIAGRAM FOR ENCODER:

68
TRUTH TABLE:

INPUT OUTPUT

Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C

1 0 0 0 0 0 0 0 0 1

0 1 0 0 0 0 0 0 1 0

0 0 1 0 0 0 0 0 1 1

0 0 0 1 0 0 0 1 0 0

0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 1 1 1 1

LOGIC DIAGRAM FOR DECODER:

69
TRUTH TABLE:
INPUT OUTPUT

E A B D0 D1 D2 D3

1 0 0 1 1 1 1

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

RESULT:
Thus the encoder and decoder circuits are implemented and their truth tables are
verified.

70