Mb25 Service Manual

1. INTRODUCTION..................................................................................................................
3
2. TUNER................................................................................................................................... 3
1.1 General description of TDTC-G101D: .................................................................. 3
1.2 Features of TDTC-G101D: .................................................................................... 3
1.3 Pin Configuration ................................................................................................... 4
3. AUDIO AMPLIFIER STAGE WITH TPA3101 ................................................................... 4
3.1 General Description of TPA3101................................................................................. 4
3.2 Features of TPA3101 .................................................................................................. 4
3.3 Pin Configuration of TPA3101 .............................................................................. 5
4. MICROCONTROLLER (MSTAR)....................................................................................... 6
4.1 Genaral Description..................................................................................................... 6
4.2 Features .................................................................................................................. 6
5. INTEGRATED DVB-T RECEIVER (CHEERTEK) ............................................................ 7
5.1 General Description...................................................................................................... 7
5.2 Features .................................................................................................................. 8
6. 4MX16 BIT SYNCHRONOUS DRAM (SDRAM) ............................................................ 10
6.1 General Description.................................................................................................... 10
6.2 Features ...................................................................................................................... 10
6.3 Pin Configuration ...................................................................................................... 11
7. 512K CMOS SERIAL FLASH MX25L512 ..................................................................... 12
7.2 Features ...................................................................................................................... 12
8. 16MX16 BIT SYNCHRONOUS DRAM (SDRAM) .......................................................... 14
8.2 Features ...................................................................................................................... 14
9. SAW FILTER ...................................................................................................................... 14
9.1 IF Filter for Audio Applications Epcos K9656M ................................................... 14
9.1.1 Standarts .................................................................................................................. 14
9.1.2 Features ................................................................................................................... 15
9.1.3 Pin Configuration .................................................................................................. 15
9.1.4 Frequency Response................................................................................................ 15
9.2 IF Filter for Video Applications Epcos K3958M.................................................... 16
9.2.1 Standarts .................................................................................................................. 16
9.2.2 Features ................................................................................................................... 16
9.2.3 Pin Configuration .................................................................................................... 16
9.2.4 Frequency Response................................................................................................ 17
10. POWER STAGE ................................................................................................................ 17
11. IC SPECIFICATIONS ....................................................................................................... 18
11.1 32K Smart Serial EEPROM 24C32 ..................................................................... 18
11.2 TL062 ...................................................................................................................... 19
11.3 PI5V330 ................................................................................................................... 20
11.4 74HCT4053............................................................................................................. 21
11.5 FMS6145................................................................................................................. 22
11.6 LM1117................................................................................................................ 23
11.7 ST24LC21 ............................................................................................................... 24
11.8 24LC02.................................................................................................................... 25
11.9 MAX810............................................................................................................... 26
11.10 TDA1308............................................................................................................... 27
11.11 MP1583 .................................................................................................................. 27
11.12 MP2112 ............................................................................................................ 29
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11.13 IRF7314............................................................................................................ 29
12. BLOCK DIAGRAMS ........................................................................................................ 30
12.1 General Block Diagram............................................................................................ 30
12.2 Integrated DVB-T Receiver Block Diagram............................................................ 32
12.3 MSTAR Block Diagram....................................................................................... 33
2
1. INTRODUCTION
17MB25 mainboard is based on MSTAR concept IC. This IC is capable of handling audio
processing, video processing, scaling-display processing, 3D comb filter, OSD and text
processing, 8 bit dual LVDS transmitter.
TV supports PAL, SECAM, NTSC colour standards and multiple transmission standards as
B/G, D/K, I/I, and L/L including German and NICAM stereo.
Sound system is able to supply 2x10W (10%THD) audio output power for stereo speakers.
Supported peripherals are:
The analog part of the moard can support DVD module which is connected to mainboard
through a cable.
The USB feature is supported through digital part of the mainboard.
1 RF input VHF1, VHF3, UHF @ 75Ohm(Common)

1 Side AV (SVHS, CVBS, HP, R/L_Audio) (Common)
1 SCART socket(Common)
1 YPbPr (Common)
1 PC input(Optional)
2 HDMI (Common)
1 Stereo audio input for PC(Common)
1 Line out(Common)
1 S/PDIF output(Common)
1 Side S-Video(Optional)
1 Headphone(Common)
1 Common interface(Optional)
1 Digital USB(Opional)
1 RS232(Optional)
2. TUNER
A horizontal mounted and Digital Half-Nim tuner is used in the product, which covers 3
Bands(From 48MHz to 862MHz for COFDM, from 45.25MHz to 863.25MHz for CCIR CH).
The tuning is available through the digitally controlled I2C bus (PLL). Below you will find
info on the Tuner in use.
1.1 General description of TDTC-G101D:

The Tuner covers 3 Bands(from 48MHz to 862MHz for COFDM, from 45.25MHz to
863.25MHz for CCIR CH). Band selection and Tuning are performed digitally via the I2C
bus.
1.2 Features of TDTC-G101D:

Digital Half-NIM tuner for COFDM
Covers 3 Bands(From 48MHz to 862MHz for COFDM,
From 45.25MHz to 863.25MHz for CCIR CH)
3
Including IF AGC with SAW Filter
Bandwidth Switching (7/8 MHz) possible
DC/DC Converter built in for Tuning Voltage
Internal(or External) RF AGC, Antenna Power Optional
1.3 Pin Configuration
3. AUDIO AMPLIFIER STAGE WITH TPA3101

3.1 General Description of TPA3101
The TPA3101D2 Rev.A evaluation module consists of a single 10-W, class-D, stereo audio
power amplifier complete with a small number of external components mounted on a circuit
board that can be used to directly drive a speaker with an external analog audio source as the
input.
The gain of the amplifier is controlled by two gain select pins. The gain selections are 20, 26,
32, 36dB.
The outputs are fully protected against shorts to GND, Vcc and output to output shorts with an
auto recovery feature and monitor output.
3.2 Features of TPA3101

10-W/ch into an 8- Load From a 13-V Supply
9.2-W/ch into an 8- Load From a 12-V Supply
Operates from 10 V to 26 V
87% Efficient Class-D Operation Eliminates
Need for Heat Sinks
Four Selectable, Fixed Gain Settings
4
Differential Inputs
Thermal and Short-Circuit Protection With
Auto Recovery Feature
Clock Output for Synchronization With Multiple Class-D Devices
Surface Mount 7 mm 7 mm, 48-pin QFN Package
Surface Mount 7 mm 7 mm, 48-pin HTQFP Package
3.3 Pin Configuration of TPA3101
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4. MICROCONTROLLER (MSTAR)
4.1 Genaral Description
The MST6WB7GQ-3 is a high performance and fully integrated IC for multi-function
LCD monitor/TV with resolutions up to full HD (1920x1080). It is configured with an
integrated triple-ADC/PLL, an integrated DVI/HDCP/HDMI receiver, a multi-standard TV
video and audio decoder, two video de-interlacers, two scaling engines, the MStarACE-3
color engine, an on-screen display controller, an 8-bit MCU and a built-in output panel
interface. By use of external frame buffer, PIP/POP is provided for multimedia applications.
Furthermore, 3-D video decoding and processing are fulfilled for high-quality TV
applications. To further reduce system costs, the MST6WB7GQ-3 also integrates
intelligent power management control capability for green-mode requirements and spread-
spectrum support for EMI management.
4.2 Features
LCD TV controller with PIP/POP display functions

Input supports up to UXGA & 1080P
Panel supports up to full HD (1920x1080)
TV decoder with 3-D comb filter
Multi-standard TV sound demodulator and decoder
10-bit triple-ADC for TV and RGB/YPbPr
10-bit video data processing
Integrated DVI/HDCP/HDMI compliant receiver
High-quality dual scaling engines & dual 3-D video de-interlacers
3-D video noise reduction
Full function PIP/PBP/POP
MStarACE-3 picture/color processing engine
Embedded On-Screen Display (OSD) controler engine
Built-in MCU supports PWM & GPIO
Built-in dual-link 8/10-bit LVDS transmitter
5-volt tolerant inputs
Low EMI and power saving features
296-pin LQFP
NTSC/PAL/SECAM Video Decoder

Supports NTSC M, NTSC-J, NTSC-4.43, PAL (B,D,G,H,M,N,I,Nc), and SECAM
Automatic TV standard detection
Motion adaptive 3-D comb filter for NTSC/PAL
8 configurable CVBS & Y/C S-video inputs
Supports Teletext level-1.5, WSS, VPS, Closed-caption, and V-chip
Macrovision detection
CVBS video output
6
Video IF for Multi-Standard Analog TV
Digital low IF architecture
Stepped-gain PGA with 26 dB tuning range and 1 dB tuning resolution
Maximum IF analog gain of 37dB in addition to digital gain
Programmable TOP to accommodate different tuner gain to optimize noise and
linearity performance
Multi-Standard TV Sound Decoder

Supports BTSC/NICAM/A2/EIA-J demodulation and decoding
FM stereo & SAP demodulation
L/Rx4, mono, and SIF audio inputs
L/Rx3 loudspeaker and line outputs
Supports sub-woofer output
Built-in audio output DACs
Audio processing for loudspeaker channel, including volume, balance, mute, tone, EQ,
and virtual stereo/surround
Optional advanced surround available (Dolby1, SRS2, BBE3 etc)
Digital Audio Interface

I2S digital audio input & output
S/PDIF digital audio input & output
HDMI audio channel processing capability
Programmable delay for audio/video synchronization
Analog RGB Compliant Input Ports

Three analog ports support up to UXGA
Supports HDTV RGB/YPbPr/YCbCr
Supports Composite Sync and SOG (Sync-on-Green) separator
Automatic color calibration
DVI/HDCP/HDMI Compliant Input Port

Two HDMI input ports with built-in switch
Supports TMDS clock up to 225MHz @ 1080P 60Hz with 12-bit deep-color
resolution
Single link on-chip DVI 1.0 compliant receiver
High-bandwidth Digital Content Protection(HDCP) 1.1 compliant receiver
5. INTEGRATED DVB-T RECEIVER (CHEERTEK)

5.1 General Description
CT216T is a highly integrated single chip for DVB-T compliant STB solution. Compared
with Cheertek's previous generations of STB receiver devices. CT216T further interates
COFDM demodulator USB 2.0 HS host controller, memory card reader, 1/2-bit SPIFlash
interface, audio DAC, PWM in/out and SAR-ADC functions. In additiont special
enhangements are provided such as MPEG-4 video decoding, 16-bit OSD with anti-flickering,
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HW JPEG decoding, flesh tone and black-white extensions, and improvement of small video
quality.
CT216T includes COFDM demodulator transport stream de-multiplexer, DVB-CSA

compliant de-scrambler, RISC MPUs, MPEG-1/2/4 AV decoder, digital T\/ encoder, audio
DACs, USB 2.0 HS host controller, memory card reader, smart card reader, CI controller and
other peripherals.
Cli216T is designed in focus on the market of single tuner input product which makes, it a
cost effective solution. Supports include free to air, conditional access for SC (Smart card)
and CI portable devices, PVR, LCD TV, and other DVB-T applications.
5.2 Features
COFDM Demodulator
ETSI EN 300 744 DVB-T NorDig Unified 1.0.3, and D-book compliant
Automatic spectral inversion, detection
Integrated ADC
Direct IF (36.167 MHz or 43.75 MHz) or low IF (4.57 MHz) supported
Single IF AGC or dual RF/lF AGC controls with modulabon
Impulsive noise cancellation
Carrier acquisition range: 400 kHz (extensible to 600 kHz in 8MHz BW)
Adjacent channel interference (ACI) filter,for supporting 6, 7, and 8MHz channels
with one 8MHz analog filter
Co-channel interterence (CCl) supression
RF signal strength monitor
MPU
Three 32-bit RISC MPU run up to 166MHz with total 448DMIPS
8KB I-Cache and 8KB D-Cache
Two general purpose timers
Watchdog timer
DSU for source level debug
Memory
6-bit SDRAM controller supports up to 32MB (16MB for l28-pin)
Unified memory architecture
Parallel flash (216-pin only)
1/2-bit SPI flash
Transport De-multiplexing
TS, PES, and ES demultiplexing
OneTS path
CI CAM interface (216-pin only)
32 general purpose PID filters
32 Section filters
CRC-32 accelerator
DVB-CSA de-scramblers
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Video Decoding and Processing
MPEG-2 MP@ML
MPEG-4 SP&ASP
PAL/NTSC format conversion
3:2 pull down
Zoom in/out from 1/16X to 16X
HW JPEG decode
4/8/16-bit OSD with anti-flickering
On chip NTSC/PAL TV encoder
CVBS, S-VHS, and component video
VBI insertion for Teletext, CC and WSS
ITU-R BT.601 and ITU-R BT.656 outputs
Flesh tone extension
Black/white extension,
Audio Decoding and Processing

MPEG-1: layer 1/2/3
MPEG-2: layer 1/2
Decode MPEG-2 and MPEG-1 audio at sampling frequency of 16K, 22.05K, 24K,
32K, 44.1K, and 48KHz
Decode CU-DA at sampling frequency of 44.1 KHz
SPDIF out for AC-3 by-pass
Embedded 2 channels audio DAC for L/R outputs
Digital mute control and volume adjustment
OSD(On Screen Display)

There are total 9 display planes: border; background. video. RS1 (Rectangle Strip 1),
RS2, OSD, RS3, RS4, and cursor.
4/8l16-bit OSD with anti-flickering and anti-flutter
Support alpha-blending per color
Adjustable brightness control in window
Bitmap OSD
Support horizontal pixel duplication to enlarge bitmap automatically
Support sub-region redraw to facilitate bitmap display.
Digitnal TV Encoder
NTSC-M, PAL-B, D, G, H, I, Nc, M encoding
Four video DACs to provide 6 configuration output: modes
Support CVBS, S-VHS. and component video outs
VBI insertion for Teletext, CC and WSS
Color burst amplitude control
Programmable sync. level
On chip, color-bar generator
High Speed I/O

USB 2.0 HS host controller
9
Memory card reader with SD, MMC, and MS interfaces
Compliant with SD spec. 1.1 and MMC spec. 4.0 with 1-bit & 4-bit modes.
Compliant with Memory Stick Pro format spec. 1.02 and Memory stick format spec
1.43 with 1-bit and 4-bit modes.
Peripherals
Up to 3 full duplex UART with 16-byte FIFO
2-wire serial (2WS) in master mode .. .
Up to 2 IS0-7816 compliant SC (1 in 128-pin, can also be used as UART)
5 digits 7-Segrnent LED control
5x3 two-dimension key scan
2 SAR-ADC input
4 PWM input/output
1 HW IR command decode
GPIO
Electrical and Physical Characteristics

Capable of using single 27MHz clock input crystal
1.8V and 3.3V dual power supply
Power standby mode
PQFP-128 (CT216T-Z) or LQFP-216 (CT216T-R) package
6. 4MX16 BIT SYNCHRONOUS DRAM (SDRAM)

The EM638165 SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It
is internally configured as 4 Banks of 1M word x 16 DRAM with a synchronous interface (all
signals are registered on the positive edge of the clock signal, CLK). Read and write accesses
to the SDRAM are burst oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. Accesses begin with the
registration of a BankActivate command which is then followed by a Read or Write
command. The EM638165 provides for programmable Read or Write burst lengths of 1, 2, 4,
8, or full page, with a burst termination option. An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy to use. By having a programmable
mode register, the system can choose the most suitable modes to maximize its performance.
These devices are well suited for applications requiring high memory bandwidth and
particularly well suited to high performance PC applications.
6.2 Features
Fast access time from clock: 4.5/5/5.4 ns
Fast clock rate: 200/166/143 MHz
Fully synchronous operation
Internal pipelined architecture
1M word x 16-bit x 4-bank
Programmable Mode registers
10
CAS Latency: 2, or 3
Burst Length: 1, 2, 4, 8, or full page
Burst Type: interleaved or linear burst
Burst stop function
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V 0.3V power supply
Interface: LVTTL
54-pin 400 mil plastic TSOP II package
Pb free and Halogen free
60-ball 6.4mm x 10.1mm VFBGA package
Pb free
6.3 Pin Configuration
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7. 512K CMOS SERIAL FLASH MX25L512
The MX25L512 is a CMOS 524,288 bit serial Flash memory, which is configured as 65,536 x
8 internally. The MX25L512 feature a serial peripheral interface and software protocol
allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a
serial data input (SI), and a serial data output (SO). SPI access to the device is enabled by CS#
input. The MX25L512 provide sequential read operation on whole chip. After program/erase
command is issued, auto program/ erase algorithms which program/ erase and verify the
specified page or sector/block locations will be executed. Program command is executed on
page (256 bytes) basis, and erase command is executes on chip or sector (4K-bytes). To
provide user with ease of interface, a status register is included to indicate the status of the
chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP
bit. When the device is not in operation and CS# is high, it is put in standby mode and draws
less than 10uA DC current. The MX25L512 utilize MXIC's proprietary memory cell, which
reliably stores memory contents even after 100,000 program and erase cycles.
7.2 Features
General
Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3
524,288 x 1 bit structure
16 Equal Sectors with 4K byte each
Any Sector can be erased individually
Single Power Supply Operation
2.7 to 3.6 volt for read, erase, and program operations
Latch-up protected to 100mA from -1V to Vcc +1V
Low Vcc write inhibit is from 1.5V to 2.5V
Performance
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High Performance
Fast access time: 85MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock
(30pF + 1TTL Load)
Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
Fast erase time: 60ms(typ.) and 120ms(max.)/sector (4K-byte per sector) ; 1s(typ.) and
2s(max.)/chip(512Kb)
Low Power Consumption
Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and
4mA(max.) at 33MHz
Low active programming current: 15mA (max.)
Low active erase current: 15mA (max.)
Low standby current: 10uA (max.)
Deep power-down mode 1uA (typical)
Minimum 100,000 erase/program cycles
Software Features
Input Data Format
1-byte Command code
Block Lock protection
The BP0~BP1 status bit defines the size of the area to be software protected against
Program and Erase instructions.
Auto Erase and Auto Program Algorithm
Automatically erases and verifies data at selected sector
Automatically programs and verifies data at selected page by an internal algorithm
that automatically times the program pulse widths (Any page to be programed should
have page in the erased state first)
Status Register Feature
Electronic Identification
JEDEC 2-byte Device ID
RES command, 1-byte Device ID
Hardware Features
SCLK Input
Serial clock input
SI Input
Serial Data Input
SO Output
Serial Data Output
WP# pin
Hardware write protection
HOLD# pin pause the chip without diselecting the chip
PACKAGE
8-pin SOP (150mil)
All Pb-free devices are RoHS Compliant
13
8. 16MX16 BIT SYNCHRONOUS DRAM (SDRAM)
The EM63A165 SDRAM is a high-speed CMOS synchronous DRAM containing 256 Mbits.
It is internally configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface
(all signals are registered on the positive edge of the clock signal, CLK). Read and write
accesses to the SDRAM are burst oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed sequence. Accesses begin with the
registration of a BankActivate command which is then followed by a Read or Write
command. The EM63A165 provides for programmable Read or Write burst lengths of 1, 2, 4,
8, or full page, with a burst termination option. An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy to use. By having a programmable
mode register, the system can choose the most suitable modes to maximize its performance.
These devices are well suited for applications requiring high memory bandwidth and
particularly well suited to high performance PC applications.
8.2 Features
Fast access time from clock: 5/5.4 ns
Fast clock rate: 166/143 MHz
Fully synchronous operation
Internal pipelined architecture
4M word x 16-bit x 4-bank
Programmable Mode registers
- CAS Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
Auto Refresh and Self Refresh
8192 refresh cycles/64ms
CKE power down mode
Single +3.3V power supply
Interface: LVTTL
54-pin 400 mil plastic TSOP II package
- Pb free and Halogen free
9. SAW FILTER
9.1 IF Filter for Audio Applications Epcos K9656M
9.1.1 Standarts
B/G
D/K
I
L/L
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9.1.2 Features
TV IF audio filter with two channels
Channel 1 (L) with one pass band for sound carriers at 40,40 MHz (L) and 39,75
MHz (L- NICAM)
Channel 2 (B/G,D/K,L,I) with one pass band for sound carriers between 32,35 MHz
and 33,40 MHz
9.1.3 Pin Configuration
1 Input
2 Switching input
3 Chip carrier - ground
4 Output
5 Output
9.1.4 Frequency Response

Frequency Response of Channel 1:
Frequency Response of Channel 2:
15
9.2 IF Filter for Video Applications Epcos K3958M
9.2.1 Standarts
B/G
D/K
I
L/L
9.2.2 Features
TV IF filter with Nyquist slopes at 33.90 MHz and 38.90 MHz
Constant group delay
9.2.3 Pin Configuration

1 Input
2 Input - ground
3 Chip - carrier ground
4 Output
5 Output
16
9.2.4 Frequency Response
10. POWER STAGE

The DC voltages required at various parts of the chassis and inverters are provided by an
external power supply unit or produced on the chassis if an adapter is used for the supply. The
12V dc voltage is switched by IRF 7314 power mosfet in TV sets with mechanical switch to
produce the required standby voltage. Also regulators and mosfets generate 1.8V, 3.3V and
5V and 1.26V voltages for other different parts of the chassis.
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11. IC SPECIFICATIONS
11.1 32K Smart Serial EEPROM 24C32
General Description
The Microchip Technology Inc. 24C32 is a 4K x 8 (32K bit) Serial Electrically Erasable
PROM. This device has been developed for advanced, low power applications such as
personal communications or data acquisition. The 24C32 features an input cache for fast write
loads with a capacity of eight 8-byte pages, or 64 bytes. It also features a fixed 4K-bit block
of ultra-high endurance memory for data that changes frequently. The 24C32 is capable of
both random and sequential reads up to the 32K boundary. Functional address lines allow up
to eight 24C32 devices on the same bus, for up to 256K bits address space. Advanced CMOS
technology makes this device ideal for low-power non-volatile code and data applications.
The 24C32 is available in the standard 8-pin plastic DIP and 8-pin surface mount SOIC
package.
Features
Voltage operating range: 4.5V to 5.5V
Peak write current 3 mA at 5.5V
Maximum read current 150 A at 5.5V
Standby current 1 A typical
Industry standard two-wire bus protocol, I2C compatible
Including 100 kHz and 400 kHz modes
Self-timed write cycle (including auto-erase)
Power on/off data protection circuitry
Endurance: 10,000,000 Erase/Write cycles guaranteed for High Endurance
Block, 1,000,000 E/W cycles guaranteed for Standard Endurance Block
8 byte page, or byte modes available
1 page x 8 line input cache (64 bytes) for fast write loads
Schmitt trigger, filtered inputs for noise suppression
Output slope control to eliminate ground bounce
2 ms typical write cycle time, byte or page
Up to 8 chips may be connected to the same bus for up to 256K bits total
memory
Electrostatic discharge protection > 4000V
Data retention > 200 years
8-pin PDIP/SOIC packages
Temperature ranges: Commercial (C): 0C to +70C, Industrial (I): -40C to
+85C
18
Pin Configuration
11.2 TL062
General Description
Low-power JFET-input operational amplifier
Features
Very Low Power Consumption
Typical Supply Current . . . 200 A (Per Amplifier)
Wide Common-Mode and Differential Voltage Ranges
Low Input Bias and Offset Currents
Common-Mode Input Voltage Range Includes VCC+
Output Short-Circuit Protection
High Input Impedance . . . JFET-Input Stage
Internal Frequency Compensation
Latch-Up-Free Operation
High Slew Rate . . . 3.5 V/s Typ
19
Pin Configuration
11.3 PI5V330
General Description
Pericom Semiconductor.s PI5V series of mixed signal video circuits are produced in the
Company.s advanced CMOS low-power technology, achieving industry leading performance.
The PI5V330 is a true bidirectional Quad 2-channel multiplexer/demultiplexer that is
recommended for both RGB and composite video switching applications. The VideoSwitch.
can be driven from a current output RAMDAC or voltage output composite video source.
Low ON-resistance and wide bandwidth make it ideal for video and other applications. Also
this device has exceptionally high current capability which is far greater than most analog
switches offered today. A single 5V supply is all that is required for operation. The PI5V330
offers a high-performance, low-cost solution to switch between video sources. The application
section describes the PI5V330 replacing the HC4053 multiplier and buffer/amplifier.
Features
High-performance, low-cost solution to switch between video sources
Wide bandwidth: 200 MHz
Low ON-resistance: 3
Low crosstalk at 10 MHz: .58 dB
Ultra-low quiescent power (0.1 A typical)
Single supply operation: +5.0V
Fast switching: 10 ns
High-current output: 100 mA
Packages available:
16-pin 300-mil wide plastic SOIC (S)
16-pin 150-mil wide plastic SOIC (W)
16-pin 150-mil wide plastic QSOP (Q)
20
Pin Configuration
11.4 74HCT4053
General Description
The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A. The
74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a common
enable input (E). Each multiplexer/demultiplexer has two independent inputs/outputs (nY0
and nY1), a common input/output (nZ) and three digital select inputs (Sn). With E LOW, one
of the two switches is selected (low-impedance ON-state) by S1 to S3. With E HIGH, all
switches are in the high-impedance OFF-state, independent of S1 to S3. VCC and GND are
the supply voltage pins for the digital control inputs (S1 to S3 and E). The VCC to GND
ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5 V for 74HCT4053. The analog
inputs/outputs (nY0 and nY1, and nZ) can swing between VCC as a positive limit and VEE as
a negative limit. VCC - VEE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically
ground).
Features
Low ON resistance:
80 W (typical) at VCC - VEE = 4.5 V
Logic level translation:
To enable 5 V logic to communicate with 5 V analog signals
Typical break before make built in
Complies with JEDEC standard no. 7A
ESD protection: HBM EIA/JESD22-A114-C exceeds 2000 V, MM EIA/JESD22-
A115-A exceeds 200 V
Multiple package options
Specified from -40 C to +85 C and from -40 C to +125 C
21
Pin Configuration
11.5 FMS6145
General Description
The FMS6145 Low-Cost Video Filter (LCVF) is intended to replace passive LC lters and
drivers with a low-cost integrated device. Five 4th-order lters provide improved image
quality compared to typical 2nd or 3rd-order passive solutions. The FMS6145 may be directly
driven by a DC-coupled DAC output or an AC-coupled signal. Internal diode clamps and bias
circuitry may be used if AC-coupled inputs are required. The outputs can drive AC- or DC-
coupled single (150) or dual (75) loads. DC coupling the outputs removes the need for
output coupling capacitors. The input DC levels are offset approximately +280mV at the
output.
Features
Five 4th-order 8MHz (SD) lters
Drives single,AC- or DC-coupled, video loads (2Vpp, 150)
Drives dual, AC- or DC-coupled, video loads (2Vpp, 75)
Transparent input clamping
AC- or DC-coupled inputs
AC- or DC-coupled outputs
DC-coupled outputs eliminate AC-coupling capacitors
5V only
Robust 8kV ESD protection
Lead-free TSSOP-14 package
22
Pin Configuration
11.6 LM1117
General Description
The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of
load current. It has the same pin-out as National Semiconductors industry standard LM317.
The LM1117 is available in an adjustable version, which can set the output voltage from
1.25V to 13.8V with only two external resistors. In addition, it is also available in five fixed
voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers current limiting and thermal
shutdown. Its circuit includes a zener trimmed bandgap reference to as-sure output voltage
accuracy to within 1%. The LM1117 series is available in SOT- 223, TO-220, and TO-252
D-PAK packages. A minimum of 10F tantalum capacitor is required at the output to improve
the transient response and stability.
Features
Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions
Space Saving SOT-223 Package
Current Limiting and Thermal Protection
Output Current 800mA
Line Regulation 0.2% (Max)
Load Regulation 0.4% (Max)
Temperature Range
LM1117 0C to 125C
LM1117I -40C to 125C
23
Pin Configuration
11.7 ST24LC21
Description
The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM),
organized by 8 Bits.This device can operate in two modes: Transmit Only mode and I2C
bidirectional mode. When powered, the device is in Transmit Only mode with EEPROM data
clocked out from the rising edge of the signal applied on VCLK. The device will switch to the
I2C bidirectional mode upon the falling edge of the signal applied on SCL pin. The
ST24LC21 cannot switch from the I2C bidirectional mode to the Transmit Only mode (except
when the power supply is removed). The device operates with a power supply value as low as
2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages are available.
Features
1 Mllon Erase/Wrte Cycles
40 Years Data Retenton
2.5v To 5.5v Sngle Supply Voltage
400k Hz Compatblty Over The Full
Range Of Supply Voltage
Two Wre Seral Interface I2c Bus
Compatble
Page Wrte (Up To 8 Bytes)
Byte, Random And Sequental Read
Modes
Self Tmed Programmng Cycle
Automatc Address Incrementng
Enhanced Esd/Latch Up
Performances
24
Pin Configuration
11.8 24LC02
Description
The Microchip Technology Inc. 24AA02/24LC02B (24XX02*) is a 2 Kbit Electrically
Erasable PROM. The device is organized as one block of 256 x 8-bit memory with a 2-wire
serial interface. Low-voltage design permits operation down to 1.8V, with standby and active
currents of only 1 A and 1 mA, respectively. The 24XX02 also has a page write capability
for up to 8 bytes of data. The 24XX02 is available in the standard 8-pin PDIP, surface mount
OIC, TSSOP and MSOP packages and is also available in the 5-lead SOT-23 package.
Features
Single supply with operation down to 1.8V
Low-power CMOS technology
- 1 mA active current typical
- 1A standby current typical (I-temp)
Organized as 1 block of 256 bytes (1 x 256 x 8)
2-wire serial interface bus, I2C compatible
Schmitt Trigger inputs for noise suppression
Output slope control to eliminate ground bounce
100 kHz (24AA02) and 400 kHz (24LC02B) compatibility
Self-timed write cycle (including auto-erase)
Page write buffer for up to 8 bytes
2 ms typical write cycle time for page write
Hardware write-protect for entire memory
Can be operated as a serial ROM
Factory programming (QTP) available
ESD protection > 4,000V
1,000,000 erase/write cycles
Data retention > 200 years
8-lead PDIP, SOIC, TSSOP and MSOP packages
5-lead SOT-23 package
Pb-free finish available
Available for extended temperature ranges:
25
- Industrial (I): -40C to +85C
- Automotive (E): -40C to +125C
Pin Configuration
11.9 MAX810
General Description
The MAX809 and MAX810 are cost-effective system supervisor circuits designed to monitor
VCC in digital systems and provide a reset signal to the host processor when necessary. No
external components are required. The reset output is driven active within 10 _sec of VCC
falling through the reset voltage threshold. Reset is maintained active for a timeout period
which is trimmed by the factory after VCC rises above the reset threshold. The MAX810 has
an active-high RESET output while the MAX809 has an active-low RESET output. Both
devices are available in SOT-23 and SC-70 packages. The MAX809/810 are optimized to
reject fast transient glitches on the VCC line. Low supply current of 0.5 _A (VCC = 3.2 V)
makes these devices suitable for battery powered applications.
Features
Precision VCC Monitor for 1.5 V, 2.5 V, 3.0 V, 3.3 V, and 5.0 V Supplies
Precision Monitoring Voltages from 1.2 V to 4.9 V Available in 100 mV Steps
Four Guaranteed Minimum Power-On Reset Pulse Width Available (1 ms, 20 ms, 100
ms, and 140 ms)
RESET Output Guaranteed to VCC = 1.0 V.
Low Supply Current
Compatible with Hot Plug Applications
VCC Transient Immunity
No External Components
Wide Operating Temperature: -40C to 105C
Pb-Free Packages are Available
26
Pin Configuration
11.10 TDA1308
Description
The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a
DIP8 plastic package. The device is fabricated in a 1 mm CMOS process and has been
primarily developed for portable digital audio applications.
Features
Operating temperature range: -40 to +85 C
No switch ON/OFF clicks
Short-circuit resistant
signal-to-noise ratio: 110 dB
total harmonic distortion: 0.001 %
Pin Configuration
11.11 MP1583
General Description
The MP1583 is a step-down regulator with a built in internal Power MOSFET. It achieves 3A
continuous output current over a wide input supply range with excellent load and line
regulation. Current mode operation provides fast transient response and eases loop
stabilization. Fault condition protection includes cycle-by-cycle current limiting and thermal
27
shutdown. Adjustable soft-start reduces the stress on the input source at turn-on. In shutdown
mode the regulator draws 20A of supply current.
The MP1583 requires a minimum number of readily available external components to
complete a 3A step down DC to DC converter solution.
Features
3A Output Current
Programmable Soft-Start
100m Internal Power MOSFET Switch
Stable with Low ESR Output Ceramic Capacitors
Up to 95% Efficiency
20A Shutdown Mode
Fixed 385KHz frequency
Thermal Shutdown
Cycle-by-Cycle Over Current Protection
Wide 4.75 to 23V operating Input Range
Output Adjustable From 1.22 to 21V
Under Voltage Lockout
Available in 8 pin SOIC Package
3A Evaluation Board Available
Pin Configuration
28
11.12 MP2112
General Description
The MP2112 is a 1MHz constant frequency, current mode, PWM step-down converter. The
device integrates a main switch and a synchronous rectifier for high efficiency without an
external Schottky diode. It is ideal for powering portable equipment that powered by a single
cell Lithium-Ion (Li+) battery. The MP2112 can supply 1A of load current from a 2.5V to 6V
input voltage. The output voltage can be regulated as low as 0.6V. The MP2112 can also run
at 100% duty cycle for low dropout applications.
The MP2112 is available in a space-saving 6-pin QFN package.
Features
High Efficiency: Up to 95%
1MHz Constant Switching Frequency
1A Available Load Current
2.5V to 6V Input Voltage Range
Output Voltage as Low as 0.6V
100% Duty Cycle in Dropout
Current Mode Control
Short Circuit Protection
Thermal Fault Protection
<0.1A Shutdown Current
Space Saving 3mm x 3mm QFN6 Package
Pin Configuration
11.13 IRF7314
General Description
Fifth Generation HEXFETs from International Rectifier utilize advanced processing

techniques to achieve extremely low on-resistance per silicon area. This benefit, combined
with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs
are well known for, provides the designer with an extremely efficient and reliable device for
use in a wide variety of applications. The SO-8 has been modified through a customized
leadframe for enhanced thermal characteristics and multiple-die capability making it ideal in a
variety of power applications. With these improvements, multiple devices can be used in an
application with dramatically reduced board space. The package is designed for vapor phase,
infra red, or wave soldering techniques.
29
Pin Configuration
12. SERVICE MENU SETTINGS

In order to reach service menu, First Press MENU Then press the remote control
code, which is 4725. In DTV mode, first press MENU and select TV SETUP.
Then, press 4725.
12.1. Video Setup

Panel Info <..................................>
32_LC_SAC1
Blue Background <.....>
If Menu selected, Blue Background item is seen in Feature
menu.
If Yes selected, Blue Background is on and not seen in
Feature menu
Film Mode <.....>
If Yes selected, Film Mode feature is active.
Dynamic Contrast <.....>
If Yes selected, Dynamic Contrast feature is active.
Game Mode <...........>
If Yes selected, Game Mode feature is active
SRGB For PC <...........>
If Yes selected, PCs can use SRGB option.
Dynamic Noise Reduction<...........>
If Yes selected, Dynamic Noise Reduction feature is active
WSS Option<...........>
If Yes selected, WSS Option can be used
12.2. AudioSetup
BG<.....>
Europe
30
New Zelland
Australia
No
DK<.....>
I<.....>
L<.....>
Equalizer <.....>
If Yes selected, Equalizer item is seen in Sound menu.
Headphone <.....>
If Yes selected, Headphone item is seen in Sound menu.
Power On/Off Melody <.....>
If Yes selected, when power on/off conditions, the power on/off
melody can be heard.
Dynamic Bass <.....>Value between 0 to 12
Effect<.....> Value between 0 to 7
Audio Delay ,offset <.....> Value between 0 to 190
Audio Setup Cont...2
Carrier mute<.......> Value between 0 to 28
Headphone Sound Select <.......>
Always Active Select
Always Inactive Select
Menu
Always Main Menu
Always PIP/PAP Window
Sound Mode Detect Time <.......> Value between 0 to 255
Noise Reduction Threshold <.......> Value between 0 to 255
Noise Reduction Time <.......> Value between 0 to 15
AVL Attack Time <.......> Value between 0 to 255
AVL Release Time <.......> Value between 0 to 255
Prescales ( AVL On)
FM Prescale<.......> Value between 0 to 255
AM Prescale <.......> Value between 0 to 255
NICAM Prescale <.......> Value between 0 to 255
SCART Prescale <.......> Value between 0 to 255
FAV Prescale <.......> Value between 0 to 255
DTV Prescale <.......> Value between 0 to 255
HDMI Prescale <.......> Value between 0 to 255
YPbPr/PC Prescale <.......> Value between 0 to 255
An. USB Prescale <.......> Value between 0 to 255
Dig. USB Prescale <.......> Value between 0 to 255
Prescales ( AVL Off)
Clipping Levels ( AVL On)
FM Clipping <.......> Value between 0 to 255
AM Clipping <.......> Value between 0 to 255
NICAM Clipping <.......> Value between 0 to 255
SCART Clipping <.......> Value between 0 to 255
FAV Clipping <.......> Value between 0 to 255
DTV Clipping <.......> Value between 0 to 255
HDMI Clipping <.......> Value between 0 to 255
YPbPr/PC Clipping <.......> Value between 0 to 255
An. USB Clipping <.......> Value between 0 to 255
Dig. USB Clipping <.......> Value between 0 to 255
Clipping Levels ( AVL Off)
12.3. Service Scan/Tuning Setup

First Search for L/L <.......>
ATS Delay Time (ms) <.......> Value between 0 to +200
Main Tuner Setup
Tuner Type
LC_TDTC_GXX1D
Thomson DTT7543X
Philips TD1318AF-3
Samsung DTOs403LH172A
Generic ( Analog Only)
Control Byte <.......> Value between 0 to +255
BSW1 <.......> Value between 0 to +255
Low-Mid Low Byte <.......>
Low-Mid High Byte <.......>
Mid-High Low Byte <.......>
Mid-High High Byte <.......>
S Band TOP <.......>
VIF TOP <.......> Value between 0 to +15
VIF TOP SECAM <.......> Value between 0 to +15
VIF TOP DK<.......> Value between 0 to +15
Synch Threshold<.......> Value between 0 to +40
16.4. Options
Options-1
Power Up
Standby
Last state
TV Open Mode
Source
1st TV
Last Tv
First APS <.......>
If Yes selected, first time TV opens by asking APS.
APS Volume <.......> Value between 0 to +63
Burn In Mode <.......>
If Yes selected, TV opens with Burn-In mode. This mode is
used in manufacturing.
APS Test
Autostore <.......>
If Yes selected, Channel is automatically stored.
Unicode Enabled <.......>
If Yes selected,Unicode characters can be read in the USB
Files.
Options-2
Source List menu <.......>
If Yes selected, Sorce List Menu appears on the screen
when press source button.
RS232 for B2B <.......>
If Yes selected, Remote Control commandsthe TV via
RS232 and vice versa.
RC Select <.......>
RC Group 1
RC Group 2
RC Group 3
RC Group 4
RC Group 5
RC Group 6
Double Digit Key <.......>
If Yes selected, Double Digit Button on RC activates.
Protection <.......>
If Yes selected,short circuit protection activates.
Led Type <.......>
1 Led 1 Color
1 Led 2 Color
2 Led 2 Color
1 Led 3 Color
2 Led 3 Color
200 Programme <.......>
If Yes selected, totaly 200 programmes can be used.
TouchPad <.......>
If Yes selected, TouchPad can be used.
Teletext Options
TXT Darkness <.......> Value between 0 to +63
TXT Type <.......>
Fasttext&Toptext
No
Default
Fastext
Toptext
TXT Language <.......>
Menu
West
East
Cyrillic
Turk/Gre
Arabic
Persian
Auto
No Txt Warning <.......>
If Yes selected, No Txt Transmission warning appears on
the screen when pressing txt button from RC.
Txt Subtitle <.......>
If Yes selected, Teletext subtitles can be seen.
Optional Features
Default Zoom <.......>
Menu
16:9
4:3
Panaromic
14:9 Zoom
Menu Timeout <.......>
Menu
15 Sec
30 Sec
60 Sec
No Time
Backlight <.......>
If Yes selected, Backlight feature is active.
100 Step Slider <.......>
If Yes selected, 64 step sliders will become 100 step sliders.
Analog USB Enabled <.......>
If Yes selected, Analog USB option is active.
Menu Double Size <.......>
If Yes selected, menu sizes increases.
CEC Enable <.......>
If Yes selected, CEC feature is active.
Digital USB Hotplug <.......>
If Yes selected, Digital USB Hotplug feature is active.
PIP Options
Pip <......>
AV PIP
No PIP
PC PIP
Hotel Options <......>
Hotel TV <......>
If Yes selected, Hotel TV feature is active.
IR Smartloader <......>
If Yes selected, IR Smartloader feature is active.
16.5. External Source Settings

TV <.......>
DTV <.......>
Ext 2 <.......>
Ext 2 S <.......>
FAV <.......>
BAV <.......>
S-Video <.......>
HDMI 1 <.......>
HDMI 2 <.......>
HDMI 3 <.......>
HDMI 4 <.......>
YPbPr <.......>
PC <.......>
16.6. Preset
User Ad.j
ADC Adj.
Service Adj.
All Adj.
Init Factory Channels.
16.7. NVM Edit

NVM-edit addr. (hex)
NVM-edit data (hex)
NVM-data dec
16.8. Programming
HDMI DDC Update Mode <.......>
HDCP Key Update Mode <.......>
Software Bypass <.......>
If On selected, speaker effects are bypassed.
LVDS Clock Step <.......> Value between 0 to +255

Memory Clock Step <.......> Value between 0 to +255
DTV Download <.......>
If On selected, DTV software can be updated from SCART.
DSUB9 Download <.......>
If On selected, DTV software can be updated from DSUB9.
16.9. Diagnostic
Eeprom I2C
Tuner I2C
IF I2C
HDMI I2C
DTV RS232
16.10. Product Info
13. SOFTWARE UPDATE DESCRIPTION

13.1 17MB25 Analog Part Software Update With Bootloader Procedure
1.1 The File Types Used By The Bootloader
All file types that used by the bootloader software are listed below:
1. The Binary File : It has .bin extension and it is the tv application. Its size is 1920
Kb.
2. The Config Binary File : It has .cin extension and it is the config of the tv
application. Its size may be 64 Kb or a few times 64 Kb.
3. The Test Script File : It has .txt extension and it is the test script that is parsed
and executed by the bootloader. It dont have to be any times of 64 Kb.
4. The Test Binary File : It has .tin extension and it is used and written by the test
groups. It is run to understand the problem part of the hardware.
Alltough a file that is used by the bootloader can be had any one of these extensions, its
name has to be VESTEL_S and it has to be located in the root directory of the usb
device.
1.2 Usage of The Bootloader

1. The starting to pass through : The chassis is only powered up.
2. The starting to download something : When chassis is powered up the menu key has
to be pushed.Before the chassis is powered up and if any usb device is plugged to the
usb port, the programme is downloaded from usb firstly.
Any usb device is plugged to usb port , user must open hyperterminal in the pc and
connect pc to chassis via Mstar debug tool and any one of scart,dsub9 or I2c
connectors. Serial connection settings are listed below:
- Bit per second: 115200

- Data bits: 8
- Parity: None
- Stop bits: 1
- Flow control: None
In this case the bootloader sofware puts C character to uart. After repeating C
characters are seen in the hyperterminal user can send any file to chassis by selecting
Transfer -> Send File menu item and choosing 1K Xmodem from protocol section.
Figure 1. The Sample Output Before Sending The File
2. EEProm update
To Update eeprom content via uart scart,dsub9 or i2c with Mstar tool can used.
Serial connection settings are listed below:

- Data bits: 8
- Parity: None
- Stop bits: 1
Programming menu item is choosed in the service menu and switch HDCP Key Update
Mode from off to on.
Figure 2. The Programming Service Menu
After then you must see Xmodem menu in the hyperterminal.To download hdcp key
press k or to download eeprom content press w.
Figure 3. Xmodem Menu
If the repeated C characters are seen you can transfer file content via select Transfer-
>Send File and choose Xmodem protocol and click the Send button.
Figure 4. The Starting To Send
16.2 17MB25 HDCP key upload procedure.

1) Turn on TV set.
2) Open a COM connection using fallowing parameters and select ISP COM Port
No
Baud Rate: 9600 bps
Data Bits: 8
Stop Bits: 1
Parity: None
Flow Control: None
3) Enter service menu by pressing 4 7 2 5 consecutively while main menu is

open
4) Select 9. Programming
5) Select HDMI HDCP Update Mode yes.
6) On Hyper Terminal Window press k
7) Click on send file under Transfer Tab.
8) Select Xmodem and choose the HDCP key to be uploaded.
9) Press send button
10)Restart TV set
13.3 17MB25 Digital Software Update From SCART
Adjusting DTV Download Mode:
1. Power on the TV.
2. Exit the Stby Mode.
3. Enter the Tv Menu.
4. Enter 4725 for jumping to Service Settings.
5. Select 8. Programming step.
6. Change 6. DTV Download to On.
7. Switch to the Stby mode.
Adjusting HyperTerminal:
1. Connect the MB25 SCART Interface to SCART1 (bottom SCART plug).
2. Also connect the MB25 SCART Interface to PC.
3. Open HyperTerminal.
4. Determine the COM settings listed and showed below.
Bit per second: 115200
Data bits: 8
Parity: None
Stop bits: 1
Flow control: None
COM Properties Window
6. Click OK.
Software Updating Procedure
1. In the HyperTerminal Menu, click the Connect button.
3. The Space button on the keyboard must be pressed, when the following window can
be seen.
Selection Window
4. Press the 2 button on the keyboard for choosing 2. Upgrade Application with
Xmodem.
5. Repeating C characters are seen in the HyperTerminal menu.
The Sample Output Before Sending The File

6. Click the Send button on the HyperTerminal
7. Select the Filename xxxx_slot1.img using Browse.
8. Choose the 1K Xmodem from Protocol option.
Selection of File
File and Protocol Selection Window
Note: In the Software updating Procedure section, when the first C character is seen,
the filename selection process must be finished before 10 seconds. If the process can
not be finished, the file sending operation will be cancelled. The following figure shows
this situation.
Capture of Receving Data Failing
9. When sending the file the following window must be seen.
Capture of Sending Process
10. After the sending process the following HyperTerminal window must be seen.
Capture of End of The Sending Process
11. For sending second program file, the Software Updating Procedure must be
repeated from the step X. Select the Filename xxxx_slot2.img using Browse.
12. After sending the second program file, the Software Updating Procedure will be
succesful.
Note: After the File Sending Process,

1. Upgrade Application with FUM
2. Upgrade Application with Xmodem, options must be seen.
End of The Sending Process

Checking Of The New Software
1. Turn off and on the TV.
2. Enter the Setup submenu in the DTV Menu.
3. Choose the Configuration option.
4. For controlling new software, check the Receiver Upgrade option.
13.4 17MB25 Digital Software Update From USB

Software upgrade is possible via USB disk by folowing the steps below.
1. Copy the bin file, including higher version than the software loaded in flash, into
the USB flash memory root directory. This file should be named up.bin.
2. Insert the USB disk.
3. Digital module performs version and CRC check. If version and CRC check is
successful, then a message prompt appears to notify user about new version. If
the user confirms loading of new version, upgrade.bin file is written into flash
unused slot.
4. Digital module disables the previous software in the flash and then a system
reset is performed.
5. After the reset, digital module starts with new software.
Revert operation:
With revert operation, it is possible to downgrade the software.

Revert operation is very similar to upgrade process. In the revert operation, file name
should be f_up.bin. Also user confirmation is not asked.
1. Copy the bin file into the USB flash memory root directory. This file should be
named force_upgrade.bin.
3. A lower version than the software in flash can be loaded with revert operation.
Digital module performs only CRC check. If CRC check is successful, then
force_upgrade.bin file is written into flash unused slot.
4. Digital module disables the previous software in the flash.
5. A message prompt is displayed to notify user about end of revert process.
6. Power off/on is required to start digital module with the new software.
For controlling new software, check the Receiver Upgrade option.
New Zelland
Australia
No
DK<.....>
I<.....>
L<.....>
Equalizer <.....>
If Yes selected, Equalizer item is seen in Sound menu.
Headphone <.....>
If Yes selected, Headphone item is seen in Sound menu.
Power On/Off Melody <.....>
If Yes selected, when power on/off conditions, the power on/off
melody can be heard.
Dynamic Bass <.....>Value between 0 to 12
Effect<.....> Value between 0 to 7
Audio Delay ,offset <.....> Value between 0 to 190
Audio Setup Cont...2
Carrier mute<.......> Value between 0 to 28
Headphone Sound Select <.......>
Always Active Select
Always Inactive Select
Menu
Always Main Menu
Always PIP/PAP Window
Sound Mode Detect Time <.......> Value between 0 to 255
Noise Reduction Threshold <.......> Value between 0 to 255
Noise Reduction Time <.......> Value between 0 to 15
AVL Attack Time <.......> Value between 0 to 255
AVL Release Time <.......> Value between 0 to 255
Prescales ( AVL On)
Prescales ( AVL Off)
Clipping Levels ( AVL On)
Clipping Levels ( AVL Off)
16.3. Service Scan/Tuning Setup

First Search for L/L <.......>
ATS Delay Time (ms) <.......> Value between 0 to +200
Main Tuner Setup
Tuner Type
LC_TDTC_GXX1D
Thomson DTT7543X
Philips TD1318AF-3
Samsung DTOs403LH172A
Generic ( Analog Only)
Control Byte <.......> Value between 0 to +255
Low-Mid Low Byte <.......>
Low-Mid High Byte <.......>
Mid-High Low Byte <.......>
Mid-High High Byte <.......>
S Band TOP <.......>
VIF TOP <.......> Value between 0 to +15
VIF TOP SECAM <.......> Value between 0 to +15
VIF TOP DK<.......> Value between 0 to +15
Synch Threshold<.......> Value between 0 to +40
16.4. Options
Options-1
Power Up
Standby
Last state
TV Open Mode
Source
1st TV
Last Tv
First APS <.......>
If Yes selected, first time TV opens by asking APS.
APS Volume <.......> Value between 0 to +63
Burn In Mode <.......>
If Yes selected, TV opens with Burn-In mode. This mode is
used in manufacturing.
APS Test
Autostore <.......>
If Yes selected, Channel is automatically stored.
Unicode Enabled <.......>
If Yes selected,Unicode characters can be read in the USB
Files.
Options-2
Source List menu <.......>
If Yes selected, Sorce List Menu appears on the screen
when press source button.
RS232 for B2B <.......>
If Yes selected, Remote Control commandsthe TV via
RS232 and vice versa.
RC Select <.......>
RC Group 1
RC Group 2
RC Group 3
RC Group 4
RC Group 5
RC Group 6
Double Digit Key <.......>
If Yes selected, Double Digit Button on RC activates.
Protection <.......>
If Yes selected,short circuit protection activates.
Led Type <.......>
1 Led 1 Color
1 Led 2 Color
2 Led 2 Color
1 Led 3 Color
2 Led 3 Color
200 Programme <.......>
If Yes selected, totaly 200 programmes can be used.
TouchPad <.......>
If Yes selected, TouchPad can be used.
Teletext Options
TXT Darkness <.......> Value between 0 to +63
TXT Type <.......>
Fasttext&Toptext
No
Default
Fastext
Toptext
TXT Language <.......>
Menu
West
East
Cyrillic
Turk/Gre
Arabic
Persian
Auto
No Txt Warning <.......>
If Yes selected, No Txt Transmission warning appears on
the screen when pressing txt button from RC.
Txt Subtitle <.......>
If Yes selected, Teletext subtitles can be seen.
Optional Features
Default Zoom <.......>
Menu
16:9
4:3
Panaromic
14:9 Zoom
Menu Timeout <.......>
Menu
15 Sec
30 Sec
60 Sec
No Time
Backlight <.......>
If Yes selected, Backlight feature is active.
100 Step Slider <.......>
If Yes selected, 64 step sliders will become 100 step sliders.
Analog USB Enabled <.......>
If Yes selected, Analog USB option is active.
Menu Double Size <.......>
If Yes selected, menu sizes increases.
CEC Enable <.......>
If Yes selected, CEC feature is active.
Digital USB Hotplug <.......>
If Yes selected, Digital USB Hotplug feature is active.
PIP Options
Pip <......>
AV PIP
No PIP
PC PIP
Hotel Options <......>
Hotel TV <......>
If Yes selected, Hotel TV feature is active.
IR Smartloader <......>
If Yes selected, IR Smartloader feature is active.
16.5. External Source Settings

TV <.......>
DTV <.......>
Ext 2 <.......>
Ext 2 S <.......>
FAV <.......>
BAV <.......>
S-Video <.......>
HDMI 1 <.......>
HDMI 2 <.......>
HDMI 3 <.......>
HDMI 4 <.......>
YPbPr <.......>
PC <.......>
16.6. Preset
User Ad.j
ADC Adj.
Service Adj.
All Adj.
Init Factory Channels.
16.7. NVM Edit

NVM-edit addr. (hex)
NVM-edit data (hex)
NVM-data dec
16.8. Programming
HDMI DDC Update Mode <.......>
HDCP Key Update Mode <.......>
Software Bypass <.......>
If On selected, speaker effects are bypassed.
LVDS Clock Step <.......> Value between 0 to +255

Memory Clock Step <.......> Value between 0 to +255
DTV Download <.......>
If On selected, DTV software can be updated from SCART.
DSUB9 Download <.......>
If On selected, DTV software can be updated from DSUB9.
16.9. Diagnostic
Eeprom I2C
Tuner I2C
IF I2C
HDMI I2C
DTV RS232
16.10. Product Info
17. SOFTWARE UPDATE DESCRIPTION

16.1 17MB25 Analog Part Software Update With Bootloader Procedure
1.1 The File Types Used By The Bootloader
All file types that used by the bootloader software are listed below:
1. The Binary File : It has .bin extension and it is the tv application. Its size is 1920
Kb.
2. The Config Binary File : It has .cin extension and it is the config of the tv
application. Its size may be 64 Kb or a few times 64 Kb.
3. The Test Script File : It has .txt extension and it is the test script that is parsed
and executed by the bootloader. It dont have to be any times of 64 Kb.
4. The Test Binary File : It has .tin extension and it is used and written by the test
groups. It is run to understand the problem part of the hardware.
Alltough a file that is used by the bootloader can be had any one of these extensions, its
name has to be VESTEL_S and it has to be located in the root directory of the usb
device.
1.2 Usage of The Bootloader

1. The starting to pass through : The chassis is only powered up.
2. The starting to download something : When chassis is powered up the menu key has
to be pushed.Before the chassis is powered up and if any usb device is plugged to the
usb port, the programme is downloaded from usb firstly.
Any usb device is plugged to usb port , user must open hyperterminal in the pc and
connect pc to chassis via Mstar debug tool and any one of scart,dsub9 or I2c
connectors. Serial connection settings are listed below:

- Data bits: 8
- Parity: None
- Stop bits: 1
In this case the bootloader sofware puts C character to uart. After repeating C
characters are seen in the hyperterminal user can send any file to chassis by selecting
Transfer -> Send File menu item and choosing 1K Xmodem from protocol section.
Figure 1. The Sample Output Before Sending The File
2. EEProm update
To Update eeprom content via uart scart,dsub9 or i2c with Mstar tool can used.
Serial connection settings are listed below:

- Data bits: 8
- Parity: None
- Stop bits: 1
Programming menu item is choosed in the service menu and switch HDCP Key Update
Mode from off to on.
Figure 2. The Programming Service Menu
After then you must see Xmodem menu in the hyperterminal.To download hdcp key
press k or to download eeprom content press w.
Figure 3. Xmodem Menu
If the repeated C characters are seen you can transfer file content via select Transfer-
>Send File and choose Xmodem protocol and click the Send button.
Figure 4. The Starting To Send
16.2 17MB25 HDCP key upload procedure.

1) Turn on TV set.
2) Open a COM connection using fallowing parameters and select ISP COM Port
No
Baud Rate: 9600 bps
Data Bits: 8
Stop Bits: 1
Parity: None
Flow Control: None
3) Enter service menu by pressing 4 7 2 5 consecutively while main menu is

open
4) Select 9. Programming
5) Select HDMI HDCP Update Mode yes.
6) On Hyper Terminal Window press k
7) Click on send file under Transfer Tab.
8) Select Xmodem and choose the HDCP key to be uploaded.
9) Press send button
10)Restart TV set
16.3 17MB25 Digital Software Update From SCART
Adjusting DTV Download Mode:
1. Power on the TV.
3. Enter the Tv Menu.
4. Enter 4725 for jumping to Service Settings.
5. Select 8. Programming step.
6. Change 6. DTV Download to On.
7. Switch to the Stby mode.
Adjusting HyperTerminal:
1. Connect the MB25 SCART Interface to SCART1 (bottom SCART plug).
2. Also connect the MB25 SCART Interface to PC.
3. Open HyperTerminal.
4. Determine the COM settings listed and showed below.
Bit per second: 115200
Data bits: 8
Parity: None
Stop bits: 1
Flow control: None
COM Properties Window
6. Click OK.
Software Updating Procedure
1. In the HyperTerminal Menu, click the Connect button.
3. The Space button on the keyboard must be pressed, when the following window can
be seen.
Selection Window
4. Press the 2 button on the keyboard for choosing 2. Upgrade Application with
Xmodem.
5. Repeating C characters are seen in the HyperTerminal menu.
The Sample Output Before Sending The File

6. Click the Send button on the HyperTerminal
7. Select the Filename xxxx_slot1.img using Browse.
8. Choose the 1K Xmodem from Protocol option.
Selection of File
File and Protocol Selection Window
Note: In the Software updating Procedure section, when the first C character is seen,
the filename selection process must be finished before 10 seconds. If the process can
not be finished, the file sending operation will be cancelled. The following figure shows
this situation.
Capture of Receving Data Failing
9. When sending the file the following window must be seen.
Capture of Sending Process
10. After the sending process the following HyperTerminal window must be seen.
Capture of End of The Sending Process
11. For sending second program file, the Software Updating Procedure must be
repeated from the step X. Select the Filename xxxx_slot2.img using Browse.
12. After sending the second program file, the Software Updating Procedure will be
succesful.
Note: After the File Sending Process,

1. Upgrade Application with FUM
2. Upgrade Application with Xmodem, options must be seen.
End of The Sending Process

Checking Of The New Software
1. Turn off and on the TV.
2. Enter the Setup submenu in the DTV Menu.
3. Choose the Configuration option.
4. For controlling new software, check the Receiver Upgrade option.
16.4 17MB25 Digital Software Update From USB

Software upgrade is possible via USB disk by folowing the steps below.
1. Copy the bin file, including higher version than the software loaded in flash, into
the USB flash memory root directory. This file should be named up.bin.
3. Digital module performs version and CRC check. If version and CRC check is
successful, then a message prompt appears to notify user about new version. If
the user confirms loading of new version, upgrade.bin file is written into flash
unused slot.
4. Digital module disables the previous software in the flash and then a system
reset is performed.
5. After the reset, digital module starts with new software.
Revert operation:
With revert operation, it is possible to downgrade the software.

Revert operation is very similar to upgrade process. In the revert operation, file name
should be f_up.bin. Also user confirmation is not asked.
1. Copy the bin file into the USB flash memory root directory. This file should be
named force_upgrade.bin.
3. A lower version than the software in flash can be loaded with revert operation.
Digital module performs only CRC check. If CRC check is successful, then
force_upgrade.bin file is written into flash unused slot.
4. Digital module disables the previous software in the flash.
5. A message prompt is displayed to notify user about end of revert process.
6. Power off/on is required to start digital module with the new software.
For controlling new software, check the Receiver Upgrade option.
12. BLOCK DIAGRAMS
12.1 General Block Diagram
31
12.2 Integrated DVB-T Receiver Block Diagram
32
12.3 MSTAR Block Diagram
33
1 2 3 4 5 6 7 8
TUNER SUPPLY OPSION

LG
AIF 12 ANALOG_IF
ACTIVE ANTENNA
A DIF1 11 DIGITAL_IF_N
1
R482
2
A
4R7
DIF2 U123
DIGITAL_IF_P
TU102 TDTC-G101D
10 2R1 LM1117
F116
IF_AGC IF_AGC_DVB_IN 5V_TUN 8V_VCC
1 2
3 IN OUT 2 5V_TUN
9 1 2
5V_TUN 330R C600

TH101 1
GND VOUT C360 C134
2
2 2
AS 8 ADDRESS_SEL_TUNER 47u 10u 100n
R408
330R
2
16V 1 4 1
10V
1
10V
NC Near Tuner
7
2
OVER_CUR_DETECT supply pin
1
R502 F234
R501
10k
1 2
B2 6 5V_TUN 1
10k
2
R460
330R 1
1k
2
2 1
SDA_TUNER S105
1
SDA 5 R622
TP151
3
1
1
1k
2 !!!En az 1.8 cm2 altta ve stte soutma alan braklmal.
SCL 4 SCL_TUNER Q102 3
FDN336P BC848B R503

2 2 1 2
RF_AGC RF_AGC 10k ANT_CTRL
1
3 Q115
ACT_ANT Connect if "33V Integrated Tuner" is used!
B1 2 33V_TUNER 1
AGC AND I2C SWITCH PART
2
B C359 B
R504
10k
2
ANT_PWR ACT_ANT 10u

1 1
10V S102 R624

1 2
1
1 2
DIGITAL_IF_N 33V_TUNER 1k 5V_TUN
5V_VCC C532 2
2
1u
C675
2
47p
50V
L117
50V
1u
Samsung/Thomson C128
1
IFOUT- 11 D121 1 2
1
1 2
R505 100n
IFOUT+ 10 DIGITAL_IF_P 1N4148 IF_AGC_DVB_IN
1
10k
2
IF_AGC_DVB
U115 10V
R111 10V
33V_TUNER 1 2
100n
1
74HCT4053
VT 9 RF_AGC_A 12k T_AGC 2
C448 C136 SCL_TUN_DVB 1 2Y1 VCC 16

DTOS403LH172A
IF_AGC IF_AGC_DVB_IN 47u SCL 2 2Y0 2Z 15 SCL_TUN

8
N.C. 2
16V RF_AGC_DVB 3 3Y1 1Z 14 SDA_TUN
+5V 5V_TUN RF_AGC 4 3Z 1Y1 13 SDA_TUN_DVB
7
This part must be placed near the tuner
TU101
RF_AGC_A 5 3Y0 1Y0 12 SDA

6 11 S101 1 2
AIF_OUT 6 ANALOG_IF 10V 1
S103 E S1
100n 1 2
7 10
C SDA_TUNER
R126
1 2
C137
2
8
VEE S2
9 1
R254
2
5V_VCC
C
SDA 5 SCL_TUNER 47R SCL_TUN GND S3 4k7
NEAR THE TUNER
2
C586
SCL 4 SCL_TUNER 47p
1
50V 3
SAS 3 ADDRESS_SEL_TUNER R595

R127 Q116 2 1
22k
2
IDTV_SW
1 2
RF_AGC S104 1 2 BC848B

2 RF_AGC SDA_TUNER 47R SDA_TUN
1
2
C587
BA ACT_ANT 47p
1 1
50V
D D
WARNING!!! Saw filter outputs must be close the chip

5V_TUN 5V_TUN
C654 C133 C597
C676
100p
C467 2
50V
2 2
C132 220u 220n 220p

1 1 1
U138
1
1 2
6V3 10V 50V
2
2
R473
R231
10u 1 2
MST6WB7GQ-3
6k8
3k3
10V 100n F187

WARNING!!! This part must be close to chip 3V3_STBY 1 2
62 AVDD_MPLL
10V 330R
C363 C131
1
C546 Z101 63
1 2 1 2
VR27 4
BA782 1 IN1 OUT1 4 SIFP
1 2
K9656M 10u 100n 64

10n 2 1
10V 10V VR12
2
D145 2 IN2 OUT2 5

SIFM F184
R474
16V
6k8
GND 3V3_VCC 1 2
65
R380 5V_TUN AVDD_RXS
3
8V_VCC 75R 330R
C364
C130
100n
2
2
10u
10V
10V
66
1
1 C520 GND_RXS
1
2
1
47u
R252
L114
680R
R735
1
4k7
67
1u
E 2
16V SIFP SIFP E
C135
100n
R594
22k
10V
68
1
SIFM
2
R483 R125 SIFM

Q140
2
1 2 1 2
1k2 47R R209
3
SIF_CTL 1
100k
2 1
VIFM 69 VIFM
L111 C545 3 BSN20
R680
2
ANALOG_IF 1 2 1
56R
2 2
Q144 C361 C129 VIFP 70 VIFP
R210
100k
1 2
1u BF799
10n 1
N.C.
1 2 1 2
71
16V 10u 100n GND_RXV
1
F185 10V 10V

2
VIFM 3V3_VCC 1 2
72 AVDD_RXV
R623
R384
10R
330R
1k
F186
C547 Z102 5V_TUN 1 2
4k7 73
1 2 TAGC
2
1 IN1 OUT1 4 330R R253

1
C510
L104
N.C.
1 2
2u2
2
K3958M 100n
10n 2 IN2 OUT2 5 1
16V 10V T_AGC

GND
1
3
VIFP
WARNING!!! This part must be close to chip
F F
VESTEL PROJECT NAME : 17MB25 A3

SCH NAME :ANALOG IF SHEET:1 OF:11
DRAWN BY :NDER GEN 4-28-2008_16:47
1 2 3 4 5 6 7 8 AX M
1 2 3 4 5 6 7 8
5V_TUN
2
2 NUP4004M5
TP101
BAV70
1
D146
2 NUP4004M5
TP240
D112 3
D106 5
2 1
C138
2
2
D102 5
1
C5V6 100n
C105
220p
R506
R507
R511
2
50V
10k
10k
10k
1
C106 R120 10V VGA_DDC_5V
C640
C18V
D176
21
!
2
1
3
10u
25V
VGA CONNECTOR
1
C658
1
1 2
1 2 10k
1
3
4
220n
1
A 20 SC1_CVBS_IN 220p 25V 8 VCC
A
50V D115 FS101 15 R584 A0 1
2 1
SC1_CVBS_OUT 12 1 2
12V_VCC 100R U112
19 8 R1 1 7 WP
C5V6 C15V 4A/24VDC R861 14 A1 2
50V 2
75R 1 PROG_EN 11 1
10k
2
3V3_VCC ST24LC21
18 220p 7 R2 2 6 SCL
D111 R644 1 2
R872 13 A2 3
75R 2 1 2 1 D163 1 2
1 2 D117 10 22k DVD_SENSE
17 6 R3 3 5 SDA GND 4
2 1
R640 C103 C5V6 F242 12
47R 9
1 2
C648 DVD_C_IN R805
SC1_FB C5V6
1
2 1 1 2
16
1
R128 75R 600R 4k7 5 R4 4
TX/SDA_SC 11
R712
R711
2 1 1 2
2k2
2k2
50V
TP103
TP104
TP102
TP105
SC1_R R641 8 F243 C628
15 220p 1 2
27p
C649 50V DVD_Y_IN 10
2 1
600R
2
2 1
7
14 100n
C104 F244 1 2
9 VGA_DDC_5V VGA_VSNC
50V 6
1 2
27p DVD_IR 10V R349
13 220p
SCART LT1
600R 50V C650 8 1

100R
2
VGA_HSNC
SC101
2 1
5 1 2
12
C107 F245 27p 7
1 2
SC1_G 4 C651 50V DVD_AUD_R_IN
11 600R
B 75R 1 2
6 B
2 1 RX/SCL_SC 3 F246
10 R643 1 2
27p C652 DVD_AUD_L_IN
R596 D116 5
C439
C437
C438
50V
50V
50V
2
2
27p
27p
27p
1
22k
2
SC1_PIN8
2 1
2 600R 50V
9
1
D140 R255 C5V6 R129
1 2
4
2 1 1
4k7
2
1 1
47R
2
27p DVD_SPDIF
8 50V
C15V 3 VGA_B
220p
C114
CN111
1
50V
C140
R642
7
75R
50V 50V
2
SC1_B 2 VGA_G
6
220p 1n
2
100n
1
VGA INPUT
2 1 1 2
2
F196 10V 1 VGA_R
1 2
C108 C477 F198

5 600R 1 2
CN118
SC1_AUD_L_IN
NUP4004M5 2
1
3
4
5 D101
600R
4
1
F197
2
R219 DVD CONNECTION
1
100R
2
SC1_AUD_L_OUT
3 C478 600R
1 2
C484
2
1n 1 2
C 1 50V 1
F194
2
1n C
SC1_AUD_R_IN
600R 50V S-VIDEO INPUT
JK102
NUP4004M5 2
1
3
4
5 D103
F195 R213 S_VIDEO_C_IN 4 3 S_VIDEO_Y_IN

1 2 1
100R
2
SC1_AUD_R_OUT 1 2
SCART1 INPUT
2
600R C475
220p
C111
C5V6
D113
C5V6
D114
220p
C112
5
1
50V
50V
1 2
2
1n
1
50V
1
D169
C5V6
D168
C5V6
50V 50V
5V_VCC
F216
2 1 1n 27p
2
600R 2 1 2 1
F211 C473 JK101 C442

1 2
SAV_AUD_R_IN RCA_PR
600R 50V 6 75R
JK106 RED 1 2
2
1n 5 R637
D D
R683
33k
6 2 1
RCA_PB
RED 5 4
F212 C474 BLU 1
75R 2
1 2 3 R638 C365
1
SAV_AUD_L_IN
4 600R RCA_Y
WHT 3 2
1 2
GRN R639
C441
10u
50V
2
27p
1 1 2
SAV_CVBS 75R
R682
10V
33k
2
1
YLW
C113
220p
1
50V
50V 1 C440
2 NUP4004M5
D105 5
4
3
1
1n 50V
1
F207 2 1
2 1 1 2 220p
600R 1 2
27p
C488 50V
F204 R217 C115
1 2 1 2
LINE_R_OUT D173
100R JK104 F210 2 1
600R 1 2
SPDIF_OUT_COAXIAL
C489 6 600R C5V6
BLK
JK105
1 2
5 F208 SIDE AV INPUT YPBPR INPUT
4 1 2
RED 3 1n YPBPR_AUD_R_IN
F205 4 600R C479
R216 50V RED
1 2
LINE_L_OUT 3
E E
5V_SPDIF
1 2
100R 1 2
2 600R
WHT 1 2 1n
WHT F209 50V
1 1 2
YPBPR_AUD_L_IN
2
600R C480
C5V6
D159
C5V6
D158
1 2
2
C5V6
D171
1n
2
1
2
F215
600R
D172 50V
R804
4k7
2 1
1
C5V6 3
1
C627
1
LINE OUTPUT 2
D170
1
COAXIAL SPDIF OUTPUT Q117 2 1
R464
2
SPDIF_OUT
R400 1 2 100R
BC848B
SUBWOOFER OUTPUT C5V6 YPBPR/PC LINE INPUT 1
1k
2
220p
C116
100n
1
50V
1
R242
10V
4k7
C229
2
F118
SPDIF_OUT_COAXIAL 1 2 1 2
5V_VCC 1 2
5V_SPDIF
S216
1
100n 330R
C366
2
10u
10V
10V
1
F SPDIF OUTPUT INTERFACE F

SCH NAME :A/V INTERFACE SHEET:2 OF:11
DRAWN BY :ONDER GENC 4-28-2008_15:57
1 2 3 4 5 6 7 8 AX M
1 2 3 4 5 6 7 8
AVDD_AU
U138 C148 AUDIO INPUT VOLTAGE DIVISION AND DC BLOCK
VIDEO TERMINATIONS AND DIFFERENTIAL TRACING 10V
Place close to Paulo
Place 75R termination resistors MST6WB7GQ-3 2 1
C512 F217 C340
100n 10u 2 1 R607
close to Paulo reference GNDs VGA_HSNC 17 HSYNC1 AVDD_AU_1 74
10V
10V 2 1
1 2
600R
8V_VCC
10V LINE_IN_0L
1
22k
2
SC1_AUD_L_IN
10u SC1_AUD_R_OUT R691
2 C121 100n 10u
18 75 2 1
C375 16V
1
33k
2
1u
VGA_VSNC VSYNC1 GND5 2 1
16V
16V C152 10V 1 2 R692 SC1_AUD_L_OUT C493
R513
10u C369 C120
2 1
47n 19 76 220p 33k C374
A 1
R143
2 1 2
C0
1 2
C151
VCLAMP AUVRM
2 1
50V 1 2
1
10k
2
1 2 A
DVD_C_IN 47R 100n 1n
75R 20 REFP AUVRP 77 R678 220p C341
1 2
C432 10V 1 2 C368 1
82k
2 1 OUT1 VDD 8 50V R606
R651 C150 C344 50V LINE_IN_0R
1
22k
2
SC1_AUD_R_IN
100n C332 R739 U118 R677
R650 21 REFM AUVAG 78
10V 1 2
SC_1_R
1
20k
2 2 IN1- OUT2 7 1
82k
2
1u
1
75R
2
R142 C434
100n 1u TL062 R738 C335 16V
DVD_Y_IN 1
47R
2
Y0 BIN1P 22 BIN1P AVDD_AU_2 79 AVDD_AU 1u R514 C492
1 2
10V 16V V+ 3 IN1+ IN2- 6 1
20k
2
SC1_L
16V 1
10k
2
47n 23 80
1 2
SOGIN1 SOGIN1 LINE_IN_0L LINE_IN_0L 4 VSS 1u

16V IN2+ 5 V+ 16V C338 1n
16V 50V R605
R653 GIN1P 24 GIN1P LINE_IN_0R 81 LINE_IN_0R LINE_IN_1L
1
22k
2
DVD_AUD_L_IN
1 2 47n
75R 1u
S_VIDEO_C_IN 47R 1 2
C1 RIN1P 25 RIN1P LINE_IN_1L 82 LINE_IN_1L

1 2
16V
R145 C423 R133 C420 R515 C495
1
47R
2
1 2
26 BIN0M LINE_IN_1R 83 LINE_IN_1R
1
10k
2
1 2
R652 C149
1 2
C422 47n 27 84 1
S106 2
C339 1n
75R R144 BIN0P 16V BIN0P AUCOM 1 2
50V R603
S_VIDEO_Y_IN 1
47R
2
Y1 R134 C419 LINE_IN_1R
1
22k
2
DVD_AUD_R_IN
1 2
1 2 28 85 100n R690 2
33k 1
47n 47R 1 2
GIN0M LINE_IN_2L 10V LINE_IN_2L 10V 2 1
R689 1u
33k
B 16V 47n 29 86
10u
R155 10V 16V
C494
B
R654 GIN0P 16V GIN0P LINE_IN_2R LINE_IN_2R LINE_R_OUT 2 1 1 2 10u R516
1 2
C424 47R F219 R153 1 2
75R 1 2 1 2 2 1
LINE_L_OUT 10k 1 2
SC1_CVBS_IN 47R SOGIN0 30 SOGIN0 LINE_IN_3L 87 C372 8V_VCC 47R

1 2 1 2 CVBS1 LINE_IN_3L 50V C511600R 1n
R146 220p C371 C336
47n 50V R601
RIN0P 31 RIN0P LINE_IN_3R 88 LINE_IN_3R
3 1 2 3
LINE_IN_2L
1
22k
2
YPBPR_AUD_L_IN
16V R522
1 2
50V R521
R686 BC848B 100n 220p BC848B
C612 32 89 POP_MUTE
1
10k
2 2
C119 16V
2 2
10k
1
POP_MUTE 1u
R773 AVDD_33 AVDD_33_3 LINE_IN_MONO 1
33k
2
Q121 1 2
Q120 16V
1 2
SOGIN0 C143 R676 C497
470R 1 2 R802 1 1 2 1 OUT1 VDD 8
1 R517
33 GND3 LINE_OUT_3L 90 1 2 82k C118 3k3 1 2
1n DSP_CH2_L 3k3 2 1 10k

1 2
U117 R675 R801
1 2
100n 2 IN1- OUT2 7 1

82k
2
1n
R649 34 HSYNC0 LINE_OUT_3R 91 DSP_CH2_R C337
50V 10V TL062 R736 C330 50V R600
2
75R
1
R141 C433 LINE_IN_2R
1
22k
2
YPBPR_AUD_R_IN
C331 R737 V+ 3 IN1+ IN2- 6 1
20k
2
LINE_OUT_L
SAV_CVBS 1
47R
2
CVBS2 SC1_FB 35 VSYNC0 LINE_OUT_2L 92 DSP_CH4_L
1 2
LINE_OUT_R
1
20k
2
1u
R687 4 VSS 1u
47n 1 2 36 93 1u IN2+ 5 V+ 16V
16V
C496
R664 16V 33k VSYNC2 LINE_OUT_2R DSP_CH4_R R518
2
75R
1
R140 C435 16V 1
10k
2
1 2
DVB_CVBS 1
47R
2
CVBS3 BIN2P 37 BIN2P LINE_OUT_1L 94 DSP_CH1_L
1 2
C343 1n
47n 50V R599
38 95
C 2
R665
1
16V SOGIN2 SOGIN2 LINE_OUT_1R DSP_CH1_R LINE_IN_3L
1
22k
2
SAV_AUD_L_IN C
75R 1u
R137 C421 GIN2P 39 GIN2P LINE_OUT_0L 96 DSP_CH3_L 16V
SC1_B 1
47R
2
1 2
BIN0P R519 C498
RIN2P 40 RIN2P LINE_OUT_0R 97 DSP_CH3_R
1
10k
2
47n 1 2
16V 1n
C1 41 C1 C342
50V R598
R138 C418 LINE_IN_3R
1
22k
2
SAV_AUD_R_IN
42 V+ 1
33k 2 8V_VCC
SC1_G
1
47R
2
GIN0P Y1 Y1 R685 1u
AVDD_AU
1 2
C327
C367
1
2
10u
10V
R667 47n 16V
43 1u
R684
2 1
C0 C0 C499
33k
75R 16V R520
2
16V 1 2
10k 1 2
Y0 44 Pin79
AVDD_AU DECOUPLING CAPACITORS

Y0
C142
100n
1n
1
10V
R666 50V
2
75R
1
CVBS3 45 CVBS3
C417
1
R139
SC1_R
1
47R
2
1 2
RIN0P CVBS2 46 CVBS2 C443 R627
DVB/YPBPR_SW
1
1k
2 10V
47n 47 Pin74
2 1
100n DVB/YPBPR SWITCH
CVBS1 CVBS1
C145
100n
16V 27p U129
10V
C425 2 1
D 1
R132
2 48 DVB_PR
50V PI5V330 D
R656 47R 1 2
VCOM1 S109 C147 F151
C428 1 2
1 16 1 2
5V_VCC C445
2
1
2 1
75R R149 R512 47n R661 S110 IN VCC
SW_PB 1
47R
2
BIN2P 1
10k
2 49 CVBS0 1
75R
2 1 2
2 S1A EN 15 330R
16V
2
1 2 1 2
R131 C416 RCA_PR 3 S2A S1D 14

F120
330R
47n 50 4 13 27p
1
47R
2
VCOM0 SW_PR DA S2D DVB_PB
16V 1 2
5 12
50V
DVB_Y S1B DD RCA_PB R663
C426 47n 51 C444 6 11
AVDD_33 AVDD_33_4 RCA_Y S2B S1C 2 1
1
R148 S108 S107 S111 75R

SW_Y 1
47R
2
GIN2P 16V 1 2
7 DB S2C 10 1 2 1 2
1 2
C144 52
2 1
1
S112 2
8 9
47n CVBSOUT1 27p GND DC SW_PB
3V3_VCC
16V 2 1 R662 50V

53 CVBSOUT0 1
75R
2
SW_Y
C490 100n
R657 R403 10V
2
75R
1 1
470R
2
1 2
SOGIN2 54 GND4
1n R228
1 2
50V DSP_CH2_L 100R HP_L R227

1 2
R655 R351 DSP_CH1_L 100R MAIN_L
C555
1
10n
16V
2
75R
1
R147 C427 CVBS0_OUT 1
100R
2
22k
C553
1 2
10n
16V
SW_PR RIN2P R419 22k
2
1 2
47R 1 2 1 2
R418
2
E 47n E
16V F119 R229
1 2
R659 5V_TUN 1 2 DSP_CH2_R 100R HP_R R226
2
75R
1
R150 C429 330R
SCART VIDEO OUTPUT AMPLIFIERS DSP_CH1_R
1
100R
2
MAIN_R
C554
1
10n
16V
VGA_B 1 2
BIN1P C326 22k
2
47R
C552
1 2 1 2
10n
16V
1u
R402
470R
R674
R420 22k
2
39k
1 2
47n 16V R417
2
16V 1
1
R151 C431 Q146

2
VGA_G 1
47R
2
1 2
GIN1P BC858B R224 R223
3 1 2 1 2
47n 3
C378 DSP_CH4_L 100R LINE_OUT_L DSP_CH3_L 100R SC1_L
Q119 C550
C549
16V 2
CVBS0_OUT
10n
16V
BC848B
2 1
2 1 1
22k 2 1
22k 2
C491 10u R415 R414
2
R658 R404 1
10n
2 1 1 2
SOGIN1 R646 R620 10V
75R 470R 1 2
SC1_CVBS_OUT 1 2 1 2
16V
75R 300R
1n
1
50V R222
100R
R221
R467
75R 1 2
15k
R660 2 1 R225 DSP_CH3_R 100R SC_1_R

2
75R
1
R152 C430 R879 DSP_CH4_R
1
100R
2
LINE_OUT_R
C548
1
10n
16V
VGA_R RIN1P C551 22k
F 1
47R
2 2
1 2
F
2
1 2
22k R413
2
47n R806 Q154 2 1 1 2
16V 2N7002 R416

GAIN_SW1
1
4k7
2 1
10n
3
16V

AUDIO OUTPUT FILTERS SCH NAME :A/V INTERFACE SHEET:3 OF:11
Place close to Paulo
1 2 3 4 5 6 7 8 AX M
1 2 3 4 5 6 7 8
U138
MST6WB7GQ-3
A
HDMI1 HDMIA_C- 1 RXACKN USB20_REXT 191 1
R119
910R
2
A
1
CN121 2
HDMI Receiver In_B HDMIA_C+ RXACKP AVDD_USB 192 AVDD_USB
21
20 R385 3
1 2
GND1 USB20_DM 193
1 10R HDMIB_2+
2 R386 4
1 2
HDMIA_0- RXA0N USB20_DP 194
3 10R HDMIB_2- BAV70
4 10R HDMIB_1+ 5
D147 GND11 195
1 2
HDMIA_0+
HDMIA_5V
R387 RXA0P
5 R388 5V_VCC
6 1 2 2 1 HDMIB_5V
10R HDMIB_1-
HDMI1
6 VDDP2 196
3
10R AVDD_33 AVDD_33_1 VDDP
7 2 1 HDMIB_0+
5V_VCC
R394 TP134 1
8 R389 7
1 2 C153 HDMIA_1- RXA1N GND12 197
9
2
10R HDMIB_0- 2
100n
TP106
R257
10 10R
4k7
1 2 HDMIB_C+ 1
10V HDMIA_1+ 8 RXA1P VDDP3 216

11 R390 VDDP
2
R391
R875
1 2
12 10R HDMIB_C- 1 A0 VCC 8 9 USB_VBUS 217
1k
1
1 S218 2 GND2
13
2
CEC
U110
R808
14
4k7
R392 2 A1 WP 7 HDMIA_2- 10 USB_DM 218
1
1 2 HDMI_WP1 RXA2N
15 10R HDMIB_SCL HDMIA_HPD
10R 24LC02
B 16 1 2 HDMIB_SDA 3 A2 SCL 6 HDMIA_2+ 11 USB_DP 219 B
1
R393 HDMIB_SCL 3
RXA2P
17
18 R876
HDMIB_5V 4 VSS SDA 5 Q162 2 1 2 12 HPLUGA USB_CID 220
19 10R HDMIB_SDA 1k
1 2 HDMIB_HPD BC848B
R396 13 ICLK 231
1
AVDD_33_2
2
AVDD_33
1
R491
R492
47k
47k
R412
14 DI[0] 232
TP132
TP133
1 2
390R REXT
1
HDMIA_SDA 15 DDCDA_SDA DI[1] 233
C154 HDMIA_SCL 16 DDCDA_SCL DI[2] 234

1 2
282 VDDC5 DI[3] 235

100n
10V VDDC
HDMIB_C- 283 RXBCKN VDDP5 236 VDDP
HDMIB_C+ 284 RXBCKP DI[4] 237
AVDD_33 285 AVDD_33_5 DI[5] 238

C C
HDMIB_0- 286 RXB0N DI[6] 239
HDMIB_0+ 287 RXB0P DI[7] 240
HDMIB_5V
288 GND DI[8] 241
HDMI2 HDMIB_1- 289 RXB1N DI[9] 242
HDMIB_1+ 290 RXB1P
2
R629
291 GND18
1k
CN122 BAV70
21 D165
HDMIB_2- 292 RXB2N
1
20 R832 5V_VCC 2 1 HDMIA_5V HDMIB_HPD
3
1 2
1 10R HDMIA_2+ HDMIB_2+ 293 RXB2P
3
2 R833 TP203 1
3 1 2
HDMIA_2- R630
R834 10R C629 Q123 2 1 2 294 HPLUGB
2
4 1 2
HDMIA_1+
2
1k
10R 100n BC848B
TP205
R807
4k7
D 5 10V D
1
R835 1
HDMIB_SDA 295 DDCDB_SDA
R258
1 2
6 HDMIA_1-
4k7
10R R836
HDMI2
1 A0 VCC 8
1
1 2
7 10R HDMIA_0+ HDMIB_SCL 296 DDCDB_SCL
8 R837 U147
1
2
9 1
10R
2
R838 HDMIA_0- 2 A1 WP 7 HDMI_WP2
10 1
10R
2
HDMIA_C+ 24LC02
TP135
TP136
11 3 A2 SCL 6
5V_VCC
R839 HDMIA_SCL
1 2
12 S217 10R HDMIA_C-
13
1 2
CEC 4 VSS SDA 5 HDMIA_SDA

14 R840
1
1 2
15 10R R841 HDMIA_SCL
1
16 1
10R 2
HDMIA_SDA VDDP Pin196 Pin216 Pin236
TP206
TP204
17 2
C155 2
C156 2
C157
18 R843 HDMIA_5V 100n 100n 100n
1 1 1
1
19 10R 2
HDMIA_HPD 10V 10V 10V
2
2
R493
R494
47k
47k
CEC CIRCUIT AVDD_33 Pin6 Pin13 Pin285

1
E 1
S116 2
2
C158 2
C159 2
C160 E
1
100n 1
100n 1
100n
10V 10V 10V
2N7002
Q101
R829 R159
CEC 1
200R
2 1
100R
2
HDMI_CEC F124
3
1 2
3V3_VCC AVDD_USB
330R
1
2
C173
1
100n
10V
2
5V_STBY
R621
27k
1
3V3_STBY
F F

SCH NAME :HDMI&USB SHEET:4 OF:11
DRAWN BY :S.SEBNEM TAS & ULAS DERELI 4-28-2008_15:57
1 2 3 4 5 6 7 8 AX M
1 2 3 4 5 6 7 8
R277 N.C.
U138
3V3_STBY
2
4k7
1
4k7 3V3_STBY
MST6WB7GQ-3 2
R293
1
DVD_IR LED1 R276 55 GPIOL[0] SAR0 204 KEYBOARD_STBY

LED
2 1
3V3_STBY 4k7 3
BC848B LED2 56 GPIOL[1] SAR1 205 SC1_PIN8
TP241 Q124
CN119
1
R694
IR_IN 2 1
3V3_VCC 57 GPIOL[2] SAR2 206
5
1 3 4k7 DVD_SENSE R742
C447
A 1
S119
2 3V3_STBY
58
2
20k
1
A
2
1 2
SIF_CTL GPIOL[3] SAR3 207 OVER_CUR_DETECT
14.31818MHz
5V_STBY
S124
R263
1 2
27p
2
4k7
F247S118 N.C. STBY_ON/OFF_NOT R267 59 GPIOL[4] PWM0 208 For Internal CPU Selection
BACKLIGHT_DIM
R498
X104
R110
50V
2
47k
R524For Internal CPU Selection
1M
1 2
IR_IN R748 3V3_STBY

2
4k7
1
4k7 3V3_STBY 2 1
C653 600R 60 PWM1 209 3V3_STBY R279
2
1 2 2 1
47R XOUT 10k
1
C446 4k7
1
1 2 3V3_STBY
2 1
DVD_IR_ON/OFF 61 XIN DDCR_SDA 210 R287 SDA

27p 1 2
50V 4k7 3V3_STBY

2 1
27p 98
50V GPIOD[0] DDCR_SCL 211 R286 SCL
4k7
2
3 3 3V3_STBY
2 1
2
2
220R 99 DDCA_SDA 212
R830
GPIOD[1] R289
2
R421 R422 3V3_STBY TX/SDA
R528
R531
10k
10k
Q130 Q131
220R
R831
1 2 2 2 1 2
10k 10k
BC848B BC848B USB_DIG_OCD 100 GPIOD[2] DDCA_SCL 213 RX/SCL
1
1 1
4k7
1
1
2 1 3V3_STBY
2
DVB_RESET 101 GPIOD[3] INT 214 R290
R265
3 3
4k7
LED2
3V3_VCC 1
4k7 2 R827
LED1
2
Q148 Q149 2
R274 102 GPIOD[4] IRIN 215 1
100R
2
IR_IN
4k7 3V3_STBY
1
2 1
BC858B 1 1 BC858B STBY_ON/OFF 103 GPIOD[5] GPIOB[0] 221 R294

B SW_UPDATE_SELECT B
3 R165
2
STBY_ON/OFF_NOT R608 GAIN_SW1 R757 104 GPIOD[6] GPIOB[1] 222 1

47R
2
HP_DETECT
220R
R382
220R
R381
2
22k
1 2
Q125 3V3_VCC 1
4k7
2
1
4k7 2 3V3_VCC
BC848B 105 GPIOD[7] PWM2 223 R275
R288
1
3V3_VCC
1
2 1
4k7
3V3_STBY 1 2
DVB/YPBPR_SW R268 106 GPIOD[8] PWM3 224 AMP_MUTE
S117 3V3_VCC 2 1
4k7
5V_STBY 1 2
DVB_IRQ 107 GPIOD[9] GND14 225 2
4k7 1
3V3_STBY
S125 R278
VDDP 108 VDDP1 VDDP4 226 VDDP
R905
VDDP VDDC 109 GND6 GPIOT[0] 227 1
47R
2
OPTION2
2
C175 2
C177 2
C176 2
C178
VDDC 110 VDDC1 GPIOT[1] 228
MECH_SWITCH_ONBOARD
1
100n 1
100n 1
100n 1
100n R269 R291
10V 10V 10V 10V 5V_VCC 2
4k7
1
5V_TOLERANT R161
2
4k7
1
3V3_VCC
KEYBOARD_ONBOARD
1
IDTV_SW R270 111 GPIOD[10] GPIOT[2] 229 1
47R
2
DVB_RXD
R724
100k
2 1
3V3_STBY 4k7 R162 1
10V
PIN108 PIN272 PIN226 PIN110 PROTECT 112 GPIOD[11] GPIOT[3] 230 1
47R
2
R292 DVB_TXD 100n
C626
1
2
C182
2
C 2
4k7
1
3V3_VCC R356 C
C5V6
D161
1 2
2
C630 NVM_WP 113 GPIOD[12] HWRESET 243 100R
2 1
C5V6
D162
220p 100n C181 4k7

1
10V 3V3_STBY 2 1
114 GPIOD[13] VDDP7 272
1N4148
50V
2
3V3_STBY R271 VDDP
D167
D160 U103 2 1
2
R793 F248
1 2
24C32 100n 115 GPIOD[14] GND17 273
1 2
1
47R
2
KEYBOARD_STBY 10V DVD_IR_ON/OFF
C5V6 600R 1 E0 VCC 8
F250 2 7 116 GPIOD[15]
MECH_SWITCH 1 2 F249 E1 WC NVM_WP GPIOE[3] 274 1 2
MAX810
1 2
3V3_STBY 3 E2 SCL 6 SCL_NVM
600R 5V_TOLERANT GND RST MAX809LTR
600R 4 VSS SDA 5 SDA_NVM HDMI_WP1 117 GPIOD[16] GPIOE[2] 275 R261 VCC U130
2 1
3V3_STBY
CN130
5V_TOLERANT 4k7 3
TP110 118 GPIOD[17] GPIOE[1] 276 10V
1
TK_SUPPLY 1
HDMI_WP2 R262 SDA_NVM
TP239 TP111 TP109 2 1
3V3_STBY 100n
1
1 1
4k7
1
TP108 HDMI_CEC 149 GPIOR[0] GPIOE[0] 277 SCL_NVM 3V3_STBY
1 2
1
TP112 5V_TOLERANT R395 C183
HDMIB_5V
1
1k
2 150 GPIOR[1] GPIOM[0] 278 USB_ENABLE
5V_TOLERANT R877 R760
1 2 151 GPIOR[2] GPIOM[1] 279 2 1
5V_VCC
PROGRAMMING PART HDMIA_5V
3V3_STBY
2
R283
4k7
1
1k 4k7
PROTECT_PANEL 152 GPIOR[3] GPIOM[2] 280

D 3V3_VCC 2
R264
1
D
4k7
ANT_CTRL 153 GPIOR[4] GPIOM[3] 281
5V_STBY
154 GPIOR[5]
PROG_EN
155 GPIOR[6]
C180
156 GPIOR[7]
U127 1 2
S122
2
1 2
3V3_VCC
R280
R281
M74HC4052 100n
4k7
4k7
UART0_RXD0 157 GPIOR[8]

10V S121
1 2Y0 VCC 16 5V_STBY
1 2
5V_VCC
2 15 158 GPIOR[9]
1
R282 2Y2 1Y2

2
4k7
1
RX/SCL_SC 3 2Z 1Y1 14 TX/SDA
4 2Y3 1Z 13 TX/SDA_SC 159 GPIOR[10]
2
RX/SCL 5 2Y1 1Y0 12 UART0_TXD0 1
6 E 1Y3 11
1
R233
7 10 1 2 Q147
VEE S0 SW_UPDATE_SELECT 4k7
BC848B
Q128
2
8 9 BC858B
GND S1 CN133
R745
1k
4k7 C530 3
E 1
R284
2 5V_STBY
MECH_SWITCH_ONBOARD MEGA_DCR_OUT E
1 2 KEYBOARD_ONBOARD 1 2 R352
1
1 2
100R
S242
220p
3 4 TK_SUPPLY 50V S123 R353
1 2 1 2
100R
3
R232 R354 DIMMING

N.C. CN110 BACKLIGHT_DIM
S237 1
4k7
2 2
Q126 1
100R
2
1
S120 2 BC848B
5V_STBY 1 R355
C529 1 1
100R
2
S238 3
2 MEGA_DCR_IN R234
C383
1 2
10u
10V
R164
1
4k7
2 2
Q127
PUSH V+ AND V- AT THE SAME TIME FOR MENU 220p BC848B
RX/SCL
1
1 2
47R 3 50V
R163 PROG_EN KEYBOARD_ONBOARD C531 1
TX/SDA 1
47R
2
4 1 2
0 HC4052 DISABLE P+ P- VOL+ TV/AV VOL- MECH_SWITCH_ONBOARD

1 HC4052 ENABLE 220p
SW103
SW104
SW105
SW106
SW107
50V
3
DEBUG SOCKET
1
3 6
SW_UPDATE_SELECT
F F
2 5
2
0 DVB_SW_UPDATE
R397
270R
R405
470R
R484
R118
R243
1k2
2k7
3k9
1 4
1 ANALOG_SW_UPDATE
SW101
1
SCH NAME :CONTROLLER SHEET:5 OF:11

1 2 3 4 5 6 7 8 AX M
1 2 3 4 5 6 7 8
F126 U138 R909

1 2
3V3_VCC VDDM
2
4k7
1
3V3_VCC
330R MST6WB7GQ-3
2
C469 2
C201 2
C202 2
C200 2
C199 2
C198 2
C197 2
C196
10u 100n 100n 100n 100n 100n 100n 100n DVB_SPDIF 119 AD[0] DQM0 160 LDM
TP116
1 1 1 1 1 1 1 1
10V 10V 10V 10V 10V 10V 10V 10V 3V3_VCC 5
TP119
120 AD[1] DQS0 161
TP117
SPDIF_OUT
1
R906
4k7
PIN131 PIN147 PIN162 PIN168 PIN173 PIN179 PIN184 3V3_VCC 121 AD[2] AVDD_MI_3 162
A F150 VDDM A
1
1 2
3V3_STBY
1
TP115
TP114
TP113
2
1
330R DVD_SPDIF 122 AD[3] MDATA[0] 163
2
C184 C643 MDATA[0]
R296
S244
4k7
2 2
R912
BACKLIGHT_ON/OFF
4k7
100n 10u
U132 1
10V
1
10V 123 WRZ MDATA[1] 164

R367 MDATA[1]
SCZ MX25L512
1
1 2
100R R907
1
1
R368 1 CS# VCC 8 Q168 1
4k7
2 124 RDZ GND9 165
SDO 1 2 2 SO HOLD# 7 BC848B
100R R370 R357
R366 3 WP# SCLK 6 1
100R
2
SCK PANEL_VCC_ON/OFF 1
100R
2 125 ALE MDATA[2] 166 MDATA[2]
1 2 4 GND SI 5 R295
3V3_STBY 100R 3V3_VCC 1 2
2
100R VDDC 4k7 BADR[1] 126 BADR[1] MDATA[3] 167

SDI MDATA[3]
R365
100R
2 1
R369 R911
C194 C195
1
2 2 3V3_VCC 1
4k7
2
127 BADR[0]
100n 100n BADR[0] AVDD_MI_4 168 VDDM
R908
TP118
1 1
1
10V 10V 3V3_VCC 1 2

4k7 RASZ 128 RASZ MDATA[4] 169 MDATA[4]
FLASH PIN129 PIN203 VDDC 129 VDDC2 MDATA[5] 170 MDATA[5]
130 GND7 MDATA[6] 171 MDATA[6]
B 131 AVDD_MI_1
B
VDDM MDATA[7] 172 MDATA[7]
CASZ 132 CASZ AVDD_MI_5 173 VDDM
WEZ 133 WEZ MDATA[8] 174 MDATA[8]
MADR[11] 134 WADR[11] MDATA[9] 175 MDATA[9]
MEMORY 8MBU131
SDRAM MADR[10] 135 WADR[10] GND10 176
MT48LC4M16A2TG8E MADR[9] 136 WADR[9] MDATA[10] 177 MDATA[10]

VDD_DMC 1 VDD1 VSS3 54
2 DQ0 DQ15 53
MADR[7] 138 WADR[7] AVDD_MI_6 179 VDDM
VDD_DMQ 3 VDDQ1 VSSQ4 52
MDATA[0] 4 R4 5 4 51
DQ1 DQ14 140 WADR[5]
C MDATA[1] 3 R3 6 MADR[5] MDATA[13] 181 MDATA[13] C
MDATA[2] 2 R2 7 5 50 4 R4 5 MDATA[15]
MDATA[3] 1 R1 8 3 R3 6 MDATA[14] MADR[4] MDATA[14] 182 MDATA[14]
100R 6 49 2 R2 7 MDATA[13]
VSSQ1 VDDQ4 VDD_DMQ 142 WADR[3]
R586
1 R1 8 MDATA[12] MADR[3] MDATA[15] 183 MDATA[15]
7 48 100R
R588 MADR[2] AVDD_MI_7 184 VDDM
8 DQ4 DQ11 47 R910
MADR[1] 144 WADR[1] DQS1 185 2
4k7
1
3V3_VCC
VDD_DMQ 9 VDDQ2 VSSQ3 46
MADR[0] 145 WADR[0] DQM1 186 UDM VDDM
MDATA[4] 4 R4 5 10 45 4 R4 5 MDATA[11]
DQ5 DQ10 146 GND8
MDATA[5] 3 R3 6 3 R3 6 MDATA[10] MCLKZ 187
2
MDATA[6] 2 R2 7 11 44 2 R2 7 MDATA[9] R499
R535
DQ6 DQ9
10k
MDATA[7] R1 8 R1 8 MDATA[8] VDDM 147 AVDD_MI_2 MCLK 188 1
100R
2
MCLK
1 1
100R 12 43 100R F157
VSSQ2 VDDQ3 VDD_DMQ 148 AVDD_MIPLL
R587 R589 MCLKE 189
1 2
3V3_VCC
1
MCLKE
330R
13 DQ7 DQ8 42 2
C213
100n MVREF 190
1
D VDD_DMC 14 VDD2 VSS2 41 10V D
2
SPI_SCK 198 SCK C501 C193
R536
10k
R828 2 2
LDM 1 2 15 DQML NC2 40 1n 100n

100R SPI_SDI 199
1
50V
1
10V
SDI
R104 R360
1
WEZ 1
22R
2 16 WE# DQMH 39 1
100R
2
UDM SPI_SCZ 200 SCZ
R105
CASZ 1
22R
2 17 CAS# CLK 38 MCLK
PIN1 PIN14 PIN27 SPI_SDO 201 SDO
R103 R361 F162
RASZ 1
22R
2 18 RAS# CKE 37 1
100R
2
MCLKE VDDM
1 2
VDD_DMC
60R GND13 202
1 C461 2
C212 2
C208 2
C712
19 CS# NC1 36 220u 100n 100n 100n
R916 1 1 1 VDDC3 203 VDDC
R900 100R 2
6V3 10V 10V 10V
BADR[0]
1
22R
2 20 BA0 A11 35 1 R1 8 MADR[11]
R927 2 R2 7 MADR[10]
BADR[1]
1
22R
2 21 BA1 A9 34 3 R3 6 MADR[9]
4 R4 5 MADR[8]
22 A10 A8 33
R915 F163 PIN3 PIN9 PIN43 PIN49

23 A0 A7 32 1 2
E MADR[0]
100R
1 R1 8
VDDM
60R
VDD_DMQ E
4 R4 5 24 31 MADR[7] C203 1 C462 C189 C210 C204 C186
MADR[1] A1 A6 2 R2 7
2 2 2 2 2
3 R3 6 MADR[6] 100n 220u 100n 100n 100n 100n

MADR[2] R2 7 3 R3 6 MADR[5] 10V
1
2
6V3
1
10V
1
10V
1
10V
1
10V
2 25 A2 A5 30
MADR[3] R1 8 4 R4 5 MADR[4]
1
100R 26 29
R917 A3 A4
VDD_DMC 27 VDD3 VSS1 28
F F
WARNING!!!DON'T USE VIA FOR MCLK AND DATA SIGNALS
SCH NAME :MEMORY INTERFACE SHEET:6 OF:11
1 2 3 4 5 6 7 8 AX M
1 2 3 4 5 6 7 8
1
S128 2
MUTE_HP_R 12V_VCC
HEADPHONE AMPLIFIER POP NOISE CIRCUIT S127
1 2
5V_VCC
S126
1
1N4148
1 2
C624 3V3_VCC
D124
2
1
2n2
A 50V A
VDD_AUDIO
16V
2
F190
100u
1
1N4148
1 2
D127
600R 2 1
9 6
8 5 C453
2
7 4 HP_DETECT
R546
10k
1N4148 1N4148
C503 C541 8V_VCC
2 1 2 1 3
2
JK107
1
2 1
C386 D126 D125 2
R123
1 2
15k
2
C625
10u 1
R212
100k
2n2
50V
1n 100u 1
2
1
10V 50V
R237
C122
220p
50V 16V
2
20k
50V
1
1 OUTA Q150
VDD 8 1n
1
2
1
C540C502
2 BC858B
AMP_EN
1
U128 F192
2
C472 1 2 INAN OUTB 7
1 2 3
2
R423
R541
1 2 3
10k
600R
F191
600R
HP_R
1
4k7
2
TDA1308T R542
R238
C123
220p
R236
1 2
100u BC848B
2
20k
50V
3k9
C350 3 INAP INBN 6 C595 2 2
10k
1
C537 2 220n 16V 100n Q132

C471
1
2n2 10V 16V
2
1
4 VSS INBP 5 4k7 HP_L 1
1
3
50V
R729
100k
1 2
1u 1 2
MUTE_HP_L
R424 R722 BC848B
16V 220n 2
C538 AMP_MUTE 1
10k
2 2
B R211 10V 2n2 Q133 B

1
1
1 2
100k 50V 1
MUTE_HP_R
3
R544 C385
BC848B 2 2 1
3
Q134 10k 1 2 5V_VCC
R904 BC848B 10u
1
FAULT 1
10k
2 2
10V
Q167
S236 D166
1
12V_AUDIO VDD_AUDIO
S235 SS33
C711
24V_VCC 220u MUTE_HP_L
35V 3
BC848B R545
VDD_AUDIO
VDD_AUDIO
2 2 1
Q135 10k POP_MUTE

1
C C
35V
POWER
22u C708
POWER
POWER
ANALOG ANALOG
C710 22u
35V
POWER
C685
50V
1u
C684
1u
50V
16V
1 R1 8
2 R2 7
3 R3 6
4 R4 5
1 R1 8
2 R2 7
3 R3 6
4 R4 5
C701
R896
100R
R894
100R
1u 1u
C702 16V
ANALOG
36
35
34
33
32
31
30
29
28
27
26
25
POWER POWER POWER POWER
ANALOG
GND_6
PVCCR_2
PVCCR_1
PGNDR_2
PGNDR_1
VCLAMPR
VCLAMPL
PGNDL_2
PGNDL_1
PVCCL_2
PVCCL_1
GND_5
37 GND_7 GND_4 24
C683 C706 C691 50V C681 CN115
C697 C690 C698 1n
1u 1n 38 23 1u
470p BSRN BSLN 470p C705 R_AUDIO_P 1
25V 50V 25V
D R_AUDIO_N
L121 F251 50V 220n 39 22 220n
50V F252 L119 D
2 1
25V ROUTN_1 LOUTN_2 1 2
L_AUDIO_N R_AUDIO_N 2
50R 25V 50R
10u 10u
40 ROUTN_2 LOUTN_1 21 L_AUDIO_P 3
F253 L118
41 ROUTP_1 LOUTP_2 20 1 2
L_AUDIO_P L_AUDIO_N 4
L120 F254 50R
C699 C70410u C680
R_AUDIO_P 2 1 42 ROUTP_2 LOUTP_1 19 470p 1n 1u
C682 10u 50R C700 C688 U150 C689
50V 50V 25V
C707 470p 43 18 25V
1u
1n 50V
BSRP TPA3101 BSLP
220n
25V
1 R1 8
2 R2 7
3 R3 6
4 R4 5
50V 220n POWER POWER
44 17
C692
R897
100R
VDD_AUDIO 100k SHUTDOWN AGND_2
16V
ANALOG
1u
25V
1 R1 8
2 R2 7
3 R3 6
4 R4 5
POWER POWER R892

R895
100R
45 MUTE VBYP 16
C703
FAULT 46 FAULT VREG 15 CLOSE TO PIN
R898 VREG ANALOG
ANALOG 47 14 100n
MSTR/SLV
AVCC_1 ROSC 100k 30000289

GAIN0_1
GAIN0_2
2 50V
AGND_1
10NF
GND_1
GAIN1
GND_2
VREG 10k 48 13
RINN
RINP
LINP
LINN
SYNC
E R887 VDD_AUDIO AVCC_2 GND_3 ANALOG E

50V
C709
35V
22u
10
11
12
1u
1
R888 C687
1 2
BC848B ANALOG
AMP_EN 10k 2
Q166 16V
POWER
POWER
R893
100k
16V ANALOG 1u
1
ANALOG
1u C693
S230
R890
100k
C694
ANALOG
CONNECT TO C552 GND
CONNECT TO C553 GND
16V 16V
PIN 1,12,13,24,25,36 AND 37
VREG
1u 1u
VREG
C695 C696
S229
R891
100k
MUST BE CONNECT TO TERMAL PAD

MAIN_R
MAIN_L
F F
VREG

SCH NAME :AUDIO SHEET:7 OF:11
DRAWN BY :S.SEBNEM TAS 4-28-2008_15:57
1 2 3 4 5 6 7 8 AX M
F
E
D
C
B
A
CN131
1 35 CI_CD
4k7
2 36 1 2
CI_D3 R851 3V3D_DVB
1
1
R811
47R
CI_D4 3 37 1 R1 8 MPEG_TS_IN_D3
USB_DIG_DM
USB_DIG_DP
2
2
R794
USB_DIG_OCD
1 2
CI_CE 7 41 47R MPEG_TS_IN_D7
10R
10R
R845
R844
4k7
1
1
8 42 1 2
100k CI_A10 R810 3V3D_DVB
1 2
R884
9 43
2
CI_OE
CI_A11 10 44 CI_IORD
3 IO2
2 GND
1 IO1
47k
R855
1
R809 11 45
2 1 CI_A9 CI_IOWR
5V_VCC 4k7
U145
CI_A8 12 46 MPEG_TS_OUT_SYNC
AZ099-04S
2
2
USB INTERFACE
IO3 4
VDD 5
IO4 6
CI_A13 13 47 MPEG_TS_OUT_D0
CI_WE 15 49 MPEG_TS_OUT_D2
R812
2 1
3V3D_DVB 4k7 16 50 MPEG_TS_OUT_D3
CI_IREQ
CI_PWR 17 51 CI_PWR
R814
CI SOCKET
2
2 1
2 GND
1 OUT
4k7
18 52 1 2
3V3D_DVB 4k7 3V3D_DVB
3 FAULT
R813
U149
1
MPEG_TS_OUT_VALID 19 53 MPEG_TS_OUT_D4
330R
F235
STMP2161
1
10V
10u
C644
IN
1
2
20 54 MPEG_TS_OUT_D5
EN 4
5
330R
F237
2
C656 2
15p 1 22 56
CI_A7 MPEG_TS_OUT_D7
1
2
3
4
50V
R791
3
3
CN128
1 2
N.C.
5V_VCC
CI_A6 23 57 150R MPEG_TS_IN_CLK
4k7
1 2
USB R815 3V3D_DVB
50V
CI_A5 24 58 1
USB_ENABLE
15p
CI_RST 2
C655
CI_A4 25 59 CI_WAIT
4k7
26 60 1 2
CI_A3 R816 3V3D_DVB
CI_A2 27 61 CI_REG
MPEG_TS_OUT_CLK
R795
1 2
CI_A1 28 62 47R
R850 MPEG_TS_IN_VALID
47R
CI_A0 29 63 1 R1 8 MPEG_TS_IN_SYNC
4
4
10k
2 1 33 67
5V_VCC R864
N.C.
34 68
5
5
CI_PWR_CTRL
3V3_VCC
6
6
R862
12V_VCC
1 2
1
10k
5V_VCC
10k
R863
2 TS_IN TS_OUT
47k
R856
2 2
2
Q158
1
3
1 BSH103
3
MPEG_TS_IN
MPEG_TS_OUT
1
B4
2
C631
Q160
1
100n
47k
BC847B
R857
B1
10V
2
CI_CONTROL/ DATA&ADDRESS BUS
330R
F236
CI 5V SWITCH CIRCUIT
1
2
10V
10u
CI
C645
1
TP207
1
2
TS ROUTING
7
7
10V
100n
C632
CI_PWR
SCH NAME :CI

DRAWN BY :MB35 HW GROUP
8
8
VESTEL PROJECT NAME : 17MB25

A3
SHEET:8 OF:11
4-28-2008_15:57
F
E
D
C
B
A
AX M
1 2 3 4 5 6 7 8
CI CONTROL SIGNALS
CI_IREQ
CI_WAIT
CI_PWR_CTRL
U134
CI_IOWR
CI_IORD
CI_REG
CI_RST
FUM Interface DVB VIDEO FILTER&AMPR461 SDRAM
CI_CE
CI_CD
CI_OE
CI_WE
R180 MT48LC4M16A2TG8E
33R ENC_CVBS 1 IN1 OUT1 14 2
75R
1
DVB_CVBS 3V3_SDRAM_DVB 1 VDD1 VSS3 54
1 R1 8 MPEG_TS_OUT_D0 C124
CN109 ENC_PR 2 13 MD0 2 DQ0 DQ15 53 MD15
3V3D_DVB
1V8D_DVB
R308 IN2 OUT2 1 2
3V3_SDRAM_DVB 3 52
2 R2 7 2 1
VDDQ1 VSSQ4
2 1 MPEG_TS_OUT_SYNC 4k7 390p MD1 4 51
ENC_PB 3 12 DQ1 DQ14 MD14
F130 IN3 OUT3 50V R457 MD2 5 50
DVB_TXD
DVB_RXD
DVB_IRQ
DQ2 DQ13
R1 8
R2 7
R3 6
R4 5
1 R1 8
2 R2 7
3 R3 6
4 R4 5
5V_VCC 1 2
4 3 3 R3 6 F138 2 1 MD13
FUM_EN U139 75R DVB_PR 6 49
R434
R3 6 R436
VSSQ1 VDDQ4
33R
R4 5 33R
330R 5V_VCC 1 2
4 11 3V3_SDRAM_DVB
A UART0_TXD0 4 R4 5 330R
VCC GND
C139 MD3 7 DQ3 DQ12 48 MD12 A
FMS6145
FUM_EN
6 5 MPEG_TS_OUT_CLK 8 47
TP121
MD4 DQ4 DQ11
1
2
3
4
R1 8
R2 7
ENC_Y 5 IN4 OUT4 10 MD11
DSU_TXD0 9 46
R435
1 2
3V3_SDRAM_DVB VDDQ2 VSSQ3
33R
UART0_RXD0 8 7 10 45
6 9 390p MD5 DQ5 DQ10 MD10
DSU_RXD0 IN5 OUT5 R458 50V MD6 11 44
DQ6 DQ9
2
1
2
3
4
10 9 2 1 MD9
75R DVB_PB
1
12 43
R406
VSSQ2 VDDQ3
1
10k
7 NC1 NC2 8 C102 3V3_SDRAM_DVB

13 42
R462
R456
R455
R454
MD7 DQ7 DQ8
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
75R
75R
75R
75R
MD8
1 2
3V3_SDRAM_DVB 14 VDD2 VSS2 41
1
R307 390p MDQM 15 DQML NC2 40
GPF28
GPF29
GPF23/CIREG
GPA8/CI0INT#
GPA9/CI1INT#
GPF31/CIIOWR#
GPF30/CI0IORD#
GPF25/CI0CE#
GPF27/CI1CE#
GPF24/CI0CD#
GPF26/CI1CD#
HWAIT/GPF22
HRD#/CI0OE#/GPOF21
HWR#/CIWE#
HA15/GPOF15
HA16/CI1IORD#/GPOF16
HA17/CI1OE#/GPOF17
HALE/GPOF20
GPB10/VSYN/KEYDET2
GPB9/HSYN/KEYDET1
GPB8/USB_DRVVBUS
GPB4/USB_DRVVBUS
GPB3/DSPLYCM3
GPB2/DSPLYCM2
GPB1/RX1/DSPLYCM1
GPB0/TX1/DSPLYCM0
VDD33_4
GPB6/DSPLYCLK
GPB5/DSPLYDAT
GPB7/IR
VDD18_3
GPA13/SC1CD
GPC8/SC1RST
GPC9/SC1PWR
GPC7/RX2/SC1DAT
GPC6/TX2/SC1CLK
GPA3/SC0CD
GPC4/SC0RST
GPC5/SC0PWR
GPC3/UART1_RX/SC0DAT
GPC2/UART1_TX/SC0CLK
GPB14/SD/MS_D2
GPB15/SD/MS_D3
GPB11/SD/MMC_CMD
GPC14/SD/MMC_CLK
GPB12/SD/MMC_DAT
GPB13/SD/MS_D1
GPA10/SD/MMC_WP
GPC13/SD/MMC_PWE
GPG6/MS_INS
GPG4/SD_PWE
GPG3
GPG2
GPG1
3V3D_DVB
2
2 1
4k7 MPEG_TS_OUT_VALID C278 R459 50V MWE 16 WE# DQMH 39
3V3D_DVB
2
2 1 MDQM
100n 75R DVB_Y MCAS 17 CAS# CLK 38
10V
1
C101 MCLK_SDRAM
MRAS 18 RAS# CKE 37 3V3_SDRAM_DVB
1 2 19 CS# NC1 36 MA12
R923 Comm.Port 390p MBS0 20 BA0 A11 35 MA11
33R 50V MBS1 21 34
MD0 1 R1 8 1 162 BA1 A9 MA9
CVBS/YPbPr Video
MD0 GPG0 MA10 22 33
MD1 2 R2 7 2 161 A10 A8 MA8
MD1 AVSS_3 MA0 23 32
MD2 3 R3 6 3 160 A0 A7 MA7
MD2 AVO3
CN107
R920 ENC_CVBS MA1 24 A1 A6 31

MD3 33R 4 R4 5 4 MD3 AVD33_3 159 MA6
1
3V3A_DVB
Outputs
MA2 25 A2 A5 30 MA5
MD4 1 R1 8 5 158
B MD4 AVO2 ENC_PR B
MD5
MD6
2
3
R2 7
R3 6
6
7
MD5
MD6
AVSS_2
AVO1
157
156 ENC_PB
==> MA3
3V3_SDRAM_DVB
26
27
A3
VDD3
A4
VSS1
29
28
MA4
RAM DATA BUS
1
MD7 4 R4 5 8 MD7 AVD33_2 155 3V3A_DVB

R919
R500
F137
4k7
3V3D_DVB
MDQM 33R 33R 9 MDQM AVO0 154

MD15 1 R1 8
1
R186
2
10 MD15 AVSS_1 153 R198

ENC_Y
27MHz VCXO 3V3_VCC 1
330R
2
C294 C245 C246 C247 C243

3V3_SDRAM_DVB
MD14 2 R2 7 11 152
2
1 2
MD14 FSADJ 470R 2 2 2 2 2
MD13 3 R3 6 12 MD13 VREF 151 10u 100n 100n 100n 100n

R921 1
10V
1
10V
1
10V
1
10V
1
10V
1
DSU_TXD0
MD12 33R 4 R4 5 13 MD12 AVD33_1 150 3V3A_DVB
C266
100n
10V
MD11 1 R1 8 14 MD11 AUDIO_DAC_VMID 149
MD10 2 R2 7 15 MD10 AUDIO_DAC_L 148 1
TP122
MD9 3 R3 6 16 MD9 AUDIO_DAC_R 147 1
TP120 C239 2
C678 2
MD8 4 R4 5 17 146 100n 22u 3V3_SDRAM_DVB
CHEERTEK
R315 MD8 GPC15/SPDIF R317 1 1
MCLK_SDRAM 1 2 18 145 1 2
10V 16V C244 C272 C236 C237
100R MCLK GPA0/CLKO/PCMACK 100R DVB_SPDIF 2 2 2 2
C715 3V3D_DVB 19 VDD33_1 HAD8/PD0/GPOE8 144 1

100n 1
100n 1
100n 1
100n
20 143 10V 10V 10V 10V
R924 R925 VSS_1 HAD9/PD1/GPOE9
MA12 33R 33R 21 MA12/GPOC11 VDD18_2 142 1V8D_DVB
10p 1 R1 8 22 141
50V MA11 MA11/GPOC10 HAD10/PD2/GPOE10
RAM ADDRESS BUS
MA9 2 R2 7 23 MA9 HAD11/PD3/GPOE11 140

MA8 3 R3 6 24 139 C716
C R922 MA8 HAD12/PD4/GPOE12 C
CT216T-R
MA7 4 R4 5 33R 25 MA7 HAD13/PD5/GPOE13 138
MA6 1 R1 8 26 MA6 HAD14/PD6/GPOE14 137
22p
U104
2
1
TP208
MA5 R2 7 27 MA5 HAD15/PD7/GPOE15 136
50V
MA4 3 R3 6 28 MA4 HA19/VSYN/GPOF19 135
4 100R UART0_TXD0
R4 5 29 134 2 1
MWE R443 MWE# HA18/HSYN/GPOF18 C717
30 133 R913
33R 1V8D_DVB VDD18_1 GPA7/PWM3/PCMSD/SCXO
1 R1 8 31 132 2
1M 1
MCAS CAS# GPA6/PWM2/PCMWS/SCXI
2 R2 7 32 131 R789
X102
MRAS RAS# GPA5/PWM1/PCMCLK/TX2 22p
MBS0 3 R3 6 33 BS0 GPA4/PWM0/PCMACK/RX2 130 50V 1 2
MBS1 4 R4 5 34 129 100R F135
MPEG DECODER
R918 R926 BS1/GPOC12 UART0_TX/GPOC0 UART0_RXD0
C296
C297
2 1
27MHz 3V3_VCC 1 2
1
50V
27p
27p
50V
MA10 33R 35 MA10 UART0_RX 128 R914 3V3A_PLL_DVB
33R 330R 16V
MA0 1 R1 8 36 127 100R C252
2
MA0 SAR_ADC_IN1 2 1 RF_AGC_DVB 1
22u
2
MA1 2 R2 7 37 MA1 SAR_ADC_IN0 126 C269 2 R319 2 1

100n
100n C352 10V
MA2 3 R3 6 38 MA2 VDD33_3 125 3V3D_DVB
R444 10V
1
MA3 4 R4 5 33R 39 MA3 VSS_2 124

CI_A14 1 R1 8 40 123 F136
HA14/GPOF14 OSCI 3V3_VCC 1 2
CI_A13 2 R2 7 41 HA13/GPOF13 OSCO 122 3V3A_ADC_DVB

330R 16V
CI_A12 3 R3 6 42 HA12/GPOF12 GPC1/COFDM_ERR 121 1
TP123 1 2
C253
R446 22u 100n
CI_A11 4 R4 5 43 120
D CI_A10
33R
1 R1 8 44
HA11/GPOF11 GPA12/AGC_RF
119 1
R320
2
10k 10k
2
C287 1
10V D
HA10/GPOF10 GPA11/AGC_IF R316 100R IF_AGC_DVB
CI ADDRESS BUS
1 2 1 2
CI_A9 2 R2 7 45 118 R348 C249R371

1 2
HA9/GPOF9 GPA15/SDA R318 100R SDA_TUN_DVB C248
2
2 2
CI_A8 3 R3 6 46 HA8/GPOF8 GPA14/SCL 117 100R

1 2
SCL_TUN_DVB 100n 100n
R437
R326
1k2
CI_A7 4 R4 5 33R 47 HA7/PD7/GPOF7 AVSS_PLL_2 116 C302 1
10V
1
10V
CI_A6 1 R1 8 48 HA6/PD6/GPOF6 VLFQ 115
C250
GPA1/CS1#/RX1/HSYN/SD_CD#
GPA2/CS2#/TX1/VSYN/PCMCLK
1 2
2
2
CI_A5 2 R2 7 49 114 C303
1
HA5/PD5/GPOF5 AVD33_PLL 3V3A_PLL_DVB 100n
R327
R328
1n
1k2
1k2
CI_A4 3 R3 6 50 HA4/PD4/GPOF4 VLFM 113 1
10V
R450 50V* Layout Req.
DSU0_RX/UART0_RX/GPD0
DSU0_TX/UART0_TX/GPD1
1 2
CI_A3 33R 4 R4 5 51 HA3/PD3/GPOF3 AVSS_PLL_1 112

1 R1 8 52 111 1n
CI_A2
1
HA2/PD2/GPOF2 VCCA 3V3A_ADC_DVB BC847B
SF_CLK/HA22/GPOD4
SF_DIO/HA20/GPOD2
50V 3
3V3D_DVB
2 R2 7 53 110
SF_DO/HA21/GPOD3
GPD6/FUM/TSO_SYN
GPD7/FUM/TSO_VLD
GPD5/FUM/TSO_CLK
CI_A1 HA1/PD1/GPOF1 VSSA R762

GPD8/FUM/TSO_D0
CI_A0 3 R3 6 54 109 1 2 2 Q153 F132

HA0/PD0/GPOF0 VCCAX 4k7 3V3_VCC 1 2
1
4 R4 5 3V3D_DVB
GPD10/TSO_D2
GPD11/TSO_D3
GPD12/TSO_D4
GPD13/TSO_D5
GPD14/TSO_D6
GPD15/TSO_D7
TSI_SYN/HSYN
TSI_VLD/VSYN
TSI_CLK/CLKO
330R
SF_CS#/FCS#
GPD9/TSO_D1
C679
22u
16V
3V3D_DVB
C288 C261 C262 C260 C263
HAD7/GPOE7
HAD6/GPOE6
HAD5/GPOE5
HAD4/GPOE4
HAD3/GPOE3
HAD2/GPOE2
HAD1/GPOE1
HAD0/GPOE0
TSI_D0/PD0
TSI_D1/PD1
TSI_D2/PD2
TSI_D3/PD3
TSI_D4/PD4
TSI_D5/PD5
TSI_D6/PD6
TSI_D7/PD7
USB_AVSS_1
USB_AVSS_2
1
2 2 2 2 2
USB_AVD33
USB_AVD18
10u 100n 100n 100n 100n
ADC_VMID
IDTV_SW
VDD33_2
USB_REF
1 1 1 1 1
10V 10V 10V 10V 10V

RESET#
USB_DN
USB_DP
OSCI1
OSCO1
VREFN
VREFP
VINP
VINN
1
C277
100n
10V
F133
100
101
102
103
104
105
106
107 10V
108100n
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
1 2
E 3V3_VCC 330R 3V3A_DVB E

C254 2
C289 2
C273 2
C259 2
C258
C265 C291
1
1
1
1
4
3 R3 6
2 R2 7
1 R1 8
2 2
10u 100n 100n 100n
100n 10u
R448
R188
R325
1 1 1 1
1
10V 10V 10V 10V

33R
4 R4 5
3 R3 6
2 R2 7
1 R1 8
33R
5k6
3V3D_DVB4 R4 5
R4
TP164
TP163
C292
1 1
3V3D_DVB
10V 10V
R447
10u
10V
33R
4 R4 5
3 R3 6
2 R2 7
1 R1 8
5
2
R449
1
33R
DSU_RXD0
DSU_TXD0
F134
3 R3 6
2 R2 7
1 R1 8
4 R4 5
3 R3 6
2 R2 7
1 R1 8
SF_CS
SF_CLK
SF_DO
SF_DIO
USB_DIG_DM
USB_DIG_DP
C267 2 2
C255
R183
R440
1 2
1V8_VCC
33R
33R
RESET_DVB
100n 100n 1V8D_DVB

10V
1 1
10V 330R
50V 2
C295 2
C256 2
C257 2
C264
2
C300 22p 10u 100n 100n 100n
DVB RESET
C268
100n
R375
1 1 1 1
10V 10V 10V 10V
10k
CI_D7
CI_D6
CI_D5
CI_D4
CI_D3
CI_D2
CI_D1
CI_D0
SERIAL FLASH
10V
SERIAL FLASH C601

1 2
C713
C251
100n
2 1n
10V
C301 RESET_DVB
2
1
15p 50V DIGITAL_IF_P
2
1 2
MPEG_TS_OUT_SYNC
MPEG_TS_OUT_VALID
MPEG_TS_OUT_CLK
MPEG_TS_OUT_D0
MPEG_TS_OUT_D1
MPEG_TS_OUT_D2
MPEG_TS_OUT_D3
MPEG_TS_OUT_D4
MPEG_TS_OUT_D5
MPEG_TS_OUT_D6
MPEG_TS_OUT_D7
1
TP124 CI DATA BUS 50V
1
S214
L115
C619
1 2
2
47p
50V
1u
DVB_RESET 33R
1
1n 390nH 2 1
2
2
MPEG_TS_IN_SYNC
MPEG_TS_IN_VALID
MPEG_TS_IN_CLK
MPEG_TS_IN_D0
MPEG_TS_IN_D1
MPEG_TS_IN_D2
MPEG_TS_IN_D3
MPEG_TS_IN_D4
MPEG_TS_IN_D5
MPEG_TS_IN_D6
MPEG_TS_IN_D7
R185
1
R376
R372
TP153
10V
100n
C275
50V
2
10k
10k
10V
1
C293 DIGITAL_IF_N
TP154
R373
1 2
2
1
10k
100n
2
S215
F 10u F
C276
100n
10V
U114
2
2 1
C240 C714
1
10V
C274
100n
10V
MX25L512
1
R190 F142
1
SF_CS 1
33R
2 1 CS# VCC 8 1 2
3V3_VCC F141
1
2 7 330R 1 2
22p
SF_DO 33R SO HOLD# R191 1V8_VCC 50V
VESTEL PROJECT NAME : 17MB25
1 2
R182 3 WP# SCLK 6 1

33R
2
SF_CLK 330R
F140 A3
<==
4 5 MPEG DEC TS OUTPUT

<==
1 2
GND SI 33R 1 2 SF_DIO 3V3_VCC
TP155 1
TP156 R192 330R SCH NAME :DVB MPEG DECODER & SDRAM SHEET:9 OF:11
1
2
C286 2
C285
TP141 1
1
TP152 10u 10u
MPEG DEC TS INPUT 1
10V
1
10V DRAWN BY :ULAS DERELI 4-28-2008_15:57

1 2 3 4 5 6 7 8 AX M
1 2 3 4 5 6 7 8
A/D DIMMING SELECTION 12V_VCC

!
TP196
Q155
TP195
R339 5 12V_STBY
1
IRF7314
6
1 2
4k7 FS104 F241
1 8
TP209
1 2
1 2
12V_STBY
FDC642P
R340 4 12V_PSU
1
60R
Q156
1
1
4k7
2
5V_VCC FS102 C659 R847 7A/32VDC
CN117
C669
220n
R882
2
25V
33k
1
R341
1 2
12V_PSU 220n
1
10R
2 2 7
3 C642 C660
R874
C667
220n
D175
C18V
2
22k
25V
30V_VCC 3V3_VCC JK103 2
1
1 2
1 2 4k7 7A/32VDC 25V 10u 220n
3 6 1
2
A 2 25V 25V R798 A
1
24V_VCC 24V_VCC 33k
1
1 2
3 4 FS103 R873 R846 4 1 2 47R
1 2
12V_INV MECH_SWITCH
1
22k
2 1
10R
2 5 R883
1
6V3 5 6 6V3 7A/32VDC
100u 100u
3
1
S245 2
2 1
7 8 1 2
C519 R817 12V_AUDIO 12V_VCC

MOSFET_CONTROL
2
4k7
1 2
Q163
C507 C506 BC848B
5V_VCC 9 10 3V3_VCC 1 2
C633 2
1
100n 5V_VCC 100n
TP199 1
10V 1
TP197 1 11 12 1
TP198 U137 5V_STBY 10V
1
C599
6
C358 R244
2
MP1583 1 2
10n 3k9
TP210
12V_STBY 13 14 12V_STBY 1 2
FDC642P
16V
1
1 BS SS 8
Q157
S211 2 7 5n6 C518NC
C668
220n
R880
1 2
IN EN
25V
33k
15 16 5V_STBY 12V_STBY 50V
3 SW COMP 6 R865
C662C568 C567 C635
1
1 2
1
TP202 2 2
4 5 1 2
12V_AUDIO 12V_VCC 220n 22u 22u GND FB 100n 10k
2
17 18 1 1
1 2
25V 16V 16V
1
16V
2
1
TP201 R797 100n
R878
1 2
TP200 1 19 20 47R
1k
U148 10V
C670 C677 R803
MP1583
1
2
TP157
B 21 22 10n
1
3k9
2
R881
1
1 2
33k
16V
1
1 BS SS 8
1
S227 2
2 7 5n6 C666
23 24 IN EN
2
12V_STBY 50V
3 6
R790
2
SW COMP
30k
C663
C671 C674 1 2 R866
1
2 2
25 26 220n22u 22u 4 GND FB 5 1

10k
2
3
100n
2
1 1
R818 25V 16V 16V
R886
16V
1
D144 L106 Q164 NC
2k
2 1 2
27 28 1 2 1 2 MOSFET_CONTROL 4k7
5V_STBY BC848B
SS33 15u C634 2
C565C566 1
1
2 2
100n
17PW26 CONNECTOR
TP211
1
22u 22u 1 10V
1
16V 16V
2
ADAPTER OPTIONS
R854
15k
D164 L116
1
1 2
1
1 2
3V3_STBY
SS33 15u
2
C673C672 2
1
22u 22u 1
16V 16V
NC
5V_VCC 20 19 3V3_VCC ADAPTER AND IPS15 OPTIONS 12V_STBY
1
S222 2
3V3_STBY
C 5V_VCC 3V3_VCC 17PW26 OPTIONS C
18 17
12V_STBY 16 15 12V_STBY
U122
! PAULO DECOUPLING
1
14 13 5V_STBY FS105 3V3_VCC

C5V6
D156
C5V6
D157
LM1117
TP143 1
3V3_STBY CAPACITORS
1
4
6
12V_AUDIO 12 11 12V_VCC 12V_VCC 3 IN OUT 2 8V_VCC 4A/24VDC F146
D174
C5V6
TP145
2
1 2
FDC642P
R345 C470 3V3_STBY VDDP
C452
1
GND VOUT
1
10u
25V
330R
Q105
10 9 1
4k7
2
DIMMING 47u C307
R411
C436
220n
R337
C408
2
1
25V
33k
10V
10u
2
1 4
2k
16V
1
2
R344 1
100n
BACKLIGHT_ON/OFF
2
1 2
8 7 4k7 10V
2
R343 R796
1
6 5 1
4k7
2
STBY_ON/OFF R378 R476
1
47R
2
1 2 1 2
R342 10k 1k F147
1
1 2
4 3 1
4k7
2
STBY_ON/OFF_NOT 1V26_STBY VDDC
R336
33k
330R
C308
C410
1
10V
10u
2
2 1 MECH_SWITCH 100n
D120
C5V6
2
10V
D CN126 3 D
1
R338
17IPS17 CONNECTOR S241 MOSFET_CONTROL
2
4k7
1 2
Q138 F145
BC848B 1 2
STBY_ON/OFF C310 2
3V3_STBY AVDD_33
100n
1
330R
C306
C409
1
10V
10u
1 2
MOSFET_CONTROL 10V 100n

1
2
S243 10V
STBY_ON/OFF_NOT
PROTECT_PANEL
3
SHORT CCT PROTECTION
BACKLIGHT_ON/OFF
INVERTER SOCKET
1
R708
Q137
C636
100n
10V
2 2
33k
1
PANEL_VCC TP236 1
R706 1
TP238
BC848B
1
10k 2 1
8V_VCC DIMMING
1 2 33k 12V_INV
R571 F169 TP237 1
2
1 2
10k
BAW56
3V3_VCC
D135
1 2
R569 60R C637 2

C661 2
C641
TP149
C664 100n 220n 10u

E S240 F170
10V
1
25V
1
25V E
CN127
1 2 220n
1
3V3_STBY C455
11
10
25V
1
5V_TUN 60R 100u
S239
5V_STBY 3V3_VCC F171 25V
1
TP142
1 2
5V_VCC PANEL_VCC
2
60R
BAW56
R565
D136
2
4
2 1
10k F172
R699
3
33k
1 2
L110
FDC642P
12V_VCC
1
S210
2
PROTECT
60R
Q104
1 2 1 2
4 VINB SW 3
1
3V3_STBY 1V26_STBY
C618
220n
R700
2
25V
33k
5V_VCC 4u7
1
R705 C665 C578 C576 MP2112 C575 C579

TP150
2
2 2 2 2
12V_VCC
1
2 1
33k 220n 22u 22u 5 VINA GND 2 22u 22u
R249
200k
1 1 1 1
1
25V 16V 16V U144 16V 16V

2
1
3
10k 6 EN FB 1
BAW56
R564 R205
D137
1 2
Q151 R568 NC
1
1 2 1 2
10k 47R
1
2 3
BC858B
R570 R702 R124
1
3 1 2 1 2
C535 1 2
1
10k 33k 160k

R566
3 2 1
33k
S134
R563 1 2 180K olacak
Q136 2 1
10k
2
2
33k 1
24V_VCC
U121 1n
R707
2
BC848B
1 LM1117 50V
F 33k 12V_AUDIO F222 TP147 F
PANEL SUPPLY SWITCH
2 1 1
3
R709 R575 3V3_VCC

1 2
3 IN OUT 2 1V8_VCC
2
PANEL_VCC_ON/OFF
2
10k
1 2
Q139 60R C543
R562
C406
GND VOUT 1
1
2
10k
10V
10u
BC848B 100u
C309
R721
100R
2
1
1 4 16V
2
2
100n 1

1
10V
1
R410 S228
1
47R
2 1 2
SCH NAME :MB25 POWER SHEET:10 OF:11
1 2 3 4 5 6 7 8 AX M
1 2 3 4 5 6 7 8
U138
C312
100n
10V
MST6WB7GQ-3
GND15 244
1
6
TP212
VDDC4 245 VDDC CN103
LVA4P 246 19" TO 22" FFC OPTIONS RX_B_0_N 1 CN105
1
A LVA4M 247 RX_B_0_P 2 RX_B_0_N 1 2 A
TP213 1
LVA3P 248 RX_A_3_P RX_B_1_N 3

LVDS CABLE RX_B_0_P
TP214 1
3 4
LVA3M 249 RX_A_3_N RX_B_1_P 4 RX_B_1_N 5 6

TP215 1
LVACKP 250 RX_A_CLK_P RX_B_2_N 5 RX_B_1_P 7 8

TP216 1
LVACKM 251 RX_A_CLK_N RX_B_2_P 6 RX_B_2_N 9 10

TP217 1
LVA2P 252 RX_A_2_P 7 RX_B_2_P 11 12
LVA2M 253 RX_A_2_N RX_B_CLK_N 8 13 14

TP220 1
PANEL_VCC
LVA1P 254 RX_A_1_P RX_B_CLK_P 9 RX_B_CLK_N 15 16
TP221 1
LVA1M 255 RX_A_1_N RX_B_3_N 10 RX_B_CLK_P 17 18

TP222 1
LVA0P 256 RX_A_0_P RX_B_3_P 11 RX_B_3_N 19 20 PANEL_VCC

B CN108 TP223 1
B
LVA0M 257 RX_A_0_N RX_A_0_N 12 RX_B_3_P 21 22 S132
1 2
RX_B_3_P 1 2 TP224 1
VDDP6 258 VDDP RX_A_0_P 13 RX_A_0_N 23 24 10k

RX_A_0_N 3 4 TP225 1
2 1 3V3_VCC
R902
GND16 259 14 RX_A_0_P 25 26 10k
2
RX_A_0_P 5 6
2 1 3V3_VCC
C311
100n
10V
R901
LVB4P 260 RX_A_1_N 15 27 28
7 8 TP226 1 MEGA_DCR_OUT
LVB4M 261 RX_A_1_P 16 RX_A_1_N 29 30
RX_A_1_N 9 10 S133
LVB3P 262
1 2
RX_B_3_P 17 RX_A_1_P 31 32
RX_A_1_P 11 12
LVB3M 263 RX_B_3_N RX_A_2_N 18 BACKLIGHT_ON/OFF TP227 1
33 34 BACKLIGHT_ON/OFF
13 14 TP235 1
TP233 1
LVBCKP 264 RX_B_CLK_P RX_A_2_P 19 TP234 1 RX_A_2_N 35 36 S141

1 2
RX_A_2_N 15 16
LVBCKM 265 RX_B_CLK_N RX_A_CLK_N 20 RX_A_2_P 37 38
RX_A_2_P 17 18
C LVB2P 266 RX_B_2_P RX_A_CLK_P 21 RX_A_CLK_N 39 40 C
2
RX_A_CLK_N 19 20
S191
2
LVB2M 267 RX_B_2_N RX_A_3_N 22 RX_A_CLK_P 41 42 OPTION1
S190
RX_A_CLK_P 21 22 OPTION1 TP230 1
LVB1P 268 RX_B_1_P RX_A_3_P RX_A_3_N
1
23 43 44 OPTION2
RX_A_3_N
1
23 24 OPTION2 TP229 1
LVB1M 269 RX_B_1_N 24 RX_A_3_P 45 46 OPTION3

RX_A_3_P 25 26 OPTION3 TP228 1
S152
LVB0P 270
2 1
RX_B_0_P 25 47 48
27 28
LVB0M 271 RX_B_0_N PANEL_VCC 2 1
26 S135
MEGA_DCR_IN 49 50
S140 2 1
29 30
2 1
27
S151
PANEL_VCC 28
29
PANEL_VCC = 5V
30
D D
26" TO 32" FFC OPTIONS

OPTION2
3V3_VCC
3V3_VCC
OPTION1
3V3_VCC
PANEL_VCC
1
1
R577
S148
S146
R582
OPTION3
PANEL_VCC
10k
10k
3V3_VCC
E E
3V3_VCC
2
PANEL_VCC = 5V/12V
PANEL_VCC
2
R903
RX_A_CLK_P
RX_A_CLK_N
10k
S153
RX_A_3_P
RX_A_3_N
RX_A_2_P
RX_A_2_N
RX_A_1_P
RX_A_1_N
RX_A_0_P
RX_A_0_N
1
1
PANEL VCC = 5V/12V

R580
R581
330R
F149
2
1
2
1
10k
10k
1
S149
S150
S147
R579
R578
330R
F148
10k
10k
2
2
1
PANEL_VCC
CN102
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
CN101
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
F F
9

SCH NAME :LVDS INTERFACE SHEET:11 OF:11
1 2 3 4 5 6 7 8 AX M
SW106 SW103 SW104 SW105 SW107 CN133
OO F236
4 5 6 1 2 1 2 1 2 1 2 1 2 C632
1
2
2 1
R118 R397 R484 4 2
2 1
2 1 2 1 2 1 1
2 1
3 2
2
R405 R243
3 1 2
1 2 3 3 4 3 4 3 4 3 4 3 4
1
Q158
R198
C645
F
1
2
2
SW101 D136 R564 Q151 R562 R434 C266
C566
2
D137 R436
F249
R790
1
1
3
3
3
1
2
1
1
2
1
8
7
6
5
8
7
6
5
2 1
C294
C289
C258
2
2
1 C243
3 2 1
2
2
2
2
1
F132
C295
R878 Q153
1
C288
1
C239
1
1
C630
1
2
3
4
1
2
3
4
F248
R793
Q136 C715
D162
1
2
1 2 2
1
2
1
2
2
1
3
2
R857
C518 2 1 34 68 R317
C631
F134
1
R856
1 2
2
R326
F137
1
1
C272
1
D161
R315
7
6
5
8
1 2
1 1
R707
R709 C565
R570
R705
C599 R865 1
C264
Q160 33 67 R348
C256
C245 R923
C261
2
2
1
2
2
CN130 R563 R565 1
4
3
2
1
1 2 2 1
1
2
3
4
R244 1 1
R913
2
2
1
5 4 1 2 1 2 32 66
1 2 R371
1
1
2
1
1
1
1
R914
S240
C519 R410 1 54 2 2
5
6
7
8
F133
2 1
1
2
1
1
2
R568
1 C248
2
2
6 3 R862 31 65 2 53 R435 2 2 2 C269
1
4 2 1 1 2
1
R721 3 52 R319
1
1
4
3
2
1
2 1
S228 R863 U104
U134
7 2 2 2 30 64
C358
4 51 C262
2
2
2
1
2
R864 C257
C259
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
5
6
7
8
C273
216
163
3 2 1 8
L116 5 50
R920
29 63
D164 S239
1 1
C671
3
2
1
L106
6 49
4
3
2
1
R816
2
28 62
1 1 2
D160
2 1 7 48
2 U137 R815 1 162
1
1 2 161
1
5
6
7
8
2 8 47
27 61
2
3 160
2 1
D144 C656 9 46 4 159
2
C626
1
2
1
2
5 158
2
1
C678
1 26 60 10 45 6 157
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1. INTRODUCTION..................................................................................................................

1 RF input VHF1, VHF3, UHF @ 75Ohm(Common)

1.1 General description of TDTC-G101D:

1.2 Features of TDTC-G101D:

1.3 Pin Configuration

3. AUDIO AMPLIFIER STAGE WITH TPA3101

3.2 Features of TPA3101

3.3 Pin Configuration of TPA3101

LCD TV controller with PIP/POP display functions

NTSC/PAL/SECAM Video Decoder

Multi-Standard TV Sound Decoder

Digital Audio Interface

Analog RGB Compliant Input Ports

DVI/HDCP/HDMI Compliant Input Port

5. INTEGRATED DVB-T RECEIVER (CHEERTEK)

CT216T includes COFDM demodulator transport stream de-multiplexer, DVB-CSA

Audio Decoding and Processing

OSD(On Screen Display)

High Speed I/O

Electrical and Physical Characteristics

6. 4MX16 BIT SYNCHRONOUS DRAM (SDRAM)

6.3 Pin Configuration

9.1.3 Pin Configuration

9.1.4 Frequency Response

Frequency Response of Channel 2:

9.2.3 Pin Configuration

10. POWER STAGE

Fifth Generation HEXFETs from International Rectifier utilize advanced processing

12. SERVICE MENU SETTINGS

12.1. Video Setup

12.3. Service Scan/Tuning Setup

16.5. External Source Settings

16.7. NVM Edit

LVDS Clock Step <.......> Value between 0 to +255

16.10. Product Info

13. SOFTWARE UPDATE DESCRIPTION

1.1 The File Types Used By The Bootloader

1.2 Usage of The Bootloader

- Bit per second: 115200

Figure 1. The Sample Output Before Sending The File

- Bit per second: 9600

Figure 3. Xmodem Menu

16.2 17MB25 HDCP key upload procedure.

3) Enter service menu by pressing 4 7 2 5 consecutively while main menu is

COM Properties Window

The Sample Output Before Sending The File

File and Protocol Selection Window

9. When sending the file the following window must be seen.

Capture of Sending Process

Note: After the File Sending Process,

End of The Sending Process

13.4 17MB25 Digital Software Update From USB

With revert operation, it is possible to downgrade the software.

16.3. Service Scan/Tuning Setup

16.5. External Source Settings

16.7. NVM Edit

LVDS Clock Step <.......> Value between 0 to +255

16.10. Product Info

17. SOFTWARE UPDATE DESCRIPTION

1.1 The File Types Used By The Bootloader

1.2 Usage of The Bootloader

- Bit per second: 115200

Figure 1. The Sample Output Before Sending The File

- Bit per second: 9600