14.

1 CMOS Digital Logic Circuits:

Digital Logic Inverters

Digital logic inverters 1

 14. CMOS Digital Logic Circuits

Contents:

14.1 Digital Logic inverters

14.2 CMOS inverter
14.3 Dynamic operation of CMOS inverter
14.4 CMOS Logic-Gate circuits
14.5 Deep-submicron design

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 14.1 Digital Logic inverters
Simple inverting MOS amplifier, used as logic inverter:

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 14.1.2 Voltage-transfer characteristic
Simplified voltage-transfer characteristic:

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 14.1.2 Voltage-transfer characteristic (cont.)

Output
Output
low
highlevel
level

Noise margin
Noise margin for high input
for low input

Output
low level

Max. input Min. input

low level high level

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 14.1.3 Noise margins

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 Static CMOS inverter: propagation of static voltages
Infinite long chain of inverters:

Vin2 Vout
1
Vin3 Vout
2
Vin4 Vout
3
Vin5 Vout
4
etc. Vine Vout
o
Vino Voue t

after passing many gates:

voltages converge to VL or VH

'mid point' or 'trip point' voltage

(omslag spanning ) VM
Vthres

'logic swing' (logische zwaai ):

VH VL
'low noise range' (lage storingsgebied ):
VL V VM
Vthres 'high noise range' (hoge storingsgebied ):
VM V VH 7
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 14.1.4 Ideal vs. real voltage transfer function

ideal real

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 14.1.4 Ideal voltage transfer function

Far from ideal :

Low noise margins
Draws current when Vout Vout ,low

Vout ,low is not zero compromise!

Slow when output should toggle from low to high

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 14.1.5 Inverter implementation

Idea: use transistor as voltage-controlled switch

'Switch-level model': transistor is either

on: acts as a resistor RON
or
off: acts as an open circuit

Ron
VOH VDD VOL VDD
R Ron

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 14.1.5 Inverter implementation (cont.)
Improved idea: use complementary switches
both VOL and VOH well defined and optimal (0 and VDD resp.)
no (static) current consumption

VOH VDD VOL 0

Basis for CMOS inverter and other gates

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 14.1.5 Inverter implementation (cont.)
Alternative idea: use 2 transistors together as double-throw switch
VOL VCC - IEE RC and VOH =VCC
constant current consumption

Basis for Emitter-Coupled Logic (ECL) and Current Mode Logic (CML)
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 14.1.6 Power dissipation
No static power
but dynamic power due to
charging/discharging of parasitic C

Equivalent circuit when v I is low Equivalent circuit when v I is high

(PU is on, PD is off) (PU is off, PD is on)
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 14.1.6 Power dissipation (cont)
Energy consumption due to charging the capacitor C during Tcharge :
Tcharge Tcharge Tcharge

EDD p t dt
0 0
VDD i D t dt VDD 0
i D t dt VDDQC

after charging to VDD : QC CVDD EDD CVDD 2

1
Energy stored in C after charging: Estored CVDD 2
2
1
so rest of energy: CVDD 2 is dissipated by pull-up switch resistance
2
Note: independent of RPU

After discharging to ground: QC 0 Estored 0

1
so energy CVDD 2 stored in C is dissipated by pull-down resistance
2
Note: independent of RPD

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 14.1.7 Propagation Delay
Charging and discharging of the load capacitance takes time
determines maximum operating frequency

tPHL : propagation delay for output high low

tPLH : propagation delay for output low high
1
'the' propagation delay tP mean tPHL , tPLH tPHL tPLH
2

Minimum period for switching cycle: Tmin tPHL tPLH 2tP

1 1
Based on max. switching frequency fmax
Tmin 2tP
assumption:
VDD/2 is
switching level Actual values of propagation delays dependent on
implementation of inverter
In case of simple switch-level model:
simple exponential responses 15
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 14.1.8 Power-Delay Product and Energy-Delay Product
Fast gates will dissipate much power, low-power gates will be slow
trade-off between power and speed
Figure of Merit (FoM) to compare technologies: Power-Delay Product (PDP )

PDP PD tP

Inverter with complementary switches: PD fCVDD

2
PDP fCVDD
2
tP

Worst-case PDP is when f is maximal

1 1
fmax PDP CVDD2
Note: in fact energy per transition
2tP 2
so PDP does not reflect propagation delay

Better FoM: Energy-Delay Product (EDP ): energy/transition tP

1
EDP 2
CVDD tP
2
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 14.1.9 Silicon Area

Moores law:
50% shrink
per 5 years

Smaller sizes of gates more functionality per mm2

smaller parasitics faster, less power consumption
compromise !
less driving capabilities slower

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 14.1.10 Digital IC Technologies and Logic-Circuit Families

CMOS:
Advantages: - gate-lengths of MOS transistors have decreased enormously (Moore's law)
- very low dissipation (statically: none) allows dense integration
- high input resistance (gates) allows temporary storage by charge storage

- Complementary CMOS: by far most used

- Pseudo-NMOS: uses (single) PMOS as DC current source
(see chapter 15.1, not part of this course)
- Pass-transistor logic: uses MOS transistors as series and parallel combinations of switches
(see chapter 15.2)
- Dynamic logic: uses clocked circuits, circuits are periodically refreshed
(see chapter 15.3, not part of this course)
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 14.1.10 Digital IC Technologies and Logic-Circuit Families (cont.)

Bipolar:
- Transistor-transistor logic (TTL): not significant anymore, vanishing
- Emitter-coupled logic (ECL): uses BJT differential pair
fast but power hungry (see chapter 15.4)

BiCMOS:
Combined CMOS and bipolar technology
Combines best of two worlds, but more expensive

Gallium Arsenide (GaAs):

Ultra fast (due to high carrier mobility of GaAs)
ultra expensive technology 19
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 Homework (clustered):

E14.7 + E14.8
E14.10 + P14.13 + P14.14
P14.6

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