2017 International Conference on Networks & Advances in Computational Technologies (NetACT) |20-22 July 2017| Trivandrum
A LOW POWER VERNIER TIME-TO-DIGITAL
CONVERTER USING ADIABATIC LOGIC
*R.Mahima,
M.Tech VLSI Design, School of Computing
SASTRA UNIVERSITY,
Thanjavur, Tamil Nadu, India.
mahi.rmc7@gmail.com
AbstractIn this paper, an adiabatic based vernier time-
to-digital converter (VTDC) is proposed. Generally, static
based vernier TDC consumes more power due to two delay
chain and D-flipflop. To avoid this issue an adiabatic based
vernier TDC is proposed. This proposed TDC is constructed
by using adiabatic inverter and D-flipflop but in classical
TDC architecture consists of static based inverter and D-
flipflop. A high resolution with low power is achieved in
proposed TDC. Here, 2 stages, 3 stages, 4 stages traditional
and proposed vernier TDC are implemented and also
discussed about power consumption comparison of 2 stages,
3 stages, 4 stages conventional and proposed vernier TDC at
different supply voltages. This vernier TDC is simulated in
180nm CMOS technology. Its operating frequency is
1.5KHZ.
Keywords Time-to-Digital Converter (TDC); Vernier
Time-to-Digital Converter (VTDC); All-Digital Phase
Locked Loop (ADPLL); Digital Phase Locked Loop
(DPLL), Delay Locked Loop (DLL).
I. INTRODUCTION
To design an all-digital phase locked loop, TDC is
a basic building block [1]. TDC is a replacement of phase
comparator in digital pll (DPLL). All the blocks in DPLL
like phase comparator, analog based loop filter and charge
pump is replaced by TDC, digital control loop and digital
filter. After this replacement, digital PLL become all digital
PLL because all the components in this PLL is digital [2].
TDC is utilized in equivalent-time sampling in oscilloscope,
particle life time detection in physics, time-interval
analyser, on-chip jitter measurement, laser range finder and
frequency counter applications [3]. Because of the fast
advancement in VLSI innovation, the vast majority of the
TDCs are incorporated into the target systems in order to
decrease the power and cost while accomplishing high
resolutions.
978-1-5090-6590-5/17/$31.00 2017 IEEE
Mr.D.Muralidharan,
School of Computing
SASTRA UNIVERSITY
Thanjavur, Tamil Nadu, India.
murali@sastra.edu
Digital approaches using delay line methods. It can
provide the merit of lower power and also concept is
simple. Due to the intrinsic gate delay of delayed
element in DLL, resolution is low. The difference
between delay of gate helps to accomplish sub gate
delay resolution. VTDC belongs to sub-gate delay
technique. Due to this, vernier TDC provides high
resolution [4]. For achieving low power vernier TDC
adiabatic logic is used in this paper.
This paper is organized into seven sections.
Section I presents the introduction about TDC. Section II
conferred the theory of delay line based TDC. The concept
of cascadable adiabatic logic and its circuit diagram is
presented in section III. A detailed analysis of conventional
delay line vernier TDC is presented in section IV. In section
V, a novel adiabatic based vernier delay line TDC concepts
and its block diagram is presented. Section VI presents the
experimental results of conventional and proposed vernier
TDC. Section VII concludes the paper.
II. OPERATION OF DELAY LINE BASED TDC
Figure 1 displays the basic configuration of
delay line based TDC. It comprises of delayed
elements and flip-flops. Also, it consists of stop and
start signals. Here, start signal is delayed by either
inverter or buffer element [4] [5]. Similarly stop
signal also delayed by delay element. At the rising
edge of another input stop signal, sampling process
takes place which means flip-flops provide the level
of delay line. Finally output will be generated in the
form of 0s and 1s. This delay line concept is simple
to understand.
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2017 International Conference on Networks & Advances in Computational Technologies (NetACT) |20-22 July 2017| Trivandrum

IV. CONVENTIONAL DELAY LINE

VERNIER TDC (VTDC)

The basic configuration of vernier delay line is

shown in figure 3. Its main task is to quantize the time
interim between start and stop signals [11] [12]. Here,
start and stop are the two input signals. These input
signals travel through two delay chains. The delay
chain is made up of a series of buffers with different
delay. Delay1 is the delay of top chain and delay2 is the
delay of bottom chain. Delay of top chain is greater
than the bottom chain [13]. Sampling process is done
by D-flipflop. Sampling of input start signal takes place
when the rising edge of other input stop signal.
Fig.1. Principle of delay line based TDC

TLSB=Delay1-Delay2 (1)
III. CASCADABLE ADIABATIC LOGIC
Currently, there is developing hobby in TLSB is the time resolution of vernier TDC as shown in
adiabatic approach for designing circuits in low power (1). In this static CMOS based vernier TDC, the power
VLSI [6]. In digital circuits power dissipation is more. consumption and area is increased due to two delay
To avoid this adiabatic approach provides better chain and register.
solution without circuit complexity. The word
adiabatic means no exchange of heat with the
environment. Adiabatic circuits work on the principle
of adiabatic charging and discharging [7]. In
conventional CMOS circuits, the energy from the
output capacitance is discharging to the ground. In
adiabatic logic, recycle back to the power supply [8].
The amount of saving energy is more in adiabatic logic
rather than conventional one. Adiabatic technique is
also named as Energy Recovery logic [9] [10].
Figure 2 shows the circuit diagram of cascadable
adiabatic logic. This circuit consists of basic CMOS
logic along with two MOS diodes which is D1 and D2.
D1 is NMOS transistor and D2 is PMOS transistor. D1
is charging path and D2 is discharging path.
Fig.3. Traditional vernier delay line based TDC

V. PROPOSED VERNIER TDC

Generally, the traditional vernier TDC improves the
time resolution by utilizing two delay lines. Here, stop signal
is applied as clock signal to D-flipflop. At the rising edge of
stop signal, the current state of start input signal is sampled
by the D-flipflop. These chains are made up of delayed
element buffer with different delay. Difference between the
gate delays of two chains is nothing but the effective time
resolution of vernier TDC. This static CMOS based vernier
TDC consumes more power due to two delay chains and flip-
flops. The delay chain can be formed by using delayed
Fig.2. Circuit diagram of cascadable adiabatic logic
element buffer. To overcome this power consumption issue,
a cascadable adiabatic logic based vernier TDC is proposed
as displayed in fig4.

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2017 International Conference on Networks & Advances in Computational Technologies (NetACT) |20-22 July 2017| Trivandrum

TABLE I. 2 STAGE CONVENTIONAL AND

PROPOSED VERNIER TDC SIMULATION
RESULTS AT 1.8V

Fig.4. Block diagram of proposed vernier TDC

Here, single time varying supply voltage is used instead of

constant supply voltage. Using this adiabatic technique, low
power can be achieved by the charge stored in load
capacitance is discharged to the power supply instead of
discharging the capacitor charge to ground [14]. It helps to
save some amount of power. The most attractive feature of
this cascadable adiabatic technique is that there is no need of
complementary inputs [15]. So, the cascadable adiabatic
logic circuit consumes less area. It helps to minimize power
consumption. This adiabatic logic has been implemented by
adding charging and discharging paths in the existing
standard CMOS logic, using diodes and capacitors. In this
proposed vernier TDC, high dynamic range is possible with
loop structure and also sub gate delay resolution is achieved. TABLE II. 3 STAGE CONVENTIONAL AND
PROPOSED VERNIER TDC SIMULATION
RESULTS AT 1.8V
VI. EXPERIMENTAL RESULTS

Here, both the classical and adiabatic based

vernier TDC circuits are analysed and simulated in
cadence 180nm technology. An adiabatic based
proposed vernier TDC consumes less power because
adiabatic logic uses time varying supply voltage but in
classical vernier TDC a constant supply voltage is used.
vpulse is used for time varying supply voltage. For
constant supply voltage vdc is used. Also in adiabatic
logic, the energy stored in load capacitance is recycle
back to power supply rather than discharging to
ground. Both the conventional and proposed vernier
TDC circuit is analyzed for different supply voltage.
Table I shows the simulation results for both 2 stage
conventional and proposed vernier TDC at 1.8V. Table
II shows the simulation results for both 3 stage
conventional and proposed vernier TDC at 1.8V.
Similarly, Table III shows the simulation results for
both 4 stage conventional and proposed vernier TDC at
1.8V. Table IV shows the power consumption
comparison of 2 stages, 3 stages, 4 stages conventional
and proposed vernier TDC with different supply
voltage.

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2017 International Conference on Networks & Advances in Computational Technologies (NetACT) |20-22 July 2017| Trivandrum

TABLE III. 4 STAGE CONVENTIONAL AND VII. CONCLUSION

PROPOSED VERNIER TDC SIMULATION
A novel design of adiabatic based vernier delay
RESULTS AT 1.8V
line TDC is presented. In this paper, a detailed analysis
of both conventional and adiabatic based vernier TDC
also takes place. This proposed vernier TDC consumes
less power compared with conventional TDC. Here,
both the TDCs are implemented in cadence 180nm
technology. The schematic diagram, output waveform
and its power consumption output of both TDCs for 2
stages, 3 stages, and 4 stages at 1.8V supply voltage is
shown here. Similarly, the power consumption
comparison of both conventional and proposed vernier
TDC for 2 stages, 3 stages, and 4 stages with different
supply voltage is presented. This power consumption
comparison of 2 stages, 3 stages, and 4 stages of both
conventional and proposed VTDC with different
supply voltage shows that if stages increases means
obviously the power consumption is increased as well
as high resolution can be achieved. Based on user
application need the number of stages can be fixed. If
resolution plays a major role means then the number of
stages should be increased and need to sacrifice power
which means power consumption should be high.
When compared with 2, 3, and 4 stages proposed
vernier TDC, 3 stages TDC consumes moderate power
and moderate resolution. Finally, this proposed vernier
TDC achieves sub gate delay resolution with low
TABLE IV. COMPARISON OF POWER
CONSUMPTION WITH DIFFERENT SUPPLY
power.
VOLTAGE
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