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1. X + 0 = X 1D. X 1 = X
2. X + 1 = 1 2D. X 0 = 0
Idempotent laws:
3. X + X = X 3D. X X = X
Involution law:
4. ( X' ) ' = X
Laws of complementarity:
Commutative laws:
6. X + Y = Y + X 6D. X Y = Y X
Associative laws:
Distributive laws:
8. X( Y + Z ) = XY + XZ 8D. X + YZ = ( X + Y ) ( X + Z )
Simplification theorems:
10. X + XY = X 10D. X ( X + Y ) = X
DeMorgans laws:
Duality:
D D
14. ( X + Y + Z + ) = X Y Z 14D. (X Y Z) = X + Y + Z +
D
15. [ f ( X1, X2, XN, 0, 1, +, ) ] = f ( X1, X2, XN, 1, 0, , + )
Consensus theorem:
EENG115 |Page
IntroductIon to LogIc Design
Eastern Mediterranean University
Department of Electrical and Electronic Engineering
=A
NOT A NOT NOT A Double Negation
(double negative) = "A"
=1
A+A A in parallel with Complement
NOT A = "CLOSED"
EENG115 |Page
IntroductIon to LogIc Design
Eastern Mediterranean University
Department of Electrical and Electronic Engineering
=0
A.A A in series with Complement
NOT A = "OPEN"
= A
A+B . B
invert and replace OR with de Morgans
AND Theorem
= A
A.B +B
invert and replace AND with de Morgans
OR Theorem
A brief description of the various Laws of Boolean are given below with A representing
a variable input.
EENG115 |Page
IntroductIon to LogIc Design
Eastern Mediterranean University
Department of Electrical and Electronic Engineering
Annulment Law A term ANDed with a 0 equals 0 or ORed with a 1 will equal
1.
Identity Law A term ORed with a 0 or ANDed with a 1 will always equal that
term.
Idempotent Law An input that is ANDed or ORed with itself is equal to that
input.
o =0
A.A A variable ANDed with its complement is always equal to 0.
o =1
A+A A variable ORed with its complement is always equal to 1.
Double Negation Law A term that is inverted twice is equal to the original term.
o =A
A A double complement of a variable is always equal to the variable.
Associative Law This law allows the removal of brackets from an expression and
regrouping of the variables.
Using the information above, simple 2-input AND, OR and NOT Gates can be
represented by 16 possible functions as shown in the following table.
EENG115 |Page
IntroductIon to LogIc Design
Eastern Mediterranean University
Department of Electrical and Electronic Engineering
1. NULL 0
2. IDENTITY 1
3. Input A A
4. Input B B
5. NOT A
A
6. NOT B
B
8. A AND NOT B
A.B
9. NOT A AND B .B
A
12. A OR NOT B
A+B
13. NOT A OR B +B
A
EENG115 |Page
IntroductIon to LogIc Design
Eastern Mediterranean University
Department of Electrical and Electronic Engineering
16. Exclusive-NOR
A.B+A.B
Q= (A + B).(A + C)
EENG115 |Page
IntroductIon to LogIc Design