Design, Modeling and Simulation of DC-DC
Converter
Subhash Chander, Student Member, IEEE, Pramod Agarwal, Member, IEEE, and Indra Gupta
Department of Electrical Engineering,
Indian Institute of Technology, Roorkee-247667-INDIA
sub70dee@iitr.ernet.in, pramgfee@iitr.ernet.in, indrafee@iitr.ernet.in
AbstractModeling and simulation generally form an integral
part of design process. The simulation tools are increasingly
important in the development of new system and their optimum
design. This paper presents design and simple method of
modeling DC-DC converter using MATLAB/Simulink. The non-
linear parameters such as equivalent series resistance of the
inductor and capacitor and the threshold voltage of MOSFET
switches are considered in the model. Similarly, the non-linear
effects such as S/H, quantization, delay, and saturation are
considered in the closed loop controller design and simulation.
The simulation results are given to support the design validation.
Keywords- DC-DC Converter;PID Controller; Modeling and
simulation
I. INTRODUCTION
The Switched-mode dcdc converters are power electronic
systems that convert one level of electrical voltage into
another level by switching action [1]. These converters are
very popular because of their high efficiency and smaller size
[1]-[2], and therefore, are used extensively in personal
computers, computer peripherals, communication, medical
electronics and adapters of consumer electronic devices to
provide different level of dc voltages. Nowadays, even the on-
board power supplies are distributed, where the regulated
converters are used both as supply converters as well as loads
[3]-[4].The widespread use of switched mode dcdc
converters in many electronic systems makes it necessary for
system design engineers to design and develop efficient and
reliable supplies according to demand.
Switching converters are in general, time-variant, non-
linear dynamic systems. The non-linearities arise primarily
due to switching, power devices, and available passive
components, such as inductors, and capacitors. As a result, the
conventional linear control techniques can not be directly
applied to analysis. Design of the feedback compensation
using linear control techniques, needs a dynamic model of the
switching converter. The dynamic system should model the
low frequency behavior of the system, but should neglect the
insignificant behavior at and beyond the switching frequency.
Therefore, modeling process should involve the approximation
to neglect the high frequency phenomena.
The inherent switching operation of power electronic
converters results in the circuit components being connected
together in periodically changing configurations. They
represent different circuit configurations within each switching
cycle. Each configuration has been described by a separate set
I would like to thanks Govt. College of Engg. & Technology, Jammu (J&K) ,
Higher Education Deptt. J&K Govt and QIP centre, IIT Roorkee for providing
me an opportunity in Ph.D programme at IIT Roorkee.
978-1-4244-7398-4/10/$26.00 2010 IEEE
of linear state equations. A number of equations must be
solved in sequence, for the transient analysis and control
design for converters and is therefore, difficult. The averaging
technique provides a solution to this problem where a single
equation may be formed to describe the converter
approximately over a number of switching cycles by simply
taking a linearly weighted average of the separate equations
for each switched configuration of the converter. The filtering
action by L-C presents a physical basis for using an average
model of the switch, which neglects its switching action while
preserving quantitative relationships between average values
of voltages and currents at its terminals [2]. The average
model provides much faster simulation and an additional
opportunity for small-signal analysis and control design using
MATLABs Control System Toolbox.
The computer simulation plays a vital role in the design and
analysis of power electronic converters and their controllers
and it shorten the overall design process [5] .The package like
the MATLAB/Simulink [6] is a very useful environment for
design and simulation of switching converters. The system
stability and transient behavior analysis can be performed using
these tools.In this paper, MATLAB/Simulink package is
chosen as software platforms for design and simulation of Buck
converter. The controller is designed, tested and simulation
results are obtained using Simulink model of the converter
topology.
II. DESIGN OF BUCK CONVERTER
The mode of operation i.e., CCM or DCM is decided by the
inductor current .If the inductor current remains positive, the
dc-dc converter is said to operate in CCM [2].The buck
converter of Fig.1 operates in CCM, the relationship between
the input voltage (Vi) and the output voltage (VO) is given as:
d =V0 /Vi (1)
Where, d=TON /TS is the duty-cycle, TS is the switching period
and TON is conducting time of the switch. The boundary
condition of CCM and DCM of the Buck converter is the
critical value of the inductor LC and is given by [2]:
LC= (1-d)R/2.fS (2)
Where, R is the load resistance, and fS is the switching
frequency. The selected inductance should be greater than LC
for CCM [2]. However, the inductor value determines the
magnitude of ripple current in the output capacitor as well as
the load current at which the converter enters discontinuous
mode. Normally, a ripple of less than 30% of the average
456 IPEC 2010
output current is considered for design [7] so as to provide the
reasonable efficiency. The value of L can be determined as:

d (Vin -V0 ) = fs. L. I (3)

Figure 2. Modeling of buck converter

For ideal non-isolated buck converter on-time:uQ1=u=1 ;off-

time: uQ2=u=1.The dynamic and output equations of buck
Figure 1. Power stage of buck converter converter are:
di L
The initial choice of the capacitor C is then determined by L = (V i VT )u V T u i L rL V 0 (6)
dt
the allowed voltage ripple V, which is typically 2% of output CdVC/dt=iL-V0/R (7)
voltage. The overall output voltage ripple is the sum of the
voltage spike caused by the ESR of the output capacitor plus V0=VC.[R/(R+rC)]+iL.[R.rC/(R+rC)] (8)
the voltage ripple caused by charging and discharging the After mathematical manipulation of above equations, the final
output capacitor and is given as[8]: dynamic and output equations of buck converter are given as
1 under:
V = I + ESR (4) di L
8
s f C L = (V i VT )u VT u i L rL V C G1 i L G 3 (9)
dt
However, the output capacitance requires to be increased to
CdVC /dt =iLG1-VCG2 (10)
account for load transient [7].The value of capacitance
depends on the change in the load, the speed of the loop and
V0=VCG1+iLG4 (11)
the size of the inductor and is given by:
2 2
( I OH I OL ) (5)
C=L Where G1=[R/(R+rC)], G2=[1/(R+rC)], G3=[rL+R.rC/(R+rC)]
(V f2 Vi2 ) and G4=[R.rC/(R+rC)] (12)
Where, IOH and IOL is the output current under heavy load and
The Simulink model of buck converter, developed using (9),
light load conditions respectively. Vf and Vi is the final peak (10),(11) and (12) is given in Fig.(3) and Fig(4) shows the
and the initial capacitor voltage respectively. The following subsystems of Fig.3.
parameters are considered for design Vi =510% V, Vref=2.5V,
R=1-2, V0=2.52%, I0=1.25amps, output ripple of 25 mV
(p-p) at 1.25 amps, (steady state), output load response of 0.25
V (load step change from 1.25 to 2.5 amps),I=0.5 amps
(20% of load current),rC=5m, rL=10m, I=20% of I0 and
fs=200KHz.The L=12H and C=47f are the values arrived
at, for the final design.
III. MODELING OF BUCK CONVERTER
Switching converters after design may be numerically
simulated using the system equations in the system level
simulation tool like Simulink [6].
Figure 3. Simulink Model of buck converter (Power stage)
A. Modeling of Power Stage
The Simulink requires the system equations of the power
stage circuit of Fig.2 [6].A Simulink model is then developed
from these system equations, as shown in Fig.3 and Fig.4. The
dynamics of this converter operating in CCM, can be
understood by using analysis of the circuit and the conduction
status of the MOSFET switches Q1and Q2.The switching
action of the switch is described by the switching function u,
which accepts the values of 0 and 1 [8] and the dynamic
equations of converter are written defining the switching
intervals [8] .For active switch (Q1) conducting:uQ1=1;uQ2=0
and for Freewheeling switch (Q2) conducting: uQ1=0;uQ2=1.
Figure 4. Simulink models of G1, G2, G3 and G4 sub-systems of Fig.3

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B. Modeling of close loop controller
Converter system requires a feedback to regulate the output
voltage. The feedback system must be designed so that the
output voltage is accurately regulated, and is insensitive to
disturbances in Vin or load current. In addition, the feedback
system must be stable, and provide good transient overshoot
and settling properties.Fig.5 shows a closed loop of digitally
controlled buck converter, where the error signal Ve, which is
the difference between the output voltage VO, and the desired
reference voltage Vref, is minimized through the compensator,
which generates the duty cycle command to the Digital Pulse
Width Modulator (DPWM). The output of the controller is a
digital representation of the duty cycle, d[MSB,.,LSB]and the
DPWM processes this duty cycle command to create a driving
signal which controls the ON-time of the main switch, S in the
power stage.
Figure 5. Digitally controlled buck Converter
To study the behavior of converters closed loop, the
linearized model of buck converter is needed. As shown in
Fig.5, the closed loop block diagram has four major modules:
power stage, ADC, PID controller and DPWM. In the
linearized model shown in Fig.6, the transfer function for each
module is required, to determine the systems frequency
response. The plant model Gsys is obtained by multiplying the
individual transfer functions.
Figure 6. Linearized model of buck converter
1) Power stage model Gvd(s)
The Small signal control to output transfer function Gvd(s) of
the buck converter shown in Fig 2, is given by [9]
Vi (s .rC .C + 1)
G (s ) =
vd
R + rC R + rL L R + rL
s 2 LC + s rC .C + + rL .C +
R R R R G C (z ) =
With specified parameters, the Gvd (s) is given by:
1.175e 006.s + 5
Gvd (s ) =
5.654 e 010 s 2 + 6.706 e 006.s + 1.005
2) ADC model Gadc (s)
The ADC gain depends on the resolution of ADC. The 8-bit
ADC operating from a 4.0V supply provides the discrete
levels separated by approximately 15.6 mV (4.0/255).So the
resolution is VQ =15.6 mV, Hence the ADC gain is
Kadc=1/VQ=64. Let tadc is the conversion time of ADC then the
transfer function of ADC is given by:
Gadc (s ) = K adc .e t adc (15)
3) DPWM model Gdpwm(s)
The DPWM module gain Kdpwm is defined as
K dpwm = 1 n
(16)
2 1
Where n is the resolution of selected DPWM, for 8-bit
resolution Kdpwm =1/255. Let d is the steady state duty cycle of
the power converter, TS is the switching period, tdpwm is the
delay time due to signal latch between DPWM and controller.
Then the transfer function of DPWM is given by:
s( d .TS + t dpwm ) (17)
G dpwm ( s ) = K dpwm .e
The plants model Gvd(s) is obtained as:
s( tadc + dTs +tdpwm )
Gsys = K adc K dpwm .Gvd .e (18)
The time delay associated with the ADC sampling, duty
calculation and DPWM duty ratio updating is normally taken
equals to switching period i.e Ts= (tadc+dTs+tdpwm). This
includes the sample and hold effect of both ADC and PWM.
Gsys = K adc K dpwm .Gvd .e s( Ts ) (19)
The plants transfer function of (19) is used to design a PID
controller.
IV. DESIGN OF PID CONTROLLER
The performance of a closed loop converter is highly
influenced by controller parameters. The controller ensures
stable operation of the converter. A PID controller is designed,
considering small-signal average model of the buck converter
[9].The digital redesign approach is selected for controller
design; as it requires minimal design in the discrete z-domain
[10].
An analog controller is first designed as if one were
building continuous time control system by ignoring the
effects of S/H associated with the ADC and the digital PWM
circuits. The analog controller is then converted to a discrete
time compensator by using pole-zero matching method. This
method produces simpler transfer functions in the z-domain
[10].It preserves the pole and zero locations of the analog
controller [11].The control law of discrete form of PID
compensator has the following forms:
d (n ) a + bz 1 + cz 2
= (20)
e (n ) 1 z 1
(13)
The corresponding difference equation for implementation,
which is utilized to calculate a new duty cycle, is given as:
(14) d(n)=d(n-1)+a.e(n)+b.e(n-1)+c.e(n-2) (21)
Where e(n), e(n-1), e(n-2) are the error signals of the nth,
(n-1)th and (n-2)th sample, respectively. The d(n-1) is the
duty-cycle command stored from the previous cycle, d(n) is
the current duty cycle command which is the controller output
for nth sample. Here, a, b and c are the controller coefficients
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to be determined.
A PID controller is designed initially assuming Kadc=1,
Kdpwm=1 in (19) .The controller is first designed in the analog
domain, then its discrete equivalent is obtained and the initial
values of coefficients a, b and c are determined. They are then
scaled by taking into account the actual values of Kadc and
Kdpwm i.e 64 and 1/255 respectively to determine actual
values of controller coefficients a, b and c. Equation (19), with
switching frequency fs=200KHz, Ts=td=5e-006 sec , can be Figure 7. Simulink Model of PID controller
written as:
1 . 175 e 006 s + 5
G sys ( s ) = G vd .e s .Ts = e 5 e 006 . s
5 . 654 e 010 s 2 + 6 . 706 e 006 s + 1 . 005
(22)
Using pade approximation, the transfer function Gsysd is
given by:

1.175e 006.s 2 4.53.s + 2e006 (23)

Gsysd (s ) =
5.654 e 010 s 3 + 0.0002329 s 2 + 3.687 s + 4.02e005
The design must satisfy the following criteria:
The gain at low frequencies should be high enough to
minimize the steady-state error [12].
The 0-dB frequency of the closed-loop system should Figure 8. Step input response of PID controller
be lower than one-third of the switching frequency
[12]. Fig.9 shows the Bode plots of open loop buck converter, when
processing delay zero, which indicates that although the
The phase margin of the compensated system should system is stable; but it has a small phase margin, of 9.29 deg.
be in the range of 45 to 60 [13]. The Bode plots of Fig.10 of buck converter with processing
After attempting several combinations of numbers for the delay Ts, shows that the system is unstable.
PID coefficients as shown in Table 1 in the stable region, the
selection of the controller parameters is done by comparing
their transient responses.

TABLE I. CONTROLLER PARAMETERS AND CORRESPONDING TRANSIENT

RESPONSE

PID Controller Step Response performance

Parameters Parameters
a b c Overshoot Settling Rise time
(%) Time (ms) (us)
09.88 -17.74 07.95 14.00 00.364 10.80
10.70 -19.20 08.65 15.50 00.396 09.90
12.55 -23.90 11.36 07.11 12.600 08.76
13.10 -24.80 11.80 09.59 01.260 08.48
11.80 -21.50 09.80 14.40 00.377 08.81
Figure 9. Bode Plots of buck converter (power stage) model (td=0 )
Finally a PID controller with a combination of scaled
controller coefficient a=13.10, b=24.80 and c=11.80, was
found to be of reasonable controller coefficients for the
application. The z-domain transfer function using scaled
controller co-efficient and the corresponding difference
equation is given by (24) and (25). The Simulink model of
PID controller is developed using (25), as shown in Fig.(7)
d ( n ) 13.10 24 .80 z 1 + 11 .80 z 2
GC ( z ) = = (24)
e( n ) (1 z 1 )
d(n) = d(n-1)+13.10 e(n)-24.80 e(n-1)+11.80 e(n-2) (25)
Step input tests were conducted to test the designed PID
controller of Fig. (7).Fig.8. is the result from estimated model;
it shows a rise time of 8.48 us and a settling time of 1.26 ms,
with overshoot of 9.59 Figure 10. Bode Plot of buck converter model with Ts delay

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The presence of delay term in the model makes the system
unstable. The magnitude plots of both figures are same, but the
phase plots are different .It can be concluded the delay term
affects the phase only. A controller is designed as above to
overcome these limitations to ensure stable response. From
Fig.11, the proposed controller gives a positive gain margin of
13.7db and a positive phase margin of 49.5 deg of the closed
system, which make the system stable. The proposed closed-
loop system has a bandwidth of about 22.9 KHz .This design
controller has good performances as verified in section V.
Figure 11. Closed loop Bode plot of buck converter
V. SIMULATION RESULTS
A Matlab/Simulink model developed for Buck converter of
Fig.5 is shown in Fig.12. It is composed of power stage
modeled in section II, feedback controller designed in section
IV, ADC and DPWM models, in addition to the variable load
and source voltage. The ADC model consists of an element
that performs subtraction of the output voltage from the
reference to generate the error voltage, ADC gain, S/H,
quantization effects, delay, and saturation blocks.
Figure 12. Closed loop Simulink model of buck converter of Fig.5
In the considered model, the DPWM generates the pulse signal
corresponding to duty cycle command is presented by the
controller and it has 8-bit resolution. The quantizer, gain block
and a duty ratio limiter are included. The variable load source
voltage models are included in the converter to study the
dynamic performances of the converter and The variable
source block and a variable load block provide voltage
460
Vi=510% V and the load transition from 2-1-2 . Fig.13.
shows the simulation results for, the output current i0, inductor
current iL and output voltage V0. The change in input voltage is
shown in Fig.13 (b), the nominal voltage of 5V changes to
5.5V, 5V, 4.5V and back to 5V at 2 ms, 4ms, 6ms and 8ms
respectively. The converter has load of 1.25 amps and changes
to 2.5 amps and back to 1.25 amps in t= 0, 2.5ms, 5ms
respectively corresponding to R=2-1-2 ohms as shown in Fig
13(a).
Figure 13. Closed loop response of buck converter
The variation of error voltage e(n) is shown in Fig.(14a).The
e(n) varies between 4 ,because of error limiter present in the
ADC model. The PID controller model represented by (25)
and shown in Fig.7 is designed, simulated and explained in
section IV. The duty cycle command d(n) generated by PID
controller corresponds to the error signal e(n) is shown in
Fig(14b).The duty command values varies between 0.0-0.8.
Figure 14. Variation of error voltage e(n) and duty command d(n)
The transient response of the closed loop buck converter is
shown in Fig.15. It can be concluded that the output voltage
settles to steady state with in 0.1ms after the input voltage
transition, with overshoot and undershoot is less than 4%. The
settling times for (L to H) 1.25 to 2.5 amps load transition is
0.3ms and for (H to L) is 0.4ms.The overshoot and undershoot
for these conditions are 11% and 14% respectively for 0 to
100% and 100% to 0% (of the nominal load) load transitions.
Simulation results demonstrate that the approach presents both
high steady state and dynamic performances.
Figure 15. Transient response of buck converter
VI. CONCLUSION
In this paper, the MATLAB/Simulink environment is used
for design and simulation of closed loop Buck converter .The
different subsystem models including the PID controller are
designed and simulated. These models are then used to
evaluate the closed-loop behavior of the converter. The
accuracy of this approach is verified from the simulation
results presented in section-V.The ADC and PWM are
designed and developed using the simulink blocks taking a
number of non-linear effects. The simulation results show that
such method of modeling is very useful to study the closed
loop behavior of converters, before its implementation in a
dedicated FPGA or ASIC.
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Subhash Chander graduated in Electronics and Communication
Engineering from National Institute of Technology, Srinagar
(J&K) India in 1993. He completed his Post-graduate in
Electronics and Communication Engineering from Indian
Institute of Technology, Roorkee-India in 2004. He is an
Assistant Professor in the Department of Electronics and
Communication, Govt. College of Engineering and Technology, Jammu
(J&K). Currently, he is pursuing research in the field of DC-DC Converters
for low power applications at the Electrical Engineering Dept. Indian Institute
of Technology Roorkee, India. His fields of interest include Micro-electronics,
Low-power VLSI designs and FPGA based design, DC-DC Converters for
low power applications.
Pramod Agarwal obtained his Bachelors degree in Electrical
Engineering from University of Roorkee, now Indian Institute of
Technology Roorkee (IITR), India. He received his Post-
graduate and completed his PhD in Electrical Engineering from
IITR in 1985 & 1995 respectively. He was a Postdoctoral
Fellow with the University of Quebec, Montreal, QC, Canada, from 1999 to
2000. Currently, he is a Professor in the Department of Electrical Engineering,
IITR. His fields of interest include electrical machines, power electronics,
power quality, FPGA based design, microcontroller, microprocessors and
microprocessor-controlled drives, active power filters, multilevel converters,
and application of dSPACE for the control of power converters.
Indra Gupta obtained his Bachelors degree in Electrical
Engineering from HBTI Kanpur, in 1984 He received his Post-
graduate and completed his PhD in Electrical Engineering from
University of Roorkee now Indian Institute of Technology
Roorkee, India in 1986 & 1996 respectively. Currently, he is a
Associate Professor in the Department of Electrical Engineering, IITR. His
fields of interest include simulation, Process Control applications,
Microprocessor applications, ANN, Online Control applications and FPGA
based Design.