Single-Phase Hybrid Switched-
Capacitor
Voltage-Doubler SEPIC PFC Rectifiers
Paulo J. S. Costa, Carlos H. Illa Font, Member, IEEE, Telles B. Lazzarin, Member, IEEE
Abstract In this paper, the switched-capacitor concept is
extended to the voltage-doubler DCM SEPIC rectifier. As a
result, a set of single-phase hybrid SEPIC PFC rectifiers able to
provide lower voltage stress on the semiconductors and/or higher
static gain, which can be easily increased with additional
switched-capacitor cells, is proposed. Hence, these rectifiers
could be employed in applications that require higher output
voltage. In addition, the converters provide a high power factor
and a reduced total harmonic distortion in the input current. The
topology employs a three-state switch, and three different
implementations are described, two being bridgeless versions,
which can provide gains in relation to efficiency. The structures
and the topological states, a theoretical analysis in steady state, a
dynamic model for control and a design example are reported
herein. Furthermore, a prototype with specifications of 1000 W
output power, 220 V input voltage, 800 V output voltage and 50
kHz switching frequency was designed in order to verify the
theoretical analysis.
Index Terms Voltage-doubler DCM SEPIC, Single-phase
rectifier, Switched capacitor, Bridgeless, High power factor.
I. INTRODUCTION
I high dc output voltage for use in distributed generation, n
recent years, the market demand for power supplies with
renewable energy, energy storage, dc-dc smart grids, electrical
vehicles, UPS, X-ray systems, and motor drivers has increased
[1]-[3]. In these applications the power supply can be used to
directly feed a load or as an input stage of another power
converter [3]. In both cases, the system is commonly fed by an ac
grid. Hence, a converter with power factor correction (PFC) is
required to provide a high power factor and reduce the total
harmonic distortion in accordance with the regulations and
standards, such as IEC 6100-3-2 [4].
Due to the current source characteristic at the input, structures
derived from Boost converters are normally employed in stages
with power factor correction. Some Boost rectifiers suitable for
applications with high output voltage are
This work was supported by CAPES Brazilian Federal Agency for
Support and Evaluation of Graduate Education within the Ministry of
Education of Brazil, Federal University of Santa Catarina and Power
Electronics Institute (INEP).
P. J. S. Costa and T. B. Lazzarin are with the Department of Electrical
Engineering, Federal University of Santa Catarina, Florianopolis, Brazil
(email: paulojunior@inep.ufsc.br; telles@inep.ufsc.br).
0885-8993 (c) 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
C. H. Illa Font is with the Department of Electronics Engineering, Federal
University of Technology Paran, Ponta Grossa, Brazil (e-mail:
illafont@utfpr.edu.br).
proposed in [5]-[8]. These topologies are referred to as voltage-
doubler rectifiers and provide, when compared to the
conventional Boost rectifier, gains in relation to cost and
efficiency and supply twice the output voltage (hence the term
voltage-doubler) or a lower voltage stress on the
semiconductors.
Other examples of PFC rectifiers available for application with
higher output voltage are the voltage-doubler SEPIC converters
addressed in [6], [9] and [10]. These converters operate in
discontinuous conduction mode (DCM), because in this
operation mode the input current naturally has the same shape (if
the high-frequency ripple of this current is neglected) and phase
of the input voltage [9], [11], [14]. Hence, the rectifier does not
require a current control loop, which simplifies its control system.
Furthermore, in the case of these rectifiers, the input current does
not have the third harmonic, do not need additional bulk filters
[10], [13], [14], and impose reduced voltage stress on the
semiconductors.
On the other hand, recent publications describe a new class of
PFC rectifiers, referred to as hybrid (pulse-width-modulated +
switched capacitor) rectifiers [3]. This class integrates
conventional rectifiers with the switched-capacitor converters
(SCC), which are able to divide or multiply a voltage without
increasing the voltage stress across the semiconductors [3], [15]-
[18]. Hence, this new class of PFC rectifiers can be employed in
applications that require higher dc output voltage (above 400 V).
Although the concept of hybrid rectifiers is recent, it has
already provided opportunities for new lines of research [3], [16],
[19], [20]. In this context, based on the voltage-doubler SEPIC
rectifier in [10], multiplier SEPIC dc-dc converter in [15],
switched capacitor (SC) cell in [17], hybrid rectifiers in [3], [16],
[19], [20] and studies described in [9], [11], [12] and [21]-[27],
this paper proposes a set of single-phase hybrid voltage-doubler
SEPIC rectifiers. These rectifiers provide a high power factor,
reduced total harmonic distortion (THD), reduced voltage stress
on the semiconductors and higher dc output voltage values
(above 800 V).
The Boost converters integrated to SC cells approached in [3]
and [16], in contrast to the proposed rectifiers in this paper,
operate in continuous conduction mode (CCM). Therefore, these
structures require a control loop to regulate the input current,
which makes the control system of the converter more complex.
Furthermore, the Boost rectifiers operate with variable duty
cycle, which increases the losses in the SC. The converters
addressed in [15] and [17]-[18] use the conventional ladder SC
 cell in dc-dc and ac-ac conversion and the same cells are applied
in [3] and [16]. The conventional ladder SC cell does not work in
the SEPIC rectifier. Hence, in [19-20] was proposed a modified
ladder SC cell that allows the integration between SCC and
classical SEPIC rectifier. Despite employing an additional
semiconductor, this modified cell allows the rectifier to work
properly and it preserves the high quality of the input current,
which is an important characteristic of the SEPIC rectifiers that
operate in DCM. However, only a partial analysis of the
switched-capacitor integrated to the classical SEPIC rectifier is
approached in [19] and [20].
The proposed converters provide an increase of the static gain
and a reduction in the voltage stress on the semiconductors in
relation to the rectifier addressed in [10], but the structures use
more elements. With regard to the converters described in [19]
and [20], the proposed rectifiers also employed a greater number
of components. Nevertheless, these rectifiers provide, for a same
number of switched capacitor cells, a reduction in the voltage
stress on the semiconductors and are able to process twice more
power, because these converters work as two half-wave rectifiers,
one for each half-line cycle. Due to the characteristic of operation
in half-line cycle, the current and voltage stress are divided
among the elements of the circuit and, consequently, the
proposed rectifiers can process higher power levels.

II. THE PROPOSED SINGLE-PHASE HYBRID

VOLTAGEDOUBLER SEPIC RECTIFIERS
The structure of the hybrid voltage-doubler SEPIC rectifier
(seen in Fig. 1) requires a three-state switching cell, which can be
implemented in three modes: the first (1S) employs one active
switch, as seen in Fig.1 (b); the second (2S) is shown in Fig. 1 (c)
and uses two active switches; and the third (4S) is shown in Fig.
1 (d) and employs four active switches. These cells can be used
in applications that require a static gain (M) less than, equal to or
greater than one (M 1, M 1). It is important to highlight that
regardless of the cell employed the main topological states of the
circuit are not changed.
Fig. 1. (a) The proposed single-phase hybrid voltage-doubler SEPIC rectifier
The proposed structure increases the static gain of the voltage-
with three-state generic active switching cell and generic switched-capacitor
doubler SEPIC rectifier by adding of ladder-type switched- cell, (b) three-state switch with one active switch (1S), (c) three-state switch
capacitor cells. The elements CS1, CS2, Co3, Co4, De1, De2, De3, De4, with two active switches (2S - bridgeless version), and (d) three-state switch
De5, De6, Do2 and Do4 integrate the first and second modified with four active switches (4S - bridgeless version).
switched-capacitor cells. These two cells have two extra diodes
(De1-Do2 and De4-Do4) (when compared to the conventional
switched-capacitor cell [3], [15]-[18]) which allow the charge A. Operation Stages of the Proposed Rectifier
and discharge of the switched capacitors CS1 and CS2, without The bridgeless version with two active switches (Fig. 1 (a) and
changing the voltage in Ci1 and Ci2 (this modified cell was (c)) and two ladder-type switched-capacitor cells (n = 2) were
proposed for the conventional SEPIC rectifier in [19] and [20]). chosen to analyze the proposed converter. The structure 2S
The resulting structure is able to provide a high quality input presents a lower number of components and thus the conduction
current [20] and thus the switched-capacitor can be applied in the losses can be reduced. It employs two switches, but these use the
SEPIC rectifier. The other cells, seen in Fig 1 (a) (CS_n-De_n- same gate drive signal. The structure analyzed is shown in Fig. 2.
De_n+1-Co_n, and CS_n+1De_n+2-De_n+3-Co_n+1), are conventional The rectifier presents eight topological states in DCM, four of
ladder switchedcapacitor cells and are added to increase the static them for the positive cycle of the grid. In these states, the current
gain of the rectifier. It is important to highlight that in the case of flows through the green and black connections (as illustrated in
the proposed rectifier in Fig. 1 the step-down and step-up Fig. 3). The other four topological states are for the negative
operation of the conventional SEPIC is maintained. cycle, when the current flows through the blue and black
connections. In steady-state operation, the voltage stresses on Ci1-
Ci2 and CS1-CS2-Co1-Co2-Co3-Co4 are, respectively, vg and Vo/(2 +
n), where vg is the input voltage and Vo is the average value of

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 the output voltage. The first four states are described below in
detail.
Stage 1 (Fig. 3 (a)): This stage starts when the switch S1 is
turned on. The diodes D1, De1 and De2 are forward-biased while
all other diodes are reversed-biased. The elements S1,
De1 and De2 connect the capacitors Co1 and CS1 in parallel.
However, the charge current of CS1 does not flow through Ci1 due
to the modified switched-capacitor cell. The switched capacitor
CS1 is charged by Co1 from S1, De1 and De2 and it presents voltage
equal to vCo1 which, in turn, is equivalent to vo/(2 + n). The
current in the inductors Li and Lo1 increases linearly in agreement
with the vg/Li and vg/Lo1 ratios, respectively. The load Ro is fed by
the capacitors Co1, Co2, Co3 and Co4.
Stage 2 (Fig. 3 (a)): This state is initiated when the switch S1
is turned off. Diodes D1, Do1, Do2 and De3 are forwardbiased and
all other diodes are blocked. The elements Do2, Do1 and De3
connect CS1 and Co4 in parallel. Hence, the voltages on theses
capacitors are equal to Vo/(2 + n). The current that flows through
these elements is provided by inductors Li and Lo1. The current in
the inductors Li and Lo1 decreases accordingly with relations
[Vo/(2 + n)]/Li and [Vo/(2 + n)]/Lo1, respectively. The load Ro
and output capacitors are supplied by energy previously stored in Fig. 2. The proposed single-phase hybrid voltage-doubler SEPIC rectifier with
Li and Lo1 in the first stage. two active switches (2S-bridgeless version) and with n = 2.
Stage 3 (Fig. 3 (c)): During this stage the switch S1 remains
turned off and the diodes D1, Do2 and De3 are forward-biased. III. DESIGN EQUATIONS
Diode Do1 and all other semiconductors are blocked. The A. Voltage-Doubler SEPIC Converter Cell Design
capacitors CS1 and Co4 remain connected in parallel through the
The main design equations for the voltage-doubler SEPIC
diodes Do2, Do1 and De3. The energy stored in the inductors Li and
converter cell are reported in Table I. Details of the determination
Lo1 flows through Do2, CS1 and De3 to the load Ro and the output
of these numerical expressions can be found in [10].
capacitors.
Stage 4 (Fig. 3 (d)): This subinterval is the traditional B. Switched-Capacitor Cell Design
discontinuous stage of the SEPIC converter. During this stage all
Fig. 7 (a) highlights the ladder-type switched-capacitor cells
of the semiconductors are turned off and the current in the
integrated with the voltage-doubler SEPIC rectifier. These cells
inductors Li and Lo1 is constant. Hence, the voltage across these
can be represented by an equivalent circuit, such as that shown in
inductors is zero. The voltage on the capacitors CS1, CS2 Co1, Co2,
Fig. 7 (b), where Ron-c is the total conduction resistance of the
Co3 and Co4 is equal to Vo/(2 + n). The load Ro is fed by the output
switched capacitor (semiconductors resistances (Ron) plus the
capacitors.
capacitor resistances (Rce)).
B. Main Ideal Waveforms The switched-capacitor cell shown in Fig. 7 (b) can be
represented by an equivalent resistance (Req) as shown in Fig. 7
The main theoretical waveforms of the proposed converter, for
(c). The value of Req is defined by the expression (1) [23] and it
the case where the input voltage achieves the highest level, which
is a function of the system switching frequency (fs), duty cycle
is denominated as (Vp), are shown in Fig. 4, Fig. 5 and Fig. 6. The
waveforms for one switching period are shown in Fig. 4 and Fig. (D) and time constant defined in (2).
5. These figures show the current and voltage in the inductors Li,
Lo1 and Lo2, the current in the capacitors Ci1, Ci2, CS1 and CS2, and
the current and voltage on the semiconductors S1, S2 and Do1, (1)
Do2, Do3 and Do4. Fig. 6 shows, for one grid period, the input Req = D 1

voltage (vg), input current (iLi), current in the output inductors

(iLo1 and iLo2), output voltage (vo) and voltage on capacitors Ci1,
Ci2, Co1, Co2, Co3, Co4, CS1 and CS2 (vCi1, vCi2, vCo1, vCo2, vCo3,
vCo4, vCS1, vCS2). It can be verified that the proposed rectifier has
a high power factor and ensures the multiplication of the output
where Ron is the conduction resistance of the semiconductors and
Rce is the equivalent series resistance of the capacitors.
Based on (1), the behavior of the equivalent resistance in
relation to fs to one fixed duty cycle was traced, as shown in Fig.
8 (a). The value of D = 0.35 was chosen because this ensures the
MCD of the voltage-doubler SEPIC converter. From this curve
one can define three different operating modes of the switched
capacitor: Total charge (Tc), Partial

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 ( )c
Operation stages of the rectifier 2S with n = 2 for positive cycle of voltage grid: (a) first stage, (b) second stage and (c) third stage, and (d) fourth stage.
charge (Pc) and No charge (Nc) [22]. For each mode the behavior
of the current in the capacitor differs, as is demonstrated in Fig.
8 (b), (c) and (d).
Based on the curve of Req (Fig. 8 (a)) and the current behavior
in each operating mode (Fig. 8 (b), (c) and (d)) it can be
concluded that the Tc mode presents greater loss due to the higher
peak current; however, it requires a lower capacitance value
(considering constant switching frequency). The Nc mode
presents less loss; however, it requires higher capacitance values.
Therefore, in relation to losses and volume, Pc is the best
operating mode.
( )d
Fig. 3.
The Pc boundaries are shown in Fig. 8 (a). The border with Tc
presents Req = 14.4 Ron-c and fs = 0.07. On the other hand, the
border with Nc occurs at Req = 4.44 Ron-c and fs = 1.306. Thus,
there is a considerable difference between these limits. Fig. 8 (a)
also defines an internal operation point, where fs is equal to 0.5.
This point has an equivalent resistance of 1.08 pu regarding the
minimal resistance (when fs tends to infinity Req reaches its
lowest value of 4.4, considering D = 0.35). After fs = 0.5, if the
fs value is increased by a factor of two, the Req value reduces by
only 6%. This analysis suggests the use of an fs value equal to
or close to 0.5, because fs > 0.5 increases the volume of the CS
or the switching frequency; however, it

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 Stages Stages

T
S De6 are described, respectively, in
Fig. 4. Ideal waveforms (currents) for a switching period of the rectifier 2S with n
= 2.

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 switchedcapacitor cell employed in the proposed rectifier and (c) equivalent
resistance of the switched-capacitor cells.

(4 DV Vo ) ,
2 2
DVIC
p S 1 max IC S 1 min p
(5)
IC S 1 _ RMS = C S 2 _ RMS =
2 Vo
IC o 3 _ RMS = IC o 4 _ RMS =
(6)
( )+
2
( IC S 1max IR o ) Vo
2 2 3
2 DV p R o Vo
2
VR
oo

Fig. 7. Switched-capacitor cell: (a) switched-capacitor cell integrated with

voltage-doubler SEPIC rectifier, (b) equivalent circuit of the

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 n is an even number which is greater than or equal to two.
Vp: peak value of the input voltage; Vo: average value of the output voltage;
Po: output power; Ro: load resistance; Req: equivalent resistance of the
C. Generalization of Switched-Capacitor Cell Number
switched capacitor cell; L : equivalent inductance; i : ripple current of the
eq Li
The proposed converter is able to provide high output voltage,
inductor Li; VCi1: ripple voltage of the capacitor Ci1; fs: switching frequency; since it can be generalized by adding switchedcapacitor cells, in
D: duty cycle and thut: hold-up-time, ICS1max: maximum current in CS1; ICS1min: a modular way, as demonstrated in Fig. 1. Thus, the number of
minimum current in CS1. components in the multiplication stage, the average values for the
output voltage and the voltage stress on the elements are directly
and proportional to the number of switched-capacitor cells employed.
A generalization in relation to the number of switched-capacitor
Req cells (n) can be seen in Table III.
20 Ronc

[.007144
, .]
IV. CONTROL AND DYNAMIC MODEL
A. Dynamic Model for Control
12Ronc
SEPIC rectifiers, when operating in DCM, do not require a
control loop for the input current because in this operation mode
[.005472
,. ] [.1306444
,. ] the converter emulates a load with resistive characteristic.
Therefore, the proposed rectifiers need only an output voltage
4 Ronc control, which is demonstrated in Fig. 9.
The equivalent electric circuit shown in Fig. 10 is used to
0 analyze the dynamic model for the output voltage in relation to
0 0.2 0.4 0.6 0.8 1 1.2 1.4 f s
Total charge - Tc Partial charge - Pc No charge - Nc the duty cycle of the proposed topology. It considers the average
Ronc = Ron + Rce ()a quantities and it is valid for small signals.
ic s ic s ic s The value of the current io illustrated in Fig. 10 is defined by

d I2 eq
io = . (8)
4M
t t t
()b ()c ()d
This current is modified when the output voltage (vo) or the
duty cycle (d) is changed. However, vo is also dependent on d.
Fig. 8. Switched-capacitor cell: (a) behavior of Req as a function of fs, (b)
Therefore, there is a correlation between the variables io, d and
current in CS for total charge mode, (c) current in CS for partial charge mode
and (d) current in CS for no charge mode.
vo, which has to be considered in the dynamic model.
Therefore, the output current is defined as
TABLE II
RANGES FOR THE OPERATING MODES OF CS
Operating mode Operating Interval Req regarding
minimal resistance
( ) dvo vo ,
(9)

Tc fs 0.07 fs 0.07 3.27 pu io d v, o = Coeq +

fs 0.5 1.08 pu dt Ro
Pc 0.07 < fs < 1.306
fs 1.0 1.02 pu
Nc fs 1.306 fs 1.4 1.01 pu where

TABLE III (Cox1 +Cox2 ) 4DVp (Cox3 +Cox2 )

SWITCHED-CAPACITOR CELL: GENERALIZATION OF THE NUMBER OF
ELEMENTS AND VOLTAGE STRESS
D C Cox1 ox2 + C Cox3 ox2 . (10) Vo
Number of Elements or Voltage Stress Design Equation
Coeq =
n is an Number of Diodes 2 4n+ even + Vo
C Cox2 ox4 Vo
Number of capacitors 2n number
(1D)4DVp
which Value of the output voltage
(2+ n VC) o1 is greater
than or equal to and (Cox2 +Cox4 )
two. Maximum voltage stress on Do2 and Vp
Do4
Maximum voltage stress on Do2, Do4, (C +C )C C Co2 o3
Vp
De1 and De4 o1 S1 o4
IDe1_ Maximum voltage stress on De2, De3, Vo
De5, De6 and De_n 2 +n
AVG...IDe6_ AVG = D I2 eq . (7) Maximum voltage stress onCS_n and Vo
4M Co_n 2 +n

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 Cox1 =;Cox2 = (Co1 +CS1)+Co4 Co2 +Co3 , (11) (Co4 +CS1)Co1 C Co1 o4
Cox3 =;Cox4 =
(Co4 +CS1)+Co1 Co1 +Co4

Cox1, Cox2, Cox3 and Cox4 being auxiliary variables.

From the (9) is obtained likewise as in [10] the equation

( ) dvo vo .
(12)

io d v, o = Coeq +
dt Ro

Applying (7) in (11) gives

DIeq D2 ,

( )=
v (13)
i d v, d
o o 2 o
2M 4M Leq sf

which, matched to (8), results in

Vrf Cp ( s ) M pwm G (s ) vo

H vo
Fig. 9. Bloc diagram for the output voltage control.

iC oeq iRo

io (dv, o ) Coeq Ro vo

Fig. 10. Equivalent circuit of the output for voltage control. Fig. 11. Dynamic Model of the rectifier 2S with n = 2: (a) steady-state and
transient-state behavior, and (b) steady-state detail of vo and vmod.

TABLE IV
DESIGN SPECIFICATIONS
Specification Value
Input voltage 220 V
Frequency of the input voltage 60 Hz
Output voltage 800 V
Output power 1000 W
Switching frequency 50 kHz
Maximum duty cycle 0.35
Hold-up time 8.333 ms
Capacitors Ci1 and Ci2 ripple 20%
Inductor Li ripple 10%

DIeq d D2 2 vo = Coeq dvdto Rvoo . (14)

+
2M 4M Leq sf

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 On applying the Laplace transform in (14) is obtained the transfer of 0.4 kW/kg and power density of 0.31 kW/L. It was built based
function on the specifications and list of components reported in Tables
IV and V, respectively. The experimental results were obtained
with the rectifier operating with rated power (1000 W) and in
TABLE V closed-loop.
LIST OF COMPONENTS The experimental waveforms for the voltage and the input
Component Specifications current are shown in Fig. 13. The current has a sinusoidal shape
Inductance: 3.385 mH and it is in phase with the respective voltage, even without a
Turns: 156 current control. It has a THD of 1.96% and power factor of
Inductor Li
Wire: 16 AWG 0.9991. Its harmonic spectrum is shown in Fig. 14,
Core: APH46P60
Inductance: 60.3 H
Turns: 29
Inductor Lo
Wire: 64 x 32 AWG Core:
EE42/20 3c94
Transistors S1 and S2 IPZ65R019C7 (650 V/19 m)
Diodes Do1 and Do2 MUR1560 (600 V/15 A)
Diodes De1 ... De6 C3D08060A (600 V/11 A)
Diodes D1 and D2 MUR860 (600 V/8 A)
Capacitors Ci1 and Ci2 B32672P5155K (1.5 F/520 V)
Capacitors Co1 Co4 B43845-A0158-M (2 x 1.5 mF/250 V)
Capacitors CS1 and CS2 C4AEGBW6100A3NJ (100 F/450
V)
Fig. 12. Photograph of the rectifier 2S with n = 2 implemented: A = Capacitors
CS1 and CS2; B = output capacitors; C = output inductors; D = input inductor;
vo ( ) s
E = capacitors Ci1 and Ci2; F = drivers for the switches S1 and S2.
k (15)
G s( )= =
d s( ) R Co oeqs+ Dk +1 vg
2Vo
iLi
which represents the converter model for small-signal average
values, where

k= DR Io eq . (16)
2M

T :5 ms
B. Validation of Dynamic Model for Control Fig.13. Input voltage (100 V/div) and input current (5 A/div) of the rectifier
The small-signal model proposed for the control was validated 2S with n = 2.
by numeric simulation using the specifications shown in Tables
IV and V. During the test, at t = 4.2 s the duty cycle is increased 2.5
in 1.4% and after 1.8 s (t = 6 s) the value returns to the standard
value. This procedure provided the output voltage waveforms of 2.0
the converter (Fig. 2) and of the model (15), which are shown in
Fig. 11 (a) and (b). The results reported in this figure demonstrate 1.5
that the proposed model adequately represents the converter in
IEC 61000-3-2 Limits
steady and transient states. It can be seen, as expected, that the 1.0
Harmonic Val ue
model does not represent the 120 Hz ripple and high frequency
ripple. 0.5

V. PROTOTYPE AND EXPERIMENTAL RESULTS 0

3 9 15 21 27 33 39
A. Verification of the Proposed Rectifier Harmonic Number
In order to verify the concept of the proposed converters a 1 Fig. 14. Harmonic spectrum of input current of the rectifier 2S with n = 2 and
IEC61000-3-2 limits.
kW prototype was built. The three-state switch chosen for the
implementation was that referred to as 2S (Fig. 2 (c)). The
number of switched-capacitors cells used in the implementation
was two (n = 2). The prototype 2S (Fig. 12) has a specific power

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 times higher than the voltage of a classic SEPIC rectifier and
twice the voltage of the voltagedoubler SEPIC rectifier addressed
vo in [6], [9] and [10].
The experimental waveforms of the currents in the capacitors
iRo CS1 and CS2 are shown in Fig. 18. As in the case of the voltage,
the capacitor currents present two components: one at 60 Hz and
another at 50 kHz. The peak and rms values are close to 15 A and
5.9 A, respectively.
The voltage waveforms across the semiconductors S1-S2 and
Do1-Do3 are seen in Fig. 19 and Fig. 20, respectively. The voltage
stresses on these elements were 566 V-557 V and 565 V-562 V,
:5
Tms respectively. From the design specifications (listed in Table IV),
Fig. 15. Output voltage (100 V/div) and current (300 mA/div) waveforms of the theoretical maximum voltage applied on S1, S2, Do1 and Do3
the rectifier 2S with n = 2. is equal to 511 V, namely, the sum of

Fig. 16. Output voltage (100 V/div) and voltages on capacitors Co1, Co4 and
CS1 (50 V/div) of the rectifier 2S with n = 2.

Fig. 17. Output voltage (100 V/div) and voltages on capacitors Co2, Co3 and
CS2 (50 V/div) of the rectifier 2S with n = 2.

where all harmonics are lower than the IEC61000-3-2 limits.

The waveforms of the voltage and output current can be seen
in Fig. 15. These variables presents a ripple of 120 Hz and
average values of 802 V and 1.26 A, respectively. Thus, at this
operation point, the output power supplied by the rectifier was
1010 W.
The waveforms of the output voltage and the voltages across
the capacitors CS1, CS2, Co1, Co2, Co3 and Co4 are shown in Fig. 16
and Fig. 17. The results verified the voltage balance among Co1,
Co2, Co3 and Co4, which was supported by capacitors CS1 and CS2.
The capacitor voltages are around 200 V and these present two
components, one low frequency component (at 60 Hz) and
another high frequency component (at 50 kHz). The average
value of the output voltage (vo) is close to 800 V, which is equal
to four times the voltage on the capacitors. This value is four

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 with n = 2. Fig. 23. Voltages across the diodes De1, De2 and De3 (100 V/div) of the rectifier
2S with n = 2.

the peak value of the input voltage and a quarter of the output
voltage (for a case with two switched-capacitor cells). On the
vDo1 other hand, the conventional SEPIC rectifier with the same
specifications would have a theoretical voltage stress on the
semiconductors of 1111 V. Hence, it would be necessary to use
higher voltage devices, which would lead to higher conduction
losses.
The waveforms of the currents that flow through the
vDo3 components S1-S2 and Do1-Do3 are shown in Fig. 21 and Fig. 22.
These currents have one frequency component at 60 Hz and
T:10
s
another at 50 kHz. The rms values of the currents in switches S1
Fig. 20. Voltages across the diodes Do1 and Do3 (200 V/div) of the rectifier 2S and S2 are approximately 10 A and 9.5 A, respectively, while the
with n = 2. average values of the currents in Do1Do3 are 1.28 A and 1.2 A,
respectively.
The waveforms of the voltages across the diodes De1, De2 and
De3 are shown in Fig. 23. The voltage on De1 has a sinusoidal
envelope with frequencies of 60 Hz and 50 kHz. The maximum
iS1 voltage stress was 309 V. The measured voltages across De2 and
De3 also have one component in low frequency and another in
high frequency (60 Hz and 50 kHz, respectively). The
corresponding maximum values of these voltages are close to 204
V and 214 V.
The dynamic response of the converter to a load step of 41%
is demonstrated in Fig. 24. The output voltage presented an
iS 2
overshoot of 2% and settling time of 500 ms.
T:10
s
Fig.21. Current through the switches S1 and S2 (20 A/div) of the rectifier 2S
with n = 2.

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 Fig. 27. Measured THD of the rectifier 2S with n = 2.

vo The efficiency, THD and PF curves for the 1 kW 2S prototype

are shown in Fig. 25, Fig. 26 and Fig. 27. The maximum
efficiency was 94.3 %, obtained at half load, and the efficiency
at rated power was 93.9%. These results are significant because
the rectifier does not use the soft commutation technique and it
operates in discontinuous conduction mode. With regard to THD
iLi and PF, the best performance occurred at rated power with values
of 1.96 % and 0.9991, respectively.
iRo
T:200 ms B. Comparison between the Proposed Rectifiers and Other
Fig. 24. Response dynamics of the rectifier 2S with n = 2: vo-100 V/div; iLi5 Solutions
A/div; iRo-1 A/div. The main goal of this section is to present a comparison of the
proposed hybrid rectifier with other bridgeless SEPIC rectifiers
94.5% reported in the literature. Hence, the structures described in [10],
[20] and [21] were used for comparison purposes and to highlight
the main advantages and drawbacks of the proposed structure. In
94.0%
this regard, three converters employing the three-state switch
with two active switches (2S) were considered.
93.5% Table VI presents a qualitative comparison in relation to the
number of components. In contrast to the bridgeless SEPIC
rectifier [21], the proposed converter employs seven fast diodes,
93.0%
one inductor and six extra capacitors. In relation to the converter
reported in [10], the proposed hybrid SEPIC rectifier uses eight
92.5% extra fast diodes and four extra capacitors. When compared to the
100 200 300 400 500 700 800 900 1000
Output Power (W) converter approached in [20], the proposed converter has three
fast diodes, one inductor and four extra capacitors.
Fig. 25. Measured efficiency of the rectifier 2S with n = 2. A qualitative analysis is shown in Table VII. In relation to the
three bridgeless rectifiers considered ([10], [20] and [21]), the
1.000 proposed hybrid converter provides a higher reduced voltage
stress on the semiconductors. Consequently, semiconductors that
0.995
support lower voltage stress can be employed, or the structure can
be used to provide a higher output voltage with the same voltage
stress on the semiconductors regarding to the previously
0.990 rectifiers.
In conclusion, the main contribution of the proposed converter
is that it provides lower voltage stress on the semiconductors
0.985
when compared to the bridgeless SEPIC rectifiers in [10], [20]
and [21]. Furthermore, the gain of the proposed rectifier can be
0.980 increased by adding more switched capacitors and, thus, it has a
100 200 300 400 500 700 800 900 1000
Output Power (W) generic static gain, which is related to the number of switched-
capacitor cells. However, as a drawback, it employs a higher
Fig. 26. Measured power factor of the rectifier 2S with n = 2. number of components.

06.5%
VI. CONCLUSIONS
This paper proposed the integration of the single-phase
05.5%
voltage-doubler SEPIC rectifier with the switched capacitor (SC)
concept. As a result, a set of hybrid rectifiers was generated.
04.5%
These rectifiers improve the static gain of the voltage-doubler
SEPIC converter without increasing the voltage stress on the
03.5%
semiconductors, making them suitable for applications that
require high output voltage levels (above 800 V). The structures,
02.5%
a theoretical analysis and the experimental validation of this
integration are the main contributions of the paper.
01.5%
100 200 300 400 500 700 800 900 1000 The switched-capacitor cell integrated to the voltagedoubler
Output Power (W) SEPIC rectifier has extra diodes, which contribute to
TABLE VI

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 QUANTITATIVE ANALYSIS
Bridgeless Bridgeless Bridgeless
Proposed Voltage Stress V V V
SEPIC SEPIC SEPIC
Characteristics Rectifier Rectifier Rectifier Rectifier on Switch Vg + o Vg +Vo Vg + o Vg + o
in DCM1 in DCM in DCM in DCM 4 2 2
[21]1 [10]1 [20]1 Voltage Stress V V V
on Switch for Vg + o Vg +Vo Vg + o Vg + o
Input current 0 0 0 0
control a n generic 2+ n 2 2
Voltage Stress V V V
Current sensor 0 0 0 0
on Diodes Vg + o Vg +Vo Vg + o Vg + o
Output voltage 1 1 1 1
4 2 2
control
Voltage Stress V V V
Voltage sensor 1 1 1 1 on Diodes for Vg + o Vg +Vo Vg + o Vg + o
Number of 2 2 2 2 a n generic 2 2
2+ n
Switches1
Rms current in
Number of fast 10 3* 2 7* 1 pu 0.844 pu 0.66 pu 1.34 pu
switches
diodes Avg Current in
Number of slow 2 2 2 2 1 pu 1 pu 1 pu 1 pu
Low Diode
diodes Avg Current in
Number of 3 2 3 2 1 pu 1 pu 1 pu 1 pu
Output Diode
inductors Rms Current
1 pu 0.72 pu 0.72 pu 1 pu
Number of 8 2 4 4 in Co1 and Co2
capacitors Rms Current
1 pu - - -
1 Bridgelessstructure implemented with two active in Co3 and Co4
switches. *The converter uses the intrinsic diodes of the Rms Current 1 pu - - 1.02 pu
switches. in CS1 and CS2
Rms Current
TABLE VII in SEPIC 1 pu 1.41 pu 1 pu 1.41 pu
QUALITATIVE ANALYSIS Capacitor
Bridgeless Bridgeless Bridgeless PF 1 1 1 1
Proposed SEPIC SEPIC SEPIC The proposed converter employs a three-state switching cell,
Characteristics Rectifier in Rectifier Rectifier Rectifier which can be implemented in three forms. Of these, the
DCM1 in DCM in DCM in DCM bridgeless version with two active switches (Fig. 1 (c) - 2S) was
[21]1 [10]1 [20]1
chosen for the theoretical analysis and experimental verification.
Static gain 2 2 2 2 The converter implemented was tested at rated power (1 kW) and
DR o DR o DR o DR o
4 Leqsf 4 Leqsf 4 Leqsf 4 Leqsf it provided a current with a THD of 1.96%, PF of 0.999 and
efficiency of 93.9%. These results are significant because the
rectifier does not use the soft commutation technique and
operates in DCM.

ACKNOWLEDGMENT
The authors would like to thank the Brazilian governmental
agency CNPq (National Council for Scientific and
Technological Development) for its contribution to this work in
the form of a grant provided to Paulo Junior Silva Costa.

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c) 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more
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Paulo Junior Silva Costa was born in
So Jos do Rio Claro, Brazil, in 1988. He
received the B.S. degree in industrial
automation technology, in 2011, and the
M.S. degree in electrical engineering, in
2015, both from the Federal University of
Technology Paran (UTFPR), Ponta
Grossa, Brazil. He received the Ph.D.
degrees in electrical engineering from the Federal University of
Santa Catarina (UFSC) in 2017. His interests include PWM
rectifiers, switched-capacitors, and DC-DC converters.
Carlos Henrique Illa Font (S04M09)
was born in Erval Grande, Rio Grande do
Sul, Brazil. He received the B.S., M.S. and
Ph.D. degrees in electrical engineering from
the Federal University of Santa Catarina
(UFSC), Florianpolis, Brazil, in 2001,
2003 and 2009, respectively.
He is currently an Adjunct Professor
with the Department of Electronics
Engineering, Federal University of Technology Paran,
Campus Ponta Grossa. His research interests include power
electronics, power factor correction, AC-DC converters, and
power converters for small-scale renewable energy.
Dr. Illa Font is a Member of the Brazilian Power Electronic
Society, IEEE Power Electronics Society and IEEE Industrial
Electronics Society.
 Telles Brunelli Lazzarin (S09M12) was
born in Cricima, Santa Catarina
State, Brazil, in 1979. He received the
B.Sc., M.Sc. and Ph.D. degrees in Electrical
Engineering from the Federal
University of Santa Catarina (UFSC),
Florianpolis, Brazil, in 2004, 2006 and
2010, respectively.
He is currently an Adjunct Professor at the Department of
Electrical and Electronic Engineering (EEL) from the UFSC,
and he also works as a Researcher at the Power Electronics
Institute (INEP), UFSC. His interests include
switched-capacitor converters, inverters,
rectifiers, parallel operation of converters, highvoltage dc-dc
converters and conversion systems for small wind turbines.
Dr Lazzarin is a member of the Brazilian Power Electronic
Society (SOBRAEP), IEEE Power Electronics Society (PELS)
and IEEE Industrial Electronics Society (IES).

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