562 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO.

1, JANUARY 2013

A Compact X-Band Bi-Directional Phased-Array T/R

Chipset in 0.13 m CMOS Technology
Sanghoon Sim, Member, IEEE, Laurence Jeon, and Jeong-Geun Kim, Member, IEEE

AbstractThis paper presents an X-band bi-directional T/R

chipset in 0.13 m CMOS. The T/R chipset consists of a bi-direc-
tional gain amplifier (BDGA), a 5-bit digital step attenuator with
two BDGAs for compensating the switch losses, and a 6-bit phase
shifter using DPDT switches. The phase and attenuation coverage
is 360 with the LSB of 5.625 , and 31 dB with the LSB of 1 dB,
respectively. The circuit has a reference state gain of db,
and the return losses of db at 8.510.5 GHz. The T/R chipset
has a phase shift accuracy with the RMS phase error of ,
while the RMS amplitude error is db at 8.510.5 GHz.
The attenuation accuracy is measured to be db, while the
RMS phase error is at 8.510.5 GHz. The output P1dB
of the T/R chipset is dBm and the noise figure is db
at 8.510 GHz. The chip size is 2.06 0.58 including pads, Fig. 1. Block diagram of a typical T/R module.
and the DC power consumption is 154 mW only in the BDGAs.
To authors knowledge, this is the X-band CMOS T/R chipset
with the competitive RF performance compared to other device
technologies, which has the smallest size and the lowest power low noise performance [11][13]. CMOS back-end T/R chipset
consumption to-date. provides the multi-function such as controlling the gain and
Index TermsBi-directional T/R chipset, CMOS T/R chipset, phase to steer the antenna beam and null. Even though SiGe
phased array antenna. technology is popularly adopted to implement the T/R chipset,
FET switches are necessary in the control circuits, such as
the phase shifter and attenuator. Therefore, CMOS is a better
I. INTRODUCTION choice to implement the T/R chipset with lower manufacturing
cost and less power consumption than SiGe [14][16]. Low
loss switches are essential in the control circuits. However, the
T HE phased array antenna requires the features such as
light weight, scalability, low DC power consumption,
and low production cost [1][3]. Currently, T/R chipsets using
switch loss in bulk CMOS is usually higher than in GaAs due
to the conductive substrate. Recently, switch configurations
with low insertion loss were introduced, such as floating body
matured GaAs technology are commercially available [4],
techniques [17], [18]. To improve the gain of the T/R chipset
[5]. However, it has large chip size with high DC power
further, additional bi-directional gain amplifiers with compact
consumption, and is very expensive. As the silicon technolo-
size are required. Recently, bi-directional T/R chipsets have
gies are getting developed, silicon-based T/R chipsets have
been introduced in the literatures [19], [20]. However, they
been introduced with moderate RF performances [6][10].
have large chip size because of the separate transmitting and
Silicon-based T/R chipset enables to reduce the manufacturing
receiving amplifiers and also have narrow fractional operating
cost and integrate multiple T/R channels in a single die [8].
bandwidth.
Fig. 1 shows the typical block diagram of the recent T/R
This paper presents an X-band CMOS bi-directional T/R
module architecture using GaN and CMOS technologies. The
chipset with a BDGA, a phase shifter, and a digital step atten-
GaN-based bi-directional amplifier usually consists of two T/R
uator in a single die with the smallest chip size and the lowest
switches, PA, and LNA. It produces high output power and
DC power consumption.

Manuscript received July 11, 2012; revised October 29, 2012; accepted
November 06, 2012. Date of publication December 19, 2012; date of current
II. DESIGN OF X-BAND CMOS T/R CHIPSET
version January 17, 2013. This work was supported in part by the National
Fig. 2 shows the circuit block diagram of the proposed
Research Foundation of Korea (NRF) Grant funded by the Korea government
(MEST) (No. 2009-0080362) and in part by the Dual Use Technology Program X-band CMOS bi-directional T/R chipset. The T/R chipset
of the DUTC. This paper is an expanded paper from the IEEE MTT-S Interna- is comprised of a BDGA, 5-bit attenuation block, and a 6-bit
tional Microwave Symposium, Montreal, QC, Canada, June 1722, 2012.
digital phase shifter. The proposed BDGA provides bi-direc-
S. H. Sim and L. Jeon are with the RFcore Co, Ltd., Seongnam-si,
Gyeonggi-do 463-760, Korea (e-mail: romantic@rfcore.com). tional amplification without two T/R switches. This results in
J.-G. Kim is with the Department of Electronic Engineering, Kwangwoon reducing the switches losses and the chip size. The attenuator
University, Seoul 139-701, Korea (e-mail: junggun@kw.ac.kr).
is split to three attenuation sections with two BDGAs that
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. compensate the insertion loss. The 6-bit digital phase shifter
Digital Object Identifier 10.1109/TMTT.2012.2227786 is implemented with DPDT switches to improve the insertion

0018-9480/$31.00 2012 IEEE

SIM et al.: COMPACT X-BAND BI-DIRECTIONAL PHASED-ARRAY T/R CHIPSET
Fig. 2. Circuit block diagram of the proposed X-band CMOS T/R chipset.
Fig. 3. (a) Schematic of the bi-directional gain amplifier without two T/R
switches. (b) Equivalent circuit of the amplifier in the forward operation.
losses and reduce the chip size. All the inductors, the inter-
connection lines, and the GSG pads are simulated with EM
simulator of Sonnet.
A. Bi-Directional Gain Amplifier (BDGA)
Fig. 3(a) shows the circuit schematic of the proposed bi-di-
rectional amplifier without two T/R switches at the input and
the output. The amplifier consists of the single stage distributed
amplifier paired with the cascode configuration. In forward op-
eration from to , the transistors of and are ON
563
Fig. 4. Schematic of the switched T-type resistive attenuator with the phase
error correction capacitance of .
and the transistors of and are OFF. Therefore, there is
no current path through the transistor of and . Then, as
shown in Fig. 3(b), a single stage distributed amplifier is formed.
All the transistor sizes are 150 m. The gate inductance of
is , and the drain inductance of is . The
drain bias of is provided by the RF choke. The other sides
of the input and the output ports are terminated with the
of 50 . The simulated gain is around 8 dB at 812 GHz. The
symmetric layout is performed to provide the nearly identical
operation in the forward and the reverse modes.
B. 5-Bit Attenuation Block
As shown in Fig. 2, a 5-bit switched digital step attenuator is
designed including two BDGAs to compensate the switch losses
and increase the transmission signal level at the high attenua-
tion states. The maximum attenuation is 31 dB with the LSB of
1 dB. The MSB of 16 dB is implemented with two separate 8
dB attenuators to avoid abnormal operation by leakage signals
from the switches. Fig. 4 shows the circuit schematic of the unit
attenuator cell. Floating body and N-well technique is applied
to the FET switches to improve the insertion loss with 10 .
Since the parasitic capacitances of the ON and OFF states at
the switch transistors are very different, this results in the phase
error at high frequency. In other words, the OFF capacitance
of the makes a zero, which makes a direct signal path be-
tween and . The additional shunt capacitance of is put
in parallel with to make a pole to cancel the zero at the series
transistor of to reduce the phase error. The series inductors
of are included at the input and the output ports to
improve the matching characteristic. The designed parameters
564 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 1, JANUARY 2013

Fig. 5. Circuit schematic of the X-band 6-bit phase shifter.

TABLE I
DESIGN PARAMETERS OF THE T-TYPE RESISTIVE ATTENUATORS

of the attenuators are summarized in Table I. The simulated gain

of the attenuator is around 13 dB at 10 GHz. The proposed atten-
uation block provides bi-directional operation since the passive
attenuation networks and the BDGAs are used.

C. X-Band 6-Bit Phase Shifter

The X-band 6-bit phase shifter is designed with the phase
coverage of 360 and the LSB of 5.625 . The phase shifter
using DPDT and SPDT switches is proposed to reduce the in-
sertion losses and the chip size in Fig. 5. Since the switch ele-
ments and the phase shifting network are separated from each
other except the state of 5.625 , the optimization can be per-
formed individually. The proposed phase shifter is composed
of two SPDT switches, four DPDT switches, phase shifting el-
ements with LPF and HPF network, and a switched phase shift
network of 5.625 . The absorptive DPDT and SDPT switches
are employed in the phase shifter. Since the insertion loss of
the phase shifter is mainly determined by the series transistors
of the DPDT and the SPDT switches, the number of the series
transistors in the signal path should be reduced to improve the
insertion loss. Fig. 6(a) shows the DPDT switches using the
absorptive configuration for high isolation. The DPDT switch
is implemented with four parallel- and cross-connected series
transistors of 66 m and four shunt transistors of 7 Fig. 6. Circuit schematics of (a) the DPDT and (b) the SPDT switch using the
m . The shunt transistors improve the iso- floating body technique.
lation to prevent unwanted leakage signals. Floating body and
N-well technique is used in the switches to improve the insertion
loss. The simulated insertion loss and the isolation are db 5 series transistors is eliminated compared to a design imple-
and db in the DPDT switch. The SDPT switch with the mented only with SPDT switches.
absorptive configuration is used at the input and output ports The phase shifting elements are designed with the filter net-
in Fig. 6(b). The of is inserted to improve the works. The phase state of 5.625 is implemented using the par-
matching at the port. The simulated insertion loss and the allel connection of (50 m) and (280 ) due to low
isolation are db and db in the SPDT switch. Since phase shift in Fig. 5. The phase states of 11.25 and 22.5 are
the input signal passes through only 7 series transistors in the implemented with LPF and BPF networks, and the states of 45 ,
proposed 6-bit phase shifter configuration, the insertion loss of 90 , and 180 with LPF and HPF networks. The inductances
SIM et al.: COMPACT X-BAND BI-DIRECTIONAL PHASED-ARRAY T/R CHIPSET 565

Fig. 7. Microphotograph of the X-band CMOS T/R chipset (chip size: 2.06 0.58 including pads).

and the capacitances in the filter networks are iteratively de-

signed due to the parasitic elements of the inductors and the ca-
pacitors. Vertically stacked spiral inductors with the top metal
of M8 layer and the metal of M7 layer are used to reduce the
chip size. The capacitances are implemented with MIM capac-
itor supported by PDK. The proposed phase shifter provides
bi-directional operation since it is implemented with only pas-
sive devices. The simulated insertion loss of the reference state
is around 11 dB at 10 GHz.

III. MEASURED RESULTS

The X-band T/R chipset is fabricated in a commercial 0.13
m CMOS technology. Fig. 7 shows the microphotograph of
the fabricated X-band CMOS T/R chipset. The chip size is
2.06 0.58 including pads. On-wafer measurements are Fig. 8. Measured S-parameters of the bi-directional gain amplifier.
carried out for the performance characterization. GSG pads
are inserted between sub building blocks to test each building
block. Then, the GSG pads of the each block are bonded to-
gether with Au wire to implement and characterize the X-band
single channel T/R chipset.

A. Bi-Directional Gain Amplifier

The chip size of the BDGA is 0.39 0.58 including
pads. Fig. 8 shows the measurement results of the gain and
in/output return losses at the operating temperature of 20 and
80 . The simulation results at 20 are also plotted for the
comparison. The DC power consumption is 43 mW at 2.4 V
supply voltage. At 20 , the measured gain of db and the
in/output return losses of db are achieved at 8.510.5 GHz.
The reverse operation performs almost identically as the for-
ward operation due to the symmetric layout. The gain decreases Fig. 9. Measured output power and gain of the bi-directional gain amplifier.
as the temperature increases because of the constant voltage
bias. At 80 , the measured gain is db for 8.510.5 GHz.
The gain variation less than 0.2 dB is measured as the supply simulated results at 8.510.5 GHz. The noise figure variation
voltage varies from 2.16 V to 2.64 V, which is variation due to the supply voltage variation is negligible from 2.16 V to
of 2.4 V. 2.64 V.
Fig. 9 shows the power characteristics of the amplifier at
8.510.5 GHz. The measured output P1dB is dBm, B. 5-Bit Attenuation Block
and the saturated output power is dBm. Fig. 10 shows The chip size of the 5-bit attenuation block is 0.77 0.58
the measured noise figure for the operating temperatures at including pads. Fig. 11 shows the measured transmission
2080 . The noise figure is db for 8.510.5 GHz at gain of the attenuation block in major attenuation states. The
20 . The noise figure is increased about 0.7 dB at 80 . simulated transmission gain of the reference state is plotted for
The measurement results are around 1.3 dB higher than the comparison, which is around 13 dB at 10 GHz. The measured
566 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 1, JANUARY 2013

Fig. 10. Measured noise figure of the bi-directional amplifier as varying the Fig. 12. Measured insertion losses of the phase shifter in major phase states.
operation temperatures.

Fig. 13. Measured phase characteristic of the phase shifter in major phase
states.
Fig. 11. Measured attenuation characteristics of the attenuation block in major
attenuation states.

transmission gain of the reference state is db at 8.510.5

GHz. The maximum attenuation of 31 dB with the LSB of 1 dB
is achieved. The measured RMS attenuation error of db
and the RMS phase variation of are achieved at 811
GHz. The total DC power consumption is around 86 mW with
the supply voltage of 2.4 V due to the two additional BDGAs
for the loss compensation.

C. X-Band 6-Bit Phase Shifter

The chip size of the phase shifter is 0.88 0.58 in-

cluding pads. The measured insertion losses of the phase shifter
in major states are db at 8.510.5 GHz as in Fig. 12. The
measured insertion losses are around 2 dB higher than the simu-
lation results. Fig. 13 shows the measured phase characteristics
of the phase shifter in major phase states. The maximum phase
shift of 360 with 5.625 step is achieved. The measured RMS
phase error of and the RMS amplitude variation db
are achieved at 8.510.5 GHz, respectively. The total DC power
consumption is nearly 0 mW with 1.2 V control voltage due to
all passive operation using DPDT and SPDT switches.
Fig. 14. Measured gain of the T/R chipset in all attenuation states.
D. X-Band Single Channel T/R Chipset
The GSG pads of the each building block are bonded with Au
wire to implement X-band single channel T/R chipset. Fig. 14
shows the measured transmission gain in all attenuation states
at the reference phase state of 0 in the phase shifter. The trans-
mission gain at the reference state is around 3.8 dB at 10 GHz.
SIM et al.: COMPACT X-BAND BI-DIRECTIONAL PHASED-ARRAY T/R CHIPSET 567

Fig. 18. Measured transmission gain of the T/R chipset as varying the operation
Fig. 15. Measured input and output return losses of the T/R chipset. temperatures.

Fig. 16. Measured phase characteristics of the T/R chipset in all phase shift Fig. 19. Measured RMS phase and amplitude errors of the T/R chipset due to
states. the attenuator as varying the operating temperatures.

Fig. 20. Measured RMS phase and amplitude errors of the T/R chipset due to
Fig. 17. Measured output power and gain of the T/R chipset. the phase shifter as varying the operating temperatures.

The input and output return losses are db at 811 GHz Fig. 17. The total DC power consumption is around 154 mW
as shown in Fig. 15. Fig. 16 shows the measured phase charac- with 2.4 V supply voltage, which is only from three BDGAs.
teristics in all phase states at the reference state of 0 dB in the Fig. 18 shows the measured gain characteristics due to the
attenuation block. temperature variation from 20 to 80 at the supply voltage
The output P1dB of the T/R chipset is dBm and the of 2.4 V as well as the supply voltage variation from 2.16 V
saturated output power is dBm at 8.510.5 GHz as in to 2.64 V at 20 . The gain is decreased due to biasing the
568
PERFORMANCE COMPARISON OF THE X-BAND PHASED-ARRAY T/R CHIPSETS
Fig. 21. Measured gain variation of the T/R chipset for all phase states.
Fig. 22. Measured noise figure of the T/R chipset as varying the operation tem-
peratures.
constant voltage at the gate of the BDGAs as increasing the
temperatures. This can be solved with PTAT bias circuits. The
gain variation due to the supply voltage variation is around 1
dB from 2.16 V to 2.64 V. As shown in Fig. 19, the measured
RMS amplitude error of db and the RMS phase error of
are achieved at the reference state of the phase shifter
as varying the temperature from 20 to 80 . In Fig. 20, the
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 1, JANUARY 2013
TABLE II
measured RMS phase error of and the RMS amplitude
error db are achieved at the reference state of the attenu-
ator as varying the temperature from 20 to 80 . The RMS
phase and amplitude errors do not change much even though the
operating temperatures are varied from 20 to 80 . Fig. 21
shows the measured gain variation for all phase states of the
T/R chipset. The gain variation is db at 8.510.5 GHz.
Fig. 22 shows the measured noise figure of the T/R chipset as
varying operation temperature. The noise figure at 20 of the
T/R chipset is db at 8.510.5 GHz. The noise figure is in-
creased by less than 1.2 dB at 80 . The performances of the
X-band bi-directional T/R chipset using various device tech-
nologies are compared in Table II. It shows that the demon-
strated CMOS T/R chipset shows the lowest power consump-
tion and the smallest chip size with the competitive RF perfor-
mances except the output P1dB.
IV. CONCLUSION
This paper presents an X-band bi-directional T/R chipset in
a commercial 0.13 m CMOS technology. The low loss circuit
topologies such as the phase shifter using DPDT switches and
floating body techniques are incorporated in the T/R circuit. The
BDGA without T/R switches is proposed to provide the bi-di-
rectional operation with the moderate gain and compact size.
The circuit provides the phase shift of 360 with 5.625 , and the
attenuation of 31 dB with 1 dB with low RMS phase and am-
plitude errors. The gain is db at 8.510 GHz. The output
P1dB of the T/R chipset is dBm and the noise figure is
db at 8.510 GHz. The compact chip size of 2.08 0.58
is achieved with the low DC power consumption of 154
mW. The demonstrated X-band T/R circuit shows the compet-
itive RF performance except the output power, which can be
overcome by increasing the transistor size and the stages. The
proposed CMOS T/R chipset can be applied to the low cost
X-band phased array antenna.
ACKNOWLEDGMENT
The authors thank Prof. G. M. Rebeiz in University of Cali-
fornia, San Diego, Prof. Y. Eo in Kwangwoon University, and
Prof. D. Baek in Chung-Ang University for the helpful discus-
sion and encouragement.
SIM et al.: COMPACT X-BAND BI-DIRECTIONAL PHASED-ARRAY T/R CHIPSET
REFERENCES
[1] E. Brookner, Never ending saga of phased array breakthroughs, in
Proc. IEEE Phased Array Syst. Tech. Symp. Dig., Oct. 2010, pp. 6173.
[2] P. Schuh, H. Sledzik, R. Reber, K. Widmer, A. Fleckenstein, B.
Schweizer, and M. Oppermann, T/R module technologies today and
future trends, in Proc. 39th Eur. Microwave Conf., Oct. 2010, pp.
15401543.
[3] C. E. Patterson, T. K. Thrivikraman, A. M. Yepes, S. M. Begley, S.
K. Bhattacharya, J. D. Cressler, and J. Papapolymerou, A lightweight
organic X-band active receiving phased array with integrated SiGe am-
plifiers and phase shifters, IEEE Trans. Antennas Propag., vol. 56, no.
1, pp. 100109, Jan. 2011.
[4] Datasheet of XZ1002-BD. M/A-COM Tech Asia, Hsinchu, Taiwan
[Online]. Available: www.macomtechasia.com/pdf/XZ1002-BD.pdf
[5] Datasheet of CGY2170YUH. OMMIC, Limeil-Brvannes, France
[Online]. Available: www.ommic.com/prod/telechargement/
Datasheets/CGY2170YUH_PDS_160412.pdf
[6] J. P. Comeau, M. A. Morton, W. L. Kuo, T. Thrivikraman, J. M. An-
drews, C. M. Grens, J. D. Cressler, J. Papapolymerou, and M. Mitchell,
A silicon-germanium receiver for X-band transmit/receive radar mod-
ules, IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 18891896, Sep.
2008.
[7] N. Carosi, A. Bettidi, A. Nanni, L. Marescialli, and A. Cetronio, A
mixed-signal X-band SiGe multi-function control MMIC for phased
array radar applications, in Proc. 39th Eur. Radar Conf., Oct. 2009,
pp. 240243.
[8] D. W. Kang, J. G. Kim, B. W. Min, and G. M. Rebeiz, Single and
four-element Ka-band transmit/receive phased-array silicon RFICs
with 5-bit amplitude and phase control, IEEE Trans. Microw. Theory
Tech., vol. 57, no. 12, pp. 35343543, Dec. 2009.
[9] J. C. Jeong and I. B. Yom, X-band high power SiGe BiCMOS multi-
function chip for active phased array radars, Electron. Lett., vol. 47,
no. 10, pp. 618619, May 2011.
[10] T. Dinc, S. Zihir, and Y. Gurbuz, SiGe building blocks for on-chip
X-band T/R modules, in Proc. IEEE Topical Meeting SiRF, Jan. 2012,
pp. 5760.
[11] A. Bettidi, A. Cetronio, M. Cicolani, C. Costrini, C. Lanzieri, S. Macca-
roni, L. Marescialli, M. Peroni, and P. Romanini, X-band T/R module
in state-of-the-art GaN technology, in Proc. 39th Eur. Radar Conf.,
Oct. 2009, pp. 258261.
[12] P. Schuh, H. Sledzik, R. Reber, A. Fleckenstein, R. Leberer, M. Op-
permann, R. Q. F. van Raay, M. Seelmann-Eggebert, R. Kiefer, and M.
Mikulla, GaN MMIC based T/R-module front-end for X-band appli-
cations, in Proc. 38th Eur. Microwave Conf., Oct. 2008, pp. 274277.
[13] A. Bettidi, D. Carosi, A. Cetronio, F. Corsaro, C. Costrini, C. Lanzieri,
and L. Marescialli, X-band transmit/receive module MMIC chipset on
emerging GaN and SiGe technologies, in Proc. IEEE Phased Array
Syst. Tech. Symp. Dig., Oct. 2010, pp. 250255.
[14] D. H. Shin and G. M. Rebeiz, A high-linearity X-band four-element
phased-array receiver: CMOS chip and packaging, IEEE Trans. Mi-
crow. Theory Tech., vol. 59, no. 8, pp. 20642072, Aug. 2009.
[15] B. H. Ku, D. W. Kang, and S. C. Hong, CMOS integrated circuits for
X-band phased array systems, in Proc. 54th MWSCAS Symp., Aug.
2011, pp. 15.
[16] M. K. Cho, S. H. Yoon, S. H. Sim, L. Jeon, and J. G. Kim, CMOS-
based bi-directional T/R chipsets for phased array antenna, in Proc.
IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2012, pp. 13.
[17] B. W. Min and G. M. Rebeiz, Ka-band low-loss and high-isolation
switch design in 0.13 m CMOS, IEEE Trans. Microw. Theory Tech.,
vol. 56, no. 6, pp. 13641371, Jun. 2008.
569
[18] T. Dinc, S. Zihir, and Y. Gurbuz, CMOS SPDT T/R switch for
X-band, on-chip radar applications, Electron. Lett., vol. 46, no. 20,
pp. 13821384, Sep. 2010.
[19] E. Cohen, M. C. G. Jakobson, S. Ravid, and D. Ritter, A bidirectional
TX/RX four-element phased array at 60 GHz with RF-IF conversion
block in 90-nm CMOS process, IEEE Trans. Microw. Theory Tech.,
vol. 58, no. 5, pp. 14381446, May 2010.
[20] J. Kim and J. F. Buckwalter, A switchless, Q-band bidirectional trans-
ceiver in 0.12- m SiGe BiCMOS technology, IEEE J. Solid State Cir-
cuits, vol. 47, no. 2, pp. 368380, Feb. 2012.
Sanghoon Sim received the B.S., M.S., and Ph.D.
degrees in electrical engineering from the Korea
Advanced Institute of Science and Technology
(KAIST), Daejeon, Korea, in 2001, 2003, and 2009,
respectively.
From 2009 to 2010, he was a postdoctoral
researcher with the department of electrical en-
gineering, KAIST, where he was engaged in
millimeter-wave IC design for UWB radar appli-
cations. From Jun. 2010 to Oct. 2010, he was a
senior researcher with the department of electrical
engineering, Korea Electronics Technology Institute (KETI), Sungnam, Korea.
In 2010, he joined RFcore Co., Ltd Sungnam, Korea, where he is currently a
senior researcher. His research interests include millimeter-wave ICs and radar
systems.
Laurence Jeon received the B.S., M.S., and Ph.D.
degrees in electrical engineering from the Korea
Advanced Institute of Science and Technology
(KAIST), Daejeon, Korea, in 1991, 1993, and 1998,
respectively.
From 1998 to 2000, he held position of Engineer at
Material and Device Lab. in LGCIT (LG Corporate
Institute of Technology), Seoul, Korea. During that
time he worked in development of various MMIC
and hybrid technology based circuits including
millimeter wave power amplifiers, mixers, LNA
and switches operating from L band through W band. His masters research
concerned the numerical charge control model of GaAs HEMT and MESFET.
This theme continued and extended through his Ph.D. research regarding the
large signal modeling of HEMT and MESFET. He is now the president of
RFcore Co., Ltd Sungnam, Korea, since November 2000.
Jeong-Geun Kim (M08) received the B.S., M.S.,
and Ph.D. degrees in electrical engineering from the
Korea Advanced Institute of Science and Technology
(KAIST), Daejeon, Korea, in 1999, 2001, and 2005,
respectively.
From October 2005 to February 2008, he was a
Postdoctoral Research Fellow with the Department
of Electrical and Computer Engineering, University
of California at San Diego (UCSD), La Jolla. In 2008,
he joined the Department of Electronic Engineering,
Kwangwoon University, Seoul, Korea, where he is
currently an Assistant Professor. His research interests include millimeter-wave
ICs and systems for short-range radar and phased-array antenna applications.