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Proc. of Int. Conf. on Advances in Electrical & Electronics 2012

A CMOS Source Follower and Super Source


Follower
1
Mr. D. K. Shedge, 2Mr. D. A. Itole, 3Mr. M. P. Gajare and 4Dr. P. W. Wani
1, 2,3
Electronics Engineering Dept. AISSMS IOIT, Pune, India
dshedge@yahoo.com, dev_itole@yahoo.co.in
4
Electronics and Telecommunication Dept. College of Engineering, Pune, India
pwwani@gmail.com

Abstract The source follower circuit is used as voltage buffer


and level shifter. It is more flexible level shifter as the dc
value of voltage level can be changed by changing aspect ratio
of MOSFET. It is desired to have low output resistance for
such applications. Source follower can give minimum output
resistance 1/(g m +g mb ) with load resistance and channel
resistance tending to infinity. The super source follower is a
circuit formed using negative feedback through another
MOSFET. This offers even reduced output resistance but with
reduced voltage gain as that of source follower.

Keywords-Source follower, Super source follower, Voltage


buffer, Level shifter, output resistance.

Figure 1. Source follower circuit


I. INTRODUCTION From (1) substituting for vgs in (2) and rearranging,
A high voltage gain can be achieved from common source
amplifier with high load impedance [5]. If amplifier is required
to drive a low impedance load then a buffer must be placed
after amplifier. A buffer will drive the low impedance load with
negligible loss of signal strength [2]. The common drain stage
(source follower) can work as a voltage buffer as shown in (3)
Fig. 1. The input signal is applied to the gate and output is
taken from the source. For signal levels above threshold If RL , (3) simplifies to
voltage, the output voltage is equal to input voltage minus
gate source voltage. The gate source voltage consist of
threshold and over drive voltage. If both these voltages are (4)
constant, then output voltage is simply input voltage added
with offset. The small signal gain would then be unity. Thus If ro is finite, the open circuit voltage gain of source follower
the source follows the gate and circuit is known as a source is less than unity even if body effect is neglected. The variation
follower. Actually threshold voltage depends on the body in output voltage changes the drain-source voltage and the
effect and the over drive depends on drain current. Also current through ro. The large signal analysis shows that the
even if the drain current is kept constant, the over drive over drive on gate also depends on the drain source voltage
depends to some extent on the drain-source voltage. unless channel length modulation is negligible. This causes the
small signal gain to be less than unity.
A. Small Signal Analysis
If RL and ro ,
The small signal equivalent circuit of source follower is
shown in Fig. 2. The body terminal is connected to lowest supply (5)
voltage (ground) to maintain source body junction reverse
biased. Since source is connected to output, vbs changes with
output [1].
Applying KVL around input loop,
vi = vgs + vo (1)
When the output is open circuited, io= 0 and applying KCL
at output node gives

(2)
Figure 2. Small signal equivalent circuit of source follower
2012 ACEEE 63
DOI: 02.AETAEE.2012.3.30
Full Paper
Proc. of Int. Conf. on Advances in Electrical & Electronics 2012

The (5) shows that the voltage gain of the source follower is As a result the drain current of M2 increases, reducing the
less than unity and it depends on = gmb/gm, which is in the output resistance.
range of 0.1 to 0.3. Also depends on source-body voltage which The dc bias current in M2 is the different between I1 and I2,
is Vo when the body is grounded. Hence gain found out in (5) therefore I1 > I2 is required for proper operation. This condition
depends on output voltage, causing distortion for large signal can be used to find small signal parameters of MOSFETs. The
changes in the output. This can be overcome by selecting the small signal equivalent circuit is shown in Fig. 4. The body effect
type of source follower n-channel or p-channel fabricated in an of M2 is neglected because vbs2= 0. The polarities voltage
isolated well. The well can be connected to source making vsb controlled current sources for NMOS and PMOS are identical.
=0. In this case the parasitic capacitance from well to substrate The current sources I1 and I2 are replaced by their internal
increases reducing the bandwidth of source follower. resistances r1 and r2 respectively. If current I1 and I2 are ideal,
The output resistance of source follower can be calculated r1 and r2 . For practical current sources these
from Fig. 2 by driving the output with a voltage source vo and resistances are large but finite.
setting vi = 0. To find output resistance of the super source follower, set vi
vgs=-vo and io is =0 and find the current io that flows into the output node when
it is driven by a voltage vo. Applying KCL at output under these
(6) conditions,
(8)
Then
(7) Similarly applying KCL at drain of M1 with vi = 0,
(9)
It is seen that the body effect reduces the output resistance,
which is desirable as the source follower produces a voltage Substituting for v2 from (9) into (8) and rearranging gives,
output. This desired effect results from the non-zero small signal
current drawn by the gmb generator. As RL and ro , (10)
this output resistance becomes 1/(gm+gmb), same as input
resistance of common gate amplifier. The source followers are Assuming I1 and I2 to be ideal current sources, also ro2 and
used as buffers and level shifters. They are more flexible as a (gm1+gmb1)ro1>>1,
level shifter because the dc value of VGS can be change by
aspect ratio W/L. (11)
B. The Super source Follower
This is the output resistance of super source follower.
The output resistance of source follower is approximately 1/
Comparing (11) with the output resistance of source follower
(gm+gmb) [3]. As MOSFETs have much lower transconductance,
(7), shows that the negative feedback through M2 reduces the
this output resistance may be too high especially when a resistive
output resistance by a factor of about gm2ro1.
load is to be driven. The output resistance can be reduced by
The open circuit of gain follower can be found out from
increasing aspect ratio W/L of source follower and its dc bias
small signal equivalent circuit with the output open circuited.
current. This requires a proportionate increasing the area and
Applying KCL at the output node gives,
power dissipation. To minimize the area and power dissipation
required for low Ro, the source follower configuration is used as (12)
shown in Fig. 3. The super follower uses negative feedback
through M2 to reduce the output resistance [4]. The qualitative Also applying KCL at drain of M1 gives
analysis shows that, when the input voltage is constant and the
output voltage increases, the drain current of M1 also increases, (13)
resulting into increased gate-source voltage of M2.
Substituting for v2 from (12) into (13) and rearranging gives

(14)

With ideal current sources,

(15)

comparing the open circuit voltage gain of the super source


follower (15) with the open circuit voltage gain of a simple source
Figure 3. Super-source follower circuit follower (4) shows that the deviation of this gain from unity is
2012 ACEEE 64
DOI: 02.AETAEE.2012.3.30
Full Paper
Proc. of Int. Conf. on Advances in Electrical & Electronics 2012

Figure 4. Small signal equivalent circuit of super source follower


greater in super source follower than a simple source follower. If
gm2ro2 >>1, this difference is small and the conclusion is that the
super source follower has little effect on the open circuit voltage Figure 5. Source follower with current source load
gain. The product gmro for MOSFET is given by relation.

(16)

Where is mobility of charge carriers, Cox is gate oxide


capacitance, is channel length modulation coefficient and W/
L is aspect ratio
Also 1/L, hence we get
(17)

Therefore the width and length can be adjusted to get desired


product gmro without changing Id.

II. THE SIMULATED CIRCUITS


A. The Source Follower Figure 6. Super source follower with current mirror sources

The circuit of source follower is formed with load supplied by upper current source M3 is addition of dc bias
resistance replaced by simple MOS current source using M2 current required for M1 and dc bias current required for M2.
as shown in Fig. 5. This current source offers high resistance As M2 provides negative feedback for super source follower
if operated in saturation region [6]. The voltage applied at circuit, it is desired to draw less amount of current. Hence the
gate of M2 that is Vb1 makes sure that M2 operates in saturation dimensions of M2 is selected 1/1 (m/m). This selected Wand
all the time. The source follower circuit is designed with dc L of M2 will ensure small feedback current through M2 with
bias drain current of 160A and dc level shift of 0.43V with high gmro as per (16) and (17). The dc bias current of M1 is
supply voltage 2.5V. This is achieved by selecting aspect 160A, thus the dimension of M4 is selected W/L=100/0.5
ratio of M1 and M2 each 100/0.5 (m/m) and applying dc (m/m) with gate bias Vb2= 0.6V. The aspect ratio of M3 is
voltage Vb1 = 0.6V. selected to be 150/0.5 (m/m) with gate bias Vb1=1.9V to
The circuits is simulated using EDA tool Tanner V14.1 supply desired bias currents to M1 and M2.
with 0.25 m technology. The length L of both MOSFETs is The result of simulation gives a small signal voltage gain
selected 0.5 m to minimize channel length modulation effect. 0.42 and the output resistance 4.7k .
The small signal voltage gain as per simulation of the circuit TABLE I. DIMENSIONS OF MOSFET DEVICES
comes out to be 0.8383 and output resistance comes out to
be 9.32k .
The result shows large deviation of small signal voltage
gain from unity and the higher output resistance as compared
to emitter follower.
B. The Super Source Follower
TABLEII. SIMULATED RESULTS
For super source follower M1 is selected with aspect ratio
200/0.5 (m/m), being PMOS with bias current 160A. Both
current sources I1 and I2 (Fig. 3) are implemented using single
MOSFETs M3 and M4 as shown in Fig. 6. The total current

2012 ACEEE 65
DOI: 02.AETAEE.2012.3.30
Full Paper
Proc. of Int. Conf. on Advances in Electrical & Electronics 2012

CONCLUSION REFERENCES
It is observed from simulated results that significant re-
[1] A S Sedra and K C Smith Microelectronic circuits theory and
duction in the output resistance of source follower can be applications Oxford University press, 7 th edition 2010, pp.
achieved with super source follower. The voltage gain of 660-689
super source follower gets reduced by almost same propor- [2] Apisak Worapishet, Andreas Demosthenous, and Xiao Liu,
tion as that of output resistance. The super source follower A CMOS Instrumentation Amplifier With 90-dB CMRR at
is useful in driving low input resistance loads. It is also used 2-MHz Using Capacitive Neutralization: Analysis, Design
in bipolar technologies to reduce the current conducted in a Considerations, and Implementation, IEEE transactions on
weak pnp transistor load. Due to use of long channel device circuits and systemsi: regular papers, vol. 58, no. 4, april
M2 at output, the higher junction capacitances may shunt 2011.
[3] Gray, Hurst, Lewis and Meyar, Analysis and Design of
the output reducing bandwidth of the circuit. The proposed
Analog Integrated Circuits John Wiley and sons Inc., 5 th
circuit can be used as a level shifter output stage in opera- edition 2010, pp. 170-275.
tional/instrumentation amplifiers with lowered output resis- [4] E. Sackinger and W. Guggenanbuhl, A High swing, High
tance. The circuit is operated with supply voltage VDD=2.5V. Impedance MOS Cascode circuit, IEEE journal of solid state
cicuits, Vol. 25, pp. 289-298, February 1990.
[5] B. J. Hosticka, Improvement of the Gain of MOS
Amplifiers, IEEE journal of solid state cicuits, Vol. SC-14,
pp. 1111-1114, December 1979.
[6] B Razavi, Design of analog CMOS Integrated Circuits, Tata
Megraw Hill, 2002 edition, pp. 47-92,135-154.

2012 ACEEE 66
DOI: 02.AETAEE.2012.3.30

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