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MODEL NO.
BC1602A series
FOR MESSRS:
________________________________________________
ON DATE OF:
________________________________________________
APPROVED BY:
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CONTENTS
1. Numbering System
3. General Specification
5. Electrical Characteristics
6. Optical Characteristics
8. Power supply for LCD Module and LCD operating voltage adjustment
9. Backlight information
11. Reliability
1. Numbering System
B C 2004 A G P L E B xxx
0 1 2 3 4 5 6 7 8 9
0 Brand Bolymin
3. General Specification
Normal Wide
TOP 0 +50
Normal Type
TSTG -10 +60
Operating Storage
Item Comment
(Min.) (Max.) (Min.) (Max.)
Humidity Note (2) Note (2) Without condensation
Vibration -- 4.9M/S2 -- 19.6M/S2 XYZ Direction
Shock -- 29.4M/S2 -- 490M/S2 XYZ Direction
5. Electrical Characteristics
Ta=-20 5.2 V
Ta=+70 3.6 V
6. Optical Characteristics
a. STN
Contrast Ratio CR 3
b. FSTN
Contrast Ratio CR 5
6.1 Definitions
Brightness (%)
Non-selected state
LCD
X
Bs
I
Bns
90 %
Brightness
100 %
10 %
tr td
Rise Time Decay Time ( fall time tf )
1 Vss 0V Ground
8. Power Supply for LCD Module and LCD Operating Voltage a Adjustment
Standart Type
typ.: 4.0V
typ.: 4.0V
(Option) LCM operating on " DC 3V " input , with built-in negative Voltage
typ.: 4.0V
9.Backlight Information
9.1 Specification
(1) LED array / yellow-green
Reverse Voltage VR 8 V
Reverse Voltage VR 8 V
Color White/Blue
Reverse Voltage VR 6 V
(4) EL / Blue
Parameter Symbol Min Typ Max Unit Test Condition
Voltage Vrms -- 110 (AC) --
Frequency HZ -- 400 --
Brightness* cd/m2 48 60 --
X -- 0.330 --
CIE
Chromaticity
Diagram 110Vrms
Y -- 0.365 --
400Hz
Color Blue
(recommending)
SM>1 1 RL= 8.2 1
ILED=100mA
SM>1 1 1
I LED =20m A
SM>1 1 1
I LED =20m A
(recommending)
SM>1 1 RL= 8.2 1
ILED=100mA
SM>1 1 1
I LED =20m A
SM>1 1 1
I LED =20m A
45
11. Reliability
Content of Reliability Test
Environmental Test
Applicable
No. Test Item Content of Test Test Condition
Standard
High Temperature Endurance test applying the high 60
1
storage storage temperature for a long time. 200hrs
Low Temperature Endurance test applying the high -20
2
storage storage temperature for a long time. 200hrs
Endurance test applying the electric
High Temperature stress (Voltage & Current) and the 50
3
Operation thermal stress to the element for a 200hrs
long time.
Endurance test applying the electric
Low Temperature 0
4 stress under low temperature for a
Operation 200hrs
long time.
Endurance test applying the high
High Temperature/ 60,90%RH
5 temperature and high humidity
Humidity Storage 96hrs
storage for a long time.
Endurance test applying the electric
High Temperature/ stress (Voltage & Current) and 40,90%RH
6
Humidity Operation temperature / humidity stress to the 96hrs
element for a long time.
Endurance test applying the low and
high temperature cycle.
-20 25 60 -20/60
7 Temperature Cycle
10 cycles
30min 5min 30min
1 cycle
Mechanical Test
10~22Hz1.5mmp-p
Endurance test applying the vibration
8 Vibration test 22~500Hz1.5G
during transportation and using.
Total 0.5hrs
Constructional and mechanical 50G Half sign
9 Shock test endurance test applying the shock wave 11 msedc
during transportation. 3 times of each direction
Endurance test applying the
Atmospheric 115mbar
10 atmospheric pressure during
pressure test 40hrs
transportation by air.
Others
VS=800V,RS=1.5k
Endurance test applying the electric
11 Static electricity test CS=100pF
stress to the terminal.
1 time
***Supply voltage for logic system=5V. Supply voltage for LCD system =Operating voltage at 25
31.0
5.1 9.5
E5652Z O
15.0
21.0
G I
4.5 20.0
I Input DC Voltage.
G DC/AC ground.
O Output AC Voltage.
RS R/W Operation
When the busy flag is 1, the controller LSI is in the internal operation mode, and the next
instruction will not be accepted. When RS=0 and R/W=1, the busy flag is output to DB7. The
next instruction must be written after ensuring that the busy flag is 0.
The address counter (AC) assigns addresses to both DDRAM and CGRAM
DDRAM Address
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F
Write into DDRAM the character code at the addresses shown as the left column of table 1. To
show the character patterns stored in CGRAM.
Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character Patterns
(CGRAM Data)
F o r 5 * 8 d o t c h a ra c te r p a tte rn s
C h a ra c te r C o d e s C h a ra c te r P a tte rn s
C G R A M A d d re s s
( D D R A M d a ta ) ( C G R A M d a ta )
7 6 5 4 3 2 1 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0
H ig h Low H ig h Low H ig h L ow
0 0 0 * * * 0
0 0 1 * * * 0 0 0
0 1 0 * * * 0 0 0
0 1 1 * * * 0 C h a ra c te r
0 0 0 1 0 0 * * * 0 0 0 p a tte rn ( 1 )
0 0 0 0 * 0 0 0
1 0 1 * * * 0 0 0
1 1 0 * * * 0 0 0
1 1 1 * * * 0 0 0 0 0 C u rs o r p a tte rn
0 0 0 * * * 0 0 0
0 0 1 * * * 0 0 0
0 1 0 * * *
0 1 1 * * * 0 0 0 0 C h a ra c te r
0 0 0 0 * 0 0 1 0 0 1 1 0 0 * * * p a tte rn ( 2 )
1 0 1 * * * 0 0 0 0
1 1 0 * * * 0 0 0 0
1 1 1 * * * 0 0 0 0 0 C u rs o r p a tte rn
0 0 0 * * *
0 0 1
0 0 0 0 * 1 1 1 1 1 1 1 0 0
1 0 1
1 1 0
1 1 1 * * *
F o r 5 * 1 0 d o t c h a ra c te r p a tte rn s
C h a ra c te r C o d e s C h a ra c te r P a tte rn s
C G R A M A d d re s s
( D D R A M d a ta ) ( C G R A M d a ta )
7 6 5 4 3 2 1 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0
H ig h Low H ig h Low H ig h Low
0 0 0 0 * * * 0 0 0 0 0
0 0 0 1 * * * 0 0 0 0 0
0 0 1 0 * * * 0 0
0 0 1 1 * * * 0 0
0 1 0 0 * * * 0 0 0
0 0 0 0 * 0 0 0 0 0 0 1 0 1 * * * 0 0 0
0 1 1 0 * * * 0 C h a ra c te r
0 1 1 1 * * * 0 0 0 0 p a tte rn
1 0 0 0 * * * 0 0 0 0
1 0 0 1 * * * 0 0 0 0
1 0 1 0 * * * 0 0 0 0 0 C u rs o r p a tte rn
1 1 1 1 * * * * * * * *
: " H ig h "
U p p er
4 b it
L ow er LLLL LLLH LLHL LLHH LHLL LHLH LHHL LHHH HLLL HLLH HLHL HLHH HHLL HHLH HHHL HHHH
4 b it
CG
RAM
LLLL ( 1 )
LLLH ( 2 )
LLHL ( 3 )
LLHH ( 4 )
LHLL ( 5 )
LHLH ( 6 )
LHHL ( 7 )
LHHH ( 8 )
HLLL ( 1 )
HLLH ( 2 )
HLHL ( 3 )
HLHH ( 4 )
HHLL ( 5 )
HHLH ( 6 )
HHHL ( 7 )
HHHH ( 8 )
Upper
4 bit
Lower LLLL LLLH LLHL LLHH LHLL LHLH LHHL LHHH HLLL HLLH HLHL HLHH HHLL HHLH HHHL HHHH
4 bit
CG
LLLL RAM
(1)
CG
LLLH RAM
(2)
CG
LLHL RAM
(3)
CG
LLHH RAM
(4)
CG
LHLL RAM
(5)
CG
LHLH RAM
(6)
CG
LHHL RAM
(7)
CG
LHHH RAM
(8)
CG
HLLL RAM
(1)
CG
HLLH RAM
(2)
CG
HLHL RAM
(3)
CG
HLHH RAM
(4)
CG
HHLL RAM
(5)
CG
HHLH RAM
(6)
CG
HHHL RAM
(7)
CG
HHHH RAM
(8)
Upper
4 bit
Lower LLLL LLLH LLHL LLHH LHLL LHLH LHHL LHHH HLLL HLLH HLHL HLHH HHLL HHLH HHHL HHHH
4 bit
CG
LLLL RAM
(1)
CG
LLLH RAM
(2)
CG
LLHL RAM
(3)
CG
LLHH RAM
(4)
CG
LHLL RAM
(5)
CG
LHLH RAM
(6)
CG
LHHL RAM
(7)
CG
LHHH RAM
(8)
CG
HLLL RAM
(1)
CG
HLLH RAM
(2)
CG
HLHL RAM
(3)
CG
HLHH RAM
(4)
CG
HHLL RAM
(5)
CG
HHLH RAM
(6)
CG
HHHL RAM
(7)
CG
HHHH RAM
(8)
Instruction Code
Execution
Instructio time
Description
n (fosc=270K
hz)
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
dont care
VIH1 VIH1
RS VIL1 VIL1
tAS tAH
PWEH tAH
tEf
VIH1 VIH1
E VIL1 VIL1 VIL1
tEr tDSW tH
VIH1 VIH1
DB0 to DB7 VIL1 Valid data VIL1
tcycE
Ta=25,Vdd=5.00.5V
Item Symbol Min Typ Max Unit
VIH1 VIH1
RS VIL1 VIL1
tAS tAH
VIH1 VIH1
R/W
PWEH tAH
tEf
VIH1 VIH1
E VIL1 VIL1 VIL1
tEr tDDR tDHR
VOH1 VOH1
DB0 to DB7 VOL1*
Valid data
*VOL1
t
cycE
Ta=25,Vdd=5.00.5V
Power on
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set ( Interface is 8 bits long. Specify
0 0 0 0 1 1 N F * * the number of display lines and font. )
0 0 0 0 0 0 1 0 0 0 The number of display lines and character font
0 0 0 0 0 0 0 0 0 1 can not be changed after this point.
0 0 0 0 0 0 0 1 I/D S Display off
Display clear
Entry mode set
Initialization ends
8-Bit Ineterface
Power on
RS R/W DB7 DB6 DB5 DB4 BF can be checked after the following instructions.
0 0 0 0 1 0 When BF is not checked , the waiting time between
0 0 0 0 1 0 instructions is longer than execution instruction time.
0 0 N F * *
Function set ( Set interface to be 4 bits long. )
0 0 0 0 0 0 Interface is 8 bits in length.
0 0 1 0 0 0
0 0 0 0 0 0 Function set ( Interface is 4 bits long. Specify
0 0 0 0 0 1 the number of display lines and character font. )
0 0 0 0 0 0 The number of display lines and character font
0 0 0 0 can not be changed after this point.
I/D S
Display off
Display clear
Entry mode set
Initialization ends
4-Bit Ineterface