RC CookBook PDF

RTL Compiler (RC) Cook Book
RTL Compiler (RC) Cook

Book
Version 11.20
Cadence Design Systems, Inc
9/17/2012
This document summarizes the usual practices and strategies that can be used in RC optimization. Also
included in this some new attributes that are introduced in RC 11.2 version
COPYRIGHT 2012, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED

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Contents
1 PURPOSE ............................................................................................................................................... 3
2 RC SYNTHESIS FLOW ............................................................................................................................. 3
2.1 Whats Needed to Synthesize a Design with RC? ......................................................................... 3
2.2 What Tool Does During Synthesis? ............................................................................................... 4
3 Area-based Optimizations..................................................................................................................... 5
3.1 General Recommendations .......................................................................................................... 5
3.2 New Attributes .............................................................................................................................. 6
4 Timing-based Optimizations ................................................................................................................. 6
4.1 General Recommendations .......................................................................................................... 6
5 Power Optimization .............................................................................................................................. 8
5.1 Reducing Dynamic Power ............................................................................................................. 8
5.2 Reducing Leakage Power .............................................................................................................. 8
5.3 Reducing both dynamic power and leakage power...................................................................... 9
5.4 Reporting power ......................................................................................................................... 10
6 Clock Gating Enhancements ............................................................................................................... 10
7 Basic DFT Flow & Useful Commands.................................................................................................. 11
8 Special Care abouts & Recommendations .......................................................................................... 12
9 LEC Flow & Care Abouts ...................................................................................................................... 15
10 Tcl Procedures ................................................................................................................................. 20
11 Some useful Utilities and Applets.......................................................................... 29

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1 PURPOSE
This document summarizes the usual practices and strategies that can be used in RC optimization. This
AppNote also includes some new attributes that are introduced in RC 11.1 and 11.2 versions.
2 RC SYNTHESIS FLOW
2.1 Whats needed to synthesize a Design with RC?
(i) Liberty Format Library (.lib) File(s)
(ii) Library Exchange Format (.lef) Technology File(s)
(iii) Verilog and/or VHDL and/or System Verilog File(s)

RC accepts verilog/vhdl and even mixed style of RTL. The RTL files can contain structural
code for combining lower level modules, behavioral design specifications, or RTL
implementations.
(iv) Synopsys Design Constraints (.sdc) File(s)

RC supports reading SDC format for constraints. Make sure that all clock definitions,
proper i/o delays ,correct uncertainty and derates included in the sdc file.
(v) Dont Use Cell List
(vi) Dont touch cells/instances/modules: There might be certain cells/instances/modules in the

design which have to be kept as dont touch during synthesis. So, the dont touch list is needed.
In order to preserve these cells/instances, use the following command in RC:
set_attr preserve true [find / -instance <instance name>]
If it is desired to preserve a particular cell with upsizing and downsizing, use:
set_attr preserve size_ok [find / -instance <instance name>]
To allow the tool to resize or delete a mapped subdesign or child instance during optimization,
but not rename or remap it, use :
set_attr preserve size_delete_ok [find / -instance <instance name>]
(vii) Optional but Recommended Files:

Capacitance Table File (.captbl)
Design Exchange Format (.def) Floorplan File
Switching Activity File(s): .saif, .tcf, .vcd
Common Power Format (.cpf) File
Note : For PLE synthesis, DEF, LEF and Captable files are needed.

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2.2 What Tool Does During Synthesis?
RC Synthesis involves the following stages:

(i) Elaboration
(ii) Generic Synthesis
(iii) Global Mapping
(iv) Incremental Optimization.
(i) Elaboration.
Before Elaboration the design should be read in along with other inputs. Make sure that general
compiler settings are done.
Elaboration is required on the top level design which automatically elaborates all its references.
The elaborate command does following things:
-Builds Data structures and infers registers in the design.
-Performs High level HDL optimization, such as dead code removal.
-Identifies Clock Gating and operand isolation candidates.
During elaboration, the tool reports the following :

-Unresolved references, that is the instances found with no corresponding module or library cell.
-Semantic problems, including unused ports, inconsistent resets..etc
check_design command can be used to report all these things in detail.
(ii) Generic Synthesis:

A technology independent synthesis is done during this stage. Following are some of the optimizations
done in this stage:
-Carry save arithmetic optimization
-Logic Pruning
-Resource Sharing
-Implementation Selection
-Redundancy Removal
-Mux Optimizations
-Common Sub-expression sharing
(iii) Global Map:

The global mapping process in RC involves:
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- Structuring
- Mapping
- Target setting
- Restructuring/Mapping as per target settings
(iv) Incremental Optimization:

Incremental mapping performs :
- Critical range re-synthesis
- Pin swapping, sizing offloading critical signals.
- DRC fixing
- Buffering
- Area recovery
3 Area-based Optimizations
3.1 General Recommendations
(i) Analyze the timing reports prior to synthesis, i.e., at pre-synthesis diagnosis stage. If the I2C,
I2O paths are already meeting timing, then area can be recovered from these paths. For
this, under constrain these path groups before the global mapping stage:
Ex: The following command will relax the timing on I2O paths by 200 ps. So, now the
effective clock-period for these paths are [Clock_period + 200].
path_adjust name UNDER_CON delay 200 from [all::all_inps] to [all::all_outs]
After global mapping phase, remove the path-adjust, so that timing reports would be
accurate and with respect to the actual clock period.
(ii) Synthesize -to_generic effort medium
As per LEC requirement,it is preferred to use medium effort for synthesize to_generic. In
cases where timing is critical ,the effort level can be set to high if and only if LEC is not an
issue.Here ,RC uses more aggressive csa optimization algorithms for better timing. This
might result in larger area as well.
(iii) Set the attribute drc_first to false, in case if you have set it to true (default is false). This has
to be set to false, so that RC does not fix DRCs aggressively & bump up the area.
(iv) Review and remove any preserve attributes (dont_touch) that are not needed. This will
help RC to optimize the results better.
(v) Check if there are any datapath elements in the critical paths with preserve attributes.
(vi) Set the attribute dp_postmap_downsize to true on data path elements present in the
design before incremental synthesis. This will perform architecture downsizing after
mapping. This attribute is effective only in incremental optimization.

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(vii) If timing is not critical in the design, you do not need to turn on the attribute tns_opto.
(viii) Area multiplier: The area of a cell can be modified by using the attribute area_multiplier.
The default value for this attribute is 1.0. When set to a value less than default value can
favor a cell to be picked up by the tool. For example, when applied on complex cells, it can
bias the tool for mapping them on non-critical paths. To do so, one could set the
area_multiplier value to less than one 1.0 for these kind of cells. However, for accurate area
reporting, you should change the multiplier to 1.0 before issue any cell or area reporting
command.
(ix) Check if proper complex libcells are selected when needed. Otherwise one can bias the tool
to pick them up using area multiplier trick discussed above.
(x) If you have a max_delay constraint set on your design, RTL Compiler interprets the
constraint more restrictively and may produce larger area and instance count. To improve
area, check for these and convert them in to set_input_delay set_output_delay constraints
that refererence to the appropriate clock.
3.2 New Attributes

(i) Operator budgeting : This technique is available only when ultra global map is enabled. It
analyses positive slack paths and premaps the CSA to HALF/FULL Adders to gain max area.
Ultra global map does structuring twice for better target generations. Set the attribute
ultra_global_mapping to true to use this feature.
Setting the variable enable_ultra_gmap_redrem to 1 will enable powerful redundancy
removal in between the two condenses.
4 Timing-based Optimizations
4.1 General Recommendations
Following are the important steps in addition to those mentioned in the flow, which will improve the
performance:
(i) Do a detail analysis of timing reports in RC just prior to synthesis, i.e., just after loading the
RTL into RC (Pre-synthesis Diagnosis). If there is some MACRO, which is in the critical path of
reg-to-reg path groups and which has huge delay, then make a separate path group for all
the paths passing through that MACRO. This will greatly improve the optimizations of all the
other reg-to-reg paths not passing through that MACRO.This MACRO path can also be
optimized in a better way by over constraining it.

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(ii) At the beginning of global mapping, based on the libraries, logic structure and constraints RC
will estimate a target slack for all cost groups. RC tries to meet these numbers. In the logfile
look for the word target slack. If there is a cost group with large negative slack normally is
a problem area. If the constraints are clean, one could set the initial target to 0 or some
positive value using the initial_target attribute. This forces the mapper to do aggressive
structuring and optimization on them to meet the target set.
set_attribute initial_target 0 [find / -cost_group name_cg]
Note : This may increase area.
(iii) Over constrain the paths, which are not meeting timing.
Ex: The following command will over constrain the reg-to-reg paths by 200 ps. So, the
effective clock-period for these paths is now [Clock_period 200 ps]. Hence, the tool will try
to meet its target in this effective clock-period.
path_adjust name OVER_CON delay -200 from [all::all_seqs] to [all::all_seqs]
This command is to be used before global mapping stage. After global mapping, remove the
over constraint and do report timing, so that the timing reports are with respect to the
actual clock-period.
(iv) If timing degradation is due to high fanout nets in the design, idealizing those nets improves
timing at the synthesis stage. In the later stages a place and route tool can build a better
buffer tree for these nets. The script mentioned in the Tcl procedures section can be used to
find out the high fanout nets and idealizing them.
(v) Usage of Low Vth cells significantly improves timing. But usage of these cells significantly
increases the power numbers as these have high leakage power.
(vi) Set the attribute tns_opto to true. When set, it forces the tool to consider all the
endpoints for the optimization.
Note: This may increase the area.
(vii) Make sure that the attribute drc_first is not set to true. By default it is set to false. If
set to true the tool will give higher priority to design rule constraints than the timing
constraints.
(viii) Set the attribute iopt_ultra_optimization to true .When set, it enables ultra optimization
in incremental optimization to achieve best QOR with higher runtime.

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5 Power Optimization
5.1 Reducing Dynamic Power
RC can read either the Toggle Count Format (TCF) or the Switching Activity Interchange Format
(SAIF) for the switching power information.
Please set rtl_name_scope_framework to true before reading the rtl for relating rtl name to
internal object association information present in TCF or SAIF.
For dynamic power optimization, after reading in the libraries, loading the design and elaborating
set the following:
set_attr max_dynamic_power /designs/*
specifies the desired value for the dynamic power target in nW
read_tcf <TCF file>

OR
read_saif <SAIF file>
If no TCF/SAIF file is provided, RC engine will use default values for the toggle rate. From 11.1
version onwards, its ON with a value of 0.20 (20%) .
Enabling Clock Gating Insertion: To enable clock gating insertion during synthesis, set the attribute
lp_insert_clock_gating to true.
5.2 Reducing Leakage Power
To perform leakage power optimization, RC would require multi Vth libraries. After reading in the
multi Vth libraries, loading the design and elaborating, do the following:
set_attr max_leakage_power /designs/*
specifies the desired value for the leakage power target in nW.
Specify the multi-Vt optimization effort using the following command:
set_attr lp_multi_vt_optimization_effort <low|medium|high>

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When set to high, RTL Compiler focuses on leakage power optimization and uses mainly high
Vth cells (low leakage power, slow timing performance). The usage of low Vth cells (faster cells, higher
leakage power) is restricted.
Note : There will be an impact on the runtime when these attributes are set.
5.3 Reducing both dynamic power and leakage power
set_attribute lp_power_optimization_weight weight /designs/*
Controls the weight factors to be used when optimizing leakage power and dynamic power
simultaneously during global mapping, mapping, and incremental optimization. Specify a value
between zero and one. Assuming the attribute is set to w, the RC-LP engine optimizes for total
power. Total power is computed as follows:
Total power = w x leakage_power + (1-w) x dynamic_power
The weight factor will be taken into account only when both the max_dynamic_power and
max_leakage_power attribute are set. If you do not set this attribute, tool issues warning POPT-501
and will ignore dynamic power optimization.
Multibit coverage: Make sure that the root level attribute use_multibit_cells is not set to false. By
default its set to true. Following are the advantages of multibit cells:
a. Smaller area and delay, due to shared transistors (as in select or set/reset logic) and
optimized transistor-level layout. In the use of single-bit components, the select or
set/reset logic is repeated in each single-bit component.
b. Reduced clock skew in sequential gates, because the clock paths are balanced
internally in the hard macro implementing the multibit component.
c. Lower power consumption by the clock in sequential banked components, due to
reduced capacitance driven by the clock net.
d. Better performance, due to the optimized layout within the multibit component.
RTL Compiler recognizes the following style of components for multibit merging:
a. Flops (non-scan and scan) with one or more of the following shared input pins: flop
clock, async_set, async_reset, sync_set, sync_reset, sync_enabe
b. Latches with one or more shared control pins: latch gate/ enable, async_set,
async_reset
c. Three-state cells that share the enable pins.
d. Combinatorial cells (muxes, inverters, nand, nor, xor, xnor) that share all pins, that
are not bundled in the Liberty description.
e. State retention (SRPG) cells that share the same retention control pins(s)

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Below is rtl of a 4 bit latch which can be inferred as a multibit cell by the tool:
module ff(ld,rst,cp,d,q);
input ld,rst,cp;
input [3:0] d;
output [3:0] q;
reg[3:0] q;
always @(cp) begin
if (rst==0) q = 0 ;
else if (ld==1) q = d;
end
endmodule
As the module contains common control pins ld and rst the tool maps the latch to a multibit
cell.
5.4 Reporting power
Use the following commands to report power:
report power depth 0

report gates power
6 Clock Gating Enhancements
lp_clock_gating_register_aware
Root level boolean attribute. Default is False
When this is true ,clock gating will be register bank aware
For example, if we have flops like a[0], a[1], a[2], b[0], b[1], b[2] in same hierarchy, one clock
gating cell will be added for a[0], a[1], a[2] flops and one clock gating cell for b[0], b[1], b[2]
flops. By default, when this attribute is off, one clock gating cell may be inserted for all the flops.
Note : clock gating declone command is not register bank aware.
lp_clock_gating_rc_inserted
This is an instance level boolean attribute.
If queried on an instance, it returns true if the instance is a RC inserted clock gating instance.
Otherwise it will return false.

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lp_clock_gating_gated_clock_gates
This is an instance level attribute.
When queried on a clock gating instance, this returns a list of clock gates immediately gated by
this clock gating instance
lp_clock_gating_stage
This is an instance level attribute and return an integer.
If queried on a clock gating instance, this return what is the stage of the clock gating instance.
For example, if CG1 is gating CG2 and CG2 is gating flop. then stage of CG2 is 2 and stage of CG1
is 1.
lp_clock_gating_gated_flops
This is an instance level attribute. When queried on a clock gating instance, this will return the
flops immediately gated by this clock gating cell.
Note : Using the above attributes, there is a script available in the TCL procedures section to get RC
inserted CG and Non-RC inserted CG and their corresponding flops in a design.
7 Basic DFT Flow & Useful Commands
Following are the basic steps to be followed during DFT flow :
(i) Run the design through DFT checks

(ii) Define the scan chain information
(iii) Synthesize
(iv) Insert scan chains
(v) Do an Incremental synthesis
Below are some useful dft Commands :
(i) Below is a tcl which helps in applying dft_dont_scan on user_defined_segment :
set absSyncInst [filter dft_status "Fails DFT rules" [filter user_defined_segment true [find
/designs/* -scan_segment *<baseNameOfAbsSegmentsforSyncFlops>*]]]
foreach inst $absSyncInst {
set_attr dft_dont_scan true $inst
}
(ii) If the core .libs doesnt have non-scan flops then to allow the mapper to be able to tie-off
the pins of the scan-flop (i.e. degenerate the scan flop to create a more simple D-flop
implementation) for the non-first registers in the shift-register, then you must set the
following attribute to:
set_attr use_scan_seqs_for_non_dft degenerated_only /

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8 Special Care abouts & Recommendations

1. Boundary optimization
By default, RTL Compiler performs boundary optimization during synthesis for all subdesigns in
the design. It controls boundary optimization on the subdesign and hierarchical pin inversion.
To preserve the input and output pins of a subdesign, you can turn off the boundary
optimization. In this case, no hierarchical pin inversion will be done either for this subdesign.
Note: To exclude individual pins from boundary optimization, use the preserve attribute
The boundary optimization can be turned off as below :
set_attr boundary_opto false [find / -subdesign <subdesign_name>]
2. Retiming
Improves the performance of the design by either optimizing the area or the clock
period (timing) of the design. Retiming moves the registers across the combinational logic to
improve the performance without changing the input/output behavior of the circuit .Generally it
is not recommended retiming on the whole design due to multiple reasons :
a. You will lose traceability of the flops since all the retimed flops will become
retime*reg. Verification could be a major issue for both formal and simulation. The
retiming space explodes to the complete design and flops can get spread out e from one
module to one or more others
b. There will be runtime increase since the Retiming flow would require an initial mapping
during prepare phase, retiming step and a final mapping on the whole design
c. It is recommended to use Retiming only on selected subdesigns. The ideal subdesign

would those which have been designed for pipelining or if not choose that would
benefit from register spreading based on unbalanced paths paths which have positive
slack on one side and negative slack on the other side. So moving the registers in the
direction of positive slack would reduce the negative slack.
d. On a Post-mapped design, you could try incremental retiming which makes use of
the unbalanced paths. But on typical designs, if the negative slack cannot be improved
by incremental retiming, then success would be limited.
To retime a design use the below command :
retime [-prepare] [-min_area] [-min_delay] [-effort {medium|low|high}] [-clock clocks]

[design|subdesign]

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3. Ungrouping
RC by default ungroups the user created hierarchies during synthesis to improve area and timing
during synthesis.. This can be controlled by setting the attribute auto_ungroup to both/none and
must be specified before synthesis.
none Ungrouping will not be performed.
Both Ungrouping will be performed with an emphasis on both optimizing timing and area.
You can also set the ungroup_ok attribute to false to control any subdesign/hierarchy not to
ungrouped. This way, while achieving better QoR, you can also keep the hierarchy of interest intact.
Note: Ungrouping of user hierarchies happens during

RTL optimization--synthesize -to_gen -effort high
Technology mapping--synthesize -to_map -effort high
4. Physical Aware structuring*
PAS works on better structuring of MUXes in the design. The tool has choice between using binary
and one-hot muxes. Binary muxes are generally good for congestion and worse for timing. PAS tries
to make this choice based on timing and congestion tradeoff. When PAS set, one can see timing
degrades at synthesis stage but will help in meet timing during Iopt and placement stages.
Usage : set_attribute physical_aware_structuring true /
Note : PAS preserves the binary mux structures throughout the flow.Please use following variable to
remove the hard preserve constraint from these inferred binary muxes :
set physical_aware_structuring_structure_preserve 0
*This is a Beta feature.
5. Global Parallel Synthesis*
This feature helps in reducing the Iopt run times. Setting this attribute, enables the super threading
feature in Iopt stage . This is built on the existing super threading infrastructure. Below is the usage
model :
set_attr super_thread_servers {localhost localhost localhost localhost} /

set_attribute enable_parallel_iopt true /
synthesize to_map incr
*This feature is still under qualification.

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6. Information to be looked in the log file.
(i) For unresolved instances during elaboration. The command for checking unresolved
instances is check_design unresolved
(ii) check if any sdc errors exist and verify the SDC summary report in the log file.
(iii) Warnings pertaining to sequential logic deletion (GLO-32,GLO-12)
(iv) Clock gating fanout statistics.
(v) At the beginning of the global mapping step, RC will estimate a target slack for each cost
group. This estimated target is based on the libraries, the logic structure, and the
constraints. RC will work toward this target number during the optimization process. In
the logfile, search for the keyword target slack, as it will be printed before and after
the global mapping step for each cost group in the design. A cost group with large
negative target slack would normally indicate a problem area. Also check whether these
targets are met after mapping or not.
(vi) On some designs RC might spend time in incremental optimization. To debug such cases
one should have set the debug variable iopt_stats to 1 and the attribute
information_level to 9. When set, RC dumps out tables in the logfile as shown
below:
Trick Calls Accepts Attempts Time

-----------------------------------------------------------
undup 0 ( 0/ 0) 8
rem_buf 0 ( 0/ 0) 0
rem_inv 0 ( 0/ 0) 0
merge_bi 0 ( 0/ 0) 0
rem_inv_qb 0 ( 0/ 0) 0
io_phase 0 ( 0/ 0) 12
gate_comp 0 ( 0/ 0) 120
gcomp_mog 0 ( 0/ 0) 0
glob_area 50 ( 0/ 50 ) 8
area_down 0 ( 0/ 0) 0
In the table, if you see huge numbers in the 'Time' column, that could be a problem
trick. Another thing to watch out for is the number of accepts and attempts.
For example if you see tricks which gets called many times and accepts are only a few
(5% to 10% of the attempts), those tricks can be switched off as shown below:
set trick_name 0
This should be done before iopt stage in the consecutive runs, to speed up the runtime.
(vii) Before attempting to run synthesis, the user should check the input data, pay attention
to the warning messages and correct any obvious issues.

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7. Runtime related attributes :
Following attributes can be used for debugging runtime related issues :
(i) set_attr heartbeat 200 / : Prints a short runtime/memory message every 200 secs.
These timestamps interspersed in the logfile can show how long the run has been stuck
in some area
(ii) set_attr dump_stack_trace <100> / : Prints the timestamp along with the stack trace
during the specified intervals.
(iii) set_attr profile_output_filename "file.pf" : Set this attribute at the place which
consumes long runtime to identify which particular routine takes maximum time.
9 LEC Flow & Care Abouts

The RC command write_do_lec dumps a dofile which can be used for LEC.
Make sure that the command is used after applying all change_name rules in RC so that appropriate
naming rules gets captured in the dofile.
During synthesis, RC creates a fv directory and dumps the dofile and intermediate netlist. The
intermediate netlist is referred as G1 netlist and final synthesized netlist is referred as G2 netlist.
During RTL to NETLIST Verification, it is always better to do two step verification as below :
(i) RTL vs G1 dumped in fv directory (this is preferably hierarchical comparison)

(ii) G1 vs G2 (this is flat comparison)
Things should be taken care of before running LEC dofile :
1. If RTL has instantiation of ChipWare/DesignWare component, then ensure LEC uses the
simulation model from the same RC release that synthesize the design. Before generating
the write_do_lec dofile, you must set the following attribute:
rc:> set_attr wlec_set_cdn_synnth_root true /
With the above attribute, the following lines are inserted at the beginning of
the write_do_lec generated dofile:
tclmode
setenv(CDN_SYNTH_ROOT)/path_to_rc_release/rc/rccurrent/tools.lnx86
vpxmode
2. For comparing netlist to netlist, -gate_to_gate option need to be used.

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3. In case of parameterized root module design, the parameters used during elaboration in RC
should be in consistent with that used during read design in LEC. In some cases, RC and LEC
result in a different number of modules, especially when the modules perform the same
function, but have different parameters.
4. If possible, avoid using combinational loops. Try the following options in LEC if automatic loop
cutting is unbalanced/mismatched:
analyze setup cut
set flatten model CUT_REMOVE_REDUNDANT
add cut point <pathname> [-net|-pin][-golden|-revised|-both]
5. Once the mapping is done do cross verify the unreachable points dumped by LEC.
6. In case ,the design has DW components ,make sure to uncomment following command in do
file:
analyze module *DW02_multp* -partial_sum_outputs
If non-eqs are present due to DW component then following proc might help in solving the
issue:
Note : This needs to be used in RC during synthesis.
hidden_proc ::dp_utils::dp_limit_boundary_opto_on_comps {} {
foreach subdesign [find / -subdesign *] {
set impl [get_attribute implementation $subdesign]
if {![string equal $impl ""]} {
set comp [dirname [dirname $impl]]
if {[get_attribute carrysave_outputs $comp]} {
set_attr -quiet boundary_opto false $subdesign
}
}
}
}
This proc essentially switches off boundary optimization on the DW components and the netlist
generated can be LEC cleaned with the help of this boundary optimization.
7. Instance naming in VHDL generate block is not covered by LRM. Currently LEC and RC have
different naming convention. However,write_do_lec automatically includes set naming
rule command to make the instance naming consistent.

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8. Ungrouping prevents LEC from hierarchically comparing certain sub-modules, which can
cause aborts. Before generating G1 netlist, do not ungroup any high complexity sub-modules
(especially with datapath operators) using:
set_attribute auto_ungroup_ok false [find / -instance <name>]
set_attribute auto-ungroup_ok false [find / -subdesign <name>]
After generating the G1 netlist, do not change any datapath architecture nor any retiming or
pipelining.
9. In case of mixed rtl usage (verilog+vhdl), its better to follow strict LRM rules while writing RTL
Below is the snippet of top (verilog) rtl where ctm_top (vhdl module) is instantiated. LEC will not
elaborate the following rtl scenario:
ctm_top #
(
.CTM_NUMINPT (31),
.CTM_NUMCNTR (8),
.CTM_NUMTIMR (2),
.CTM_TIMEVT_PORTWIDTH(2), //same as CTM_NUMTIMR
.CTM_TIMINTPOLARITY (1),
.CTM_TIMINTWIDTH (2),
.CTM_NUMSTM (0),
.CTM_CCMAVAIL (0),
.CTM_NUMDBGSGL (0),
.CTM_DBGSGL_PORTWIDTH(2),//default
.CTM_ASYNCIDLEREQ (0) ,
.CTM_CNTR_CHAINSHADOW("00000000000000000000000000010100") <----- bitwidth
mismatch seen here
)
u0_sctm
(
// Top Clock
.gl_clk_r (sctm_clk),
// Global Reset
.gl_reset_nr (sctm_rst_n),
// IDLE Realted
.gl_fclken_tr (1'b1), // to eve_FClken?
.gl_sidlereq_tr (sctm_SIdleReq),

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.ctm_sidleack_tr (sctm_SIdleAck),
);
Here is the snippet of ctm_top.vhd :
ENTITY ctm_top IS
GENERIC (
CTM_NUMINPT : INTEGER := N_CTM_NUMINPT ;
CTM_NUMCNTR : INTEGER := N_CTM_NUMCNTR ;
CTM_NUMTIMR : INTEGER := N_CTM_NUMTIMR;
CTM_TIMEVT_PORTWIDTH : INTEGER := N_CTM_NUMTIMR ;
CTM_TIMINTPOLARITY : INTEGER := 1 ;
CTM_TIMINTWIDTH : INTEGER := 1 ;
CTM_NUMSTM : INTEGER := N_CTM_NUMSTM ;
CTM_CCMAVAIL : INTEGER := 1 ;
CTM_NUMDBGSGL : INTEGER := 2 ;
CTM_DBGSGL_PORTWIDTH : INTEGER := 2 ;
CTM_ASYNCIDLEREQ : INTEGER := 0 ;
CTM_CNTR_CHAINSHADOW : STD_LOGIC_VECTOR(N_CTM_NUMCNTR-1 DOWNTO 0) :=
"00000000000000000000000000000000" <-------default parameter
);
where N_CTM_NUMCNTR = 32.
During elaboration bit width mismatch is seen as indicated above.
The problem is parameter "CTM_CNTR_CHAINSHADOW" is passed as a string instead of 32

bit std_logic_vector (which got described in the VHDL ENTITY ctm_top).
To fix the error, instead of using double quote ("") for passing parameter to
CTM_CNTR_CHAINSHADOW as below:
.CTM_CNTR_CHAINSHADOW("00000000000000000000000000010100")
Use the following:
. CTM_CNTR_CHAINSHADOW (32'b00000000000000000000000000010100)
10. Make sure to edit dft constraints dumped by write_do_lec.
11. write_do_lec does not deposit constant constraints information into dofiles. The corresponding
pin constraints need to be added manually.
12. write_do_lec can handle sequential merges by default with the following command:
set analyze option auto

Page 18
13. In LEC, undriven signals are handled by one command:
set undriven signal < z|0|1> -golden
In LEC, Z is the default. Using any other value has verification risks.
14. These RC attributes must be used for retiming verification:
For each module to be retimed, enable the retiming attribute

set_attr retime true [find / -subdesign *]
Set the following for each retimed module for easier verification:
set_attribute boundary_opto false [find / -subdesign rt_mod]
set_attribute retime_hard_region true [find / -subdesign rt_mod]
(By default its set)
The following global setting is required for running lec on a retimed design. It enables the
retiming verification with LEC.
set_attribute retime_verification_flow true /
There should be no blackbox inside retiming modules.
set_attribute wlec_add_noblack_box_retime_subdesign true /
It controls whether to add the Conformal LEC command that excludes the specified retimed
modules from the hierarchical dofile script generation. Specify this attribute before writing out
the intermediate netlist.
To generate additional netlist for debugging retiming:

set retime_write_debug_info 1
Set the following if retiming async set/reset flops is needed
set_attr retime_async_reset true /
One must use hierarchical comparison to verify the retimed netlist. The command
write_do_lec can handle retiming by default with the following commands:
add module attribute <module_name*..> -pipeline_retime golden

add module attribute <module_name*..> -pipeline_retime revised
set retiming option auto retimed_module

Page 19
10 Tcl Procedures
1. set_hfn : This procedure looks for high fanout nets over a specified threshold and then idealizes
them. The user also has an option to add a path_adjust # through these nets to account for the
missing delay.
proc set_hfn { args } {

regexp {\d+(\.\d+)+} {$Revision: 1.7 $} pkgRev
switch -- [parse_options "[calling_proc] $pkgRev" {} $args \
"-threshold srs Fanout threshold" threshold \
"-noideal bos Do not idealize the nets, just report them" noideal \
"-preserve bos Preserve the net (all nets in all levels of hierarchy are preserved)"
preserve_net \
"-cost_group sos Put paths through the high fanout nets in the specified cost group"
costgroup_name \
"-path_adjust_ps sos Path adjust through the nets (in ps, negative number removes
slack)" path_adj_ps] {
-2 { return }
0 { return -code error }
}
puts "INFO: Finding all nets with a fanout greater than $threshold"
if {$noideal} {
puts "INFO: The nets will be not be idealized, just reported"
if {$preserve_net} {
puts "ERROR: Cannot use -noideal and -preserve switch together."
puts " It does not make sense to preserve the net without idealizing it."
return -code error
}
}
if {$preserve_net} {puts "INFO: The nets will be preserved."}
set _count 0
# if desired, create a cost_group
if {![string match $costgroup_name ""]} {
puts "INFO: Defining a cost_group named $costgroup_name"
define_cost_group -name $costgroup_name
}
# look for high fanout nets in the design
foreach net [find / -net *] {
set _driver [get_attr driver $net]
if {![string match [llength $_driver] "1"]} {
#puts "NOTE: found [llength $_driver] drivers on net: [vname $net]"

Page 20
continue
}
# get the type of net.
set _type [basename [dirname [dirname [dirname $_driver]]]]
# if driver is a constant, then continue
if {[string match [what_is $_driver] "constant"]} {continue}
# if driver is a subport, then continue
if {[string match [what_is $_driver] "subport"]} {continue}
set is_port [string match [what_is $_driver] "port"]
set is_seq_pin [expr {[string match [what_is $_driver] "pin"] && [string match $_type
"instances_seq"]}]
set is_comb_pin [expr {[string match [what_is $_driver] "pin"] && [string match $_type
"instances_comb"]}]
set is_not_clock [expr {[string match [get_attr propagated_clocks $_driver] ""]}]
if {[string match [what_is $_driver] "pin"]} {
set is_libpin [expr {![string match [get_attr libpin $_driver] ""]}]
} else {set is_libpin 0}
######puts "$_driver : $_type : $is_port : $is_seq_pin : $is_comb_pin : $is_libpin :
$is_not_clock"
# if driver is a port, or sequential or combinational pin, or a libpin then check the fanout.
# but not if it is a clock
if {[expr {($is_port || $is_seq_pin || $is_comb_pin || $is_libpin) && $is_not_clock}]} {
set _fanout [llength [fanout -max_pin_depth 1 $_driver]]
#puts "$_fanout ... $threshold"
if {[expr {$_fanout > $threshold}]} {
incr _count
# create path_group?
if {![string match $costgroup_name ""]} {
puts " Creating a path group through [vname $_driver], and putting it in
cost_group $costgroup_name"
path_group -through $_driver -group $costgroup_name
}
if {$noideal} {
puts " [vname $net] : $_fanout"
} else {
puts " Setting [vname $net] as ideal (fanout $_fanout)"
dc::set_ideal_network -no_propagate $net
# set a path_adjust?
if {![string match $path_adj_ps ""]} {
puts " Applying path_adjust through driver: [vname $_driver]"
path_adjust -through $_driver -delay $path_adj_ps

Page 21
}
# preserve?
if {$preserve_net} {
set_attr -quiet preserve true $net
# preserve all hierarchical nets in the fanout
foreach fo [fanout -max_pin_depth 1 $_driver] {
set sub_net [get_attr "net" $fo]
dc::set_ideal_network -no_propagate $sub_net
set_attr -quiet preserve true $sub_net
}
}
}
}
} else {
#puts "DEBUG: Driver not accepted: $_driver : $_type : [get_attr libpin $_driver]"
}
}
# display a count of how many HFNs were found
puts "INFO: Found $_count nets with a fanout more than $threshold"
add_command_help set_hfn "Finds high fanout and declares them as ideal" "Constraint"
regexp {\d+(\.\d+)+} {$Revision: 1.7 $} pkgRev

package provide set_hfn $pkgRev
2. report_cg_tree : this procedure gives a detail report for RC inserted CG and Non RC inserted CG.
proc report_cg_tree {} {
set debug 0
if {[llength [find / -design *]] < 1} {
puts "Error: There is no design loaded. Load the design and map it before running this util"
return
}
if {[llength [find . -design *]] > 1} {
puts "Error: There are multiple designs loaded."
puts " : [find / -design *]"
puts " : 'cd' to target design"
return
}
if {[llength [find . -design *]] == 1} {

Page 22
set sav_des [find . -design *]

} else {
set des_chk [pwd]
if {[string match [what_is $des_chk] design]} {
set sav_des [pwd]
} else {
puts "Error: This util can only work from design vdir. 'cd' to top design"
return
}
}
set sav_rc_cg_list [filter lp_clock_gating_rc_inserted true [find / -inst *]]
puts "=============================================================="
puts " Report Format "
puts " ---------------"
puts " CG-Inst top/m1/m2/RC_CG_HIER_INST1 -->"
puts ""
puts " Gated flops -- top/m1/m2/reg1"
puts " -- top/m1/m2/reg2"
puts " -- top/m1/reg3"
puts ""
puts "=============================================================="
puts " RC INSERTED CG "
puts "=============================================================="
foreach sav_rc_cg $sav_rc_cg_list {
puts "[vname $sav_rc_cg] -->"
foreach sav_gff [get_attr lp_clock_gating_gated_flops $sav_rc_cg] {
puts " -- [vname $sav_gff]"
}
puts " ----------------------------------------------------------"
}
puts ""
puts "=============================================================="
puts " NON-RC INSERTED CG "
puts "=============================================================="
cg_utl::get_non_rc_gated_cgs $sav_des sav_other_cg_list
if {$debug} {
puts "sav_other_cg_list = $sav_other_cg_list"
}
foreach sav_other_cg $sav_other_cg_list {
set sav_other_gff_list [cg_utl::getGatedFlopsOfCG $sav_other_cg]
puts "[vname $sav_other_cg] -->"

Page 23
foreach sav_other_gff $sav_other_gff_list {

puts " -- [vname $sav_other_gff]"
}
puts " ----------------------------------------------------------"
}
}
3. analyze_critical_path : This procedure helps in analysis of Logic Depth for a design. It should be noted
that this is only for analysis. The tool doesnt perform any optimization based on this script.
proc analyze_critical_paths {report_cmd} {
set allInstances [getLibOnPath $report_cmd]
set totalCount [llength $allInstances]
set UniqueInstances [lsort -unique $allInstances]
puts "\nINFO:\tCritical path reported by the command \"$report_cmd\" \n\tconstains the
following library cells\n"
set rtobp [string repeat " " 70]
set rtobp [string replace $rtobp 1 8 "Library"]
set rtobp [string replace $rtobp 40 47 "Libcell"]
set rtobp [string replace $rtobp 60 65 "Count"]
puts $rtobp
puts "[string repeat "-" 70]"
set totalCnt 0
foreach UniqueLIBCELL_ut $UniqueInstances {
set LibraryName_ut [basename [dirname [dirname $UniqueLIBCELL_ut]]]
set LibcellName_ut [basename $UniqueLIBCELL_ut]
set rtobp [string replace $rtobp 1 [expr 1 + [string length $LibraryName_ut]]
$LibraryName_ut]
set rtobp [string replace $rtobp 40 [expr 40 + [string length $LibcellName_ut]]
$LibcellName_ut]
set rtobp [string replace $rtobp 62 67 [llength [lsearch -all -inline $allInstances
$UniqueLIBCELL_ut]]]
set totalCnt [expr $totalCnt + [llength [lsearch -all -inline $allInstances $UniqueLIBCELL_ut]]]
puts $rtobp
}
puts " Total [string repeat " " 54] $totalCnt\n\n"
foreach UniqueInst $UniqueInstances {

set TECH_LIB [basename [dirname [dirname $UniqueInst]]]
lappend TECH_LIB_GRP $TECH_LIB
}

Page 24
set UNIQ_TECHLIB [lsort -unique $TECH_LIB_GRP]
foreach elem_UNIQ_TECLIB $UNIQ_TECHLIB {

set LIB_LIST ""
set SPL_allInst [split $allInstances " "]
foreach elem_1 $SPL_allInst {
if {$elem_1 != "" } {
set SPL_Inst [lindex [split $elem_1 /] 2]
if {[string compare $SPL_Inst $elem_UNIQ_TECLIB] == 0} {
lappend LIB_LIST $elem_1
}
}
}
lappend WHOLE_LIST $LIB_LIST
}
foreach wh_list $WHOLE_LIST {
set rtobp [string replace $rtobp 1 8 "Library"]
set rtobp [string replace $rtobp 40 47 "Libcell"]
set rtobp [string replace $rtobp 60 65 "Count"]
puts $rtobp
set all_cell_spl_r_temp ""
set Uniq_wh_list [lsort -unique $wh_list]
foreach uniq_elem $wh_list {
set Tech_libname [basename [dirname [dirname $uniq_elem]]]
set cell_spl_r [lindex [split $uniq_elem / ] 4]
set cell_spl_r_temp [lindex [split $cell_spl_r _] 0 ]
lappend all_cell_spl_r_temp $cell_spl_r_temp
}
set all_cell_spl_r_temp [lsort $all_cell_spl_r_temp]
set count 0
set prev [lindex $all_cell_spl_r_temp 0]
foreach libcell $all_cell_spl_r_temp {
if {$libcell == $prev} {
set count [expr $count + 1]
} else {
set rtobp [string replace $rtobp 1 [expr 1 + [string length $Tech_libname]] $Tech_libname]
set rtobp [string replace $rtobp 40 [expr 40 + [string length $prev]] $prev]
set rtobp [string replace $rtobp 62 67 $count]

Page 25
puts "$rtobp"
set count 1
}
set prev $libcell
}
set rtobp [string replace $rtobp 1 [expr 1 + [string length $Tech_libname]] $Tech_libname]
set rtobp [string replace $rtobp 40 [expr 40 + [string length $prev]] $prev]
set rtobp [string replace $rtobp 62 67 $count]
puts "$rtobp\n"
}
puts " Total Count [string repeat " " 48] $totalCount\n\n"
set isThereB2BInvBuf [check_b2b_inv_buf $allInstances]

if {[lindex $isThereB2BInvBuf 0]} { puts "INFO: Back to back inverters FOUND\n" } else { puts
"INFO: No back to back inverters \n" }
if {[lindex $isThereB2BInvBuf 2]} { puts "INFO: INVERTER-PAIR COUNT is [lindex
$isThereB2BInvBuf 2]\n" } else { puts "INFO: No INVERTER-PAIR found\n"}
if {[lindex $isThereB2BInvBuf 1]} { puts "INFO: Back to back buffers FOUND\n" } else { puts
"INFO: No back to back buffers \n"}
}
proc check_b2b_inv_buf { instList } {
set foundBuf 0
set foundInv 0
set isB2BInv 0
set isB2BBuf 0
set inv_pair 0
#puts "Inst list is $instList"
foreach Inst $instList {
if {[get_attr inverter $Inst] && ($foundInv == 1) } then {
set isB2BInv 1
set inv_pair [expr $inv_pair + 1]
set foundInv 0
} elseif { [get_attr inverter $Inst] } {
set foundInv 1
} else {
set foundInv 0
}

Page 26
if {[get_attr buffer $Inst] && ($foundBuf == 1) } then {

set isB2BBuf 1
} elseif { [get_attr buffer $Inst] } {
set foundBuf 1
} else {
set foundBuf 0
}
}
#puts "total inv pair $inv_pair"
return [list $isB2BInv $isB2BBuf $inv_pair]
}
proc get_timing_path {fil path_num total_num arr req summary} {

set ::arr($path_num) $arr
return
}
proc getLibOnPath {report_cmd} {

global ::pathLibCells
array unset ::pathLibCells
set libcells ""
set pins ""
eval "$report_cmd -format_proc get_timing_path"
foreach p [array names ::arr] {
set libs ""
set path [join $::arr($p)]
set pin_indexs [lsearch -all $path type]
foreach index $pin_indexs {
set PThis [lindex $path [expr $index+1]]
if {$PThis != "ext delay" && $PThis != "in port" && $PThis != "out port" } {
lappend libs [lindex $path [expr $index+1]]
}
}
lappend libcells [join [lrange $libs 1 [expr [llength $libs]-2]]]
set ::pathLibCells($p) [join [lrange $libs 1 [expr [llength $libs]-2]]]
}
array unset ::arr
return [join $libcells]
}
proc analyzeCellDepth {report_cmd} {

Page 27
global ::pathLibCells
# Generate the arrays

set allInstances [getLibOnPath $report_cmd]
set cnt 0
set total 0
set max 0
set min 100000
# Process the data
foreach p [array names ::pathLibCells] {
incr cnt
set length [llength $::pathLibCells($p)]
if {$length > $max} {
set max $length
set max_chain $p
}
if {$length < $min} {
set min $length
set min_chain $p
}
set total [expr $total + $length]
}
puts "Max length = $max on report number $max_chain"
puts "Min length = $min on path number $min_chain"
puts "Average length = [expr $total / $cnt] over $cnt total paths"
}

Page 28
11 Some useful Utilities and Applets
1. timestat
Usage : timestat <stage_name>
Cmd : timestat GENERIC
Where GENERIC is the one of the stages during synthesis.

It will display Runtime and Memory usage at a stage in the format below:
============================================
The RUNTIME after GENERIC is 5022 secs
and the MEMORY_USAGE after GENERIC is 1903.15 MB
============================================
2. generate_reports
Usage : generate_reports -outdir <reports_dir> -tag <tag_name>
Cmd : generate_reports -outdir $_REPORTS_PATH -tag generic
generates the QoS statistics at any stage in the flow. Statistics include Timing, Area, Instance
count, Utilization, Congestion and Power details. This command is followed by summary_table
command to generate a summary table for these QoS statistics.
dumps out reports (area,gates,qor,time) with a tag-name as below:

generic_area.rpt generic_gates.rpt generic_qor.rpt generic_time.rpt
3. summary_table
Usage : summary_table outdir <reports_dir>
Cmd : summary_table -outdir $_REPORTS_PATH
Reports the summary of the design in the following format based on the generate_reports tag-
name as below:
Working Directory = /run_dir_path

QoS Summary for chip
=================================================================
Metric generic
=================================================================
Slack (ps): -5387.7
R2R (ps): -5387.7
I2R (ps): -557.4
R2O (ps): 1221.4
I2O (ps): -313.2
CG (ps): 1714.4
TNS (ps): 11049131
R2R (ps): 11007439
I2R (ps): 3248
R2O (ps): 0
I2O (ps): 38443

Page 29
CG (ps): 0
Failing Paths: 7077
Area: 30152
Instances: 399188
Utilization (%): 4.59
Tot. Net Length (um): no_value
Avg. Net Length (um): no_value
Total Overflow H: 0
Total Overflow V: 0
Route Overflow H (%): 0.00
Route Overflow V (%): 0.00
=================================================================
CPU Runtime (m:s): 85:10
Real Runtime (m:s): 88:19
CPU Elapsed (m:s): 85:41
Real Elapsed (m:s): 88:20
Memory (MB): 1903.15
=================================================================
=================================================================
Flow Settings:
=================================================================
Total Runtime (m:s): 88:47
Total Memory (MB): 1903.15
Executable Version: 12.10
4. Loading the applet

Use the following :
Usage : applet load <applet_name>
Cmd : applet load measure
This loads the applet measure.
5. To get the applet command options/details/help

Usage : <applet_name> -help
Cmd : applet load measure
Cmd : measure -help
6. Usage : applet load measure

Usage : measure qor name <run_name> <htmlfile_name>
Cmd : measure qor -name $runName $qorHTML
Dumps out qor reports into an html format, which can be viewed using htmlview.
measure qor -name generic qoR.html
measure qor -name map qoR.html
measure qor -name incr qoR.html
The result is you will see the comparative qor reports for generic,map,incr in html format in the
file qoR.html
Page 30
7. Cmd : applet load compare_area
Usage : compare_area -instance -detail -name <run_name> -module /designs/*

<html_filename>
Cmd : compare_area -instance -detail -name test_comparearea -module /designs/*
test_compare.html
compares instances with respect to instances/sequential/combinational elements and updates

the test_compare.html.Individual runs can be named respectively using name run_map
run_incr1 run_incr2 etc.
Without instance option the above applet dumps out the area corresponding to each instance
in the html file.
8. Similarly we have applets like

compare_gates,compare_power,compare_runtime,compare_memusage.We can get the syntax
using compare_gates help
Lets say we have 3 independent runs, A B and C.We can save the gate comparison for the three
runs post mapping using compare_gates with names as map_A , map_B, map_C in a common
html file map.html for easy comparison.
Similarly post incremental synthesis incr1, as incr1_A, incr1_B, incr1_C in a common html file as
incr1.html
9. Cmd : applet load set_cost_groups

Cmd : set_cost_groups -help
set_cost_groups: Automate the setup of all cost groups per standard strategies used
Usage: set_cost_groups [-mode <string>] [-add][-mode] <string>
CostGrouptrategy(edi|clock|clock_location|clock_location_single_io|location|none)
[-add]:add to existing cost groups(default is overwrite)
Cmd : set_cost_groups -mode clock

=> cost groups based on endpoint clocks , report qor looks like :
Cost Critical Violating
Group Path Slack TNS Paths
---------------------------------------
default No paths 0 0
refclk 6.6 0 0
a_clk 7193.4 0 0
b_clk 10365.3 0 0
c_clk 15153.3 0 0
m_ram_clk 9529.8 0 0
m_digit_clk 15153.3 0 0
---------------------------------------
Total 0 0

Page 31
Cmd : set_cost_groups -mode edi
=> cost groups based on edi default strategy, report qor looks
like :
Cost Critical Violating

Group Path Slack TNS Paths
---------------------------------------
default 15694.8 0 0
in2reg 7193.4 0 0
reg2out 15153.3 0 0
reg2reg 6.6 0 0
in2out No paths 0
---------------------------------------
Total 0 0
10. Cmd : applet load create_tcase
Usage : create_tcase -mode <save/create> -archive <archive_name>

Cmd : create_tcase -mode save -archive testcase_name
Creating testcase-setup to be used for the debug purpose. It creates a tarball of the testcase.Use
the automatically generated collateral in the auto-generated directory.
gtar -zxvf <archive>.tgz
cd archive
You may need to modify the automatically generated Tcl script to suite the needs of individual
users. Some known modifications to be done to the automatically created Tcl file is as below.
# Comment out the following line: applet load generate_report

and put suspend after design is elaborated and sdc is read.
Following this, based on the user requirements/debugging purpose, this script can be modified
to run the full synthesis.
Please go through the README file generated with create_tcase for more details.

Page 32

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COPYRIGHT 2012, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED

COPYRIGHT 2012, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED

(i) Liberty Format Library (.lib) File(s)

(ii) Library Exchange Format (.lef) Technology File(s)

(iii) Verilog and/or VHDL and/or System Verilog File(s)

(iv) Synopsys Design Constraints (.sdc) File(s)

(vi) Dont touch cells/instances/modules: There might be certain cells/instances/modules in the

(vii) Optional but Recommended Files:

COPYRIGHT 2012, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED

2.2 What Tool Does During Synthesis?

RC Synthesis involves the following stages:

During elaboration, the tool reports the following :

(ii) Generic Synthesis:

(iii) Global Map:

(iv) Incremental Optimization:

(ii) Synthesize -to_generic effort medium

COPYRIGHT 2012, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED

3.2 New Attributes

COPYRIGHT 2012, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED

Note : This may increase area.

COPYRIGHT 2012, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED

set_attr max_dynamic_power /designs/*

specifies the desired value for the dynamic power target in nW

read_tcf <TCF file>

5.2 Reducing Leakage Power

set_attr max_leakage_power /designs/*

Specify the multi-Vt optimization effort using the following command:

set_attr lp_multi_vt_optimization_effort <low|medium|high>

COPYRIGHT 2012, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED

5.3 Reducing both dynamic power and leakage power

set_attribute lp_power_optimization_weight weight /designs/*

Total power = w x leakage_power + (1-w) x dynamic_power

COPYRIGHT 2012, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED

5.4 Reporting power

Use the following commands to report power:

report power depth 0

6 Clock Gating Enhancements

COPYRIGHT 2012, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED

7 Basic DFT Flow & Useful Commands

Following are the basic steps to be followed during DFT flow :

(i) Run the design through DFT checks

Below are some useful dft Commands :

(i) Below is a tcl which helps in applying dft_dont_scan on user_defined_segment :

set_attr use_scan_seqs_for_non_dft degenerated_only /

COPYRIGHT 2012, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED

8 Special Care abouts & Recommendations

set_attr boundary_opto false [find / -subdesign <subdesign_name>]

c. It is recommended to use Retiming only on selected subdesigns. The ideal subdesign

To retime a design use the below command :

retime [-prepare] [-min_area] [-min_delay] [-effort {medium|low|high}] [-clock clocks]

COPYRIGHT 2012, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED

Note: Ungrouping of user hierarchies happens during

4. Physical Aware structuring*

Usage : set_attribute physical_aware_structuring true /

*This is a Beta feature.

5. Global Parallel Synthesis*

set_attr super_thread_servers {localhost localhost localhost localhost} /

*This feature is still under qualification.

COPYRIGHT 2012, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED

6. Information to be looked in the log file.

Trick Calls Accepts Attempts Time

analyze module DW02_multp -partial_sum_outputs