Design and implementation of 4-bit BCD adder

Abstract:

Introduction

There is a growing importance of decimal arithmetic in commercial, financial and internet

based applications. These applications cannot tolerate errors that result from the conversion
of binary format to decimal format. Thus, hardware support for decimal arithmetic is
receiving considerable attention. Recently, specifications for decimal floating point
arithmetic have been added to the draft revision of IEEE-754 standard for floating point
arithmetic Despite the widespread use of binary arithmetic, decimal computation remains
essential for many applications.

One digit BCD adder(or)4-bit BCD adder

A BCD 1-digit adder is a circuit that adds two BCD digits in parallel and also produces the
Sum digit in BCD along with the necessary correction logic. The conventional
implementation of addition as mentioned. It can be seen that a 4-bit binary adder is used
initially to add two BCD digits (each digit expressed using 4 bits) with a carry-input. An
overflow detection circuit is used (to check if the Sum of the BCD digit has exceeded 9)
which is designed using two 2-input AND gates and a 3-input OR gate. Finally, another 4-bit
binary adder is used as a correction stage, which comes in the path of final Sum computation.
Thus, the critical path in this circuit consists of a 4-bit binary adder, overflow logic and one
more 4-bit binary adder. Assuming, in the best case, that the 4-bit binary adder is a carry
look-ahead adder, a gate level analysis would indicate that it consists of 4-gates in the critical
path. It can be observed that the overflow detection circuit comes into picture only after the
topmost 4-bit binary adder performs its operation and it consists of 2 gates in the critical path.
Thus, a minimum of a 10-gate delay can be expected in conventional implementation [44].
The above design can however be optimized by removing those gates that are completely
redundant in their operation. Such a modification which results in a smaller critical path. A
faster carry prediction for this implementation is proposed in [45], which uses carry look-
ahead logic to predict the carry in advance. These 1-digit full adders can be cascaded to
realize higher digit BCD adders.
Circuit diagram:

1. As shown in the Fig, the two BCD numbers, together with input carry, are first added
in the top 4-bit binary adder to produce a binary sum.
2. When the output carry is equal to zero (i.e. when sum <= 9 and C_out = 0) nothing
(zero) is added to the binary sum.
10.When it is equal to one (i.e. when sum > 9 or C_out = 1), binary 0110 is added to
the binary sum through the bottom 4-bit binary adder.
3. The output carry generated from the bottom binary adder can be ignored, since it
supplies information already available at the output carry terminal.
Truth table:

1. Y=1 indicates sum is greater than 9. We can put one more term, C_out in the above
expression to check whether carry is one.
2. If any one condition is satisfied we add 6(0110) in the sum.
3. With this design information we can draw the block diagram of BCD adder, as shown
in figure below.

Faculty In-Charge: Submitted By

Mr. Subba Reddy Vasipalli 160030867 M.srinivas
Assistant Professor 160030871 M.hussain

160030874 M.zamrud