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Code: 9D06106c

M.Tech - I Semester Regular & Supplementary Examinations, April/May 2013

LOW POWER VLSI DESIGN
(Common to DSCE and DECS)

Time: 3 hours Max Marks: 60

Answer any FIVE questions
All questions carry equal marks
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1 (a) What are the low-voltage, low-power design considerations? Explain.

(b) What are the advantages and limitations of silicon-on-insulator technology?

2 (a)
(b)

L D
What are the BICMOS manufacturing and integration considerations? Explain.
How graded drain structure can be produced? Mention the advantages.

3 (a)

(b)
power lateral BJT on SOI.

O R
Give the device structure and describe the fabrication process of low-voltage/low-

With schematic diagrams explain about deep submicron processes.

4 (a)
(b)
W
What are the features of HSPICE level 50 (Phillip MOS 69) model? Explain.
Discuss in detail about limitations of MOSFET models.

U
T
5 Draw the circuit for conventional BICMOS two-input NAND gate and describe its
characteristics.

6 (a)

(b)
J N
Give the comparative evaluation of all the BICMOS circuits employing lateral
parasitic PnP BJTs.
What are the quality measures for latches and flip-flops? Explain.

7 (a) Explain about power reduction in clock networks.

(b) Explain in detail about low power techniques for SRAM.

8 Write short note on the following:

(a) Sub-half micron MOS devices.
(b) Design perspectives of latches and flip-flops.

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