www.jntuworld.com www.android.jntuworld.com www.jwjobs.

net

Code: 9D57104

M.Tech - I Semester Regular & Supplementary Examinations, April/May 2013

HARDWARE DESCRIPTION LANGUAGES
(Common to VLSIS, VLSISD, VLSI, VLSID, VLSIES, ESVLSI and VLSIESD)
Time: 3 hours Max Marks: 60
Answer any FIVE questions
All questions carry equal marks
*****

1 (a) Design a 2-1 multiplexer by using UDP. The select signals, inputs are i0, i1 and the output
is out. If the select signal s=x, the output out is always 0. If s = 0, then out = i0, if s = 1 then
out = i1.
(b)

D
Explain conditional operator, operator precedence in VERILOG.

2 (a)

(b)
each positive edge of clock for the non-blocking assignments.

R L
Write short notes on non-blocking assignments and what are the sequences takes place at

How intra assignment delay control, event based timing control takes place in vrilog HDL?

3 (a)
(b)
O
Under what conditions will a synthesis tool create an edge-triggered sequential circuit?
Explain a synthesis-tool organization and a Y-chart representation of verilog constructs.

4 (a)
(b)

U W
Briefly explain about compiler directives.
Develop verilog model code of a 4 bit BCD counter and write algorithm, flowchart.

T
Draw the circuit diagram for AND and OR gates, using nmos and pmos switches. Write the
verilog description for the circuit.

N
J
6 (a) Write a procedure for converting integers between 0 and 255 to a byte.
(b) Briefly explain top down design and bottom up implementation in VHDL.

7 (a) Write objects and classes in a VHDL.

(b) How signal assignment can do in the VHDL?

8 (a) What is a process statement? Write about declarative part of a process, statement part of a
process.
(b) Write about implementing handshaking clock in VHDL.

*****

www.jntuworld.com