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Course Introduction
Electronics of today
Digital Camera PDAs Camcorder
and tomorrow demand
higher performance
(speed) circuits
low power circuits for
portable applications
more mixed signal
emphasis
MP3/CD Player Laptop Cell phone
wireless hardware
high performance signal
processing Handheld
Games
sensors and
& Video Players
microsystems
ECE 410, Prof. A. Mason Lecture Notes Page i.2
VLSI Design Flow
VLSI = very large scale Top
integration
Down System Specifications
Design
lots of transistors
Abstract High-level Model
VHDL, Verilog HDL
Procedure
for rapid design
ECE410 Finished VLSI Chip
LVS
digital only (layout vs. schematic)
Process
transistor-level design Physical Design
Design
with focus on circuit Simulation
Process Models
performance SPICE
L = channel length
critical dimension = feature size
nMOS pMOS
transistors /
chip channel length
power /
transistor supply voltage
rref: Kuo and Lou, Low-Voltage CMOS VLSI Circuits, Fig. 1.3, p. 3
Moore's observation, now known as Moore's Law, described a trend that has
continued and is still remarkably accurate. In 26 years the number of
transistors on a chip has increased more than 3,200 times, from 2,300 on
the 4004 in 1971 to 7.5 million on the Pentium II processor in 1998.
10m 1m 0.35m
Feature Size
(ref: http://www.intel.com/intel/museum/25anniv/hof/moore.htm)
Modern CMOS
10 um
Beginning of
Submicron CMOS
Deep UV Litho
1 um
90 nm in 2004
37 Years
of Scaling History 65 nm in 2006
Features:
Die Size: 13.3mm2
5.9M bits SRAM
1.9M gates of logic
eFuse (dieID) and repair
ARM7 uC
LEAD3 DSP (250K gates)
MegaCell (300K gates)
ASIC gates (1.3M gates)
In Volume Production
Pwr_Idle = Leakage
- Leakage: Increases with technology advance & with temperature
MHz Phone Performance Requirement Power vs. Technology
700 10000
MCU Without PM
600
With PM
1000
Leakage Power
500
400
100
300
200
10
100 Product
available
0 1
180nm 130nm 90nm 65nm 45nm
1993 1995 1997 1999 2001 2003 2005 2007
1.2 V
0.9 V
0.6 V 0.6 V