Professional Documents
Culture Documents
Magliacane, KD2BD
1320 Willow Drive, Sea Girt, NJ 08750; kd2bd@amsat.org
A Frequency Standard
for Todays WWVB
The author shares the design of his frequency standard
thats fully compatible with todays WWVB.
Figure 3 Space and Naval Warfare Systems (SPAWAR) Command computer simulations illustrate how the WWVB 100 mV/m signal level
contours contract during the day and expand during nighttime hours. (Images from NIST website.)
QX1511-Magliacane05
R8
200 k
Loop Antenna
40 turns #28 wire
5 meter circumference U2
C4 AD744
R6
10 k 330 pF 1
2
5
C1 6
680 pF R7
270 3
C7
C2 7
1 F J1
580 pF 4
To
D2 D1 Receiver
6.2 V 6.2 V
L2
R2 R1 10 mH
2.0 M 2.0 M R10
390 k
R4 C3
5.1 k 1 F
C6 R9 D3
1 F 390 k 15 V
3 5 2
6
1
R5
5.1 k U1 R3
AD620 4.7 k
7 8
4
QX1511-Magliacane07
Figure 7 60kHz WWVB loop antenna preamplifier. In addition to providing 40dB of gain, the preamp properly interfaces the balanced loop
antenna with the ground-referenced circuitry in the frequency standard.
+45
Phase
Shift
Mixer
MCU
0
Variable Controlled 10 kHz
Phase
Attenuator Phase IF Output
Shift
Select
60 kHz 60 kHz 10 kHz
Differential Amplifier Amplifier
Amplifier 45 50 kHz
AGC
Control Phase Local
Voltage Shift Oscillator
Figure 8 This block diagram illustrates the overall RF to IF conversion process. The +45 and 45 phase shift networks were used in the past
to compensate for the WWVB hourly phase signature, but have not been required since the introduction of BPSK modulation was made in 2012.
R17
10 k
R18 +12 V
100 k
Q5
A In
2N3904 R9
10 k +12 V
R12
100 k
R11
Q4
B In 56 k
2N3904
+12 V +12 V
10
Q1 Q2
R15 R16 2
2N3904 2N3904 R6
10 k 10 k 1.1 k 15 60 kHz
1 RF Out
C8 C9
R7
0.001 F 0.001 F U10B
R3 R4 2.7 k
1 k 1 k
U2A +12 V
Noise 11
Gate In 9 D7 D8
16
1N5231 1N914
8
10 kHz 12
IF In 14 10
5.1 V R14
C6 D5 D6 R13 8 0.5 W 1 k
470 pF 1N914 1N914 51 k C7 U3C
6 7 0.33 F LMC6484N
QX1511-Magliacane09
CD4053BE
Figure 9 Details of the RF AGC circuitry and legacy carrier phase shift networks of the frequency standard.
QX1511-Magliacane10 60 kHz
RF Out
C12 C15 R27 +6 V +12 V
330 pF R23 330 pF 200 k
+6 V
200 k
16
C11 R31 U4C
9 R21 +12 V
C10 330 pF C14 51 k LM837N 13
10 k R25
8 6 10 14
330 pF 10 k 330 pF
10 7 2 R29 8 12 8
60 kHz 4
100 k
RF In R22 5 1 9
R19 7
300 R26
100 k U1C 3
U1B 300 6
LM837N 11
R24 LM837N U1A
200 k R28 LM837N
+6 V C13 R30 11
+6 V 200 k
0.01 F C16 100 k
+6 V
0.01 F
C17 R20 U5A
0.01 F 100 k CD4053BE
50 kHz
LO In
R49 +6 V
+12 V
C20 100 k U27A
0.1 F CD4070B
2 14
10 kHz
LO In 3
1
BPSK
7
In
R32 10 kHz
10 k IF Out
19
A 90 phase shift in the lower IF path drives I and Q demodulators that provide outputs at baseband (DC) levels.
power from the frequency standard through Inductor L1 and capacitor C1 form a bias path would again be selected through U10B.
the same length of coax. This connection tee network that feeds DC operating voltage If the frequency standard were powered on
provides a voltage transfer rather than a to the preamplifier while simultaneously between 10 and 15minutes past the hour,
power transfer of RF energy between the pre- directing RF from the preamplifier into a cur- the WWVB carrier would have already been
amplifier and the frequency standard. Since rent controlled RF attenuation network. This advanced +45. Therefore, the frequency
the length of coax will be small in terms network is part of the frequency standard standard would continue using the 0 path,
of wavelength, transmission line effects AGC circuitry, and it consists of resistors R1 and later select the +45 path when WWVB
and impedance matching concerns can be and R2, and diodes D1 through D4. would have shifted back 45 at 15minutes
ignored, and coaxial cable of any convenient Capacitor C6 along with diodes D5 and after the hour.
surge impedance can be employed. D6 and resistor R13 charge capacitor C7
The amount of capacitance required in to the peak level of the IF voltage. Analog
switch U2A is opened when strong atmo- Converting to a 10 kHz IF
parallel with the loop to achieve resonance
at 60kHz depends on the size, shape, dis- spheric discharges are detected. This action Phase and amplitude conditioned 60kHz
tributed capacitance, and overall inductance prevents C7 from charging to the peak level signals are next handled by the circuitry illus-
of the loop. The 40turn loop described here of the noise impulse, which would otherwise trated in Figure 10. Here, additional RF gain
required about 1050pF of capacitance. engage the AGC more heavily, and desensi- and selectivity are provided by active band-
Capacitor C1 should be a silver mica or simi- tize the frequency standard in the moments pass filters designed around op-amps U1A
lar low-loss, temperature stable capacitor. I following the static crash. and U1B. As was the case in the preamplifier,
used an Elmenco 467 110pF to 580pF com- The voltage across C7 is buffered by op- the 330pF capacitors at C11, C12, C14, and
pression trimmer capacitor at C2 to carefully amp U3C, level shifted through diodes D7 C15 should be of a temperature stable, low-
bring the loop to resonance at 60kHz. and D8, and used to control the RF attenua- loss chemistry. An AGC conditioned 60kHz
Signal-to-noise ratios at LF are often tion network through transistors Q1 and Q2. RF sample from the output of U1A is buff-
enhanced by desensitizing the near-field With no current applied to the network, ered and made available for use outside the
response of the receiving antenna to E-Field the dynamic resistance of all four diodes is frequency standard.
energy. This effect is often accomplished by high, and very little RF signal attenuation U4C forms a 180 unity gain phase
employing an electrostatic shield around the takes place across resistors R1 and R2. As inverter that forms a balanced mixer along
perimeter of the loop. In this design, E-Field the IF signal level begins to rise above the with U5A, one section of a CD4053BE triple
desensitization is achieved by employing a threshold set by diodes D7, D8, and the SPDT analog switch. Driven by a 10MHz
high common-mode-rejection differential base-emitter junctions of transistors Q1 and derived 50kHz local oscillator, this mixer
amplifier as the first stage of the preamplifier. Q2, the DC current passing through diodes converts the 60kHz RF signal down to a
Capacitor C8 provides an AC ground to the D1 through D4 begins to increase. This cur- 10kHz IF. Op-amps U4A, U4B, and U4D
electrical center of the loop, to enhance the rent decreases the dynamic resistance of the form a 10kHz biquad active bandpass filter
preamplifier rejection of out-of-band signals. diodes, and causes an increasing amount of that serves as a high-gain, narrow bandwidth
Zener diodes D1 and D2 help protect the RF to be conducted through them to ground. IF amplifier. This amplifier provides 46dB
Analog Devices AD620 differential ampli- A fairly constant peak RF level remains after of gain and a 3dB bandwidth of 100Hz.
fier from damage when nearby lightning the attenuation network, and appears on the The center frequency of the amplifier is set to
strikes induce high voltage impulses across emitter of transistor Q3. 10kHz through careful alignment of poten-
the antenna. For many decades, WWVB employed tiometers R36 and R39. The 330pF capaci-
The differential amplifier is followed by a method of station identification where its tors employed at C18 and C19 must be of a
a 60kHz second-order active bandpass fil- transmitter would advance the phase of its low-loss variety.
ter designed around an AD744 operational carrier +45 10minutes after the start of each Working from within the AGC loop, the
amplifier. This stage provides additional RF hour, and return to normal phase 5minutes IF amplifier provides an output voltage of
selectivity beyond that of the loop antenna later. These hourly phase shifts were discon- about 8Vp-p. A sample of the 10kHz IF is
alone, and raises the overall voltage gain of tinued when BPSK modulation was added made available for use outside the frequency
the preamplifier to 40dB. The AD744 has in 2012. Nevertheless, the circuitry used to standard.
the capability of driving capacitive loads, and compensate for these phase shifts worked
can deliver output voltages as high as 10Vp-p extremely well, and is included here for dis- Demodulating I and Q
without distortion. cussion. The 10kHz IF signal is split between a
Resistor R3 sets the gain of the AD620, 60kHz RF appearing on the emitter of straight-through path and a path through op-
and may be increased in value if less pream- transistor Q3 is simultaneously applied to a amp U6B that produces a 90 phase shift.
plifier gain is desired. For best performance, +45 phase shift network (C3, R10), a 45 A balanced mixer consisting of op-amp
capacitors C4 and C5 should be low-loss, phase shift network (R8, C4), and a resistive U6C and analog switch U5B is driven by
high temperature stability devices (such voltage divider (R6, R7) having the same a 10MHz derived 10kHz local oscillator,
as silver mica), and all resistors should be attenuation characteristic as each phase shift and forms an in-phase (I channel) demodu-
within 5% tolerance. network. In the past, the appropriate RF path lator. The 90 phase shifted path feeds a
would be selected by the microcontroller second balanced mixer consisting of op-amp
based on the current time of day. The 0 U6C and analog switch U5C. This mixer is
RF Amplitude and Phase
path would normally be selected when the driven by the same 10kHz local oscillator
Management
frequency standard was initially powered on. after it has passed through exclusive OR gate
Figure 8 illustrates the overall process of
At 10minutes after the hour, the 45 path U27A, and produces a quadrature (Q chan-
converting the WWVB 60kHz signal down
would be selected through analog switch nel) demodulator.
to a 10kHz IF, where separate amplitude and
U10C and into U10B to compensate for the The output of the I channel demodula-
phase detection takes place. Figure 9 illus-
+45 phase advance that would occur at that tor is a +6V referenced baseband DC voltage
trates the frequency standard RF circuitry in
time. At 15minutes after the hour, the 0 that is linearly proportional to the WWVB
greater detail.
Figure 11 This block diagram illustrates the post-detection processing. The WWVB amplitude shift keying and phase shift keying are demodulated from the I channel while the Q channel
VCTCXO
AM Time
tude. After the effects of BPSK modulation
Voltage
Voltage
Control
Control
Carrier
BPSK
Audio
Audio
Noise
Code
AGC
have been removed by the action of U27A
and its associated circuitry, the Q channel
demodulator produces a +6V referenced
baseband DC voltage that is linearly propor-
tional to a WWVB carrier having no phase
Slicer
modulation.
Peak
Hold
Figure 11 presents an overview of the
signal path taken by the 10kHz IF. As illus-
trated in Figure 12, op-amps U3D and U7D
function as a 3.685Hz wide four pole Bessel
low-pass filter, and set the frequency standard
Detector
Gated
I channel RF bandwidth to 7.37Hz. Output
Noise
AGC
Peak
Gate
from the filter drives op-amps U25A and
U25B. Using a virtual ground DC reference
of +6V, op-amp U25A acts as a voltage com-
parator and demodulates the WWVB BPSK
into a 12Vp-p square wave. U25B serves as a Rectifier
Carrier
Slicer
and U26C when the WWVB carrier phase
is inverted, a BPSK-free I channel is pro- 0.025 Hz
LPF
Rectifier
BPSK
also applied to exclusive OR gate U27A to
control the phase of the 10kHz local oscil-
lator fed to the Q channel demodulator,
and allows the demodulator to maintain a
constant output polarity.
The filtered and BPSK-free I channel
5 Hz
LPF
energy is applied to op-amp U7A and diode
Enable
(PLL)
Phase
Shift
L.O.
L.O.
10 kHz
10 kHz
1 kHz
R139
100 k R141 U25B
U26C
47 k LMC6482N
5 5
C
7 3 4 Modulation
B A
6 Out
CD4066B
R140
100 k
+12 V
R58 68 k
D10 +5 V
Time Code
+12 V
+6 V
+6 V
+12 V 16 U7B R61 R63
U7A R57 9
13 LMC6484N R60 1.5 k 10 k
LMC6484N R56 4.7 k
3 14 130 k 8
4 10 M Time
1 12 8 5 10
Code
C27
2 7 7 Out
D9 4.7 F R59 R62
11 6 U7C
1N914 6 100 k 100 k
LMC6484N
Q6
2N3904
11
U10A
CD4053BE
Noise
Gate In QX1511-Magliacane12a
Voltage
Figure 12 This schematic diagram shows the details of the I and Q channel filtering and processing. Both amplitude and phase shift keying signals are demodulated from the I channel,
Controlling The VCTCXO
QX1511-Magliacane12b
Error
MHz
Out After passing through analog switch U2B, the out-
Out
10
put of the Q channel demodulator is fed through
a 0.025Hz wide second order low-pass filter (U3B)
before being applied to the 10MHz VCTCXO. Low
leakage, metalized polypropylene film capacitors were
8 employed at C28 and C29.
VCTCX0 The resistive network between the low-pass filter
14
10 MHz
CMOS
7
+5 V
while the Q channel develops the tuning voltage that forces the 10MHz oscillator to track the phase of the WWVB carrier.
setting is fairly critical, since a third-order phase-locked
loop (PLL) function is produced by the VCTCXO and
the second order low-pass filter that precedes it. Third-
order PLLs offer superior noise rejection and lower
C30
0.1 F
10 k
2.0 M
CCW
R74
CW
56 k
R73
R75
0.33 F
+6 V
1 k
R69
SW1
PLL
R64
100 k
+6 V
R128
47 k U24D
Divider Q9 9 8
Reset In R127 2N3904
1 k 74HC14
+5 V
U21C 5 6
74HC14
2
3
12
13
14
15
1
J5
U21D 9 8 STD
D1
D2
D4
D7
D6
D3
D5
U17 74HC14 Output
74HC151
A
Y
W D0
C
G
B
U21E 11 10
6
5
Output Frequency
7
9
11
10
Selector +5 V 74HC14
U21A
10 MHz, 1 2 13 12 J6
1 MHz,
10 MHz
100 kHz,
74HC14 U21F Output
50 kHz,
74HC14
25 kHz,
10 kHz, SW4 U24B 3 4
1 kHz, BCD Switch 74HC14
100 Hz 11 10 U24E J7
U24C 5 6 74HC14
U24A 10 MHz
74HC14 Output
10 MHz 1 2 13 12 U24F
In 74HC14
74HC14
25
selection of 100Hz, 1kHz, 10kHz, 25kHz, 50kHz, 100kHz, 1MHz, and 10MHz signals for use in the laboratory.
QX1511-Magliacane14 +5 V +5 V
U11 24X2 LCD
Display
14
+VDD 2
+VDD
C71 6 11
0.1 F RB0 DB4 R135
7 12 +5 V
5 RB1 DB5 24
13 13 A
RB7 DB6 +LED
R129 9 14 3 R136
RB3 DB7 VO Contrast
10 k
BPSK 4 10 4 K 10 k Control
RA5 RB4 RS LED
In 12 6 5
R130 RB6 E R/W
6.8 k 1
VSS
Time 17
Code RA0
3 Divider
In
RA4 Reset
10 Hz 18 Out
RA1
In 15
RA6 A Out
Error 1
Voltage RA2
In 16
R131 R132 C72 RA7 B Out
+6 V
4.7 k 4.7 k 0.1 F
R133 J8
4.7 k
2 U9
RA3
2 1
8 12 14
9 8 7 6
R134 C73 C74 RB2
4.7 k 10 F 0.1 F 11 11 13
RB5
5 4 3
+5 V
PIC16F88
16
19.2 kbps
C75 C76 RS-232 Out
0.1 F 0.1 F 1
+12 V
Source 2 C79
U29 6 3 0.1 F
VI VO 4
C78
GND C82 C77
0.1 F
0.47 F 15 5 0.1 F
LM7805
DS232A
+5 V
U30 Source
+6 V
VI VO
Source
C82 GND C84
0.47 F 0.47 F
LM78L06
F1
J9 Bourns U28
SW5
RX110
+13.8 V +12 V
VI VO
In Source
GND C81
Power C80 D15
47 F
On / Off 0.47 F 1N4004
LM2940T12.0 Low ESR
Figure 14 A PIC microcontroller decodes the WWVB time code, functions as a real-time UTC clock driven by the disciplined oscillator, and
provides date and time of day information via the liquid crystal display and RS-232 serial port.
R97
10 k
+12 V
Q7 +6 V +12 V
2N3904 CW CCW Noise Gate Threshold
R88 R89 Noise
"Q" 56 k 56 k Voltage
Channel R92 R95 Out
In C44 C45 200 k 200 k R96 +12 V
0.022 F 0.01 F R93 100 k +12 V
C46 R91 100 k D11 D12 R94
1 F 100 k 1N914 1N914 100 k C47
6 8 R99
0.47 F 1 M
7 2 6
R90 +12 V TR THR
5 7
10 k +6 V DIS
R98 C49
2 4 U20B 200 k 4 1 F
Reset
1 U20A LMC6484N
3 LMC6484N
+6 V Noise
11 5 3
+12 V CV Q Gate
Out
1 R100
C48
C50 C52 D14 1.5 k
R101 +5 V 0.01 F
0.01 F U19 47 F Low SNR
160 k
3 1 D13
10 kHz U22
R105 Noise
IF In 4 LM555
1.5 k
C53 2 8
0.047 F 7
R102
6 5 C51
C54 56 k
15 F Q8
0.001 F
2N3904
R104 LMC567 R103
30 k 10 k
QX1511-Magliacane15
27
detected on the Q channel trigger a noise gate that temporarily inhibits AGC action and time code detection. Noise energy can also be monitored through the audio amplifier.
in which it begins decoding the frame and Once the validation process is complete, approach, much of the circuitry was built
evaluating the integrity of the data being the frequency standard begins sending the on a series of 95 70mm and 70 45mm
collected. A countdown timer representing current UTC time and date, once every sec- perforated circuit boards that have all been
the number of seconds until the completion ond, to any connected peripherals via the interconnected to one another to form a
of this process is displayed on the top right RS-232 port (Figure 18). These peripherals complete unit. Figure 19 is a view inside the
hand side of the display. If the data collected might include a PC with a real-time clock cabinet of my unit. With the exception of the
looks reasonable, a real-time clock/calendar that can be set through appropriate software, DC power supply, antenna, and remote RF
operating within the firmware of the micro- or an external digital clock display. While preamplifier, all circuitry is housed in a single
controller is set to the time and date decoded. this frequency standard is not intended to Ten-Tec model BK-1249 enclosure that mea-
The microcontroller then looks for vali- serve as an NIST-traceable time source, sures 12inches 4inches 9inches (HWD)
dation of the information received by exam- the date and time reported through both the Figure 20 is a photo of the front of the unit.
ining the next frame of data, and compares serial port and the LCD are advanced by In an effort to enhance frequency stabil-
the result with that of the real-time clock one 100ms to compensate for the nearly equal ity, thermal effects caused by heat dissipa-
minute later (Figure 17D). If the received amount of signal processing delay inher- tion of the frequency standard electronics are
time and date match that of the clock, then ent within the electronics in the frequency minimized by keeping the DC power supply
the microcontroller begins displaying the standard. physically removed from the enclosure, and
locally running clock and calendar from that by mounting both the LM2940T-12.0 and the
point forward. See Figure 17E. If the valida- LM7805 voltage regulators to the enclosures
Parts and Construction back panel. The greatest single sources of
tion fails, then the process reverts to the point
This frequency standard was developed heat outside of the voltage regulators are the
illustrated in Figure 17C, in which the recep-
and tested in discrete stages over a period LCD backlight, and interestingly enough, the
tion and validation routines are repeated
of several years. Due to this modular design VCTCXO, itself.
until the current time and date are finally
confirmed.
C56
C59
0.01 R108
+12 V
0.01 R112
390 k C62
C55 390 k 1 kHz
R106
1 kHz 13 100 F Sinusoidal
In R110 C58
14 9 Output
150 k 0.01 U20D LM386N
R114 C61
8 2
R107 150 k 0.01 U20C 6 C64 J2
12 LMC6484 5
680 100 k 0.047
R111 U23
C57 10 LMC6484 10 k
R109 680 1 kHz 220 F
4 R116
+6 V C60 Sinusoidal
R113 R115 3 10
390 k Output R117
0.1 +6 V
Level C63 1k
0.1 390 k 0.1
1: Modulation R123
2: Peak Signal
3: Center Tuning 100 k
4: Noise Level Modulation In
1 C65 R121 LM837N
S3A 2 13 J3
Peak Signal In 10 kHz IF In C67 10 kHz IF
R118 14
3 "Q" Channel In 1M Sample
0.01 U6D
+ 4 120 k 0.01 Output
M1 +6 V 12
100 A A
R120 R122
2.2 k C66
+6 V 100 k
1 24 k 0.01
S3B 2
3 +6V
R126
4 R119
Noise Voltage In 1M
6.8 k
C68 R124 LM837N
13 J4
60 kHz RF In C70 60 kHz RF
14
0.01 100 k U1D Sample
Decimal values of capacitance are in microfarads (F);
others are in picofarads (pF); Resistances are in ohms; 0.01 Output
k=1,000, M=1,000,000. 12
R125
C69
1M
0.01
QX1512-Maglicane16
+6V
Figure 16 Metering and various sinusoidal output signals are shown on this schematic diagram. In addition to providing buffered 60kHz RF
and 10kHz IF samples, a precise 1kHz sinusoidal waveform capable of driving a small speaker is provided.
Figure 17 These images show the various LCD screens depicting each of the five stages Figure 18 At the beginning of every
of frequency standard operation following power up. The final stage is where the UTC date second, the 19.2kbps RS-232 serial port
and time are continuously displayed and made available to peripheral equipment via the provides the current UTC time and date in the
RS-232 port. form of HH:MM:SS MM/DD/YY followed by a
line feed and carriage return.
Figure 20 Front view of the frequency standard in operation. The large knob on the upper left permits manual fine tuning of the VCTCXO,
while the display provides the UTC date and time.