Professional Documents
Culture Documents
Compal Confidential
2
Kenting Schematics Document 2
2010-03-18
REV: 0.2
3 3
@ : Nopop Component
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Tuesday, April 27, 2010 Sheet 01 of 35
A B C D E
A B C D E
Compal Confidential
Model Name : PIM10
Project Code : ANRPIM1000
Project Name : Kenting
1 1
Thermal Sensor
W83L771AWG
LCD Conn. LVDS page 5
page 9
Atom Processor N455 Memory BUS(DDRIII)
DDRIII-DIMM X1
page 7 Clock Generator
1.5V/800MHz
CRT Conn RGB 22x22mm CK505 page 8
page 23
page 4,5,6
DMI X2 mode
page 23
NM10 Express chipset SD/MMC/MS
page 20
SATA
LS-6501P
PCI-Express 17x17mm
Daughter board HDA Port 0 USB Port X1
page 10,11,12,13
2.5" HDD (R) page 23
page 18
page 14 page 19
PCIE-Port 2 PCIE-Port 1 page 17
Power ON/OFF DC/DC Interface Through power buttom cable Through LED cable
page 22 page 24
PWR buttom board LED/B
DC IN 3VALW/5VALW Int.KBD Touch Pad SPI ROM
page 26 page 28 LS-5732P LS-5733P
page 21 page 22 page 22
4
CHARGER 1.5V/VCCP 4
page 27 page 29
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Monday, May 10, 2010 Sheet 02 of 35
A B C D E
A B C D E
ZZZ
PCB
DA60000I100
1 1
Voltage Rails
Power Plane Description S1 S3 S5
External PCI Devices
VIN Adapter power supply (19V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A
DEVICE IDSEL # REQ/GNT # PIRQ
+CPU_CORE Core voltage for CPU ON OFF OFF
No PCI Device
+0.75VS 0.9V switched power rail for DDR terminator ON OFF OFF
+VCCP VCCP switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.5V 1.5V power rail for DDR ON ON OFF
+1.8VS 1.8V switched power rail ON OFF OFF
+0.89VS CORE VOLTAGE FOR CPU VGA ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
2 2
+VS VS always on power rail ON ON ON*
+RTCBATT RTC power ON ON ON
EC SM Bus1 address EC SM Bus2 address
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Device Address Device Address
Smart Battery 0001 011X b W83L771AWG 1001_100X b
EEPROM(24C16/02) 1010 000X b EMC1402 100_1100X b
SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
3
BOARD ID Table(Page 21) Tiger Point SM Bus address
3
1 R02 (PT) 100K +/- 5% 8.2K +/- 5% 0.168V 0.250V 0.362V DDR DIMMA 1010 000Xb
* 2 R03 (ST) 100K +/- 5% 18K +/- 5% 0.375V 0.503V 0.621V
3 R10 (X build) 100K +/- 5% 33K +/- 5% 0.634V 0.819V 0.945V
4 Reserved 100K +/- 5% 56K +/- 5% 0.958V 1.185V 1.359V
5 Reserved 100K +/- 5% 100K +/- 5% 1.372V 1.650V 1.838V
6 Reserved 100K +/- 5% 200K +/- 5% 1.851V 2.200V 2.420V
7 MP 100K +/- 5% NC 2.433V 3.300V 3.300V
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Tuesday, April 27, 2010 Sheet 03 of 35
A B C D E
5 4 3 2 1
PINEVIEW_M
PINEVIEW_M
U31A U31B
REV = 1.1
DMI
<7> DDR_A_DM[0..7] DDR_A_MA6 DDR_A_MA_5 DDR_A_DQ_1 DDR_A_D2
AK14 DDR_A_MA_6 DDR_A_DQ_2 AF4
DDR_A_MA7 AJ12 AG2 DDR_A_D3
<7> DDR_A_DQS[0..7] DDR_A_MA8 DDR_A_MA_7 DDR_A_DQ_3 DDR_A_D4
AH13 DDR_A_MA_8 DDR_A_DQ_4 AB2
D DDR_A_MA9 DDR_A_D5 D
<7> DDR_A_MA[0..14] AK12 DDR_A_MA_9 DDR_A_DQ_5 AB3
N7 L10 DDR_A_MA10 AK20 AE2 DDR_A_D6
<8> CLK_CPU_EXP# EXP_CLKINN EXP_RCOMPO DDR_A_MA_10 DDR_A_DQ_6
N6 L9 R1172 49.9_0402_1% DDR_A_MA11 AH12 AE3 DDR_A_D7
<8> CLK_CPU_EXP EXP_CLKINP EXP_ICOMPI DDR_A_MA_11 DDR_A_DQ_7
L8 R1171 750_0402_1% DDR_A_MA12 AJ11
EXP_RBIAS DDR_A_MA13 DDR_A_MA_12 DDR_A_DQS1
R10 AJ24 AB8
EXP_TCLKINN DDR_A_MA14 DDR_A_MA_13 DDR_A_DQS_1 DDR_A_DQS#1
R9 EXP_TCLKINP RSVD_TP N11 T1 AJ10 DDR_A_MA_14 DDR_A_DQS#_1 AD7
N10 P11 AA9 DDR_A_DM1
RSVD RSVD_TP T2 DDR_A_DM_1
N9 RSVD DDR_A_WE# AK22 AB6 DDR_A_D8
<7> DDR_A_WE# DDR_A_WE# DDR_A_DQ_8
DDR_A_CAS# AJ22 AB7 DDR_A_D9
<7> DDR_A_CAS# DDR_A_RAS# DDR_A_CAS# DDR_A_DQ_9 DDR_A_D10
<7> DDR_A_RAS# AK21 DDR_A_RAS# DDR_A_DQ_10 AE5
K2 K3 AG5 DDR_A_D11
RSVD RSVD DDR_A_BS0 DDR_A_DQ_11 DDR_A_D12
J1 RSVD RSVD L2 <7> DDR_A_BS0 AJ20 DDR_A_BS_0 DDR_A_DQ_12 AA5
M4 M2 DDR_A_BS1 AH20 AB5 DDR_A_D13
RSVD RSVD <7> DDR_A_BS1 DDR_A_BS2 DDR_A_BS_1 DDR_A_DQ_13 DDR_A_D14
L3 N2 <7> DDR_A_BS2 AK11 AB9
RSVD RSVD DDR_A_BS_2 DDR_A_DQ_14 DDR_A_D15
AD6
DDR_A_DQ_15
1 OF 6 DDR_A_DQS2
PINEVIEW-M_FCBGA8559 AD8
DDR_CS#0 DDR_A_DQS_2 DDR_A_DQS#2
<7> DDR_CS#0 AH22 DDR_A_CS#_0 DDR_A_DQS#_2 AD10
DDR_CS#1 AK25 AE8 DDR_A_DM2
<7> DDR_CS#1 DDR_A_CS#_1 DDR_A_DM_2
AJ21
DDR_A_CS#_2 DDR_A_D16
AJ25 AG8
DDR_A_CS#_3 DDR_A_DQ_16 DDR_A_D17
DDR_A_DQ_17 AG7
C906 DMI_RX0_R CONN@ DDR_CKE0 DDR_A_D18
<12> DMI_RX0 1 2 <7> DDR_CKE0 AH10 DDR_A_CKE_0 DDR_A_DQ_18 AF10
0.1U_0402_10V7K JP80 DDR_CKE1 AH9 AG11 DDR_A_D19
<7> DDR_CKE1 DDR_A_CKE_1 DDR_A_DQ_19
<5> XDP_PREQ# XDP_PREQ# 1 AK10 AF7 DDR_A_D20
C907 DMI_RX#0_R XDP_PRDY# 1 DDR_A_CKE_2 DDR_A_DQ_20 DDR_A_D21
<12> DMI_RX#0 1 2 <5> XDP_PRDY# 2 AJ8 AF8
2 DDR_A_CKE_3 DDR_A_DQ_21 DDR_A_D22
0.1U_0402_10V7K 3 AD11
XDP_BPM#3 3 M_ODT0 DDR_A_DQ_22 DDR_A_D23
<5> XDP_BPM#3 4 4 <7> M_ODT0 AK24 DDR_A_ODT_0 DDR_A_DQ_23 AE10
C908 DMI_RX1_R XDP_BPM#2 M_ODT1
<12> DMI_RX1 1 2 <5> XDP_BPM#2 5 5 <7> M_ODT1 AH26 DDR_A_ODT_1
0.1U_0402_10V7K 6 AH24 AK5 DDR_A_DQS3
XDP_BPM#1 6 DDR_A_ODT_2 DDR_A_DQS_3 DDR_A_DQS#3
C909 <5> XDP_BPM#1 7 AK27 AK3
C 1 2 DMI_RX#1_R XDP_BPM#0 7 DDR_A_ODT_3 DDR_A_DQS#_3 DDR_A_DM3 C
<12> DMI_RX#1 <5> XDP_BPM#0 8 8 DDR_A_DM_3 AJ3
0.1U_0402_10V7K 9
@ R1173 1
@R1173 9 DDR_A_D24
<5,12> H_PWRGD 2 1K_0402_1% 10 AH1
@R1174
@ R1174 10 M_CLK_DDR0 DDR_A_DQ_24 DDR_A_D25
1 2 1K_0402_1% 11 AG15 AJ2
Close to CPU <12> SLPIOVR#
<8> CPU_ITP
CPU_ITP
CPU_ITP#
12
13
11
12
<7>
<7>
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR#0
M_CLK_DDR1
AF15
AD13
DDR_A_CK_0
DDR_A_CK_0#
DDR_A_DQ_25
DDR_A_DQ_26 AK6
AJ7
DDR_A_D26
DDR_A_D27
<8> CPU_ITP# 13 <7> M_CLK_DDR1 DDR_A_CK_1 DDR_A_DQ_27
+VCCP 14 M_CLK_DDR#1 AC13 AF3 DDR_A_D28
+1.5V 14 <7> M_CLK_DDR#1 DDR_A_CK_1# DDR_A_DQ_28
<5,12,14,18,20> PLTRST#
PLTRST# 1 R1175 2 @ 1K_0402_1% 15 AH2 DDR_A_D29
15 DDR_A_DQ_29 DDR_A_D30
T44 16 16 DDR_A_DQ_30 AL5
17 AC15 AJ6 DDR_A_D31
17 DDR_A_CK_3 DDR_A_DQ_31
2
DRAM_PWROK 22 DDR_A_D32
2 1 2 1 23 AE19
23 DDR_A_DQ_32
0.1U_0603_25V7K
@ R1188
C78
DDR_A_D36
1
AB17 AG17
0_0402_5%
RSVD DDR_A_DQ_36
@ R136
DDR_A_DQ_38 DDR_A_D39
+1.5V AD21
Q84 DDR_A_DQ_39
1
1
3
2
1 2 DDR_A_DQ_44 AC22
R1183 51_0402_5%~D AL28 AG24 DDR_A_D45
XDP_TMS R1179 DDR_VREF DDR_A_DQ_45 DDR_A_D46
1 2 AK28 AD27
1
Differential Clock Signal Table DDR_RPD DDR_A_DQ_46
.1U_0402_16V7K~D
R1184 51_0402_5%~D 1 R1181 80.6_0402_1% AJ26 AE27 DDR_A_D47
R1180 DDR_RPU DDR_A_DQ_47
C1102
XDP_TDO 1 2 80.6_0402_1%
Signal Name Description Direction Type R1185 51_0402_5%~D 1 AK29 AE30 DDR_A_DQS6
XDP_PREQ# 1K_0402_1% C256 RSVD DDR_A_DQS_6 DDR_A_DQS#6
1 2 AF29
2 DDR_A_DQS#_6 DDR_A_DM6
BCLKP[0] Differential Core Clock In
2
AF30
0.01U_0402_25V7K~D DDR_A_DM_6
BCLKN[0] I Diff Clk CMOS 2
DDR_A AG31 DDR_A_D48
DDR_A_DQ_48 DDR_A_D49
HPL_CLKINP Differential Host Clock In R1186 51_0402_5%~D
DDR_A_DQ_49 AG30
I Diff Clk CMOS XDP_TRST# 1 2 AD30 DDR_A_D50
HPL_CLKINN R1187 51_0402_5%~D DDR_A_DQ_50
AD29 DDR_A_D51
XDP_TCK DDR_A_DQ_51 DDR_A_D52
EXP_CLKINP Differential DMI Clock In 1 2
DDR_A_DQ_52
AJ30
I Diff Clk CMOS AJ29 DDR_A_D53
EXP_CLKINN DDR_A_DQ_53 DDR_A_D54
NOTE DDR_A_DQ_54
AE29
REFCLKINP Differential PLL Clock In AD28 DDR_A_D55
DDR_A_DQ_55
REFCLKINN I Diff Clk CMOS Place 0.1uF CAP close to CPU.
AB27 DDR_A_DQS7
DDR_A_DQS_7 DDR_A_DQS#7
REFSSCLKINP Differential Spread Spectrum Clock In DDR_A_DQS#_7
AA27
I Diff Clk CMOS AB26 DDR_A_DM7
REFSSCLKINN DDR_A_DM_7
+1.5V AA24 DDR_A_D56
XDP_TDI DDR_A_DQ_56 DDR_A_D57
DDR_A_DQ_57 AB25
XDP_TMS W24 DDR_A_D58
DDR_A_DQ_58
2
W22 DDR_A_D59
DDR_A_DQ_59
3
PSOT24C_SOT23-3
W27 DDR_A_D63
1
@ DDR_A_DQ_63
D5 R288
1
PSOT24C_SOT23-3
A DRAMRST#_R 1 DRAMRST# A
2 DRAMRST# <7> 2 OF 6
XDP_TRST# PINEVIEW-M_FCBGA8559
XDP_TCK 0_0402_5%
1
3
@
D8
PSOT24C_SOT23-3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Pineview(1/3)-DMI,DDR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Monday, May 10, 2010 Sheet 04 of 35
5 4 3 2 1
5 4 3 2 1
PINEVIEW_M
U31C
VGA
D9 LA_DATAP_0 LINT0 H_NMI
XDP_RSVD_09 <9> LVDSA1- N26 F11 H_NMI <11>
T22 C8 LA_DATAN_1 LINT1 H_IGNNE#
XDP_RSVD_10 <9> LVDSA1+ N27 E5 H_IGNNE# <11>
T16 B8 LA_DATAP_1 IGNNE# H_STPCLK#
XDP_RSVD_11 <9> LVDSA2- R26 F8 H_STPCLK# <11>
T13 C10 L31 GMCH_CRT_DATA <22> LA_DATAN_2 STPCLK#
XDP_RSVD_12 CRT_DDC_DATA
ICH
<9> LVDSA2+ R27 LA_DATAP_2
T23 D10 XDP_RSVD_13 CRT_DDC_CLK L30 GMCH_CRT_CLK <22>
T17 B11 R1190
XDP_RSVD_14 R1189 665_0402_1% G6 H_DPRSTP#
T14 B10 P28 2.37K_0402_1% DPRSTP# H_DPRSTP# <12>
XDP_RSVD_15 DAC_IREF R22 G10 H_DPSLP#
T15 B12 LIBG DPSLP# H_DPSLP# <12>
XDP_RSVD_16 J28 G8 H_INIT#
T24 C11 Y30 CPU_DREFCLK LVBG INIT# H_INIT# <11>
XDP_RSVD_17 REFCLKINP CPU_DREFCLK <8> N22 E11 XDP_PRDY#
Y29 CPU_DREFCLK# LVREFH PRDY# XDP_PRDY# <4>
REFCLKINN CPU_DREFCLK# <8> N23 F15 XDP_PREQ#
R1198 AA30 CPU_SSCDREFCLK LVREFL PREQ# XDP_PREQ# <4>
REFSSCLKINP CPU_SSCDREFCLK <8> GMCH_ENBKL L27
1K_0402_1% AA31 CPU_SSCDREFCLK# <20> GMCH_ENBKL LBKLT_EN
LVDS
REFSSCLKINN CPU_SSCDREFCLK# <8> L26 LBKLT_CTL H_THERMTRIP#
L23 LCTLA_CLK THERMTRIP# E13 H_THERMTRIP# <11>
T25 L11 RSVD K25 LCTLB_DATA
<9> EDID_CLK_LCD K23 LDDC_CLK
0_0402_5% <9> EDID_DAT_LCD K24
R1252 LDDC_DATA
PM_EXTTS#1 <9> GMCH_LVDDEN H26 LVDD_EN
PM_EXTTS#_1/DPRSLPVR K29 PM_DPRSLPVR <12> H_PROCHOT#
PM_EXTTS#0 PROCHOT# C18
PM_EXTTS#_0 J30 PM_EXTTS#0 <7> H_PWRGD
H_PWROK CPUPW RGOOD W1 H_PWRGD <4,12>
PW ROK L5
AA3 PLTRST# R1192
RSTIN# PLTRST# <4,12,14,18,20>
100K_0402_5%
A13 H_GTLREF
W8 CLK_CPU_HPLCLK# GTLREF
HPL_CLKINN CLK_CPU_HPLCLK# <8> H27
W9 CLK_CPU_HPLCLK VSS
HPL_CLKINP CLK_CPU_HPLCLK <8>
AA7
MISC
T26 RSVD_TP
T27 AA6 @ R1193
RSVD_TP H_PWROK 1 2 L6
C
T28 R5 VGATE <8,12,20,30> RSVD C
RSVD_TP 0_0402_5% E17
T29 R6 RSVD
RSVD_TP R1194 <4> XDP_BPM#0 G11 BPM_1_0# CLK_CPU_BCLK#
1 2 PCH_POK <12,20> <4> XDP_BPM#1 E15 BPM_1_1# BCLKN H10 CLK_CPU_BCLK# <8>
T30 AA21 RSVD_TP CLK_CPU_BCLK
0_0402_5% <4> XDP_BPM#2 G13 BPM_1_2# BCLKP J10 CLK_CPU_BCLK <8>
T31 W 21 RSVD_TP <4> XDP_BPM#3 F13 BPM_1_3#
T32 T21 RSVD_TP CPU_BSEL0
BSEL_0 K5 CPU_BSEL0 <8>
T33 V21 RSVD_TP CPU_BSEL1
T34 B18 BPM_2_0#/RSVD BSEL_1 H5 CPU_BSEL1 <8>
T35 B20 K6 CPU_BSEL2
BPM_2_1#/RSVD BSEL_2 CPU_BSEL2 <8>
CPU
T36 C20 BPM_2_2#/RSVD
T37 B21 H30 CPU_VID0
BPM_2_3#/RSVD VID_0 CPU_VID0 <30>
H29 CPU_VID1
VID_1 CPU_VID1 <30>
H28 CPU_VID2
VID_2 CPU_VID2 <30>
G30 CPU_VID3
VID_3 CPU_VID3 <30>
T38 G5 G29 CPU_VID4
RSVD VID_4 CPU_VID4 <30>
XDP_TDI D14 F29 CPU_VID5
<4> XDP_TDI TDI VID_5 CPU_VID5 <30>
XDP_TDO D13 E29 CPU_VID6
<4> XDP_TDO TDO VID_6 CPU_VID6 <30>
XDP_TCK B14
<4> XDP_TCK TCK
XDP_TMS C14 L7
<4> XDP_TMS TMS RSVD
XDP_TRST# C16 D20
<4> XDP_TRST# TRST# RSVD
RSVD H13
RSVD D18
H_THERMDA D30
H_THERMDC THRMDA_1
E30 THRMDC_1 RSVD_TP K9 T39
RSVD_TP D19 T40
K7 H_EXTBGREF
EXTBGREF
+VCCP
+3VS
B 3 OF 6 B
1
PINEVIEW-M_FCBGA8559 R1196
R1195 68_0402_5% C30 THRMDA_2/RSVD
D31 THRMDC_2/RSVD
10K_0402_5%
H_PROCHOT# 4 OF 6
2
PM_EXTTS#0 PINEVIEW-M_FCBGA8559
1U_0603_10V4Z
R1203
GMCH_CRT_R
1U_0603_10V4Z
1 2 1
C940
150_0402_1% 1 R1202
@ C939
GMCH_CRT_G 1 R1200 2 R1201
0.1U_0402_16V4Z~D
1 3.3K_0402_1%
150_0402_1% 2K_0402_1%
C914 GMCH_CRT_B 1 R1204 2 @ 2
U33 150_0402_1% 2
2 GMCH_ENBKL R1205
100K_0402_5%
1 8 EC_SMB_CK2 EC_SMB_CK2 <20>
VDD SCL
H_THERMDA 2 7 EC_SMB_DA2
placed within 0.5" placed within 0.5"
A D+ SDA EC_SMB_DA2 <20> A
1
C915
2 H_THERMDC 3 6 2 R1206 1
of processor pin. of processor pin.
D- ALERT# +3VS
2200P_0402_50V7K 10K_0402_5%
4 T_CRIT_A# GND 5
U31F PINEVIEW_M
GFX/MCH
W19 E22 +VCCP AA8 J15
VCCGFX VCC VSS VSS
E24 AB19 J4
VCC VSS VSS
E27 AB21 K11
CPU
VCC +CPU_CORE VSS VSS
F21 AB28 K13
VCC 4.7U_0603_6.3V6K~D VSS VSS
VCC
F22 2 x 330uF(9mohm/2) AB29
VSS VSS
K19
F25 1 AB30 K26
VCC C924 VSS VSS
VCC G19 1 1 1 1 1 AC10 VSS VSS K27
G21 @ @ AC11 K28
VCC + + C918 + C925 C926 VSS VSS
VCC G24 AC19 VSS VSS K30
H17 C921 C923 2 AC2 K4
GND
VCC 330U 2.5V Y 330U 2.5V Y 330U 2.5V Y 2 2 VSS VSS
H19 AC21 K8
DDR supply current: 2.27A VCC 2 2 2 22U_0805_6.3V6M 1U_0603_10V4Z VSS VSS
H22 AC28 L1
+1.5V VCC VSS VSS
VCC H24 AC30 VSS VSS L13
J17 Close to U31.U10 AD26 L18
1U_0402_6.3V6K1U_0402_6.3V6K VCC VSS VSS
AK13 J19 AD5 L22
VCCSM VCC VSS VSS
AK19 VCCSM VCC J21 Close to U71.E2 AE1 VSS VSS L24
1 1 1 1 1 AK9 J22 Close to U71.D4 AE11 L25
VCCSM VCC R1207 VSS VSS
AL11 K15 AE13 L29
C273 C928 C929 C930 C931 VCCSM VCC VSS VSS
AL16 VCCSM VCC K17 +RING_EAST AE15 VSS VSS M28
1 2
AL21 VCCSM VCC K21 AE17 VSS VSS M3
22 2 2 2 1
AL25 L14 AE22 N1
VCCSM VCC VSS VSS
22U_0805_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K L16 0_0603_5% C932 AE31 N13
C VCC VSS VSS C
+1.5V VCC L19 1U_0603_10V4Z AF11 VSS VSS N18
L21 2 AF17 N24
VCC VSS VSS
22U_0805_6.3V6M
C379
U5 AH28 P16
VCCA_DDR VSS VSS
U6 VCCA_DDR AH4 VSS VSS P18
U7 AH6 P19
VCCA_DDR VSS VSS
POWER
0.1U_0402_16V4Z~D
0_0603_5%
@C409
C409
@ C401
B B
B22 VSS VSS W26
R1212
1U_0603_10V4Z
B9 W5
1
VSS VSS
AC31 C1 W6
VCCSFR_AB_DPL +VCC_ALVD RSVD_NCTF VSS
1 1 V30 C12 W7
VCCALVDS +VCC_DLVD VSS VSS
W31 C21 Y28
VCCDLVDS VSS VSS
C941
C942
+VCC_CRT_DAC D22
+3VS 1 2 VSS
E1 RSVD_NCTF
GIO supply current:0.006A MBK2012601_YZF C943 E10
+VCC_DMI VSS
T31 VCC_GIO VCCA_DMI T1 E19 VSS
+RING_EAST J31 T2 E21
+RING_WEST VCCRING_EAST VCCA_DMI DMI analog supply current: 0.48A 10U_0603_6.3V6M VSS
C3 T3 E25 T29
DMI
2
0.1U_0402_10V6K
C946
2 100_0402_1%
10U_0805_10V6K~D
A 1 R1217 2 +VCC_DLVD A
1U_0402_6.3V6K
R1219
330U 2.5V Y
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 VSSSENSE 1 2 0_0805_5% 1
1 1 100_0402_1%
C947
C949
C950
C951
C952
C954
C948
1 1 1 1 1 1 1
C927
C995
C1000
1 +
C953
1U_0603_10V4Z
2
2 2 2
2 2 2 2 2 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Pineview(3/3)-POWER,GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Monday, May 10, 2010 Sheet 06 of 35
5 4 3 2 1
5 4 3 2 1
0.1U_0603_25V7K
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z
<4> DDR_A_DQS[0..7] DDR_A_DM0 11 12 DDR_A_DQS0
DM0 DQS0
D 1 1 1 13 VSS5 VSS6 14 D
C421
C1124
C1125
<4> DDR_A_MA[0..14] DDR_A_D2 15 16 DDR_A_D6
DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 DQ3 DQ7 18
19 VSS7 VSS8 20
2 2 2 DDR_A_D8 DDR_A_D12
21 DQ8 DQ12 22
DDR_A_D9 23 24 DDR_A_D13
DQ9 DQ13
25 VSS9 VSS10 26
DDR_A_DQS#1 27 28 DDR_A_DM1
DDR_A_DQS1 DQS#1 DM1 DRAMRST#
Layout Note: Layout Note: 29
DQS1 RESET#
30 DRAMRST# <4>
31 VSS11 VSS12 32
Place near JDIMM1.1 Place near JDIMM1.126 DDR_A_D10 33
DQ10 DQ14
34 DDR_A_D14
DDR_A_D11 35 36 DDR_A_D15
DQ11 DQ15
37 VSS13 VSS14 38
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 42
+1.5V +1.5V DQ17 DQ21
43 44
DDR_A_DQS#2 VSS15 VSS16 DDR_A_DM2
45 46
DDR_A_DQS2 DQS#2 DM2
47 48
DQS2 VSS17 DDR_A_D22
49 50
VSS18 DQ22
1
1
DDR_A_D18 51 52 DDR_A_D23
R336 +DIMM_VREF_DQ R339 +DIMM_VREF_CA DDR_A_D19 DQ18 DQ23
53 54
DQ19 VSS19 DDR_A_D28
55 56
1K_0402_1% 1K_0402_1% DDR_A_D24 VSS20 DQ28 DDR_A_D29
57 58
DDR_A_D25 DQ24 DQ29
59 60
2
2
DQ25 VSS21 DDR_A_DQS#3
61 VSS22 DQS#3 62
DDR_A_DM3 63 64 DDR_A_DQS3
DM3 DQS3
1
1
1 1 65 66
R337 C1135 R338 C1136 DDR_A_D26 VSS23 VSS24 DDR_A_D30
67 68
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 70
1K_0402_1% 0.1U_0402_16V4Z 1K_0402_1% 0.1U_0402_16V4Z DQ27 DQ31
71 72
2 2 VSS25 VSS26
2
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 <4> DDR_A_WE# DDR_A_WE# 113 114 DDR_CS#0 DDR_CS#0 <4>
WE# S0#
330U 2.5V Y
C1113
C1114
C1115
C1116
C1134
+ 117 118
VDD15 VDD16
20mils
C969
C388
C389
C386
C384
C382
C390
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z
0.1U_0603_25V7K
DDR_A_DQS#4 135 136 DDR_A_DM4
DDR_A_DQS4 DQS#4 DM4
137 DQS4 VSS31 138 1 1 1
C1117
C1118
C422
139 140 DDR_A_D38
DDR_A_D34 VSS32 DQ38 DDR_A_D39
141 DQ34 DQ39 142
DDR_A_D35 143 144
DQ35 VSS33 DDR_A_D44 2 2 2
B 145 146 B
DDR_A_D40 VSS34 DQ44 DDR_A_D45
147 148
DDR_A_D41 DQ40 DQ45
Layout Note: 149
DQ41 VSS35
150
DDR_A_DQS#5
151 152
Place near JDIMM1.203 & JDIMM1.204 DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5
153 DM5 DQS5 154
155 156
DDR_A_D42 VSS37 VSS38 DDR_A_D46
157 158
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 160
+0.75VS DQ43 DQ47
161 VSS39 VSS40 162
DDR_A_D48 163 164 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
167 168
DDR_A_DQS#6 VSS41 VSS42 DDR_A_DM6
169 170
DQS#6 DM6
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C1121
C1120
C1119
.1U_0402_16V7K~D
C1131
205 206
G1 G2
R349
2 2 FOX_AS0A626-U4RN-7F DIMM_A(REV)
4H
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM A
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Friday, May 07, 2010 Sheet 07 of 35
5 4 3 2 1
5 4 3 2 1
+3VM_CK505 +1.5VM_CK505
FSC FSB FSA CPU SRC PCI REF DOT_96 USB Co-Layout circuit @ R94 0_0805_5% R102 0_0805_5%
+3VS
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz +3VS 1
R78
2
0_0805_5%
1 2 1 2 +1.5VS
1 1 1 1 1 1 1 1 1 1
10U_0805_10V6K~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
47P_0402_50V8J
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10U_0805_10V6K~D
C151 C181 C175 C197 C936 C199 C155 C154 C182 C156 R112 R108
0 0 0 266 100 33.3 14.318 96.0 48.0
2.2K_0402_5% 2.2K_0402_5%
2 2 2 2 2 2 2 2 2 2 2N7002DW-T/R7_SOT363-6
0 0 1 133 100 33.3 14.318 96.0 48.0 Q10A
2
+1.05VM_CK505
D
0 1 1 166 100 33.3 14.318 96.0 48.0
* +3VS
D
5
+VCCP 1 2
1 0 0 333 100 33.3 14.318 96.0 48.0 R131 0_0805_5% 1 1 1 1 1 1 1 1
C163 C198 C152 C153 C167 C189 C200 @ <12> ICH_SMBCLK 3 4 CLK_SMBCLK
C945
1 0 1 100 100 33.3 14.318 96.0 48.0 10U_0805_10V6K~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 47P_0402_50V8J
2 2 2 2 2 2 2 2 Q10B
2N7002DW-T/R7_SOT363-6
1 1 0 400 100 33.3 14.318 96.0 48.0
2
R435 R102,C182,C156,C936,R116
10K_0402_5% +1.5VM_CK505 +3VM_CK505
1 1
9 CLK_SMBDATA
Q32 55
VDD_SRC
SDA CLK_SMBDATA <7> R102,C182,C156,C936,R118
10 CLK_SMBCLK
+VCCP SCL CLK_SMBCLK <7>
6
VDD_REF
ICS,Silego
De-pop R102,C182,C156,
2 12 71 CLK_CPU_BCLK +3VS
<30> CLK_ENABLE# VDD_PCI CPU_0 CLK_CPU_BCLK <5> C936,R118;pop R94,R116
2
R140
72 70 CLK_CPU_BCLK#
DTC124EK_SC59 VDD_CPU CPU_0# CLK_CPU_BCLK# <5>
470_0402_5%~D
R138 19 68 CLK_CPU_HPLCLK
3
VDD_48 CPU_1 CLK_CPU_HPLCLK <5>
2.2K_0402_5%
SRC PORT LIST
1
FSA 2 1 27 67 CLK_CPU_HPLCLK#
VDD_PLL3 CPU_1# CLK_CPU_HPLCLK# <5>
+1.05VM_CK505 1 2 31 25 CPU_DREFCLK#
VDD_PLL3_IO SRC_0#/DOT_96# CPU_DREFCLK# <5>
@ R141
1
R118 0_0402_5%
2 62
SRC0 CPU_VGA
+1.5VS VDD_SRC_IO
1K_0402_1% CPU_SSCDREFCLK
52
LCDCLK/27M
28 CPU_SSCDREFCLK <5> SRC2 DMI
2
VDD_SRC_IO CPU_SSCDREFCLK#
23
LCDCLK#/27M_SS
29 CPU_SSCDREFCLK# <5> SRC3
VDD_IO
+VCCP 38 32 CLK_CPU_EXP
CLK_CPU_EXP <4>
SRC4 PCIE_SATA
VDD_SRC_IO SRC_2
1 R137
<12> CLK_ICH_48M 2
33_0402_5% 33 CLK_CPU_EXP#
CLK_CPU_EXP# <4>
SRC6 PCIE_WLAN
SRC_2#
2
R81
2
5P_0402_50V8C
1
C832 FSA 20
SRC7
USB_0/FS_A
R86 470_0402_5%~D FSB 2
SRC_3
35
SRC8 CPU_XDP
FS_B/TEST_MODE
1K_0402_1% 1 R101 2 36
SRC9 PCIE_LAN
1
<5> CPU_BSEL1 1 2
1
C392
2
10P_0402_50V8J~D 8 39 CLK_PCIE_SATA
CLK_PCIE_SATA <11>
SRC10 PCIE_TigerPoint
R91 CLK_EN REF_1 SRC_4
0_0402_5% 40 CLK_PCIE_SATA#
CLK_PCIE_SATA# <11>
SRC11
SRC_4#
1
1 2 1
@ R82 <5,12,20,30> VGATE 0_0402_5% @ R1327 CKPWRGD/PD#
11 57 CLK_PCIE_WLAN
NC SRC_6 CLK_PCIE_WLAN <14>
0_0402_5%
56 CLK_PCIE_WLAN# +3VS
CLK_PCIE_WLAN# <14>
2
SRC_6#
H_STP_CPU# 53 R139
<12> H_STP_CPU# CPU_STOP# WWAN_REQ#11
61 2 1 10K_0402_5%
H_STP_PCI#_R SRC_7 R84
1 2 54
<12> H_STP_PCI# R150 @ PCI_STOP# WLAN_CLKREQ#
60 2 1 10K_0402_5%
+VCCP 0_0402_5% SRC_7# R111
B CLK_XTAL_IN 5 CLKREQ_LAN# 2 1 10K_0402_5% B
XTAL_IN CPU_ITP
64 CPU_ITP <4>
SRC_8/CPU_ITP
2
CLK_XTAL_OUT 4
@ R97 XTAL_OUT CPU_ITP# R121
63 CPU_ITP# <4>
SRC_8#/CPU_ITP# H_STP_CPU#
Schematic Note: 2 1 10K_0402_5%
R100 470_0402_5%~D R124
10K_0402_5%
33 ohm series-resistor need add for singal end clock. 13 44 CLK_PCIE_LAN H_STP_PCI#_R 2 1 10K_0402_5%
CLK_PCIE_LAN <18>
1
PCI4_SEL
@ R98
<20> CLK_PCI_LPC 1
R1335
2 16
PCI_4/SEL_LCDCL
SRC_10#
51 CLK_PCIE_ICH#
CLK_PCIE_ICH# <12>
REQ PORT LIST
1 2 33_0402_5% ITP_EN 17
10P_0402_50V8J~D
10P_0402_50V8J~D
SRC_11
@ @ CLK_PCIE_WWAN#
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP# 2 2
18
VSS_PCI SRC_11#
47 CLK_PCIE_WWAN# <14>
A A
14.318MHZ_16PF_7A14300083~D
ITP_EN PCI4_SEL PCI2_TME
2
CLK_XTAL_OUT
C162 22P_0402_50V8J
Security Classification Compal Secret Data Compal Electronics, Inc.
2
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Friday, May 07, 2010 Sheet 08 of 35
5 4 3 2 1
5 4 3 2 1
2
R70 R63
470_0805_5% 1M_0402_5%
D D
+3VS +3VS +CAM_VDD
6 2
1
+LCDVDD +LCDVDD_R +3VS +3VS_LCD +3VS +VMIC
L21 L22 L37
W=60mils R35 W=20mils
Q29A Q3 1 2 1 2 1 2 1 2
3
S
R73 G 1
2 1 2 2 AO3413_SOT23 FBMA-L11-201209-221LMA30T_0805 1 0_0603_5% FBMA-L11-201209-221LMA30T_0805 1 FBMA-L11-201209-221LMA30T_0805 1
2N7002DW-T/R7_SOT363-6 100K_0402_5% +LCDVDD C398 C45
C397 0.1U_0402_16V4Z~D C399 C647
D
W=60mils
1
1
4.7U_0805_10V4Z~D 0.1U_0402_16V4Z~D 2 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
2
3
C395 2 2 2
0.1U_0402_16V4Z~D @ 1
Q29B C396 C394
5 1 4.7U_0805_10V4Z~D 0.1U_0402_16V4Z~D
<5> GMCH_LVDDEN
2
2
4
R72
100K_0402_5% 2N7002DW-T/R7_SOT363-6
+3VS
+3VS
1
+CAM_VDD +LCDVDD_R INVPWR_B+ +3VS_LCD +VMIC
1
R69 R65
R60 CONN@
4.7K_0402_5% JP24 2.2K_0402_5% 2.2K_0402_5%
42 41
2
GND GMD
40 39
2
40 39
38 37
38 37
36 35 EDID_CLK_LCD <5>
C 36 35 C
34 34 33 33 EDID_DAT_LCD <5>
32 31 R44
<5> LVDSA0+ 32 31
<5> LVDSA0- 30 29 LVDSA1+ <5> 1 2
30 29
28 28 27 27 LVDSA1- <5>
26 25 0_0402_5%
<5> LVDSA2+ 26 25 LVDC+ R1027
<5> LVDSA2- 24 23 1 2 0_0402_5% LVDSAC+ <5>
24 23 LVDC- R1026 @
22 22 21 21 2 1 0_0402_5% LVDSAC- <5>
20 19 WCM2012F2S-900T04_0805
<15> MIC_DATA 20 19
L25 1 2 18 17 USBP3 4 3
<15> MIC_CLK 18 17 4 3 USB20_P3 <12>
FBMA-L10-160808 301LMT_0603 16 15
16 15
14 14 13 13
12 11 USBN3 1 2
12 11 1 2 USB20_N3 <12>
10 10 9 9
BKOFF# 8 7 L64
<20> BKOFF# 8 7 INVT_PWM <20>
6 5
@ @ 6 5 LCD_TST
1 1 4 3 LCD_TST <20>
4 3 R46
2 1 1
C229 C230 2 1
1 2
ACES_87242-4001-09 1 C231
100P_0402_50V8J 2 2 100P_0402_50V8J C600 0_0402_5%
100P_0402_50V8J 2 100P_0402_50V8J
B B
B+ L18 INVPWR_B+
FBMA-L11-201209-221LMA30T_0805
2 1
1 1
C85 C393 LVDSAC+
@ C232
100P_0402_50V8J
@ C233
100P_0402_50V8J
@ Q80
SI3457BDV-T1-E3_TSOP6~D 1 1
D
40mil 6
S
4 5
2 2
2
1 40mil
G
1
1
1 @ C830
3
@ C829 @ R1158
0.1U_0603_50V4Z~D
1000P_0402_50V7K~D 100K_0402_5% 2
2
2
PWR_SRC_ON
@ Q81
A RHU002N06_SOT323-3~D A
1 2 1 3
D
@ R1159 100K_0402_5%
G
2
BKOFF#
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/03/18 Deciphered Date 2011/03/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/INVERTER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Friday, May 07, 2010 Sheet 09 of 35
5 4 3 2 1
5 4 3 2 1
D D
A5 B22
R1220 PCI_DEVSEL# PAR AD0
8.2K_0402_5% B15 D18
@R1322
@ R1322 CLK_PCI_ICH DEVSEL# AD1
<8> CLK_PCI_ICH J12 PCICLK AD2 C17
<20> PCI_RST# 1 2 A23 C18
PCIRST# AD3
2
0_0402_5% PCI_IRDY# B7 B17
C @ R1154 8.2K_0402_5% R1221 IRDY# AD4 C
C22 PME# AD5 C19
PCI_SERR# B11 B18
100K_0402_5% 8.2K_0402_5% R1222 PCI_STOP# SERR# AD6
F14 B19
8.2K_0402_5% R1224 PCI_PLOCK# STOP# AD7
A8 D16
1 8.2K_0402_5% R1223 PCI_TRDY# PLOCK# AD8
A10 TRDY# AD9 D15
8.2K_0402_5% R1225 PCI_PERR# D10 A13
8.2K_0402_5% R1226 PCI_FRAME# PERR# AD10
A16 FRAME# AD11 E14
8.2K_0402_5% R1227 H14
AD12
AD13 L14
J14
AD14
A18 GNT1# AD15 E10
E16 C11
GNT2# AD16
AD17 E12
PCI_REQ1#
8.2K_0402_5% R1228 PCI_REQ2#
G16
A20
REQ1# PCI AD18
B9
B13
8.2K_0402_5% R1229 REQ2# AD19
L12
AD20
B8
AD21
G14 A3
GPIO48/STRAP1# AD22
A2 B5
GPIO17/STRAP2# AD23
C15 GPIO22 AD24 A6
10K_0402_5% R1230 C9 G12
10K_0402_5% R1231 GPIO1 AD25
CLK_PCI_ICH H12
AD26
1
R1233 R1234 C8
R1232 AD27
10K_0402_5% 10K_0402_5% D9
@ 33_0402_5% PCI_PIRQA# AD28
@ @ B2 C7
8.2K_0402_5% R1235 PCI_PIRQB# PIRQA# AD29
D7 C1
8.2K_0402_5% R1236 PCI_PIRQC# PIRQB# AD30
1 B3 B1
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Tigerpoint(1/4)-PCI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Friday, May 07, 2010 Sheet 10 of 35
5 4 3 2 1
5 4 3 2 1
D D
U34C TGP
SATA
W10
RSVD13
V12
C RSVD14 C
AE21 RSVD15
AE18
RSVD16
AD19
RSVD17
U12 RSVD18
SATA_CLKN AD4 CLK_PCIE_SATA# <8>
AC17 AC4 CLK_PCIE_SATA <8> +3VS
RSVD19 SATA_CLKP
AB13 RSVD20
AC13 AD11 R1247
RSVD21 SATARBIAS# SATARBIAS R1246 24.9_0402_1%
AB15 RSVD22 SATARBIAS AC11
Y14 AD25 SATA_LED# SATA_LED#
RSVD23 SATALED# SATA_LED# <22>
10K_0402_5%
AB16
RSVD24 Close to TigerPoint R1248
AE24 RSVD25 GATEA20
AE23 pin U16
RSVD26 10K_0402_5%
R1249
AA14 U16 GATEA20 GATEA20 <20> SERIRQ
RSVD27 A20GATE H_A20M#
V14 Y20 H_A20M# <5> 10K_0402_5%
RSVD28 A20M#
Y21
CPUSLP# H_IGNNE#
IGNNE# Y18 H_IGNNE# <5>
AD16 AD21 +VCCP
RSVD29 INIT3_3V# H_INIT#
AB11 AC25 H_INIT# <5>
RSVD30 INIT# H_INTR
+3VS AB10 AB24
RSVD31 INTR H_INTR <5> 56 ohm5% pull-up resistor has
HOST
1
Y22 H_FERR#
FERR# H_FERR# <5>
R1250 8.2K_0402_5% AD23
GPIO36 NMI
T17 H_NMI
H_NMI <5>
R1251 to be within 1" from the Tiger
AC21 KB_RST# Point chipset.
RCIN# KB_RST# <20>
AA16 SERIRQ 56_0402_5%
SERIRQ SERIRQ <20>
AA21 H_SMI#
H_SMI# <5>
2
SMI# H_STPCLK#
V18 H_STPCLK# <5>
STPCLK#
AA20 H_THERMTRIP# <5>
THRMTRIP#
B B
TIGERPOINT_ES1_BGA360
ESD request
H_A20M# C450 @
1 2 100P_0402_50V8J
H_IGNNE# C451 @
1 2 100P_0402_50V8J
+VCCP
H_INIT# C452 @
1 2 100P_0402_50V8J
H_INTR C453 @
1 2 100P_0402_50V8J
R198
56_0402_5% H_FERR# C454 @
1 2 100P_0402_50V8J
H_NMI C455 @
1 2 100P_0402_50V8J
H_FERR#
H_SMI# C456 @
1 2 100P_0402_50V8J
Close to TigerPoint H_STPCLK# C457 @
1 2 100P_0402_50V8J
pin Y22
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Tigerpoint(2/4)-HOST,SATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Friday, May 07, 2010 Sheet 11 of 35
5 4 3 2 1
5 4 3 2 1
6 WLAN + BT
U34D TGP 7 CardReader
AA5 T15 GPIO0
LDRQ1#/GPIO23 BMBUSY#/GPIO0 GPIO6
<20> LPC_AD0 V6 LAD0/FWH0 GPIO6 W16
LPC
SLPIOVR# U34B TGP
<20> LPC_AD1 AA6 LAD1/FWH1 GPIO7 W14 SLPIOVR# <4>
Y5 K18 EC_SMI#
<20> LPC_AD2 LAD2/FWH2 GPIO8 EC_SMI# <20>
W8 H19 EC_SCI# R23 H7 USB20_N0
<20> LPC_AD3 LAD3/FWH3 GPIO9 EC_SCI# <20> <4> DMI_TX#0 DMI0RXN USBP0N USB20_N0 <22>
C416 Y8 M17 ACIN_C R24 H6 USB20_P0
LDRQ0# GPIO10 <4> DMI_TX0 DMI0RXP USBP0P USB20_P0 <22>
10P_0402_50V8J~D Y4 A24 GPIO12 P21 H3
<20> LPC_FRAME# LFRAME#/FWH4 GPIO12 <4> DMI_RX#0 DMI0TXN USBP1N
2 1 @ GPIO13 C23 EC_LID_OUT#
EC_LID_OUT# <20> <4> DMI_RX0 P20 DMI0TXP USBP1P H2
33_0402_5% 1 R1259 2 P6 P5 GPIO14 T21 J2 USB20_N2
<15> HDA_BITCLK_AUDIO R1261 2 HDA_BIT_CLK GPIO14 <4> DMI_TX#1 DMI1RXN USBP2N USB20_N2 <22>
33_0402_5% 1 U2 E24 GPIO15 T20 J3 USB20_P2
<15> HDA_RST_AUDIO# HDA_RST# GPIO15 <4> DMI_TX1 DMI1RXP USBP2P USB20_P2 <22>
1 0_0402_5%
AUDIO
33_0402_5% 1 R1262 2 W2 AB20 2 R1263 T24 K6 USB20_N3
<15> HDA_SDIN0 HDA_SDIN0 DPRSLPVR PM_DPRSLPVR <5> <4> DMI_RX#1 DMI1TXN USBP3N USB20_N3 <9>
V2 Y16 T25 K5 USB20_P3
HDA_SDIN1 STP_PCI# H_STP_PCI# <8> <4> DMI_RX1 DMI1TXP USBP3P USB20_P3 <9>
DMI
P8 AB19 T19 K1 USB20_N4
33_0402_5% R1260 2 HDA_SDIN2 STP_CPU# H_STP_CPU# <8> DMI2RXN USBP4N USB20_N4 <14>
1 AA1 R3 T18 K2 USB20_P4
<15> HDA_SDOUT_AUDIO HDA_SDOUT GPIO24 DMI2RXP USBP4P USB20_P4 <14>
33_0402_5% 1 R1264 2 Y1 C24 1 R1265 2 U23 L2
<15> HDA_SYNC_AUDIO HDA_SYNC GPIO25 DMI2TXN USBP5N
AA3 D19 1K_0402_1% U24 L3
<8> CLK_ICH_14M
1
USB
2 P7 LANR_RSTSYNC <18> PCIE_PTX_IRX_N1 K21 PERN1 OC1# C5 USB_OC#1 <22>
B23 AB22 H_PWRGD K22 D3 USB_OC#2
For EMI, Close to TigerPoint LAN_RST# CPUPWRGD/GPIO49 H_PWRGD <4,5> <18> PCIE_PTX_IRX_P1 PERP1 OC2# USB_OC#2 <22>
AA2 C996 0.1U_0402_10V7K PCIE_ITX_C_PRX_N1_R J23 D2 USB_OC#3
LAN
MISC
C LAN_RXD0 EC_THERM# <18> PCIE_ITX_C_PRX_N1 C997 0.1U_0402_10V7K PCIE_ITX_C_PRX_P1_R PETN1 OC3# USB_OC#4 C
AD1 LAN_RXD1 THRM# AB17 EC_THERM# <20> <18> PCIE_ITX_C_PRX_P1 J24 PETP1 OC4# E5
AC2 V16 VGATE M18 E6 USB_OC#5
LAN_RXD2 VRMPWRGD <14> PCIE_PTX_IRX_N2 PERN2 OC5#/GPIO29
W3 AC18 MCH_SYNC# M19 C2 USB_OC#6
LAN_TXD0 MCH_SYNC# <14> PCIE_PTX_IRX_P2 PERP2 OC6#/GPIO30
T7 E21 PBTN_OUT# C960 0.1U_0402_10V7K PCIE_ITX_C_PRX_N2_R K24 C3 USB_OC#7
LAN_TXD1 PWRBTN# PBTN_OUT# <20> <14> PCIE_ITX_C_PRX_N2 PETN2 OC7#/GPIO31
U4 H23 ICH_RI# C961 0.1U_0402_10V7K PCIE_ITX_C_PRX_P2_R K25
LAN_TXD2 RI# T42 <14> PCIE_ITX_C_PRX_P2 PETP2
SUS_STAT#/LPCPD# G22 <14> PCIE_PTX_IRX_N3 L23 PERN3
PCI-E
RTCX1 W4 D22 T43 L24
RTC
1
SMLINK0 F25 J16 SB_SPKR
SMLINK0 SPKR SB_SPKR <15> R1268
SMLINK1 F24 SMLINK1 33_0402_5%
SLP_S3# H20 PM_SLP_S3# <20>
R2 E25 @
SPI_MISO SLP_S4# PM_SLP_S4# <4,20>
T1 F21 PM_SLP_S5# <20> 1
2
SPI_MOSI SLP_S5#
SPI
M8 SPI_CS#
P9 B25 PM_BATT_LOW# +1.5VS C964
SPI_CLK BATLOW# H_DPRSTP# R1269 24.9_0402_1% @ 22P_0402_50V8J
R4 SPI_ARB DPRSTP# AB23 H_DPRSTP# <5>
H_DPSLP# 2
DPSLP# AA18 H_DPSLP# <5> 1 2 H24 DMI_ZCOMP
F20 J22 For EMI, Close to TigerPoint
RSVD31 DMI_IRCOMP
B
2.2K_0402_5% 1 R1273 2 ICH_SMBCLK B
2.2K_0402_5% 1 R1274 2 ICH_SMBDATA
10K_0402_5% 2 R1275 1 LINKALERT#
10K_0402_5% 2 R12791 PM_CLKRUN# +3VALW
0_0402_5%
10K_0402_5% 2 R1276 1 SMLINK0 USB_OC#3
10K_0402_5% 2 R12771 T_PWROK
T_PWROK 1 R1278 2 VGATE
VGATE <5,8,20,30> USB_OC#4
10K_0402_5% 2 R1280 1 SMLINK1 @
10K_0402_5% 2 R1282 USB_OC#5
8.2K_0402_5% R1281 PM_BATT_LOW# 1 EC_RSMRST#R
R1283 USB_OC#6
1 2 PCH_POK <5,20> USB_OC#7 R247 2
1K_0402_1% R1284 2ICH_PCIE_WAKE# 1
1 0_0402_5% 10K_0402_5%
10K_0402_5% 2 R1285 1 SYS_RST#
8.2K_0402_5% USB_OC#0 1 R249 2
R1286 ICH_RI# +3VS D53 RB751V_SOD323
10K_0402_5%
10K_0402_5% ACIN_C 2 1 ACIN
R1287 1 SMBALERT# ACIN <20,25> USB_OC#1
8.2K_0402_5%
2
R1288 GPIO12
10K_0402_5% 2 R1289
1 MCH_SYNC#
+3VALW 2 1 2 1
RSMRST circuit USB_OC#2 1 R248 2
R1292 10K_0402_5%
8.2K_0402_5% R1293 8.2K_0402_5% SLPIOVR# R1291 @
GPIO14 R1290 R1298
8.2K_0402_5% R1295 GPIO38 100K_0402_1% 0_0402_5% 0_0402_5%
8.2K_0402_5% R1294 GPIO15
8.2K_0402_5% R1296 GPIO39 1 2
8.2K_0402_5% R1299 EC_LID_OUT#
8.2K_0402_5% R1300 GPIO0 Q82
EC_RSMRST#R
C
<20> EC_RSMRST# 3 1
+RTCBATT 8.2K_0402_5% R1301 GPIO6
E
1M_0402_5% 8.2K_0402_5% @ BAV99DW-7_SOT363 @ MMBT3906_SOT23-3
R1303 PM_CLKRUN#
R1302
1 2 INTRUDER#
B
1 2 +3VALW
1 2
R1304 @ 4.7K_0402_5%
2
1 R1305 2 INTVRMEN
332K_0402_1% R1306 D54B
C965 @ 2.2K_0402_5% @
15P_0402_50V8J Routing the trace at least 10mil @ D54A
+RTCBATT 1 R1307 2 RTCRST# 2 1 RTCX1 BAV99DW-7_SOT363
1
20K_0402_5% R1308
6
A 1 2 A
J9
1 2 @ 2.2K_0402_5%
10M_0402_5%
1
3MM Y5
1
@ @
R1309
2 NC IN 1
Y8
C966 32.768KHZ_12.5PF_9H03200584~D 3 4
1U_0603_10V4Z NC OUT
Security Classification Compal Secret Data Compal Electronics, Inc.
2
1 2 32.768K_1TJS125BJ4A421P
C967 Issued Date 2010/03/18 Deciphered Date 2011/03/18 Title
15P_0402_50V8J
RTCX2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Tigerpoint(3/4)-DMI,PCIE
2 1 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Friday, May 07, 2010 Sheet 12 of 35
5 4 3 2 1
5 4 3 2 1
TGP
D U34E U34F TGP D
+5VS +3VS
F12 +V5REF_RUN A1
VCC5REF VSS01
A25
VSS02
1
VSS03 B6
R1310 D55 VSS04 B10
F5 +V5REF_SUS B16
VCC5REF_SUS VSS05
100_0402_5% RB751V-40TE17_SOD323-2 B20
+SATAPLL VSS06
VCCSATAPLL Y6 VSS07 B24
2
E18
VSS08
0.01U_0402_16V7K
+V5REF_RUN VCCRTC AE3 +RTCBATT VSS09 F16
0.1U_0402_10V6K
VSS10 G4
1 Y25 +DMIPLL G8
C968 VCCDMIPLL 1 1 VSS11
C970
H1
10mA +VCCP VSS12
C43
1U_0603_10V4Z F6 H4
VCCUSBPLL VSS13
2 H5
2 2 VSS14
K4
14mA VSS15
K8
1 VSS16
W18 0.1U_0402_10V6K K11
V_CPU_IO C971 VSS17
VSS18 K19
K20
2 VSS19
+5VALW +3VALW 1.3A VSS20 L4
0.1U_0402_25V4Z~D
VCC1_5_1 AA8 +1.5VS VSS21 M7
1U_0603_10V4Z
1U_0603_10V4Z
0.1U_0402_25V4Z~D
M9 1 M11
VCC1_5_2 VSS22
1
M20 1 1 1 1 N3
C974
C975
D56 POWER VCC1_5_3 VSS23
C972
C973
N22 C976 N12
R1311 VCC1_5_4 10U_0805_10V6K~D VSS24
N13
2 VSS25
10_0402_5% RB751V-40TE17_SOD323-2 2 N14
2 2 2 VSS26
N23
VSS27
2
+V5REF_SUS P11
VSS28
0.1U_0402_10V6K
C P13 C
1U_0603_10V4Z
0.98A VSS29
10U_0805_10V6K~D
1U_0603_10V4Z
J10 +VCCP P19
1 VCC1_05_1 VSS30
C977 VCC1_05_2 K17 VSS31 R14
P15 1 1 1 1 R22
C978
C979
C980
VCC1_05_3 VSS32
C981
0.1U_0402_10V6K VCC1_05_4 V10 VSS33 T2
2 VSS34 T22
V1
2 2 2 2 VSS35
V7
VSS36
0.29A V8
VSS37
H25 +3VS V19
0.1U_0402_10V6K
1U_0603_10V4Z
1U_0603_10V4Z
1U_0603_10V4Z
0.1U_0402_10V6K
VCC3_3_1 VSS38
AD13 V22
VCC3_3_2 VSS39
F10 V25
VCC3_3_3 VSS40
C982
C983
G10 1 1 1 1 1 W12
C984
C985
C986
VCC3_3_4 VSS41
VCC3_3_5 R10 VSS42 W22
VCC3_3_6 T9 VSS43 Y2
Y24
2 2 2 2 2 VSS44
AB4
F18
0.13A VSS45
AB6
VCCSUS3_3_1 VSS46
N4 AB7
VCCSUS3_3_2 +3VALW VSS47
1U_0603_25V6-K~D
1U_0603_25V6-K~D
VCCSUS3_3_3 K7 VSS48 AB8
VCCSUS3_3_4 F1 VSS49 AC8
1 1 1 AD2
VSS50
C988
C989
C987 AD10
VSS51
VSS52 AD20
0.1U_0402_10V6K AD24
2 2 2 VSS53
VSS54 AE1
AE10
VSS55
5 AE25
VSS56
TIGERPOINT_ES1_BGA360
B B
0.01U_0402_16V7K
4.7U_0603_6.3V6K~D
AE16
0_0805_5% 1 RSVD32
1 1
+3VALW
C990
C991
C992
2 2
2
1 TIGERPOINT_ES1_BGA360
C378
0.1U_0402_16V4Z~D
2
0_0805_5% A
0.1U_0402_25V4Z~D
1 1
C993
C994
2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Tigerpoint(4/4)-Power,GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Monday, May 10, 2010 Sheet 13 of 35
5 4 3 2 1
A B C D E
+3VS_WLAN
4.7U_0805_10V4Z~D
0.1U_0402_16V4Z~D
47P_0402_50V8J
1 1
C195
C98
C903
2 2
Layout Note:
1
Mini-Express Card for WLAN Place near JP54 1
CONN@
JP54 +1.5VS
ICH_PCIE_WAKE# 1 2 +3VS_WLAN R62 1 2 0_0805_5%
<12> ICH_PCIE_WAKE# 1 2 +3VS
3 3 4 4
BT_RADIO_OFF# @ R159 1 2 0_0402_5% 5 6
<20> BT_RADIO_OFF# 5 6 +1.5VS
0.01U_0402_25V7K~D
4.7U_0805_10V4Z~D
0.1U_0402_16V4Z~D
WLAN_CLKREQ# 7 8
<8> WLAN_CLKREQ# 7 8
SIM Interface
47P_0402_50V8J
9 9 10 10
<8> CLK_PCIE_WLAN# 11 12 1 1 1
11 12
C121
C118
C113
C904
<8> CLK_PCIE_WLAN 13 13 14 14
15 16 +UICC_PWR CONN@
15 16 R160 0_0402_5% JP73
17 18
BT_RADIO_OFF# R167 1 0_0402_5% 17 18 WL_OFF# 2 2 2
2 19 20 1 2 WL_OFF# <20> 1
19 20 PLTRST# 1
21 21 22 22 PLTRST# <4,5,12,18,20> 2 2
23 24 1 2 +3VS 3
<12> PCIE_PTX_IRX_N2 23 24 0_0402_5% +3VS 3
<12> PCIE_PTX_IRX_P2 25 26 R83 4
25 26 4
27 28 1 2 5
29
27 28
30 @R348
@ R348 0_0402_5% +3VALW UICC_CLK 6
5
29 30 6
<12> PCIE_ITX_C_PRX_N2 31 32 7
31 32 UICC_DATA 7
33 33 34 34 8 8
<12> PCIE_ITX_C_PRX_P2 USB20_WLAN_N R1166 UICC_VPP
35 35 36 36 1 2 0_0402_5% USB20_N6 <12> 9 9
37 38 USB20_WLAN_P R1167 1 2 0_0402_5% UICC_RESET 10
37 38 USB20_P6 <12> 10
+3VS_WLAN 0.1U_0402_16V4Z~D 39 40 11
39 40 GND
1 2 C222 41 42 12
41 42 GND
43 44
43 44 ACES_87036-1001-CP
45 45 46 46
47 47 48 48
EC_TX R85 1 2 0_0402_5% 49 50
<20> EC_TX EC_RX 49 50
R87 1 2 0_0402_5% 51 52
2 <20> EC_RX 51 52 2
53 54
GND1 GND2
2
R74
ACES_88910-5204
100K_0402_5%
1
+3VS_WWAN
4.7U_0805_10V4Z~D
0.1U_0402_16V4Z~D
47P_0402_50V8J
C196
C106
C905
1 1
@ @ @
2 2
Layout Note:
Mini-Express Card for WWAN Place near JP56
3 +3VS_WWAN 3
+UICC_PWR
CONN@ @ J5 +1.5VS
JP56
W=120mils
0_0402_5%1 <20> EC_SWI# R135 1 @ 2 2 +3VS_WWAN 1 2 +3VS
1 2 1 2
0.01U_0402_25V7K~D
4.7U_0805_10V4Z~D
0.1U_0402_16V4Z~D
3 4
3 4
47P_0402_50V8J
5 6 JUMP_43X39 +1.5VS
WWAN_REQ#11 5 6
<8> WWAN_REQ#11 7 8
7 8 UICC_DATA
9 10 1 1 1
9 10
C123
C120
C114
C910
<8> CLK_PCIE_WWAN# CLK_PCIE_WWAN# 11 12 UICC_CLK
CLK_PCIE_WWAN 11 12 UICC_RESET
<8> CLK_PCIE_WWAN 13 13 14 14
15 16 UICC_VPP
15 16 @ @ 2 @ 2 @ 2
17 17 18 18
19 20 3G_OFF# <20>
@ R406 0_0402_5% 19 20 PLTRST#
21 21 22 22 1 2
PCIE_PTX_IRX_N3 1 2 PCIE_C_RXN3 23 24 R14 @ 0_0402_5%
<12> PCIE_PTX_IRX_N3 23 24
<12> PCIE_PTX_IRX_P3 PCIE_PTX_IRX_P3 1 2 PCIE_C_RXP3 25 26
@ R407 0_0402_5% 25 26
27 28
27 28
29 30
PCIE_ITX_C_PRX_N3 29 30
<12> PCIE_ITX_C_PRX_N3 31 32
PCIE_ITX_C_PRX_P3 31 32
<12> PCIE_ITX_C_PRX_P3 33 34
33 34
35 35 36 36 USB20_N4 <12>
37 38 USB20_P4 <12>
37 38
+3VS_WWAN 39 39 40 40
1 2 41 42
0.1U_0402_16V4Z~D @ C224 41 42
43 44
43 44
45 45 46 46
47 48
EC_TX R114 1 @ 0_0402_5% 47 48
2 49 50
EC_RX R115 1 0_0402_5% 49 50
2 51 52
@ 51 52
53 GND1 GND2 54
4 4
ACES_88910-5204
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/BT CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Friday, May 07, 2010 Sheet 14 of 35
A B C D E
A B C D E
+VDDA +VDDA
+3VS
1
R149
1
CH751H-40PT_SOD323-2
10K_0402_5%
@ R1160
C216
1
10K_0402_5%
2
1
2 1
@ D1
R293
(output = 150 mA)
2
1
@R1170
@ R1170 1U_0603_10V4Z C213 680P_0402_50V7K~D LINE_OUTL 0_0603_5%
10K_0402_5% 2 1
2
1 R152 C833 680P_0402_50V7K~D LINE_OUTR +5VS +5VAMP +VDDA 1
1
10K_0402_5%
C220
@ R1161
L15
2
1 2 MONO_IN1 2 1 MONO_IN 10K_0402_5% @ U20 4.75V for LDO pop
R153 20K_0402_5% 1 2 60mil 1 40mil
1U_0603_10V4Z IN
5
2
OUT
1
R155 FBMA-L11-201209-221LMA30T_0805 2
C218 GND
10U_0805_10V6K~D
1U_0603_10V4Z
560_0402_5% C Q13 1 1
20K_0402_5%
1U_0603_10V4Z
<20> BEEP# 2 1 1 2 2 3 SHDN BYP 4 1
R151
C405
C406
1 B 2SC2411KT146_SOT23-3
C408
1U_0603_10V4Z E APL5151-475BC-TRL_SOT23-5 1
2
@ C226 2 2 @C407
@C407
0.1U_0402_16V4Z~D 2
2 R156 0.01U_0402_25V7K~D
C219 2
560_0402_5%
<12> SB_SPKR 2 1 1 2
1
1U_0603_10V4Z 1
D13
@ R154 CH751H-40PT_SOD323-2
10K_0402_5%
2
+5VS
HD Audio Codec 1
C377
0.1U_0402_16V4Z~D
2
FBMA-L11-160808-800LMT_0603
2 +AVDD_AC97 +VDDC 2
L23
1 2
40mil 20mil 0.1U_0402_16V4Z~D 1 2
+VDDA +3VS
10U_0805_10V6K~D C258
1 1 1 L24
C402
C170
1 1 1 FBMA-L11-160808-800LMT_0603
C210 C403
C404
2 2 2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10U_0805_10V6K~D
2 2 2
0.1U_0402_16V4Z~D
25
38
9
U23 1 2
@ C174 1000P_0402_50V7K~D
DVDD_IO
AVDD1
AVDD2
DVDD
1 2
R309 @ C385 1000P_0402_50V7K~D
0_0402_5%
14 35 1 2 C_LINE_OUTL 1 2 LINE_OUTL
LINE2_L LOUT1_L LINE_OUTL <16>
C187 0.1U_0603_25V7K
15 36 C_LINE_OUTR 1 2 LINE_OUTR
LINE2_R LOUT_R LINE_OUTR <16>
C173 0.1U_0603_25V7K
16 39
MIC2_L LOUT2_L
17 41
MIC2_R LOUT2_R
23 45
LINE1_L SPDIFO2
24 46 MIC_CLK <9>
LINE1_R DMIC_CLK1/2
18 43
LINE1_VREFO NC
20 44
3 LINE2_VREFO DMIC_CLK3/4 3
HDA_BITCLK_AUDIO <12>
19 MIC2_VREFO
6 1 2 1 2
BITCLK @ R405 10_0402_5% @ C400 10P_0402_50V8J~D
21 MIC1_L
22 8 1 2 HDA_SDIN0 <12>
MIC1_R SDATA_IN R133 39_0402_5%
MONO_IN 12 37 @ R307 1 2 0_0402_5%
PCBEEP_IN MONO_OUT C376
29 2 1 C374
CBP 2.2U_0603_6.3V6K~D
<12> HDA_RST_AUDIO# 11 RESET#
31 2.2U_0603_6.3V6K~D 2 1
CPVEE
<12> HDA_SYNC_AUDIO 10 SYNC
28
MIC1_VREFO
<12> HDA_SDOUT_AUDIO 5 SDATA_OUT
32 1 2 HP_R
HPOUT_R HP_R <16>
<9> MIC_DATA 2
GPIO0/DMIC_DATA1/2 R15
3 30
GPIO1/DMIC_DATA3/4 CBN 75_0402_1%
13
R310 SENSE A ACZ_VREF
1 2 <16> JACK_PLUG_HP 1 2 5.1K_0402_1%~D 34 27
R130 @ 0_0603_5% SENSE B VREF
EAPD R96 1 2 0_0402_5% 47 40 ACZ_JDREF
<20> EAPD EAPD JDREF
1 2
R105 @ 0_0603_5% 48 33 1 2 HP_L
SPDIFO1 HPOUT_L HP_L <16>
ACZ_VREF
1 2 4 26 R25 1 1
R103 @ 0_0603_5% DVSS1 AVSS1 75_0402_1% ACZ_JDREF
7 DVSS2 AVSS2 42
C188 @ C192
1
1 2 ALC272-GR_LQFP48 10U_0805_10V6K~D 0.1U_0402_16V4Z~D
R79 0_0603_5% 2 2
DGND AGND R92
20K_0402_1% Close to codec
4 4
1 2
2
R281 0_0603_5%
1 2
R313 0_0603_5%
GAIN0 GAIN1
0
0
0
1
6dB
10dB
APA2031A SPK Amplifier
+5VAMP
1
1
1
0
1
15.6dB
21.6dB
* 1
W=40mil
+5VAMP +5VAMP
0.1U_0402_16V4Z~D
4.7U_0805_10V4Z~D
1 1 Close to Speaker CONN for ESD.
C375 C383
2
2
+3VALW
2
@ 2 2
R713 R714 D18
1
100K_0402_1% 100K_0402_1% PJDLC05_SOT23-3
2 1
2 1
2
R715 R716 16 12
100K_0402_1% 100K_0402_1% VDD NC EC_MUTE#
6 19 EC_MUTE# <20>
1
PVDD SHUTDOWN#
15
1
PVDD SPK-
LOUT- 8
GAIN0 2
GAIN0
14
GAIN1 ROUT-
3
GAIN1 SPK+
LOUT+ 4
22P_0402_50V8J
22P_0402_50V8J
10 1 1
2 BYPASS @ @ ACES_88462-0271-20 2
20mil
1 1 APA2031RI-TRL_TSSOP20 1 Speaker Conn. C270 C268
1
R711 R712
C814 C813 C34 2 2
10K_0402_5%
10K_0402_5%
1
@
R197
0_0402_5%
2
HeadPhone JACK CONN@
JP60
3 3
<15> JACK_PLUG_HP 5 8
9
4 10
1 2 HPR 3
<15> HP_R
L50 BLM15AG121SN1D_0402
6
1 2 HPL 2
<15> HP_L
L51 BLM15AG121SN1D_0402 1
7
2
SINGA_2SJ1012-000111
1 1
@ C768 @ C769 JACK-AGND
1
10P_0402_50V8J~D 10P_0402_50V8J~D @ J7 @ J8
1
2 2
JUMP_43X39 JUMP_43X39
D45
2
1
PJDLC05_SOT23-3
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Speaker/Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Monday, May 10, 2010 Sheet 16 of 35
A B C D E
A B C D E F G H
CONN@
JP48
1 GND
SATA_ITX_C_DRX_P0 2
<11> SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0 A+
<11> SATA_ITX_C_DRX_N0 3 A-
4 GND
SATA_IRX_DTX_N0 C414 2 1 0.01U_0402_16V7K SATA_IRX_C_DTX_N0 5
<11> SATA_IRX_DTX_N0 SATA_IRX_DTX_P0 SATA_IRX_C_DTX_P0 B-
C415 2 1 0.01U_0402_16V7K 6
<11> SATA_IRX_DTX_P0 B+
7
GND
8
V33
9
V33
+3VS 10 V33
+5VS 11
GND
12 GND
13
GND
14
V5
15
V5
16 V5
1000P_0402_50V7K~D
0.1U_0402_16V4Z~D
10U_0805_10V6K~D
17 GND
1U_0603_10V4Z
18
Reserved
1 1 1 1 19 GND GND 23
C22
C19
20 24
V12 GND
C419
C410
21
V12
22 V12
2 2 2 2
OCTEK_SAT-22KH0B
2 2
+5VALW +5VALW
3 3
2
1 2 DC1 DC1 <22> 1 2 DC2 DC2 <22>
R314 820_0402_5%~D R886 R315 300_0402_5%
2
R883
1
R1104 100K_0402_5%
1
1
R1103 100K_0402_5%
3
3
1
100K_0402_5%
100K_0402_5% Q31B Q75B
2
5 5 2N7002DW-T/R7_SOT363-6
2
2N7002DW-T/R7_SOT363-6
6
6
4
4
Q31A Q75A
2 2N7002DW-T/R7_SOT363-6 2 2N7002DW-T/R7_SOT363-6
<20> PWR_LED# <20> CHARGE_LED#
1
2 1 2 1
@R90
@ R90 0_0402_5% @ R104 0_0402_5%
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SATA/LED
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Monday, May 10, 2010 Sheet 17 of 35
A B C D E F G H
A B C D E
U22
+3VS +3V_LAN
1
@
Y1 R42 R333 +3V_LAN R148 RJ45 symbol need update
LAN_X1 1 2 LAN_X2 0_0402_5% 0_0603_5%
1K_0402_1% 1 2
1 CONN@
2
1 25MHZ_20PF_7A25000012
1 ISOLATEB ENSWREG C732 JP71
C139 C127
1
470P_0402_50V7K~D
27P_0402_50V8J 27P_0402_50V8J R170 R334 2
13 Unused
2 2 0_0402_5%
15K_0402_5% 12
Yellow LED+
2
LAN_ACTIVITY# 2 1 14
R283 300_0402_5% Yellow LED-
2
1 2
C193
8 PR4-
68P_0402_50V8J~D
U21 2 7 PR4+
LAN_MDI0+ R161 1 2 0_0402_5% LAN_MDI0+_R 1 16 RJ45_MIDI0+ RJ45_MIDI1- 6
LAN_MDI0- RD+ RX+ PR2-
R231 1 2 0_0402_5% LAN_MDI0-_R 2 15 RJ45_MIDI0-
C129 1 LAN_CT0 RD- RX- RJ45_CT0
2 0.01U_0402_25V7K 3 14 1 2 5
CT CT R229 75_0402_1% PR3-
4 13
NC NC
5 NC NC 12 4 PR3+
LAN_CT1 6 11 RJ45_CT1 1 2
LAN_MDI1+ CT CT
R253 1 2 0_0402_5% LAN_MDI1+_R 7 10 RJ45_MIDI1+ R162 75_0402_1% 1 RJ45_MIDI1+ 3
LAN_MDI1- TD+ TX+ PR2+
R145 1 2 0_0402_5% LAN_MDI1-_R 8 TD- TX- 9 RJ45_MIDI1-
C184 RJ45_MIDI0- 2
1000P_1206_2KV7~D PR1-
GND 15
NS681695 2 RJ45_MIDI0+ 1
R144 PR1+
16
300_0402_5% GND
LAN_100M# 2 1 11
@ @ Orange LED-
1
U42 U43 C125 +3V_LAN 10
TCLAMP3302N.TCT_SLP2626P10-10 TCLAMP3302N.TCT_SLP2626P10-10 Green LED+
RJ45_MIDI0+ 1 10 RJ45_MIDI0- RJ45_MIDI1+ 1 10 RJ45_MIDI1- 68P_0402_50V8J~D 9
1 10 1 10 2 Green LED-
2 2 9 9 2 2 9 9
3
8 8
3
3 3 8 8 R157 SANTA_130451-A
4 7 4 7
GND
GND
4 7 4 7 300_0402_5%
5 5 6 6 5 5 6 6 LAN_10M# 2 1
1
11
11
C130
68P_0402_50V8J~D
1 2 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTL8105E-VC-GR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Monday, May 10, 2010 Sheet 18 of 35
A B C D E
3 in 1 Card Reader
CONN@
JP4
SDWP# 1
SD_DATA1 WP
2
SD_MS_DATA0 DAT1/SD8
3 DAT0/SD7
4 GND/VSS2/SD6
+SDPWR_MSPWR +VCC_4IN1 5
MSBS VSS/MS1
6
SDCLK BS/MS2
7
+VCC_4IN1 MS_DATA1 CLK/SD5
8
DATA1/MS3
100K_0402_5%
0.1U_0402_16V4Z
SD_MS_DATA0 9 DATA0/MS4
1
1 10 VCC/VDD/SD4
R1178
C535
MS_DATA2_SD_DATA7 11
DATA2/MS5
12
VSS1/SD3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
MSCD# 13
2 MS_DATA3_SD_DATA6 INS/MS6
14
2
SDCMD DATA3/MS7
1 1 1 15
CMD/SD2
C185
C536
C534
MSCLK 16
R438 SCLK/MS8
17 VCC/MS9
0_0603_5% SD_DATA3 18
2 2 2 DAT3/SD1
1 2 19
SD_DATA2 VSS/MS10
20 DAT2/SD9 GND 22
C580 SDCD# 21 23
CD GND
1 2
T-SOL_144-1300003901_NR
0.1U_0402_16V4Z~D
1
U12 @R458
@ R458 @ R461
2 1
C526 1U_0402_6.3V4Z~D 1 10_0402_5% 10_0402_5%
AV_PLL
2 1 3
2
C186 4.7U_0603_6.3V6K~D NC
7 NC
+SDPWR_MSPWR 9 2 2
+D3V3 CARD_3V3 C523
11 @ C540 @C539
@C539
D3V3
33 10 1 2
D3V3 VREG
Trace width 40 mil MS_D4 22 10P_0402_50V8J
1 1
10P_0402_50V8J
30
R495 1 NC 1U_0402_6.3V4Z~D
+3VS 2 0_0603_5% 8
RST# R454 1 3V3_IN
2 0_0402_5% 44
MODE SEL RST#
45 MODE_SEL
XTLO 47 43
XTLI XTLO XD_CLE_SP19
48 XTLI XD_CE#_SP18 42
41
R1164 USB20_CARD_N XD_ALE_SP17 SD_DATA2
<12> USB20_N7 1 2 0_0402_5% 4 40
DM SD_DAT2/XD_RE#_SP16
2
R1176 RTS5160-GR_LQFP48_7X7
R447 0_0402_5%
6.19K_0402_1%
1
1
2 1 XTLI
C511 18P 50V J NPO 0402
1
@
MODE SEL Y4 Y9
12MHZ_16P_6X12000012 12MHZ_16PF_7A12000026~D
2
1
@ 1 @
C513 R436 2 1 XTLO
47P_0402_50V8J 0_0402_5% C515 18P 50V J NPO 0402
2
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Carder RTS5160
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Monday, May 10, 2010 Sheet 19 of 35
+3VALW +EC_AVCC FBMA-L11-160808-601LMT_2P +3VALW
L26
2 1
KEYBOARD
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4.7U_0603_6.3V6K~D
1 1 1 1 1 1
C176 C166
C147
C148
C150
C145
2 2 2 2 2
0.1U_0402_16V4Z~D
2
4.7U_0603_6.3V6K~D
CONN.
ECAGND R330 2 1 CONN@
0_0402_5% JP13
KSI1 1
KSI7 1
2
2
111
125
KSI6
22
33
96
67
3
U27 3
9
KSO9 4
KSI4 4
5
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
KSI5 5
6 6
KSO0 7
R67 KSI2 7
+3VS 1 2 10K_0402_5% 8
+3VALW KSI3 8
<11> GATEA20 1 21 9
GA20/GPIO00 INVT_PWM/PWM1/GPIO0F BEEP# KSO5 9
<11> KB_RST# 1 2 2 23 BEEP# <15> 10
KBRST#/GPIO01 BEEP#/PWM2/GPIO10 KSO1 10
R66 0_0402_5%
<11> SERIRQ 3 SERIRQ# FANPWM1/GPIO12 26 Ra 11 11
2
For ESD. 4 27 ACOFF KSI0 12
<12> LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF <26> 12
LPC_AD3 5 KSO2 13
<12> LPC_AD3 LPC_AD2 LAD3 KSO4 13
<12> LPC_AD2 7 LAD2 PWM Output R122 14 14
LPC_AD1 8 63 100K_0402_5% KSO7 15
<12> LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <31> +5VS 15
LPC_AD0 KSO8
LAD0 LPC & MISC
@ R291 10 64 16
<12> LPC_AD0
1
BATT_OVP/AD1/GPIO39 KSO6 16
2 1 2 1 10_0402_5% ADP_I/AD2/GPIO3A 65 ADP_I <26> 17 17
@ C107 22P_0402_50V8J 12 AD Input 66 BRD_ID KSO3 18
<8> CLK_PCI_LPC PCICLK AD3/GPIO3B KSO12 18
<4,5,12,14,18> PLTRST# 13
PCIRST#/GPIO05 AD4/GPIO42
75 Rb 19
19
1
1 2 EC_RST# 37 76 KSO13 20
+3VALW ECRST# SELIO2#/AD5/GPIO43 20
0.1U_0402_16V4Z~D
EC_SCI# 20 KSO14 21
<12> EC_SCI# SCI#/GPIO0E 21
1
1
100K_0402_5% 70 KSO15 24
2
EN_DFAN1/DA1/GPIO3D 24
2
DA Output IREF/DA2/GPIO3E
71 IREF <26> R146 R143
1 2 EC_SMB_CK1 KSI0 55 72 4.7K_0402_5% 4.7K_0402_5%
CHGVADJ <26>
2
2
R324 4.7K_0402_5% KSI3 KSI2/GPIO32 GND1
58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE# <16> 26 GND2
+3VS KSI4 59 84
KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# <22>
KSI5 60 85 ACES_85208-24071
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C
61
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D
86
R323 1 2 EC_SMB_CK2 KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK <21>
2.2K_0402_5% KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <21>
R320 1 2 EC_SMB_DA2 KSO1 40
2.2K_0402_5% KSO2 KSO1/GPIO21
41
+3VALW KSO3 KSO2/GPIO22
42 KSO3/GPIO23 SDICS#/GPXOA00 97
KSO4 43 98 EN_WOL
KSO4/GPIO24 SDICLK/GPXOA01 EN_WOL <23>
KSO5
KSO5/GPIO25 Int. K/B
44 99
R71 47K_0402_1%~D KSO1 KSO6 SDIDO/GPXOA02 LID_SW#
45 109
KSO7 KSO6/GPIO26 Matrix SDIDI/GPXID0 LID_SW# <22>
46 KSO7/GPIO27 SPI Device Interface
R80 47K_0402_1%~D KSO2 KSO8 47
KSO9 KSO8/GPIO28 FRD#SPI_SO
R1 1 2 47K_0402_1%~D LID_SW# KSO10
48
49
KSO9/GPIO29 SPIDI/RD# 119
120 FWR#SPI_SI FRD#SPI_SO <21> For EMI
KSO11 KSO10/GPIO2A SPIDO/WR# SPI_CLK FWR#SPI_SI <21>
50
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58
126 SPI_CLK <21>
KSO12 51 128 FSEL#SPICS#
KSO12/GPIO2C SPICS# FSEL#SPICS# <21> 100P_1206_8P4C_50V8
KSO13 52
KSO14 KSO13/GPIO2D KSO14
53 4 5
KSO15 KSO14/GPIO2E SUSP_DL KSO11
54 73 SUSP_DL <23> 3 6
VGATE R301 1 KSO15/GPIO2F CIR_RX/GPIO40 KSO10
<5,8,12,30> VGATE 2 0_0402_5% 81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74 2 7
82 89 KSO15 1 8
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG <26>
for KB926C/D chip BATT_CHGI_LED#/GPIO52
90
91
CP1
EC_SMB_CK1 CAPS_LED#/GPIO53 CHARGE_LED# 100P_1206_8P4C_50V8
<31> EC_SMB_CK1 77
SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54
92 CHARGE_LED# <17>
EC_SMB_DA1 78 93 KSO6 4 5
<31> EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55
EC_SMB_CK2 79 SM Bus 95 SYSON SYSON <4,23,28> KSO3 3 6
<5> EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56
EC_SMB_DA2 80 121 KSO12 2 7
<5> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <30> EC_RSMRST# <12>
127 KSO13 1 8
AC_IN/GPIO59 ACIN <12,25>
1 2
C831 100P_0402_50V8J @ R76 @ D24 CP4
<12> PM_SLP_S3#
R120 1 2 0_0402_5% 6 100 R123 1 2 0_0402_5% 2 1 2 1 VGATE
R89 1 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 100P_1206_8P4C_50V8
<12> PM_SLP_S5# 2 0_0402_5% 14 101 EC_LID_OUT# <12>
10K_0402_5%
EC_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_ON KSO8
<12> EC_SMI# 15 EC_SMI#/GPIO08 EC_ON/GPXO05 102 EC_ON <21> 4 5
LCD_TST EC_SWI# @ D14 RB751V-40_SOD323-2 RB751V-40_SOD323-2 KSO7
<9> LCD_TST 16 103 EC_SWI# <14> 3 6
LID_SW#/GPIO0A EC_SWI#/GPXO06 PCH_POK KSO4
2 1 17 104 1 2 PCH_POK <5,12> 2 7
SUSP#/GPIO0B ICH_PWROK/GPXO06 KSO2
R1155 100K_0402_5% 18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# <9> 1 8
BT_RADIO_OFF# 19 GPIO 106 WL_OFF# 1 2 1 2 +3VS
<14> BT_RADIO_OFF# INVT_PWM EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# <14> CP2
25 107 R106 0_0402_5% @ R107 10K_0402_5%
<9> INVT_PWM EC_THERM#/GPIO11 GPXO10 3G_OFF# <14> 100P_1206_8P4C_50V8
28 108
FAN_SPEED1/FANFB1/GPIO14 GPXO11 +3VALW KSI0
29 4 5
EC_TX FANFB2/GPIO15 KSO1
<14> EC_TX 30 3 6
EC_RX EC_TX/GPIO16 KSO5
<14> EC_RX 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 PM_SLP_S4# <4,12> 2 7
2
32 112 KSI3 1 8
<21> ON/OFF# ON_OFF/GPIO18 ENBKL/GPXID2 GMCH_ENBKL <5>
34 114 R1153
<17> PWR_LED# PCI_RST# EC_PCI_RST# PWR_LED#/GPIO19 GPXID3 EAPD <15> CP3
<10> PCI_RST# 1 2 36 NUMLED#/GPIO1A GPI GPXID4 115 EC_THERM# <12>
@ R319 0_0402_5% 116 SUSP# 10K_0402_5%
GPXID5 SUSP# <23,26,28,29> 100P_1206_8P4C_50V8
117 PBTN_OUT#
PBTN_OUT# <12>
1
GPXID6 KSI2
118 LAN_WAKE# <18> 4 5
XCLKI GPXID7 KSO0
122 3 6
XCLKO XCLK1 V18R KSI5
123 124 2 7
XCLK0 V18R KSI4 1 8
AGND
R327
GND
GND
GND
GND
GND
0.1U_0402_16V4Z~D CP5
4.7U_0603_6.3V6K~D
XCLKI 1 2 XCLKO @
1 1
100P_1206_8P4C_50V8
C146
C144
20M_0603_5% @ KB926QFD3_LQFP128_14X14
11
24
35
94
113
69
KSO9 4 5
X4 KSI6 3 6
2 2
ECAGND
1 2 KSI7 2 7
KSI1 1 8
32.768KHZ_12.5PF_9H03200584~D
1 1 CP6
C160 C161
27P_0402_50V8J 27P_0402_50V8J
2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB926-E0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Friday, May 07, 2010 Sheet 20 of 35
A B C D E
1
Touch/B Connector 1
CONN@
JP20 U28 R1068
1 R1067 1 2 0_0402_5% 5 2 1 2
1 <20> FWR#SPI_SI D Q FRD#SPI_SO <20>
<20> TP_CLK 2
2 R1069
<20> TP_DATA 3 3 <20> SPI_CLK 1 2 33_0402_5% 6 C
0_0402_5%
4
4 R1070
5 GND <20> FSEL#SPICS# 1 2 0_0402_5% 1 S
3
100P_0402_50V8J
100P_0402_50V8J
1U_0402_6.3V4Z~D
1 1 2 6
GND
+3VALW 7
HOLD
C749
C750
C177
ACES_88514-0441
1 3 W
2 2 1 C179
8 VCC VSS 4
D48 0.1U_0402_16V4Z~D
PJDLC05_SOT23-3 2 S IC FL 16M EN25F16-100HIP
1
1
R305
10_0402_5%
@
2
1 1
C122 C119
22P_0402_50V8J 4.7P_0402_50VNPO
2 @ @ 2
2 2
1
R125
PUT ON TOP SIDE
100K_0402_5%
TJG-533-V-T/R_6P
2
D22
1
SW2 3 ON/OFFBTN# 1
2 ON/OFF# <20>
3 51_ON# <25>
2 4
CHN202UPT SC-70
6
5
Q18
1000P_0402_50V7K
2N7002LT1G_SOT23-3
1
3 SB770020010 3
1
1
D
C158
2 D19
<20> EC_ON
G RLZ20A_LL34
2
CONN@ S 2
2
JP42 R126
1 ON/OFFBTN#
1 10K_0402_5%
2 1
1
2 C900
ACES_88462-0271-20 0.1U_0402_25V6
2
3
2
D15
1
PJSOT24C_SOT23-3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS/TP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Monday, May 10, 2010 Sheet 21 of 35
A B C D E
A B C D E
CONN@
U7 @ PJDLC05_SOT23-3 JP16
1 8 WCM2012F2S-900T04_0805 1
GND OC1# USB_OC#0 <12> USBN0 VCC
2 7 <12> USB20_N0 2 1 2
IN OUT1 2 1 USBP0 D-
3 EN1# OUT2 6 3 D+
1 4 EN2# OC2# 5 4 GND
USB_OC#2 <12>
<12> USB20_P0 3 4
C95 TPS2062ADR_SO8~D 3 4
5 GND1
0.1U_0402_16V4Z~D L62 6
2 GND2
7 GND3
1 8
@ C77 R36 GND4
1 1
1 2 C21 ACON_UARB2-4K1926
1000P_0402_50V7K~D C363 +
2 0_0402_5%
USB_EN# 150U_B2_6.3V-M~D 2 470P_0402_50V7K~D
<20> USB_EN# 2
2 +5VALW 2
+3VALW +5VS
CONN@
JP62
2 1
LID_SW# 2 1
<20> LID_SW# 4 4 3 3
6 5
DC1 6 5
<17> DC1 8 8 7 7
10 9
R1256 2K_0402_1% SATA_LED#_N 10 9
<11> SATA_LED# 12 11
DC2 12 11
<17> DC2 14 13
14 13
16 15
16 15
ACES_85203-08421-11
+5VALW +5VS
+3VALW +3VS
CONN@
JP25
1 2 GMCH_CRT_R
3 1 2 GMCH_CRT_R <5> 3
3 3 4 4
5 6 GMCH_CRT_G
5 6 GMCH_CRT_G <5>
7 8
7 8 GMCH_CRT_B
9 9 10 10 GMCH_CRT_B <5>
11 12
USBN2 11 12 GMCH_CRT_VSYNC
13 14 GMCH_CRT_VSYNC <5>
USBP2 13 14 GMCH_CRT_HSYNC
15 16 GMCH_CRT_HSYNC <5>
15 16 GMCH_CRT_DATA
17 18
17 18 GMCH_CRT_CLK GMCH_CRT_DATA <5>
19 20
+USB_VCCC 19 20 GMCH_CRT_CLK <5>
21 21 22 22
23 23 24 24
25 26
25 26
27 27 28 28
29 30
@ D27 29 30
R75 2 31
GND1
1 2 1 32
GND2
3
0_0402_5% ACES_88242-3001
PJDLC05_SOT23-3
@L67
@ L67
<12> USB20_N2 3 4 1
3 4
1
+
2 1 C238 C18
<12> USB20_P2 2 1
WCM2012F2S-900T04_0805 150U_B2_6.3V-M~D 2 2 470P_0402_50V7K
R99
1 2
4 4
0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB PORTS/DB CN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Friday, May 07, 2010 Sheet 22 of 35
A B C D E
+5VALW TO +5VS +3VALW TO +3VS
+5VALW +5VS +3VALW +3VS
2
6 3 1 1 6 3 1 1
1 1 5 R50 1 1 5 C202 R179
C74 C76 470_0603_5% C201 470_0603_5%
10U_0805_10V6K~D 1U_0603_10V4Z @ @
4
C97 C96 2 2 C215 C214 2 2
1 1
2 2 10U_0805_10V6K~D 10U_0805_10V6K~D 2 2 10U_0805_10V6K~D 1U_0603_10V4Z
10U_0805_10V6K~D 10U_0805_10V6K~D D
1
D
2 SUSP
2 SUSP G
1 2 5VS_GATE G S Q16
B+
3
R68 S Q9 B+ 1 2 2N7002_SOT23
3
4.7K_0402_5% 1 2N7002_SOT23 @
1
D C108 @ R185 47K_0402_1%~D 1
1
SUSP D C255
2
Q8 G 0.1U_0402_25V4Z~D SUSP 2
2N7002_SOT23 S 2 Q17 G 0.1U_0402_25V7K~D
3
2N7002_SOT23 S 2
3
+3VALW to +3V_LAN
+3VALW +3V_LAN
If the +1.5V discharge
@ J4 circuit is pop, R302,
1
1 2
2 Q28 need pop.
+1.5V to +1.5VS Transfer JUMP_43X39
Q19
SI3445ADV-T1-E3_TSOP6 +5VALW
D
B+ +1.5V +1.5VS
S
6
4 5
2
U41 2 1
1
8 1 1 1 C164 @ R302
D S
2
47K_0402_1%~D
R134 100K_0402_5%
G
7 D S 2
R559
3
D S 0.1U_0402_16V7K 2
5 4 1 1
1
C727 D G C728 C697 2
R189 C239
2
SI4800DY_SO8 10U_0805_10V6K~D
1
1
1.8VS_GATE D Q4
1
0.47U_0603_25V4
1 2 2N7002_SOT23
<20> EN_WOL
2
G @Q28
@ Q28
OUT
C696
R608 S DTC124EKAT146_SC59-3
3
1M_0402_5%
1
D 2 SYSON
<4,20,28> SYSON 2
IN
2
GND
1
SUSP 1 2
3
2
2
@ R298 R297
SUSP_DL# 1 2 100K_0402_5% 100K_0402_5%
1
R666 SUSP
<29> SUSP
0_0402_5%
1
Q27
OUT
DTC124EKAT146_SC59-3
<20,26,28,29> SUSP# 2
IN
GND
+RTCVREF
+1.5VS +VCCP +0.75VS +1.5V +5VALW
3
2
2
R18 R280 R61 R279 @ R299 R303
470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 100K_0402_5% 100K_0402_5%
@ @ @ @
1
1
SUSP_DL#
<29> SUSP_DL#
1
D D D D
1
2 SUSP 2 SUSP 2 SUSP 2 SYSON#
G G G G Q30
OUT
S Q2 S Q24 S Q7 S Q23 DTC124EKAT146_SC59-3
3
GND
3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/03/18 Deciphered Date 2011/03/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC INTERFACE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Friday, May 07, 2010 Sheet 23 of 35
A B C D
1 1
H4 H32
H H
@ @
1
H35 H39 H16 H15 H24 H29 H30 H31 H38 H42
H H H H H H H H H H
@ @ @ @ @ @ @ @ @ @
1
2 H41 H33 H34 H36
AGND 2
H H H H
@ @ @ @
1
H7 H37 H40
H H H
@ @ @
1
3 3
@ @ @ @ FIDUCIAL_C40M80
1
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Screw
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Tuesday, April 27, 2010 Sheet 24 of 35
A B C D
5 4 3 2 1
Vin Detector
VIN
High 17.944 17.706 17.470
PL1
Low 16.242 16.027 15.808
D D
JP53 SMB3025500YA_2P
4 APDIN 1 2
4
3 3
2 2
1 1
G1 5
G2 6
1
PC3
@ ACES_85204-04001 PC1 PC2 100P_0402_50V8J PC5 PR2
1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K 1M_0402_1%
2
1 2
VIN
VS
VIN
0.01U_0402_25V7K
10K_0805_5%
84.5K_0402_1%
1
1
PC6
PR4
PR3
PR5
10K_0402_1%
2
1 2
ACIN <12,20>
2
PR6
8
22K_0402_1%
1 2 3
P
+ PACIN
0.068U_0603_25V7M
1
O PACIN <26>
22K_0402_1%
2 -
G
1
VIN
10K_0402_1%
PU1A
0.1U_0402_16V7K
1
1
PR7
LM393DG_SO8 PD1
4
PC7
PC8
PR8
2
2
2
GLZ4.3B_LL34-2
2
C PD2 PR9 C
2
LL4148_LL34-2 10K_0402_1%
2 1
PD3
+RTCVREF 3.3V
1
LL4148_LL34-2
BATT+ 2 1
1
PR10 PR11
PQ1 68_1206_5% 68_1206_5%
TP0610K-T1-E3_SOT23-3
PR12 2
2
200_0603_5%
CHGRTCP 1 2 N1 3 1
VS
0.22U_0603_25V7K
1
1
PC9
PR13 PC10
100K_0402_1% 0.1U_0603_25V7K PJ1 PJ2
+3VALWP 2 1 +3VALW +1.8VSP 2 1 +1.8VS
1
PR14 2 1 2 1
2
PJ3 PJ4
+5VALWP 2 2 1 1 +5VALW +0.75VSP 2 2 1 1 +0.75VS
+RTCVREF
1
@ JUMP_43X118 @ JUMP_43X79
APL5156-33DI-TRL_SOT89-3 PR15
200_0603_5%
B PR16 PU2 B
0_0402_5% 3.3V
2
1 2 3 2 N2 PJ12 PJ6
VOUT VIN
+CHGRTC +0.89VSP 2 2 1 1 +0.89VS +1.5VP 2 2 1 1 +1.5V
1
PJ7
+VCCPP 2 2 1 1 +VCCP
@ JUMP_43X118
PD16 JP79
+CHGRTC 2 1
CH751H-40PT_SOD323-2 PR17
PD4 1K_0402_1%
+RTCBATT 1 2 2 1 1 + - 2
CH751H-40PT_SOD323-2
@
SUYIN_060003FA002G201NL~D
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN/DECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 07, 2010 Sheet 25 of 35
5 4 3 2 1
5 4 3 2 1
P3
B+ PQ30
P2 AO4435_SO8
1 8
PQ29 2 7
PD17 AO4435_SO8 PL5 3 6
B340A_SMA2 FBMA-L11-201209-121LMA50T_0805 CHG_B+ 5
PR162 0.05_1206_1%
VIN 2 1 1
2
8
7 1 4 1 2
4
0.1U_0603_25V7K
3 6
5 2 3 2009-08-17 modify
1
D D
2200P_0402_50V7K
4
PC14
0.1U_0603_25V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PQ31
2
47K_0402_5%
1
2
200K_0402_1%
0.1U_0603_25V7K
DTA144EUA_SC70-3
PC161
1
PR163
PC159
PC160
CSIN
3
PC162
PR164
PC13
CSIP
1
PR165
47K_0402_1%
2
2
2 1 2
2
VIN
1
2
PD18
PR166 3 ACOFF
1
PD19 10K_0402_1% 1
1 2 6251VDD 2
2.2U_0603_6.3V6K
2 PR167
1 1
PC163
PQ32 CH751H-40PT_SOD323-2
PR168 BAS40CW_SOT323-3200K_0402_1%
1
10K_0402_1% 1 2 VIN
DTC115EUA_SC70-3 FSTCHG 2 1 PU16 PC165
0.1U_0603_25V7K
3
2
1 2 1 24 6251DCIN 2 1 PQ33
VDD DCIN
100K_0402_1%
PC164 DTC115EUA_SC70-3 2
PQ34 0.1U_0402_16V7K
1
D 2N7002KW_SOT323-3
150K_0402_1%
PR169
2 ACSET ACPRN 23
PR170
2 PR171
0.1U_0603_25V7K
G 20_0402_5%
3
5
1
6251_EN CSON D
S 3 22 1 2
3
EN CSON
1
PC167
PC166 PQ35 2 PACIN
2
3
C CELLS CSOP PR172 PQ36 C
PC168 6800P_0402_25V7K 20_0402_5% 4 2N7002KW_SOT323-3
PR174 PQ37 1 2 5 20 2 1
ICOMP CSIN
1
2
3K_0402_1% D 2N7002KW_SOT323-3 PR173
PACIN 1 2 2 PC169 PR175 6.81K_0402_1% PC170 20_0402_5%
<25> PACIN
G 1 2 1 2 6 19 0.1U_0402_16V7K
1 2 PL15
3
2
1
VCOMP CSIP PR176 10UH_FMJ-0630T-100 HF_3A_20%
S
3
5
<20> ADP_I 100_0402_1% 2 3
4.7_1206_5%
6251_VREF 8 17 DH_CHG PQ39
VREF UGATE
1
PR179
PQ38 PR180 1 2 PR181 PC173 AON7408L 1N DFN
10U_1206_25V6M
10U_1206_25V6M
DTC115EUA_SC70-3 32.4K_0402_1% PC172 2.2_0402_5% 0.1U_0603_25V7K
2 1 0.1U_0402_16V7K 9 16 BST_CHG 1 2 BST_CHGA 2 1
<20> IREF CHLIM BOOT
1
PR182 PD20 4
1
PC174
PC175
0.01U_0402_25V7K
ACOFF 2 60.4K_0402_1%
<20> ACOFF
6251_VREF 1 2 10 15 6251VDDP
ACLIM VDDP
1
680P_0603_50V7K
CH751H-40PT_SOD323-2
2
1
PC177
PR183 1 2 6251VDD
3
2
1
1
PC178
100K_0402_1% 11 14 DL_CHG
3
2
VADJ LGATE
1
PR185 PR184
2
31.6K_0402_1% 4.7_0402_5%
2
12 13 PC179
2
GND PGND 4.7U_0805_6.3V6K
2
ISL6251AHAZ-T_QSOP24
PR186
Connect to EC A/D Pin. 15.4K_0402_1%
Iada=0~1.58A(30W) CP = 85%*Iada ; CP = 1.34A <20> CHGVADJ
1 2
B B
CP mode
1
Vaclim=2.39*(31.6K/(31.6K+60.4K))=0.8209V PR187
Iinput=(1/0.05)((0.05*Vaclm)/2.39+0.05) 33.2K_0402_1%
PQ40 TP0610K-T1-E3_SOT23-3
3 1 6251DCIN
P3
1
100K_0402_1%
PR191
PR193
2
2 1
100K_0402_1%
A A
1
PQ41 PD21
DTC115EUA_SC70-3 2 FSTCHG
FSTCHG <20>
2 1
3 SUSP#
SUSP# <20,23,28,29>
BAS40CW_SOT323-3 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/03/18 Deciphered Date 2011/03/18 Title
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 07, 2010 Sheet 26 of 35
5 4 3 2 1
A B C D
ISL6237_B+
ISL6237_B+
1
B+ 1
PL4
FBMA-L11-201209-121LMA50T_0805 PR49
0_0402_5%
1 2 1 2
2200P_0402_50V7K
2200P_0402_50V7K
10U_1206_25V6M
0.1U_0402_25V6
0.1U_0402_25V6
10U_1206_25V6M
PC141
VL
5
PC140
PC47
PC45
1
PC50
PC48
2
1U_0603_10V6K
<BOM Structure>
2
2
PC51 PQ12
4.7U_0805_6.3V6K
PQ11 0.1U_0603_25V7K AON7408L 1N DFN 4
1
PC52
4 AON7408L 1N DFN
PC53
1
+5VALWP
2
PL11
3
2
1
PL12 4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
1
2
3
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
7
PC54 1 2
1 2 1U_0603_10V6K
LDO
VIN
VCC
+3VALWP 33 19 1 2
TP PVCC
1
1
5
DH3 26 15 DH5
PR50 UGATE2 UGATE1 PR51
0_0402_5%
1 PR52 PR53
2
2
@ 61.9K_0402_1%
PR54
2.2_0603_5% 2.2_0603_5% 4
2
PC24 + 4 PC56
150U_B2_6.3VM_R35M
150U_B2_6.3VM_R35M 0.1U_0603_25V7K
1
1
PR55
2 LX3 25 16 LX5 1 2
1
3
2
1
PC67
680P_0603_50V7K 0.1U_0603_25V7K 680P_0603_50V7K +
2
1
2
3
2
PQ24 DL3 23 18 DL5
1
LGATE2 LGATE1 PQ26
IRFH3707TRPBF
2
10K_0402_1%
IRFH3707TRPBF
2
22
PGND
2
PR56
FB3 30
OUT2
0_0402_5%
PR57
10
OUT1
32
VL
1
@ REFIN2
1
11 FB5
2VREF_TPS51427 FB1
1 2 2VREF_TPS51427 1 REF
+3VALWP PC70
Imax=3.8A 0.22U_0603_25V7K
BYP
9
8
Ipeak=5.07A LDOREFIN PR58 @ 0_0402_5%
PD7 29 2 1
Iocp(minimum)=6.59A SKIP VL
1 2 +5VALWP
CH751H-40PT_SOD323-2 Imax=3.15A
20 28
PR61 NC POK2 PR60 @ 0_0402_5% Ipeak=4.201A
PD8 100K_0402_1% 1 2
VS
1 2 1 2 4 13 Iocp(minimum)=5.46A
EN_LDO POK1
2
200K_0402_1%
GLZ5.1B_LL34-2
2
PR72
PC68 14 12 ILM1 2 1
0.22U_0603_25V7K EN1 ILIM1 PR70
3 3
196K_0402_1%
1
27 31 ILIM2 2 1
GND
TON
1
1 2 PU6
5
21
VL TPS51427_QFN32_5X5
806K_0603_1%
CH751H-40PT_SOD323-2
2
PR143
PR144
0_0402_5%
2VREF_TPS514271
1U_0603_10V6K
PR68
1
PC66
@ 47K_0402_5%
PR67
1
2 1 1 2
2
<31> MAINPWON
0.047U_0402_16V7K
0_0402_5% PR69
@ 0.047U_0402_16V7K
0_0402_5%
1
2
PC65
PC69
2
2VREF_TPS51427
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VALW/5VALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 07, 2010 Sheet 27 of 35
A B C D
5 4 3 2 1
PJP1
2 2 1 1 B+
+1.8VP_B++
@ JUMP_43X79
10U_1206_25V6M
2200P_0402_50V7K
1000P_0402_50V7K
10P_0402_50V8J
0.1U_0402_25V6
<BOM Structure>
0.1U_0402_25V6
1 2
1
PL18
PC158
@ FBMA-L11-201209-121LMA50T_0805
PC193
2
2
PC139
PC78
PC142
PC157
D D
2
PR96
267K_0402_1%
1 2
5
PR92
0_0402_5% PC82 PQ16
2 1 EN_1.8 BST_1.8 2 1 1 2 AON7408L 1N DFN
+1.5VP
<4,20,23> SYSON
PR77 Imax=5.7A
1
PC93 2.2_0603_5% 0.1U_0603_25V7K
@ .1U_0402_16V7K 4 Ipeak=7.6A
Iocp(minimum)=9.88A
15
14
1
PU7 PL7
3
2
1
2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
EN/DEM
BOOT
NC
TON_1.8 2 13 UG_1.8 1 2
TON UGATE +1.5VP
LX_1.8
4.7U_0805_6.3V6K
PR85 3 12
VOUT PHASE
2
10_0603_5% PR90 1
1 2 V5FILT_1.8 4 11 TRIP_1.81 2 PR95
+5VALW VDD CS
1
PR93 13K_0402_1% 4.7_1206_5% +
0_0402_5% FB_1.8 5 10 V5DRV_1.8 1 2 +5VALW PC79
FB VDDP
1
PC95
PC97 PR94 220U_B2_2.5VM_R15M
2
2 1 6 9 LG_1.8 0_0603_5% 4 2
<4> PM_1.5V_PWRGD PGOOD LGATE
1
PGND
1U_0603_10V6K
GND
2
1
PC108
1
@ .1U_0402_16V7K PC96
2
3
2
1
2
C C
<BOM Structure> 4.7U_0805_10V6K
2
PR62
100K_0402_1%
+1.5VP 1 2 PQ17
IRFH3707TRPBF
2 1
PR78
22.1K_0402_1%
1
PR79 PJP2
22.1K_0402_1% 2 1 B+
2 1
VCCPP_B++
@ JUMP_43X79
2
2200P_0402_50V7K
10U_1206_25V6M
0.1U_0402_25V6
1
1
PC143
PC81
PC144
2
2
PR80
267K_0402_1%
2009-11-03 modify 1 2
5
PR81
47K_0402_5% PR82 PC85 PQ18
1 2 EN_VCCP BST_VCCP1 2 1 2 AON7408L 1N DFN
B <20,23,26,29> SUSP# B
0_0603_5% 0.1U_0603_25V7K
1
PC80 4
.1U_0402_16V7K
PL13
2
15
14
1
PU10
3
2
1
2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
EN/DEM
BOOT
NC
TON_VCCP 2 13 UG_VCCP 1 2
TON UGATE +VCCPP
PR84 3 12 LX_VCCP
VOUT PHASE
2
10_0603_5% PR91 1
V5FILT_VCCP TRIP_VCCP
4.7U_0805_6.3V6K
+5VALW 1 2 4 11 1 2 PR87 PC94
VDD CS
1
12.1K_0402_1% 4.7_1206_5% + PC92
FB_VCCP 5 10 V5DRV_VCCP 2 1 220U_B2_2.5VM_R15M
FB VDDP +5VALW
1
PR86
2
PC87 6 9 LG_VCCP 0_0603_5% 4 2
PGOOD LGATE
PGND
1U_0603_10V6K
GND
2
1
PQ19
1
IRFH3707TRPBF PC88
RT8209BGQW_WQFN14_3P5X3P5 PC86 680P_0603_50V7K
7
3
2
1
2
<BOM Structure> 4.7U_0805_10V6K
2
+VCCP
Imax=2.8A
2 1 Ipeak=3.56A
PR88 Iocp(minimum)=4.628A
8.66K_0402_1%
1
A A
PR89
21.5K_0402_1%
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5V/VCCP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 07, 2010 Sheet 28 of 35
5 4 3 2 1
5 4 3 2 1
D D
PL8
4
@ PJP3 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
2 2 1 10 2 LX_0.89V 1 2
+5VALW
PG
1 PVIN LX +0.89VSP
2
JUMP_43X79 9 3
PVIN LX PR99
1
1 2 PC63 PC76 8 4.7_1206_5%
+0.89VP
10U_0805_10V6K SVIN
@ PL17 10U_0805_10V6K 6 Imax=1.6A
2 1
FB
22U_0805_6.3VAM
22U_0805_6.3VAM
FBMA-L11-201209-121LMA50T_0805 5
EN Ipeak=1.98A
1
NC
NC
TP
PC73
PC74
PC72
680P_0603_50V7K Iocp(minimum)=4A
11
2
1 2 EN_1.8V
<20,23,26,28> SUSP#
0.1U_0402_10V7K
PR105 1 2
PC75
0_0402_5%
1
PR104 PR100
1
1M_0402_5% PU5 10K_0402_1%
SY8033BDBC_DFN10_3X3 2 1
2
PR103
1
20.5K_0402_1% PC71
68P_0402_50V8J
2
@
C C
+1.5V
1
@ PJ11
1
1
PU12 @ PJ9
2
1 6 JUMP_43X39
1
VIN VCNTL +3VALW
2 5
GND NC
1
2
PC136
1
4.7U_0805_6.3V6K 3 7 PC133
2
VREF NC
1U_0603_10V6K
PR148 1U_0603_10V6K
2
PC98
1K_0402_1% 4 8
VOUT NC
2
9 PC130
2
TP 10U_0603_6.3V6M
2
B APL5336 PU9 B
6 VCNTL
1
220P_0402_50V8K
1 2 2 1K_0402_1% PC138 10K_0402_1%
<23> SUSP
1
PC129
G 0.1U_0402_16V7K SUSP# 1 2 8
2
EN
1
10U_0603_6.3V6M
S PQ27 PC132 7 2 PR145
GND
3
POK FB
1
@PC134
@ PC134 2N7002KW_SOT323-3 10U_0603_6.3V6M 3.9K_0402_1%
2
2
1
PC99
0.1U_0402_16V7K
2
2
PC128 APL5930KAI-TRG_SO8
2
SUSP_DL# 1 2 0.47U_0402_6.3V6K
<23> SUSP_DL#
1
@
PR101 PR97
10K_0402_1% 3.09K_0402_1%
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8VS/0.9VS/0.89VS/1.2VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 10, 2010 Sheet 29 of 35
5 4 3 2 1
A B C D
1 1
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<20>
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
VR_ON
+3VS
1
+5VS
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
PR194
4.7K_0402_1% +CPU_B+ PL9
2
FBMA-L11-201209-121LMA50T_0805
2
PR195
1 2 B+
4700P_0402_25V7K
2200P_0402_50V7K
4.7U_0805_25V6M
4.7U_0805_25V6M
4.7U_0805_25V6M
<5,8,12,20> VGATE 2 1 3211_PWRGD PR200
0.1U_0402_25V6
10_0603_5%
1
0_0402_5%
1
PC100
PC101
PC104
PC102
32 3211_EN1
PC145
PC146
2
2
PR196
PR197
PR198
PR199
PR201
PR202
PR203
PR204
31 VID0
30 VID1
29 VID2
28 VID3
27 VID4
26 VID5
25 VID6
1
3211_VCC
5
PC182
+3VS 1U_0805_25V6K PQ13
2
AON7408L 1N DFN
VID0
VID1
VID2
VID3
VID4
VID5
VID6
EN
1
PR205 24 PR206 PC183 4
10K_0402_1% VCC 2.2_0603_5% 0.22U_0603_25V7K
1
PWRGD
BST 23 CPU_BOOST
1 2 CPU_BOOST-1
1 2
1
2
2
IMON
2
22 3211_DRVH PL14 2
3
2
1
PC184 <8> CLK_ENABLE# CLK_ENABLE# DRVH 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
3
2
CLKEN#
1000P_0402_50V7K 21 3211_SW 1 2
4
SW +CPU_CORE
FBRTN
1
20 +5VS
PVCC
5
1 2 3211_FB 5 PU15
FB
PC185 ADP3211A 19 3211_DRVL 2 1 PR115
DRVL
1
2
PC187 PGND
7
OCP=7.852A
2
GPU
1 2 1 2 3211_COMP-1
1 2 47P_0402_50V8J 17 4
AGND
1
PR208 PC188 PR207 3211_ILIM
8 VID:0.75V~1.1V
CSCOMP
1K_0402_1% 470P_0402_50V8J 28K_0402_1% ILIM PQ28
33
CSREF
AGND Io(max)=6.04A
RAMP
LLINE
CSFB
IRFH3707TRPBF PC109
IREF
RPM
2
680P_0603_50V7K
RT
3
2
1
2
PR209
9
10
11
12
13
14
15
16
2.49K_0402_1%
2 200K_0402_1%
2 274K_0402_1%
2 80.6K_0402_1%
1
3211_IREF
3211_RPM
3211_RT
3211_RAMP
3211_CSCOMP
3211_CSFB
3211_CSCOMP
3211_CSCOMP
1 PH42
2 1
PR210 1
PR211 1
PR212 1
499K_0402_1%
PR213
1
3 35.7K_0402_1% 3
1
1
PC190 PR217
2
2
PR214
1000P_0402_50V7K
2
2 1
PR218
+CPU_B+ 2 1 3211_RAMP-1
PR219 309K_0402_1%
1K_0402_1%
<6>
<6>
VSSSENSE
VCCSENSE
PC191 PC192
2
1000P_0402_50V7K 1000P_0402_50V7K 2 1
PR220
0_0603_5%
Shortest the
net trace
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 07, 2010 Sheet 30 of 35
A B C D
5 4 3 2 1
D D
1
4 PR153 1 2 1K_0402_1%
4
2
5 PC124 PC125
C 5 EC_SMDA 1000P_0402_50V7K 0.01U_0402_25V7K PR133 C
6
2
6
1
7 EC_SMCA 47K_0402_1%
7 PH3 PR134
10 8 MAINPWON <27>
GND 8 47K_0402_1%
11 9
1
GND 9 100K_0402_1%_TSM0B104F4251RZ1 2
SUYIN_200045GB009G13MZR
2
PR135
8
13.7K_0402_1%
1
D
1 2 5
P
+ PQ22
7 2
TM_REF1 O G 2N7002KW_SOT323-3
1 2 +3VALW 6 -
G
PR141 PU1B S
3
6.49K_0402_1% LM393DG_SO8
4
1000P_0402_50V7K
16.9K_0402_1%
1
0.22U_0603_25V7K
1 2 BATT_TEMP <20>
1
PR138
PR142 1K_0402_1% 2 1 VL
PC126
PC127
1 2 PR139
EC_SMB_DA1 <20>
1
PR136 100_0402_1% 100K_0402_1%
2
1 2 PR140
EC_SMB_CK1 <20>
PR137 100_0402_1% 100K_0402_1%
<BOM Structure>
2
3
2
PJSOT24C_SOT23-3
PJSOT24C_SOT23-3
PD10
PD11
@
@ A/D
1
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 07, 2010 Sheet 31 of 35
5 4 3 2 1
A B C D E
Item Reason for change Rev. PG# Modify List Date Phase
1 Reserve bead to prevent noise issue happen P27, P28 Reserve PL16, PL17, PL18 2009.07.24 PT
4
Adjust the +1.5VSP LDO feedback P28 Change PC129 to 220P 25V K NPO 0402 2009.08.05 PT
2 5 2
For reduce trace space. P30 Change JBATT1 pin3 & pin5 from +3VALWP to +3VALW. 2009.09.17 ST
9
3 3
10
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 27, 2010 Sheet 32 of 35
A B C D E
A B C D E
01 2009/12/08 Flea chip on board 0.1 P.15 Add U42,U43 and U44
1 1
05 2009/12/09 BCM BT + WLAN combo 0.1 P.14 Remove jp22, C185, C186,R2,R116
06 2009/12/09 for thermal solution 0.1 P.14 Add U3, C10, C427,R2,JP14,D6,D9,C420,C418,R307,C417
07 2009/12/28 for standard pin define for PCIE MINI Card 0.1 P.14 Connect JP56 pin 6, 28, 48 to +1.5VS, reserve C123,C120,C114,C910.
08 2010/01/06 for DDRIII SODIMM design 0.1 P.4 U31 pin AL28,AJ26 pull high to +1.5V;Add C1102,C256;Connect U31 pin AB4 to PU7 pin 6.
09 2010/01/07 for Intel CRB schematic Rev.0.5 0.1 P.6 Change C928,C929,C930,C931 from 2.2uF to 1uF;Add C273 22uF;Change C379 from 0.1uF to 1uF.
2 2
10 2010/01/14 for ICS Low Power CLK Gen. Co-lay circuit 0.1 P.8 U11 pin62 pull high to +1.5VS / +1.05VS.
P.9
11 2010/01/14 for touch screen function 0.1 P.12 Connect JP24 pin 34,36 from USB20_P6/N6 to USB20_P5/N5;Pop R1168 and R1169.
12 2010/01/14 for +1.5VS transfer circuit 0.1 P.23 Connect U41 pin 5,6,7,8 to +1.5V;pin 1,2 to +1.5VS
P.8,12,
13 2010/01/14 Change crystal package size 0.1 19,20 Co-lay Y8 and Y5,change Y1,Y6,Y4 to small size package.
14 2010/01/19 for Intel checklist Rev. 2.0 0.1 P.6 Reserve C401,C409 close to U31.AA19,de-pop C925
15 2010/01/19 for Intel CRB DRAM POWEROK circuit 0.1 P.4 Add U45,R158,R142,R294,R93,R136,R1188,C78,C178
16 2010/01/21 for POWER concern to Delete BATT_OVP circuit 0.1 P.20 Disconnect U27.64
17 2010/01/27 for WLAN+BT module card design 0.1 P.14 Add R159,R160 close to JP54 pin5 and pin20.
3 3
18 2010/01/28 for EC team concern 0.1 P.14 Add R74 close to JP54 pin49.
19 2010/01/29 for Broadcom check request 0.1 P.15 Connect U42 pin D11 directly to GND.
20 2010/01/29 for Broadcom check request 0.1 P.15 Add test points on U42 pin M8 and M9.
21 2010/01/29 for Broadcom check request 0.1 P.15 Change L68,L69 to TDK MMZ2012R601AT.
22 2010/01/29 for Broadcom check request 0.1 P.15 Change C1082 and C1083 from 15pF to 18pF;change Y7 from 7M27100019 to 7M27070004.
23 2010/02/04 for power sequence 0.1 P.04 Connect U45 pin5 to SYSON.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Hardware-PIR1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Tuesday, April 27, 2010 Sheet 33 of 35
A B C D E
A B C D E
26 2010/03/12 Change LAN IC 0.1 P.19 Change U22 from RTL8103EL-VB-GR to RTL8105E-VB-GR.
1 1
27 2010/03/16 For vender Realtek request 0.1 P.20 Change R1153 from 100K to 10K.
28 2010/03/18 Change +3V_LAN rising time > 1ms 0.1 P.23 Add C239,C165,C164,Q19,Q4,R134,R189 and de-pop J4
29 2010/03/22 Change KB926 GPIO definition 0.1 P.20 Change BT_RADIO_OFF# from pin108 to pin17
30 2010/03/22 Add card reader IC RTS5160-GR to MB 0.1 P.20 Add U12 card reader IC RTS5160-GR
Change U22 Pin 12,6,9,41 to NC;connect Pin 3,6 to together after via one 0.01uF cap.
31 2010/03/23 For vender Realtek request 0.1 P.19 to GND;change C139, C127 to 27P.
32 2010/03/24 For EC team request 0.1 P.21 Pin38 net PM_CLKRUN# BOM @ 0ohm
33 2010/03/24 For EC team request 0.1 P.12 PCH pin AC19 net PM_CLKRUN# pull low 10K ohm
34 2010/03/25 Changer FLEA card DDR3 to DDR2 for cost 0.1 P.15 Change from K4B1G1646E-HCF8 to W9751G6IB-25
2 2
35 2010/03/26 Changer USB connector 0.1 P.23 Change JP16 from SUYIN_020133MR004S536ZR to ACON_UARB2-4K1926
36 2010/03/29 Broadcom request pull up GPIO_06 to 3V_BCM 0.1 P.15 Change U43 GPIO_06 pull up to +3V_BCM
36 2010/03/30 For speaker change from 2 to 1 0.1 P.17 Change JP55 from 4 pins to 2 pins
37 2010/04/15 For BOM error 0.2 P.19 Add C535 for BOM error
38 2010/04/15 For BOM error 0.2 P.23 Add R189,Q4 for BOM error
39 2010/04/15 For EC team request add 100K pull low 0.2 P.25 Add R128 pull low for EC
40 2010/04/15 For wake on LAN control net name error 0.2 P.20 Change KB926 pin98 net name from EN_WOL# to EN_WOL
41 2010/04/15 Change LAN RTL8105 to SWR mode 0.2 P.18 BOM @ L72,C149,C411,R296,C157,C431
3 3
42 2010/04/15 Change LAN ENSWREQ pin to pull Low 0.2 P.18 Delete R333 and Mount R334
43 2010/04/15 Change BOM from SD02800008L to SD028000080 0.2 P.20 Change R127,R284,R286,R287,R288 CPN
44 2010/04/16 Change BOM from SE070104Z80 to SE070104Z8L 0.2 P.19 Change C185,C534,C536 CPN
45 2010/04/16 Change BOM from SE074102K8L to SE074102K80 0.2 P.17 Change C419 CPN
46 2010/04/16 Change BOM from SE076104K80 to SE076104K8L 0.2 P.17 Change C132,C138,C165,C239 CPN
47 2010/04/16 Add net BT_RADIO_OFF# for JP54 pin19 0.2 P.14 Add R167 0 ohm for net BT_RADIO_OFF#
48 2010/04/21 Change MB ID to R02 0.2 P.20 Change R122 to 100K ohm and R127 to 8.2K ohm
50 2010/04/21 Change BOM parts 0.2 P.10 Change U34 from SA000039N2L to SA000039N3L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Hardware-PIR-II
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Monday, May 10, 2010 Sheet 34 of 35
A B C D E
5 4 3 2 1
D 51 2010/04/21 Change BOM parts 0.2 P.23 Change Q4,Q8,Q17 from SB570020110 to SB000008J00 D
52 2010/04/21 Change BOM parts 0.2 P.21 Change D19 from SC45248B010 to SC400001100
53 2010/04/21 Change BOM parts 0.2 P.07 Change C1117,C1124 from SE049225Z8L to SE107225K8L
54 2010/04/21 Change LAN chip from ver.B to ver.C 0.2 P.18 Change U22 from SA00003PO10 to SA00003PO20
56 2010/04/27 Delete touch panel function 0.2 P.12 Delete USB port5 nets
58 2010/04/27 Delete USB port function 0.2 P.12 Delete USB port1 nets
C 59 2010/04/27 Change camera voltage from +5VALW to +3VS 0.2 P.09 Change R35 pin1 to +3VS C
60 2010/04/29 Change BOM for EOL parts 0.2 P.23 Change Q2,Q7,Q9,Q16,Q23,Q24 from SB570020110 to SB000009080 or SB000008J00
61 2010/04/29 Change BOM for EOL parts 0.2 P.12 Change X4 from SJ100005L0L to SJ10000B500
62 2010/04/29 Change BOM for EOL parts 0.2 P.21 Change U28 from SA00002TO00 to SA00002KI00
63 2010/05/06 Delete U14 for just two USB ports 0.2 P.22 Delete U14 and +USB_RIGHT,+USB_LEFT change to +USB_VCCC
65 2010/05/06 Change amplifier gain from 10dB to 15.6dB 0.2 P.16 BOM @ R714,R715 and mount R713,R716
66 2010/05/06 Add ESD solution for EMI 0.2 P.18 Add U42,U43 to RJ45 connector
B 67 B
68
69
70
71
72
73
74
A 75 A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Hardware-PIR-II
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6501P
Date: Friday, May 07, 2010 Sheet 35 of 35
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