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Abstract --- The growing market of mobile, battery standby mode. The header switch is implemented by PMOS
powered electronic systems (e.g., cellular phones, to control Vdd supply. PMOS transistor is less leaky than
personal digital assistants, etc.) demands the design of NMOS transistor of the same size. The disadvantage of the
microelectronic circuits with low power dissipation. As header switch is that PMOS has lower drive current than
density and complexity of the chips continue to increase, NMOS of a same size. As a result, a header switch
the difficulty in providing power dissipation might limit implementation usually consumes more area than a footer
the functionality of the computing systems. Especially, at switch implementation. The footer switch is implemented by
nanometer level the power dissipation consumes about NMOS transistor to control VSS supply. The advantage of
35% of the chip power. The purpose of this project is to footer switch is the high drive and hence smaller area.
analyse the performance of one of the most trustful However, NMOS is leakier than PMOS and sleep transistor
approaches to low power design called as "Power become more sensitive to ground noise. An example for the
Gating". The focus is only on CMOS devices in sleep transistor and Distributed sleep transistor network are
nanometer scale, as this technology is being the most given in the figures 1 and 2 respectively.
widely adopted in current VLSI systems. In this project,
we compare the performance of various power gating
designs using 65nm technology. In a power gating . .J........... V/JJ)
'i;
.... _ ... .
i Low VII,
; I
structure, a transistor with high threshold voltage (Vth) is i
placed in series with a low Vth device. The high Vth ! logiC !
transistor is called as the Sleep Transistor. In the power : de\'ice !
gating structure, a circuit operates in two different ;mol S"""d (vGN: H;,h V,," 'p (ran istor
modes. In the active mode, the sleep transistors are
turned ON and can be treated as the functional
redundant resistances. In the sleep mode, the sleep
transistors are turned OFF to reduce the leakage power.
When a sleep transistor is placed at VDD, it is called as Figure 1: A Power Gating Structure.
the "Header switch" and while it is placed near the
ground, it is called as "Footer switch". In this project, I
;._. . _J_... .. .... :
- r 1 1 r ... ..l. D
V,h
. . .. --._._ .'.'.'-'.'
:
have taken the footer switch exclusively for all my
_._._._ _._._ ...
r IQgfr;
designs. I
! l log,c r
i i del/ices !
---!
de'P;ces dew'ces
I. INTRODUCTION
Figure 2: A DSTN Structure.
Optimum sleep transistor design and
implementation are critical to a successful power-gating
design. There are special considerations for the sleep While implementing sleep transistors in CMOS
transistor design. Few of them are sleep transistor gate circuits, the perfonnance is found to be better when they are
length, width and body bias optimization for area, leakage interconnected to form a network. There is much such
and efficiency. In the power gating, sleep transistors are architecture out of which most notable structure is the
used as switches to shut off power to parts of a design in distributed sleep transistor network (DSTN).In a distributed
sleep transistor network gates in a cluster are connected to
II. CONVENTIONAL CMOS 4-BIT BCD ADDER Figure4: Schematic of 4 bit BCD adder.
The term BCD stands for binary coded decimal. It III. POWER GATED 4-BIT BCD ADDER DESIGN
is another method used to represent decimal numbers in
digital circuits. Since all the digital circuits need to display A. 4-BIT BCD Adder Power Gated With DSTN
the results in digital form, this circuit is inevitable in any
digital circuit. In BCD, many types of codes are used for In a distributed sleep transistor network, gates in a
conversion; but the 8 - 4 - 2 - lis the most common code. cluster are connected to the sleep transistor by virtual
8 - 4 - 2 - 1 code indicates the weight of each bit ground wires. The spot at which sleep transistor is connected
3 2 1 to logic gates is called tapping point. By adding more wires
in the following order: 2 - 2 - 2 - 2 .
For example, consider the decimal number: 9342. to form a mesh containing all virtual-ground wires, we
This value can be converted to binary form using 8-4-2-1 obtain the DSTN structure.
BCD as follows: While designing the DSTN for the BCD adder, two
9342 = 1001 0011 0100 0010 sleep transistors are placed for each fulladder circuit. One
9 3 4 2 for the sum circuit and another for the carry circuit. The
To implement a 4-bit BCD adder we need two 4-bit sleep transistor in each full adder form a single cluster. The
full adders, one to add two 4-bit BCD numbers and the other sleep transistors present in each cluster are connected
full adder to add 2's complement of the results greater than 9 through a single line which is called as the "Virtual
to the result if carry is generated. Also we need 2 AND gates Ground". The virtual ground line is excited by means of an
and one OR gate to generate carry signal. external sleep signal. The schematic for the BCD adder
designed with DSTN power gating structure is given in the
figure .
...
; --l 4 BI T ADDER
....-
__ --.:=.
c COUT +-
L-_S-",_S-". __
S !.
1 _...- S..-'c....J CN1
o o
4 BIT ADDER
+-0
_ .. U U - - -
'I LJ .
,n
'I [ T[]l
scale. The sleep transistors used are designed to have a . :U!-l==
'I :. I uIFo""'Lr T I
,.
. ==
higher WIL ratio than the ones used in the BCD adder. ,.
' LlIT] 1 0 1 I -rn u - -
I
uu un t.D K 4f.O ).C te., 010 lllC . ICO) liOJ MQ ia:_O
'I
'.bl ==' .
_ ... ._ . . . :
. . ..:
I' !-
'I I
'f ........... . .. .... . ......... .... ............
IV SIMULATION RESULTS
A. Power Analysis
s. Conventiona BCD
N Time I adder BCD adder
0 (ns) BCD adder (DSTN) (Clk gated)
B. Delay Analysis
7 6.1 0.001647 0.0001688 0.0000323
8 6.2 0.001342 0.0001653 0.000074 The delay analysis is preformed to calculate the
delay arising across the circuits designed above. This
9 6.3 0.0012 0.000164 0.00000755 allows us to determine the time interval for exciting the
sleep transistors. The results of delay analysis are listed
lO 6.4 0.00996 0.0001516 0.00000232
below.
11 6.5 0.OlOO12 0.0001624 0.00000128
12 19.2 0.00992 0.0001545 0.00000118
SNo Circuit Delay Power Delay
(in ps) Prod uct(,....)
Tablel: Power consumed conventional BCD adder,
BCD adder with DSTN and BCD adder with clock gated 1 Conventional 82.50 11.846
power gating. BCD adder
---
0.7 - Table 2: Comparison of Delay and Power delay product
Of conventional BCD adder, BCD Adder with
0.6 +-Jf.I------
Clock gated power gating.
05
-+-conventional BCD v CONCLUSION
g::I. 04 adder
OJ +-----\1-- .... BCD adder with DST N Sleep transistor is designed at 65nm scale and
Q. implemented in power gating designs. The power gating
0.2 +----tf----
___ BCD adder with clock designs discussed in this project are DSTN and Clock
gated power gating
0.1 +-----1Itt--- gating. The sleep transistors in each cluster is connected by
means of daisy chain implementation which provides
1 2 3 4 5 6 7 8 9 10 11 12
enough time for the results to propagate from one cluster to
Time(io os) the other, thus synchronizing the circuit operation with
triggering of sleep transistors. Clock gating method is
introduced in power gating design, which provides
Fig 12: Power Consumed by conventional 4- bit BCD additional control over the excitation process of sleep
Adder, BCD adder with DSTN & Clock gated 4- transistors.
Bit BCD adder.
Finally, the performances of the DSTN and Clock
0.16 ,-----
Gating are compared in terms of power consumption of the
circuit and surge current. It is found from the results that the
0.14
power gating design is more efficient than the DSTN circuits
0.12 designed at 65nm scale.
0.1
REFERENCES
0.08