FPGA Implementation of BIST Technique for UART Design

CHAPTER 1

INTRODUCTION

1.1 INTRODUCTION:

To study, design and implement BIST Technique for Universal Asynchronous

Receiver and Transmitter. Built-in Self Test, or BIST, is the technique of designing additional

hardware and software features into integrated circuits to allow them to perform self-testing,

i.e., testing of their own operation (functionally, parametrically, or both) using their own

circuits, thereby reducing dependence on an external automated test equipment (ATE). BIST

is a Design-for-Testability (DFT) technique, because it makes the electrical testing of a chip

easier, faster, more efficient, and less costly. The concept of BIST is applicable to just about

any kind of circuit, so its implementation can vary as widely as the product diversity.

Serial communication is an essential to computers and allows them to communicate

with low speed peripheral devices, such as keyboard, the mouse, modems etc. Universal

Asynchronous Receiver and Transmitter is most important component required in serial

communication. UART is an integrated circuit used for conversion of serial data to parallel

and vice versa. A BIST UART has the objectives of firstly to satisfy testability requirements

and secondly to generate the lowest-cost with highest performance implementation. In this

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project, we study, design and implement a UART and BIST environment for that UART using

VHDL.

1.2 BIST (Built In Self Test):

A built-in self test (BIST) circuit using a linear feedback shift register (LFSR) and a multiple

input signature register (MISR) requiring reduced circuitry exclusive of the number of inputs

and outputs of the circuit to be tested.

The BIST circuit is built in a prescribed circuit having a memory to test a target circuit

in the prescribed circuit. The BIST circuit includes an LFSR, including a first logic section

which is composed of a plurality of XOR gates and selection sections, and a first memory

which is a part of the memory, for performing a primitive polynomial, an MISR, including a

second logic section which is composed of a plurality of XOR gates and selection sections,

and a second memory which is a part of the memory, for performing the primitive polynomial,

and a BIST control section for controlling data input/output between the first and second

memories and the target circuit and providing selection signals for controlling the selection

sections in the first and second logic sections, the BIST control section controlling the target

circuit and comparing operation results of the target circuit to perform the test of the target

circuit.

In order to reduce the amount of hardware required to compress a multiple bit stream, a

multiple input signature analysis register can be used. The theory presented in the literature

shows that the functionality in terms of aliasing probability is unchanged for this

implementation.

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1.3 UART (Universal asynchronous receiver/transmitter):

Block Diagram:

A universal asynchronous receiver/transmitter (usually abbreviated UART and pronounced) is

a type of "asynchronous receiver/transmitter", a piece of computer hardware that translates

data between parallel and serial forms.

The Universal Asynchronous Receiver/Transmitter (UART) controller is the key component

of the serial communications subsystem of a computer. The UART takes bytes of data and

transmits the individual bits in a sequential fashion. At the destination, a second UART re-

assembles the bits into complete bytes.

When transmitting, the UART takes 8 bits of parallel data and converts the data to a serial bit

stream that consists of a start bit (logic 0), 8 data bits (least significant bit first), and one or

more stop bits (logic 1).

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 CHAPTER 2

DESIGN OF UART with BIST

2.1 BIST (Built in Self Test):

BIST Adding logic to the circuitry, so that it tests itself.

Figure 2.1

BIST is often used for testing memories. More specifically, this we call it as MBIST scheme;

it is more suitable because of its regular structures (memory).

The regular structure of a memory chip makes it easy to generate test patterns.

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A built-in self-test (BIST) or built-in test (BIT) is a mechanism that permits a machine to

test itself. Engineers design BISTs to meet requirements such as:

high reliability

lower repair cycle times

2.2 UART (Universal Asynchronous Receiver and Transmitter):

A universal asynchronous receiver/transmitter (usually abbreviated UART and

pronounced) is a type of "asynchronous receiver/transmitter", a piece of computer hardware

that translates data between parallel and serial forms.

A UART is usually an individual (or part of an) integrated circuit used for serial

communications over a computer or peripheral device serial port. UARTs are now commonly

included in microcontrollers. A dual UART or DUART combines two UARTs into a single

chip. Many modern ICs now come with a UART that can also communicate synchronously;

these devices are called USARTs (universal synchronous/asynchronous receiver/transmitter).

The above fig is standard format for serial transmission. Since no clock (clk) line, data D is

transmitted asynchronously, one byte at a time.

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 Figure 2.2 structure of UART

When no data is transmitted, D remains high.

To mark start bit, a low bit is transmitted (D will goes low).

Now, 8 bits will be transmitted, least significant bit will be first.

When text is being transmitted, ASCII code is usually used. In ASCII code each

character is represented by 7 bits and the 8th bit is the parity bit. After 8 bits are transmitted; D

should go high at least once; representing a character is transmitted.

Then, another character can be transmitted at any time.

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When transmitting, the UART takes 8 bits of parallel data and converts the data to a serial bit

stream that consists of a start bit (logic 0), 8 data bits (least significant bit first), and one or

more stop bits (logic 1).

The Universal Asynchronous Receiver/Transmitter (UART) controller is the key

component of the serial communications subsystem of a computer. The UART takes bytes of

data and transmits the individual bits in a sequential fashion. At the destination, a second

UART re-assembles the bits into complete bytes. Serial transmission is commonly used with

modems and for non-networked communication between computers, terminals and other

devices.

Asynchronous transmission allows data to be transmitted without the sender having to

send a clock signal to the receiver. Instead, the sender and receiver must agree on timing

parameters in advance and special bits are added to each word which is used to synchronize

the sending and receiving units.

An asynchronous transmitting, teletype-style UARTs send a "start" bit, five to eight

data bits, least-significant-bit first, an optional "parity" bit, and then one, one and a half, or

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two "stop" bits. The start bit is the opposite polarity of the data-line's idle state. The stop bit is

the data-line's idle state, and provides a delay before the next character can start. (This is

called asynchronous start-stop transmission). In mechanical teletypes, the "stop" bit was often

stretched to two bit times to give the mechanism more time to finish printing a character. A

stretched "stop" bit also helps resynchronization.

Asynchronous transmission allows data to be transmitted without the sender having to

send a clock signal to the receiver. Instead, the sender and receiver must agree on timing

parameters in advance and special bits are added to each word which is used to synchronize

the sending and receiving units.

2.3 Design of UART:

The structure of UART is as shown in figure 3.4, consists of Transmitter part and

Receiver part, rather we can say consists of 3 units, transmitter circuit, receiver circuit and

Control/Status Registers.

Figure 2.3. Structure of UART Block

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2.3.1 Design of UART Transmitter

The Block diagram of UART Transmitter is as shown in figure 3.5. The data is loaded

from Data Bus into TBR (Transmit Buffer Register) and from TBR to TSR (Transmit Shift

Register), based on the control and status signals produced by the Control unit. The Size of

TSR is taken in such a way that, it should accommodate the START and STOP bits along with

the Data bits which are loaded from the Data Bus.

Figure 2.4. UART Transmitter Unit

The Data loaded into TSR has the format of START-DATA-STOP bits which is as

shown in figure of which, every time one bit will be sent, with reference to baud clock.

Correspondingly, the data in TSR will keeps updating with 0s; will be completely filled with

0s, after transmission of the complete data packet.

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2.3.2 Design of UART Receiver

The Block diagram of UART Receiver is as shown in figure 3.6. The data receiving

will be captured using receiving baud clock and then loaded into RSR (Receive Shift

Register) and from RSR to RBR (Receive Buffer Register), and then to Data Bus, based on

the control and status signals produced by the Control unit. The Size of RSR is taken in such a

way that, it should accommodate the START and STOP bits along with the Data bits which

are loaded from the Data Bus.

Figure 2.5. UART Receiver

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2.3.3 SERIAL DATA FORMAT

The start bit is always a 0 (logic low), which is also called a space. The start bit

signals the receiving DTE that a character code is coming. The next five to eight bits,

depending on the code set employed, represent the character. In the ASCII code set the eighth

data bit may be a parity bit. The next one or two bits are always in the mark (logic high, i.e.,

'1') condition and called the stop bit(s). They provide a "rest" interval for the receiving DTE

so that it may prepare for the next character which may be after the stop bit(s). The rest

interval was required by mechanical Teletypes which used a motor driven camshaft to decode

each character. At the end of each character the motor needed time to strike the character bail

(print the character) and reset the camshaft.

All operations of the UART hardware are controlled by a clock signal which runs at a

multiple (say, 16) of the data rate - each data bit is as long as 16 clock pulses. The receiver

tests the state of the incoming signal on each clock pulse, looking for the beginning of the

start bit. If the apparent start bit lasts at least one-half of the bit time, it is valid and signals the

start of a new character. If not, the spurious pulse is ignored. After waiting a further bit time,

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the state of the line is again sampled and the resulting level clocked into a shift register. After

the required number of bit periods for the character length (5 to 8 bits, typically) have elapsed,

the contents of the shift register is made available (in parallel fashion) to the receiving system.

The UART will set a flag indicating new data is available, and may also generate a processor

interrupt to request that the host processor transfers the received data. In some common types

of UART, a small first-in, first-out (FIFO) buffer memory is inserted between the receiver

shift register and the host system interface. This allows the host processor more time to handle

an interrupt from the UART and prevents loss of received data at high rates.

Transmission operation is simpler since it is under the control of the transmitting

system. As soon as data is deposited in the shift register, the UART hardware generates a start

bit, shifts the required number of data bits out to the line, generates and appends the parity bit

(if used), and appends the stop bits. Since transmission of a single character may take a long

time relative to CPU speeds, the UART will maintain a flag showing busy status so that the

host system does not deposit a new character for transmission until the previous one has been

completed; this may also be done with an interrupt. Since full-duplex operation requires

characters to be sent and received at the same time, practical UARTs use two different shift

registers for transmitted characters and received characters.

Transmitting and receiving UARTs must be set for the same bit speed, character

length, parity, and stop bits for proper operation. The receiving UART may detect some

mismatched settings and set a "framing error" flag bit for the host system; in exceptional cases

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the receiving UART will produce an erratic stream of mutilated characters and transfer them

to the host system.

Typical serial ports used with personal computers connected to modems use eight data

bits, no parity, and one stop bit; for this configuration the number of ASCII character per

seconds equals the bit rate divided by 10.

2.3.4 Special Receiver Conditions

Overrun Error:

An "overrun error" occurs when the UART receiver cannot process the character that

just came in before the next one arrives. Various UART devices have differing amounts of

buffer space to hold received characters. The CPU must service the UART in order to remove

characters from the input buffer. If the CPU does not service the UART quickly enough and

the buffer becomes full, an Overrun Error will occur.

Under run Error:

An "underrun error" occurs when the UART transmitter has completed sending a

character and the transmit buffer is empty. In asynchronous modes this is treated as an

indication that no data remains to be transmitted, rather than an error, since additional stop

bits can be appended. This error indication is commonly found in USARTs, since an under run

is more serious in synchronous systems.

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Framing Error:

A "framing error" occurs when the designated "start" and "stop" bits are not valid. As

the "start" bit is used to identify the beginning of an incoming character, it acts as a reference

for the remaining bits. If the data line is not in the expected idle state when the "stop" bit is

expected, a Framing Error will occur.

Parity Error:

A "parity error" occurs when the number of "active" bits does not agree with the

specified parity configuration of the UART, producing a Parity Error. Because the "parity" bit

is optional, this error will not occur if parity has been disabled. Parity error is set when the

parity of an incoming data character does not match the expected value.

Baud rate:

In embedded designs, it is necessary to choose a proper oscillator to get the correct

baud rate with little or no error. Some examples of common crystal frequencies and baud rates

with no errors are:

2.4 SHIFT REGISTER:

One of the two main parts of an LFSR is the shift register (the other being the

feedback function). A shift register is a device whose identifying function is to shift its

contents into adjacent positions within the register or, in the case of the position on the end,

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out of the register. The position on the other end is left empty unless some new content is

shifted into the register.

The contents of a shift register are usually thought of as being binary, that is, ones and

zeroes. If a shift register contains the bit pattern 1101, a shift (to the right in this case) would

result in the contents being 0110; another shift yields 0011. After two more shifts, things tend

to get boring since the shift register will never contain anything other than zeroes.

Two uses for a shift register are

1) Convert between parallel and serial data.

2) Delay a serial bit stream.
The conversion function can go either way -- fill the shift register positions all

at once (parallel) and then shift them out (serial) or shift the contents into the register bit

by bit (serial) and then read the contents after the register is full (parallel). The delay

function simply shifts the bits from one end of the shift register to the other, providing a

delay equal to the length of the shift register.

2.4.1 Serial-in, parallel-out (SIPO)

This configuration allows conversion from serial to parallel format. Data is input

serially, as described in the SISO section above. Once the data has been input, it may be either

read off at each output simultaneously, or it can be shifted out and replaced.

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 Figure 2.6 4-Bit SIPO Shift Register

2.5 LFSR (Linear feedback shift register):

A linear feedback shift register (LFSR) is a shift register whose input bit is a linear

function of its previous state. The only linear function of single bits is xor, thus it is a shift

register whose input bit is driven by the exclusive-or (xor) of some bits of the overall shift

register value.

The initial value of the LFSR is called the seed, and because the operation of the

register is deterministic, the stream of values produced by the register is completely

determined by its current (or previous) state. Likewise, because the register has a finite

number of possible states, it must eventually enter a repeating cycle. However, an LFSR with

a well-chosen feedback function can produce a sequence of bits which appears random and

which has a very long cycle.

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Pseudorandom Pattern Generation:

Linear feedback shift registers make extremely good pseudorandom pattern

generators. When the outputs of the flip-flops are loaded with a seed value (anything except

all 0s, which would cause the LFSR to produce all 0 patterns) and when the LFSR is clocked,

it will generate a pseudorandom pattern of 1s and 0s. Note that the only signal necessary to

generate the test patterns is the clock.

LFSRs are often used for generating test patterns.

Figure 2.7 LFSR

This will generate different test patterns except 0000 pattern. To include this 0000 pattern

also; the LFSR is modified as below.

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 Figure 2.8 modified LFSR

The LFSR is a shift register that has some of its outputs together in exclusive-OR

configurations to form a feedback path. LFSRs are frequently used as pseudorandom pattern

generators to generate a random number of 1s and 0s. Each output of the LFSR is multiplexed

with an ASIC input and, when the device is placed in the LFSR (test) mode, the random, high-

toggle-rate Patterns produced are extremely good for generating high-fault coverage. To

minimize the number of results that needs to be compared to expected results, a MISR is used.

The MISR compresses multiple parallel patterns into a single pattern signature that is

compared to the expected value. If the signatures match, it is assumed that the ASIC passed

the test vectors applied and there are no manufacturing defects.

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2.6 MISR (Multiple-input Signature Register):

Figure 2.9 MISR

The test data Z1Z2Z3Z4 is XORed into the register with each clock, and the final result

represents a signature that can be compared with a signature for a known correctly

functioning component. For the above MISR, assume that the correct input sequence is 1010,

0001, 1110, 1111, 0100, 1011, 1001, 1000, 0101, 0110, 0011, 1101, 0111, 0010, 1100. This

sequence maps the signature to 1010; any sequence differ by 1 bit maps to some other

signature (take example 0001 to 1001, the resulting sequence maps to 1000).

To adapt scan test scheme for Sequential circuits; the scan register is modified so each

part of the register can serve as a state register, pattern generator, signature register and shift

register. When used as shift register, the test data can be scanned in and out in the usual way.

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Then part of scan register can be used as a PRPG and part as MISR to test one of the

combinational blocks. (The roles can be interchanged to test another combinational block).

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 A built-in self test (BIST) circuit using a linear feedback shift register (LFSR)

and a multiple input signature register (MISR) requiring reduced circuitry exclusive of the

number of inputs and outputs of the circuit to be tested.

The BIST circuit is built in a prescribed circuit having a memory to test a

target circuit in the prescribed circuit. The BIST circuit includes an LFSR, including a first

logic section which is composed of a plurality of XOR gates and selection sections, and a

first memory which is a part of the memory, for performing a primitive polynomial, an

MISR, including a second logic section which is composed of a plurality of XOR gates

and selection sections, and a second memory which is a part of the memory, for

performing the primitive polynomial, and a BIST control section for controlling data

input/output between the first and second memories and the target circuit and providing

selection signals for controlling the selection sections in the first and second logic

sections, the BIST control section controlling the target circuit and comparing operation

results of the target circuit to perform the test of the target circuit.

In order to reduce the amount of hardware required to compress a multiple bit

stream, a multiple input signature analysis register can be used. The theory presented in

the literature shows that the functionality in terms of aliasing probability is unchanged for

this implementation.

For testable design purposes, a multiple-output digital system needs a multiple-

input signature register. This register accelerates the testing task by compressing multiple-

input data streams into one signature. Existing designs depend on parallel feeding the

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 input polynomials to the storage elements. These designs give a good compression but,

suffer from some drawbacks. The paper proposes a new design for the multiple-input

signature register. This proposed design aggregates all inputs at a certain point and feeds

them to the shift register. By adopting this concept, we are able to improve the operation

of the multiple-input signature register in a number of ways. Complete VHDL modeling

and simulation for the existing and the proposed designs verified the advantages of the

new structure

2.7 BILBO (Built-in Logic Block Observer):

This is a bank of circuit flip-flops with added testing hardware, which can be

configured to make the flip-flops behave like a scan chain, a linear feedback shift register

(LFSR) pattern generator, an LFSR-based response compacter, or merely as D flip-flops.

The pseudorandom test patterns and multiple-input signature registers stimulated the

development of a multifunctional subsystem called Built-In Logic Block Observer (BILB0),

which can be used for data transfer and fault detection purposes in complex digital circuits.

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Each BILBO is composed of a flip flop register row and some additional gates for shift and

feedback operations .Four different functional modes can be selected by setting two control

inputs, B1 and B2.

In the first mode (B1=1, B2=0), BILBO acts as a latch. The input data zl, z2, z3,..z7

are simultaneously clocked into the flip flops and can be read from the Q and Q outputs.

In the second mode (B1=0, B2=0), BILBO works as a shift register. Data are serially

clocked into the register through the serial input Sin pin, while the register contents can be

simultaneously read at the parallel Q and Q pin outputs data, or can be clocked out through

the serial output Sout pin. The shift register feature of BILBO may be utilized both in the

normal mode and in a test mode.

In the third mode (B1=1, B2=1) BILBO is functionally converted into a multiple-input

signature register. In this mode BILBO may be used for performing parallel signature analysis

or for issuing pseudorandom sequences.

The remaining fourth mode (B1=0, B2=1) forces Linear feedback shift register.

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 Figure 2.10 BILBO

As all practical systems are sequential circuits (Combo + sequential/FFs), we can

use the same BILBO as MISR and PRPG for testing the combinational part of the system. For

testing the sequential part, we can use the same BILBO can be used as shift register, to scan

out the data from the flip-flops in the logic. In normal modes, it acts as normal registers of

flip-flops.

2.8 Architecture of the Project:

The following fig. illustrates how to apply BILBO registers to test the UART design.

In this structure, BILBO I and BILBO II may be configured by B1, B2 signal to act as

either a shift register, a test pattern generator (PRPG), normal application mode function

(normal) or a data compressor (MISR). The test starts with the initialization of the BILBO by

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applying a seed to its serial-in (Sin) pin. The initialization can be obtained by configuring

BILBOs operating mode B1B2 to 00 (shift register mode). Following the initialization,

the bilbo_mode (B1B2) is set to 01 so that BILBO is configured as LFSR (bilbo_mode

= 01) and BILBO II as MISR (bilbo_mode = 11 (Note: XOR force 01 to 11)).

BILBO I (LFSR) produces an 8-bits pseudo random pattern data in parallel. The

parallel data is then fed to the UARTs transmitter. The UART converts the pseudo random

parallel data to serial data which is then looped back to its receiver to create an internal

diagnostic capability. The UARTs receiver converts the serial data back to parallel and will

be accepted by Register B (MISR). A signature will be produced after 127 clock iterations

(7 data bits produce 27-1 = 127 (exception, in generating all zeros) PRPG) and this completes

the test. The signature is scanned out from serial output (so) pin by configuring

bilbo_mode to 00. Following the scan, it is compared with the correct signature achieved

from the simulation of the entire self-test sequence approach in a tester. If the signature

produced by MISR is similar to the correct signature, it can be concluded that the UART is

working properl

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Figure 2.11 Architecture of the Project

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 CHAPTER 3

VLSI TESTING PROCESS AND TEST EQUIPMENT

3.1 INTRODUCTION:

1) The test should be designed to truly indicate the desired Perfection,

2) The repeat loop in our algorithm will repeat indefinitely, unless

redesign and remake could respond to or correct the errors found in testing.

Understanding the art and science of testing allows you to attain perfection in your

work, otherwise an almost superhuman task.

VLSI chip testing is done in several different places by several different types of

people. When a new chip is designed and fabricated for the first time, testing should verify

correctness of design and the test procedure. This often requires the involvement of the design

engineer and the testing may even take place in the design laboratory rather than in a factory.

Based on the result, both the design and the test procedure may be changed. This is called

verification testing. Successful verification testing usually results in some good chips. These

are the earliest chips and are normally used by the designers of systems that will use this

design. A successful verification also signals the beginning of production. Production means

large scale manufacturing. Fabricated chips are tested in the factory. This is called

manufacturing testing. Finally, when the manufactured chips are received by a customer, they

may be again tested to ensure quality. This testing, known as incoming inspection (or

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acceptance testing), is conducted either by the user or for the user by some independent

testing house.

3.2 Types of Testing

VLSI testing can be classified into four types depending upon the requirements.

1. Characterization

It is known as design debug or verification testing, this form of testing is performed on

a new design before it is sent to production. The purpose is to verify that the design is correct

and the device will meet all specifications. Functional tests are run and comprehensive AC

and DC measurements are made. Probing of internal nodes of the chip, commonly not done in

production testing, may also be required during characterization. Use of specialized tools such

as scanning electron microscopes (SEM) and electron beam testers, and techniques such as

artificial intelligence (AI) and expert systems, can be effective. A characterization test

determines the exact limits of device operating values. We generally test for the worst case

because it is easier to evaluate than average cases and devices passing this test will work for

any other conditions.

2. Production

Every fabricated chip is subjected to production tests, which are less comprehensive

than characterization tests yet they must enforce the quality requirements by determining

whether the device meets specifications. The vectors may not cover all possible functions and

data patterns but must have a high coverage of modeled faults. The main driver is cost, since

every device must be tested. Test time must be absolutely minimized. Fault diagnosis is not

attempted and only a go/no-go decision is made. Production tests are typically short but verify

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all relevant specifications of the device. It is an outgoing inspection test of each device, and is

not repetitive. We test whether some device-under-test (DUT) parameters are consistent with

the device specifications under normal operating conditions.

3. Burn-in

All devices that pass production tests are not identical. When put to actual use, some

will fail very quickly while others will function for a long time. Burn-in ensures reliability of

tested devices by testing, either continuously or periodically, over a long period of time, and

by causing the bad devices to actually fail.

4.Incoming Inspection

System manufacturers perform incoming inspection on the purchased devices before

integrating them into the system. Depending upon the context, this testing can be either

similar to production testing, or more comprehensive than production testing, or even tuned to

the specific systems application. Also, the incoming inspection may be done for a random

sample with the sample size depending on the device quality and the system requirement. The

most important purpose of this testing is to avoid placing a defective device in a system

assembly where the cost of diagnosis may far exceed the cost of incoming inspection

3.3 Test Specifications and Test Plan:

The device specification document initiates the development activity, and contains the

following information:

Functional Characteristics Algorithms to be implemented, I/O signal characteristics

(timing waveforms, signal levels, etc.), data and control signal behavior, clock rate.

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 Type of Device Logic, microprocessor, memory, analog, etc.

Physical Characteristics Package, pin assignments, etc.

Technology CMOS (or gate array), custom, standard cell, etc.

Environmental Characteristics Operating temperature range, supply voltage, humidity, etc.

Reliability Acceptance quality level (defective parts per million), failure rate per 1,000

hours, noise characteristics, etc.

Test specifications, if not given explicitly, are derived from the above data. Based on

these specifications, a test plan is generated. In the test plan the type of test equipment and the

type of tests are specified. Selection of a tester depends on such parameters as throughput,

clock rate, timing accuracy, test sequence length, tester availability, and cost. The types of test

may include parametric, functional, burn-in, margin, speed sorting, etc. The fault coverage

requirement should also be specified.

3.4 TEST GENERATION METHODS:

Automatic test pattern generation, ATPG generates pattern-data to systematically

exercise as many logic-gates, and other components, as possible.

Built-in self-test, or BIST installs self-contained test-controllers to automatically

test a logic (or memory) structure in the design

3.4.1 Automatic Test Pattern Generation:

ATPG (acronym for both Automatic Test Pattern Generation and Automatic Test

Pattern Generator) is an electronic design automation method/technology used to find an

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input (or test) sequence that, when applied to a digital circuit, enables testers to distinguish

between the correct circuit behavior and the faulty circuit behavior caused by defects. The

generated patterns are used to test semiconductor devices after manufacture, and in some

cases to assist with determining the cause of failure. The effectiveness of ATPG is measured

by the amount of modeled defects, or fault models, that are detected and the number of

generated patterns. These metrics generally indicate test quality (higher with more fault

detections) and test application time (higher with more patterns). ATPG efficiency is another

important consideration. It is influenced by the fault model under consideration, the type of

circuit under test (full scan, synchronous sequential, or asynchronous sequential), the level of

abstraction used to represent the circuit under test (gate, register-transistor, switch), and the

required test quality.

Algorithmic methods

Testing very-large-scale integrated circuits with high fault coverage is a difficult task

because of complexity. Therefore many different ATPG methods have been developed to

address combinatorial and sequential circuits.

Early test generation algorithms such as Boolean difference and literal proposition were

not practical to implement on a computer.

The D Algorithm was the first practical test generation algorithm in terms of memory

requirements. The D Algorithm introduced D Notation which continues to be used in

most ATPG algorithms.

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 Path-Oriented Decision Making (PODEM) is an improvement over the D Algorithm.

PODEM was created in 1981 when shortcomings in D Algorithm became evident when

design innovations resulted in circuits that D Algorithm could not realize.

Fan-Out Oriented (FAN Algorithm) is an improvement over PODEM. It limits the

ATPG search space to reduce computation time and accelerates backtracking.

Methods based on Boolean satisfiability are sometimes used to generate test vectors.

Pseudorandom test generation is the simplest method of creating tests. It uses a

pseudorandom number generator to generate test vectors, and relies on logic

simulation to compute good machine results, and fault simulation to calculate the fault

coverage of the generated vector

3.4.2 Built-in self-test

A built-in self-test (BIST) or built-in test (BIT) is a mechanism that permits a machine

to test itself. Engineers design BISTs to meet requirements such as:

4. high reliability

5. lower repair cycle times

constraints such as:

limited technician accessibility

cost of testing during manufacture

32
 BIST is commonplace in weapons, avionics, medical devices, automotive electronics,

complex machinery of all types, unattended machinery of all types, and integrated circuits.

Programmable Built-In Self-Test (pBIST)

Memory Built-In Self-Test (mBIST) - e.g. with the Marinescu algorithm

Logic Built-In Self-Test (LBIST)

Analog and Mixed-Signal Built-In Self-Test (AMBIST)

Continous Built-In-Self-Test (CBIST)

Periodic Built-In-Self-Test (PBIST) or Programmable Built-In-Self-Test (PBIT)

Interrupt (driven) Built-In-Self-Test (IBIST) or (user) Initiated Built-In-Self-Test

Power-up Built-In-Self-Test (PupBIST)

Automatic Built-In-Self-Test (ABIST)

33
 CHAPTER 4

FPGA IMPLEMENTATION

4.1 FPGA Design Flow:

The ISE design flow comprises the following steps: design entry, design synthesis,

design implementation, and Xilinx device programming. Design verification, which

includes both functional verification and timing verification, takes places at different points

during the design flow.

34
 Figure 4.1 FPGA Design Flow

4.1.1 Design Entry:

Create an ISE project as follows:

1. Create a project.

2. Create files and add them to your project, including a user constraints (UCF) file.

3. Add any existing files to your project.

4. Assign constraints such as timing constraints, pin assignments, and area constraints.

4.1.2 Functional Verification:

You can verify the functionality of your design at different points in the design flow as

follows:

Before synthesis, run behavioral simulation (also known as RTL simulation).

After Translate, run functional simulation (also known as gate-level simulation), using

the SIMPRIM library.

After device programming, run in-circuit verification.

4.1.3 Design Synthesis:

Synthesize your design.

4.1.4 Design Implementation:

35
Implement your design as follows:

1. Implement your design, which includes the following steps:

Translate

Map

Place and Route

2. Review reports generated by the Implement Design process, such as the Map Report

or Place & Route Report, and change any of the following to improve your design:

Process properties

Constraints

Source files

3. Synthesize and implement your design again until design requirements are met.

4.1.5 Timing Verification:

You can verify the timing of your design at different points in the design flow as follows:

Run static timing analysis at the following points in the design flow:

After Map

After Place & Route

Run timing simulation at the following points in the design flow:

After Map (for a partial timing analysis of CLB and IOB delays)

After Place and Route (for full timing analysis of block and net delays)

36
4.1.6 Xilinx Device Programming:

Program your Xilinx device as follows:

1. Create a programming file (BIT) to program your FPGA.

2. Generate a PROM, ACE, or JTAG file for debugging or to download to your device.

3. Use iMPACT to program the device with a programming cable.

4.2 Implementation Overview for FPGAs:

After synthesis, you run design implementation, which comprises the following steps:

1. Translate, which merges the incoming net lists and constraints into a Xilinx design

file

2. Map, which fits the design into the available resources on the target device

3. Place and Route, which places and routes the design to the timing constraints

4. Programming file generation, which creates a bit stream file that can be downloaded to

the device

In the Sources tab, select Synthesis/Implementation from the Design View drop-down list, and

select the top module. In the Processes tab, double-click Implement Design to run the

implementation process in one step, or double click Translate, Map, and Place & Route to run

each of the implementation steps separately. To generate the programming file, double-

37
click Generate Programming File. Alternatively, you can select Process -> Implement -> Top

Module to run Implement Design on the top module. For details, see implementing the Top

Module.

Default property values are used for the implementation process, unless you modify them.

Properties can be set for the Implement Design process or for each of the separate

implementation processes.

4.3 ASIC (Application-specific integrated circuit):

An ASIC (pronounced a-sick; bold typeface defines a new term) is an application

specific integrated circuit at least that is what the acronym stands for. Before we answer the

question of what that means we first look at the evolution of the silicon chip or integrate

circuit (IC).

Standard cell design

In the mid 1980s a designer would choose an ASIC manufacturer and

implement their design using the design tools available from the manufacturer. While third

party design tools were available, there was not an effective link from the third party design

tools to the layout and actual semiconductor process performance characteristics of the

various ASIC manufacturers. Most designers ended up using factory specific tools to

complete the implementation of their designs. A solution to this problem that also yielded a

much higher density device was the implementation of Standard Cells.

38
Gate array design

Gate array design is a manufacturing method in which the diffused layers, i.e.

transistors and other active devices, are predefined and wafers containing such devices are

held in stock prior to metallization, in other words, unconnected. The physical design process

then defines the interconnections of the final device. For most ASIC manufacturers, this

consists of from two to as many as five metal layers, each metal layer running parallel to the

one below it. Non-recurring engineering costs are much lower as photo-lithographic masks

are required only for the metal layers, and production cycles are much shorter as metallization

is a comparatively quick process.

Full-custom design

By contrast, full-custom ASIC design defines all the photo lithographic layers of the

device. Full-custom design is used for both ASIC design and for standard product design.

The benefits of full-custom design usually include reduced area (and therefore

recurring component cost), performance improvements, and also the ability to integrate

analog components and other pre-designed (and thus fully verified) components such as

microprocessor cores that form a system-on-chip.

The disadvantages of full-custom design can include increased manufacturing and

design time, increased non-recurring engineering costs, more complexity in the computer-

39
aided design (CAD) system and a much higher skill requirement on the part of the design

team.

Structured/platform design

Structured ASIC design (also referred to as platform ASIC design) has different

meanings in different contexts. This is a relatively new term in the industry, which is why

there is some variation in its definition. However, the basic premise of a structured/platform

ASIC is that both manufacturing cycle time and design cycle time are reduced compared to

cell-based ASIC by virtue of there being pre-defined metal layers (thus reducing

manufacturing time) and pre-characterization of what is on the silicon (thus reducing design

cycle time).

4.4 Xilinx ISE Overview:

The Integrated Software Environment (ISE) is the Xilinx design software suite

that allows us to take our design from design entry through Xilinx device programming. The

ISE Project Navigator manages and processes our design through the following steps in the

ISE design flow.

4.4.1 Design Entry:

Design entry is the first step in the ISE design flow. During design entry, we create our

source files based on our design objectives. We can create our top-level design file using a

Hardware Description Language (HDL), such as VHDL, Verilog, using a schematic.

40
4.4.2 Synthesis:

After design entry and optional simulation, we run synthesis. During this step, VHDL,

Verilog, or mixed language designs become Net-list files that are accepted as input to the

implementation step.

4.4.3 Implementation:

After synthesis, we run design implementation, which converts the logical design into

a physical file format that can be downloaded to the selected target device. From Project

Navigator, we can run the implementation process in one step, or we can run each of the

implementation processes separately. Implementation processes vary depending on whether

we are targeting a Field Programmable Gate Array (FPGA) or a Complex Programmable

Logic Device (CPLD).

4.4.4 Verification:

We can verify the functionality of our design at several points in the design flow. we

can use simulator software to verify the functionality and timing of our design or a portion of

our design. The simulator interprets VHDL or Verilog code into circuit functionality and

displays logical results of the described HDL to determine correct circuit operation.

Simulation allows us to create and verify complex functions in a relatively small amount of

time. We can also run in-circuit verification after programming your device.

41
4.4.5 Device Configuration:

After generating a programming file, we configure our device. During configuration,

we generate configuration files and download the programming files from a host computer to

a Xilinx device.

4.5 CPLD and FPGA Overview:

Introduction:

The Programmability of a device can be achieved using PLAs, PALs, PROMs,

EPROMs etc., The rigid two-level-logic-plus-register architecture in conjunction with the

limited numbers of inputs, outputs, product terms, and flip-flops always restricted SPLDs to

small applications. More scalable and flexible architectures had thus to be sought, and the

spectacular progress of VLSI technology has made their implementation economically

feasible from the late 1980s onwards. Two broad classes of hardware organization prevail

today.

Complex Programmable Logic Devices (CPLD):

CPLDs expand the general idea behind SPLDs by providing many of them on a single

chip. Up to hundreds of identical sub-circuits, each of which conforms to a classic SPLD, are

combined with a large programmable interconnect matrix or network, see fig.2.1. A difficulty

with this type of organization is that a partitioning into a bunch of cooperating SPLDs has to

42
be imposed artificially on any given computational task, which benefits neither hardware nor

design efficiency. Depending on the manufacturer, products are known as complex

programmable logic device (CPLD), programmable large-scale integration (PLSI), erasable

programmable logic device (EPLD), and the like in the commercial world.

Field-programmable gate arrays (FPGA):

FPGA have their overall organization patterned after that of gate arrays. Many

configurable logic cells are arranged in a two-dimensional array with bundles of parallel

wires in between. A switchbox is present wherever two wiring channels intersect, see fig.2.2.

Depending on the product, each logic cell can be configured so as to carry out some not-too-

complex combinational operation, to store a bit or two, or both.

43
 As opposed to traditional gate arrays, it is the state of programmable links rather than

fabrication masks that decides on logic functions and signal routing. Parts with this

organization are being promoted under names such as field-programmable gate array (FPGA),

logic cell array (LCA), and programmable multilevel device (PMD). The number of

configurable logic cells greatly varies between products, with typical figures ranging between

a few dozens and hundreds of thousands.

44
4.6 VLSI DESIGN FLOW

VHDL is a fairly general-purpose language, and it doesn't require a simulator on which

to run the code. There are a lot of VHDL compilers, which build executable binaries. It can

read and write files on the host computer, so a VHDL program can be written that generates

another VHDL program to be incorporated in the design being developed..

Specifications

High level design

Low level design

RTL coding

Functional
Verification

Gate level synthesis

Logic synthesis

Programming into
FPGA

Figure 4.2: Typical Design flow

45
4.6.1 Specification:

This is the stage at which we define what are the important parameters of the system

design that you are planning to design. A simple example would be: I want to design a

counter; it should be 4 bit wide, should have synchronous reset, with active high enable; when

reset is active, counter output should go to "0".

4.6.2 High Level Design

This is the stage at which you define various blocks in the design and how they

communicate. Let's assume that we need to design a microprocessor: high level design means

splitting the design into blocks based on their function; in our case the blocks are registers,

ALU, Instruction Decode, Memory Interface, etc.

Figure 4.3: I8155 High Level Block Diagram

46
4.6.3 Micro Design/Low level design

Low-level design or Micro design is the phase in which the designer describes how each

block is implemented. It contains details of State machines, counters, Mux, decoders,

internal registers. It is always a good idea to draw waveforms at various interfaces. This

is the phase where one spends lot of time.

Figure 4.4: Sample Low-level design

4.6.4 RTL Coding

In RTL coding, Micro design is converted into Verilog/VHDL code, using

synthesizable constructs of the language. Normally we like to lint the code, before starting

verification or synthesis.

4.6.5 Simulation

Simulation is the process of verifying the functional characteristics of models at any

level of abstraction. We use simulators to simulate the Hardware models. To test if the RTL

code meets the functional requirements of the specification, we must see if all the RTL blocks

47
are functionally correct. To achieve this we need to write a testbench, which generates clk,

reset and the required test vectors. A sample testbench for a counter is shown below. Normally

we spend 60-70% of time in design verification

Fig 4.5: simulation

We use the waveform output from the simulator to see if the DUT (Device Under Test)

is functionally correct. Most of the simulators come with a waveform viewer. As design

becomes complex, we write self checking testbench, where testbench applies the test vector,

then compares the output of DUT with expected values.

There is another kind of simulation, called timing simulation, which is done after

synthesis or after P&R (Place and Route). Here we include the gate delays and wires delays

and see if DUT works at rated clock speed. This is also called as SDF simulation or gate level

simulation.

48
4.6.6 COUNTER SIMULATIOIN

Fig 4.6: Counter Waveform

4.6.7 SYNTHESIS

Synthesis is the process in which synthesis tools like design compiler or Synplify take

RTL in Verilog or VHDL, target technology, and constrains as input and maps the RTL to

target technology primitives. Synthesis tool, after mapping the RTL to gates, also do the

minimal amount of timing analysis to see if the mapped design is meeting the timing

requirements. (Important thing to note is, synthesis tools are not aware of wire delays, they

only know of gate delays). After the synthesis there are a couple of things that are normally

done before passing the net list to backend (Place and Route).

4.7 VLSI Testing Problems:

VLSI hence manually testing an IC is nearly impossible.

1. Test Generation
2. I/P combinatorial problem
3. Gate to I/O pin ratio problem

Test Generation:

49
 1. VLSI has large number of gates, hence pushed automatic test generation times to

weeks and moths

2. It is nearly impossible for an external tester to handle the test cases, and hence resulted

in high cost in terms of both Money and Time.

3. Another test generation problem is, ATPG work well for combinatorial logic
But, doesnt suit for sequential logic (as it requires more space and comp time as it

has to evaluate all the states).

I/p combinatorial problem:

1. A combinatorial circuit, with N number of inputs will have a total set of 2N number of

test vectors for exhaustive testing.

2. How about a microprocessor (VLSI) chip, which has some 32 pins (and again of

course in different combinations).

3. Selective no. of inputs can be applied (but it is not an exhaustive testing).

Gate to I/O pin ratio problem:

1. Typically, a VLSI IC will have 32 pins 40 pins; but the number of gates inside the

chip will be around > 50,000.

2. To test all the gates inside, it is highly impossible; resulting in poor observability and

controllability.

4.8 Boundary Scan, JTAG, IEEE 1149.1 Tutorial

Boundary Scan Overview:

Since its introduction in the early 1990s, boundary scan, also known as JTAG or IEEE

1149, has become an essential tool used for testing boards in development, production and in

50
the field. JTAG, boundary scan is a test technique that enables information about the state of a

board to be gained when it is not possible to gain access to all the nodes that would be

required if other means of test were used.

In view of the way in which the density of boards has been increasing in recent years,

it is normally very difficult to be able to probe electronic circuits and gain the information that

is required to test these boards. As JTAG, boundary scan enables much of a board to be tested

with only minimal access, it is now widely used for the test of electronic circuits at all stages

of their life. In view of the fact that other forms of test require access either in terms of bed of

nails fixtures, while others need to probe a variety of places on the board, boundary scan

offers a unique solution to many test requirements.

Although the JTAG, boundary scan technique is aimed at testing circuits, its flexibility

enables it to be used for a wide variety of applications including test applications:

System level test

BIST access

Memory testing

Flash programming

FPGA / CPLD programming

CPU emulation

51
 While testing remains the major application for boundary scan, it can be see that it is also

useful in other applications as well. In view of its flexibility, the technique is widely used, and

a powerful tool in both development and production applications.

Boundary scan history:

With the problem of lack of access to boards starting to become a problem, a group

known as the Joint Test Action Group (JTAG) was set up in 1985. Its aim was to address the

issues being faced by electronics manufacturers in test strategies and to enable tests to be

undertaken where no other technologies could gain access.

The original goal for boundary scan was to complement existing techniques including

in-circuit test, functional built in test and other techniques and to provide a standard that

would enable the testing digital, analogue and mixed signal circuits.

The standard for boundary scan that was devised has been adopted by the Institute or

Electrical and Electronics Engineers, IEEE in the USA as IEEE 1149. The first issue of the

standard, IEEE 1149, was in 1990. The stated purpose of IEEE 1149 was to test the

interconnections between integrated circuits mounted on boards, modules, hybrids and other

substrates. As most of the problems occurring with electronics circuits occur with the

interconnections, the IEEE 1149 test strategy would reveal most of the problems.

In 1993, a revised version of the boundary scan, IEEE 1149 standard was issued which

contained many clarifications, enhancements and corrections. Then in 1994, a further issue of

the IEEE 1149 standard took place. This introduced the Boundary Scan Description

52
Language, BSDL. This enabled boundary scan tests to be written in a common language,

thereby improving the way in which tests could be written and code re-used, thereby saving

development time.

Boundary scan basics:

The JTAG, boundary scan test technique uses a shift register latch cell built into each

external connection of every boundary scan compatible device. One boundary scan cell is

included in the integrated circuit line adjacent to each I/O pin, and when used in the shift

register mode it can transfer data along to the next cell in the device. There are defined entry

and exit points for the data to enter and exit the device, and it is therefore possible to chain

several devices together.

Under normal operating conditions the cell is set so that it has no effect and it becomes

invisible. However when the device is set to test mode, it permits a serial data stream (test

vector) to be passed from one shift register latch cell to the next. Boundary-scan cells in a

device can capture data from integrated circuit line, or force data onto them. In this way a test

system that can input a data stream to the shift register chain can set up states on the board,

and also monitor data. By setting up one serial data stream, latching this into place, and then

monitor the returning data stream, it is possible to gain access to the circuits on the board and

check that a returning data stream is what is expected. If it is, then the test can pass, but if not

the boundary scan system has detected and problem that can be further investigated.

53
 There are a number of boundary scan, IEEE 1149 control and data lines. There lines

known as TCK, TMS and the optional TRST line are connected in parallel to the chips in the

boundary scan chain. Connections designated TDI (input) and TDO (output) are daisy chained

together to provide a path around the boundary scan chips for the data. Data is sent into the

TDI of the first chip, and then TDO from the first chip is connected to TDI of the next and so

forth. Finally the data is taken from the TDO of the last IC in the daisy chain.

TAP Test Access Port - The pins associated with the test access controller.

TCK Test Clock - this pin is the clock signal used for ensuring the timing of the

boundary scan system. The TDI shifts values into the appropriate register on the rising

edge of TCK. The selected register contents shift out onto TDO on the falling edge of

TCK.

TDI Test Data Input - Test instructions shift into the device through this pin.

TDO Test Data Output - This pin provides data from the boundary scan registers,

i.e. test data shifts out on this pin.

TMS Test Mode Select - This input which also clocks through on the rising edge of

TCK determines the state of the TAP controller.

TRST Test Reset - This is an optional active low test reset pin. It permits

asynchronous TAP controller initialization without affecting other device or system

logic.

54
 This technique can obviously only be used with integrated circuits that have the

boundary scan cells included in the chip. Many of the smaller devices do not have them, but

larger chips including memory devices, microprocessors and the like often do. When

designing a board, an early decision about the way in which it will be tested is needed. If

boundary scan techniques are to be used, then devices incorporating boundary scan facilities

must be chosen.

Applications for boundary scan:

JTAG, boundary scan is an ideal test tool for use in many applications. The most

obvious applications for boundary scan are within the production environment. Here the

boards can be tested and problems that might otherwise go un-detected because of lack of test

access can be adequately tested. In fact boundary scan technology is being combined with

other technologies to provide what is termed a combinational tester.

In addition to being used in production test, boundary scan, JTAG, IEEE 1149, can

also be used in a variety of other test scenarios, including product development and debugging

as well as field service. This means that the boundary scan code can be re-used for test areas,

and hence the cost can be split over these applications. Not only does this indicate that

boundary scan is a powerful tool, but it also makes it financially attractive.

Programme generation:

One of the chief costs for any development these days is the cost of the software, and

this is particularly true for boundary scan where there is little hardware. This means that any

55
savings that can be made in the time taken for the software development can significantly

reduce the costs. Accordingly a Test Programme Generator (TPG) is an integral part of a

boundary scan system.

Typically the test programme generator requires the net-list of the Unit Under Test

(UUT) and the Boundary Scan Description Language (BSDL) files of the boundary scan

components contained within the circuit. With this information it is possible for the test

programme generator to create the test patterns used for the test. These allow the system to

detect and isolate any faults for all boundary-scan testable nets within the circuit. It is also

possible for the test programme generator to create test vectors that enable the system to

detect faults on the nodes or pins components non-boundary scan components that are

surrounded by boundary scan devices.

JTAG Summary:

JTAG, boundary scan, IEEE 1149 is a test technique that is now well established.

Although it requires test programmes to be generated before it can be used, it nevertheless

provides a very cost effective method of gaining access for test vectors into an electronic

circuit board. With circuit board real estate being at a premium, the cost of adding probe or

access points for other type of electronic test technologies would be prohibitive, if indeed it

were possible.

56
SOFTWARE TOOLS:

Simulation : Xilinx ISE 9.2i

Synthesis : Xilinx XST

HARDWARE:

FPGA- Xilinx Sparten 3E-100 TQ144

Area : 5.96%

Frequency : 145.372 MHZ

57
UART with BIST (Top Module):

VHDL Source Code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity uartwithbist is

Port ( d : in STD_LOGIC;

clk,rst: in STD_LOGIC;

din : in STD_LOGIC_VECTOR (6 downto 0);

b1, b0:in std_logic;

q : inout STD_LOGIC_vector(6 downto 0));

end uartwithbist;

architecture Behavioral of uartwithbist is

signal tdata_in:std_logic_vector(6 downto 0);

signal tdata_out:std_logic;

signal dataline :std_logic;

signal rdata_out:std_logic_vector(6 downto 0);

signal z:std_logic;

signal parityerr,framingerr,overrun:std_logic;

signal rxrdy,txrdy:std_logic;

signal rd, wr: std_logic;

58
signal clk_out:std_logic;

signal rd_clk: std_logic;

component bilbo is

Port ( d : in STD_LOGIC;

clk,rst:in STD_LOGIC;

din: in STD_LOGIC_VECTOR (6 downto 0);

b1, b0: in std_logic;

q: inout STD_LOGIC_vector(6 downto 0));

end component;

component uart_transmitter is

port(clk, rst_n, wr: in std_logic;

data: in std_logic_vector(6 downto 0);

txrdy: inout std_logic;

tx: out std_logic);

end component;

component uart_receiver is

port(clk, rst_n, rd, rx: in std_logic;

parityerr, framingerr, overrun: out std_logic;

rxrdy: inout std_logic;

data: out std_logic_vector(6 downto 0));

end component;

component xorgate is

59
 Port ( x : in STD_LOGIC;

y : in STD_LOGIC;

z : out STD_LOGIC);

end component;

component tx_clkout is

Port ( clk : in STD_LOGIC;

res : in STD_LOGIC;

clk_out : out STD_LOGIC);

end component;

begin

u1: bilbo port map(

d => d,

clk => clk_out,

rst => rst,

din => din,

b1 => b1,

b0 => b0,

q => tdata_in);

u2: bilbo port map(

d => d,

clk => clk_out,

60
 rst => rst,

din => rdata_out,

b1 => z,

b0 => b0,

q => q);

u3: xorgate Port map(

x =>b0,

y =>b1,

z =>z);

u4:uart_transmitter port map(

clk => clk,

rst_n => rst,

wr => rst,

data => tdata_in,

txrdy => txrdy,

tx => tdata_out);

u5:uart_receiver port map(

clk => clk,

rst_n => rst,

61
 rd => rst,

rx => tdata_out,

parityerr => parityerr,

framingerr => framingerr,

overrun => overrun,

rxrdy => rxrdy,

data => rdata_out);

u6:tx_clkout Port map(

clk => clk,

res => rst,

clk_out => clk_out);

end behavioral;

62
 CHAPTER 5

PROJECT RESULTS

Top module Simulation Results:

Top module Synthesis Reports:

HDL Synthesis Report:

Macro Statistics

# Adders/Subtractors :1

32-bit adder :1

# Counters :5

32-bit up counter :5

63
# Registers : 38

1-bit register : 32

32-bit register :1

7-bit register :5

# Comparators :1

32-bit comparator less :1

# Multiplexers :2

7-bit 4-to-1 multiplexer :2

# Xors : 18

1-bit xor2 : 16

1-bit xor7 :2

Advanced HDL Synthesis Report:

Macro Statistics

# Adders/Subtractors :1

32-bit adder :1

# Counters :5

32-bit up counter :5

# Registers : 99

Flip-Flops : 99

64
# Comparators :1

32-bit comparator less :1

# Multiplexers :2

7-bit 4-to-1 multiplexer :2

# Xors : 18

1-bit xor2 : 16

1-bit xor7 :2

Final Register Report:

----------------------------

Macro Statistics

# Registers : 255

Flip-Flops : 255

Device utilization summary:

-----------------------------------

Selected Device : 3s500efg320-4

Number of Slices: 203 out of 4656 4%

Number of Slice Flip Flops: 255 out of 9312 2%

Number of 4 input LUTs: 389 out of 9312 4%

Number of IOs: 19

65
Number of bonded IOBs: 19 out of 232 8%

Number of GCLKs: 2 out of 24 8%

Timing Summary:

---------------

Minimum period: 7.513ns (Maximum Frequency: 133.103MHz)

Minimum input arrival time before clock: 8.015ns

Maximum output required time after clock: 4.496ns

Maximum combinational path delay: No path found

66
RTL Schematic (in FPGA):

67
Technology Schematic (in FPGA):

68
 CONCLUSION

As part of this project, BIST Architecture is developed using VHDL, the test

performance achieved with the implementation of BIST is proven to be adequate to offset the

disincentive of the hardware overhead produced by the additional BIST circuit. The technique

can provide shorter test time compared to an externally applied test and allows the use of low-

cost test equipment during all stages of production. In spite of the hardware overhead obtained

with BIST implementation, the overhead is somehow reasonable considering the test

performance obtained. With the implementation of BIST, expensive tester requirements and

testing procedures starting from circuit or logic level to field level testing are minimized.

69
 REFERENCES

[1] M. Ibrahim Abubakar, A Built in Self Testable Bit-Slice Processor, Faculty

of Computer Science & Information Technology, University of Malaya May 1995.

[2] Z. Navabi, VHDL Analysis and Modeling of Digital Systems, McGraw-Hill Inc.,

1991.

[3] M. S. Harvey, Generic UART Manual, Silicon Valley, December 1999.

[4] C. H. Roth, Digital System Design Using VHDL, PWS Publishing Company, 1998.

[5] http://en.wikipedia.org/wiki/Built-in_self-test

[6] http://www.lammertbies.nl/comm/info/serial-uart.html

70