A FULLY DIFFERENTIAL CMOS OPERATIONAL AMPLIFIER

IMPLEMENTED WITH MOS GAIN BOOSTING TECHNIQUE

by
PING LO, B.S.E.E.

A THESIS

IN

ELECTRICAL ENGINEERING

Submitted to the Graduate Faculty

of Texas Tech University in
Partial Fulfillment of
the Requirements for
the Degree of
MASTER OF SCIENCE

IN

ELECTRICAL ENGINEERING

Approved

Accepted

May, 1996
I C^Cjk ACKNOWLEDGEMENTS

I like to express my gratefulness to Professor Kwong Shu Chao, without whose

thoughtful guidance and patience, the success of this work would never have been

possible. I am also thankful to Professor Sunanda Mitra and Osamu Ishihara for their

interest and advice in this work.

I appreciate the support of my fellow students in the EE department, in particular,

Ramesh M.C. for his circuit insight, and Stephen Bayne for his help in chip testing.

Lastly, I would like to dedicate this thesis to my father, for his unprecedented love

and support throughout my graduate studies. Without him, my study here would not have

been possible.
 TABLE OF CONTENTS

ACKNOWLEDGMENTS ii

LISTOFTABLES v

LIST OF FIGURES vi

CHAPTER

I. INTRODUCTION 1

1.1 Motivation 1

1.2 Structure of Thesis 3

II. OPERATIONAL AMPLIFIER DESIGN REVIEW 4

2.1 Performance Metrics 4

2.2 Differential Amplifiers 6

2.3 Operational Amplifier Toplogies 8

2.3.1 Multi-Stage Amplifier 8

2.3.2 Single Stage Amplifier 11

2.3.3 Gain Boosting Techniques 14

III. SUPER-MOST STRUCTURE 16

3.1 Overview of Current Mirror Structures 16

3.2 Principle of Super-MOST 19

3.3 Super-MOST Topologies 23

3.3.1 Topology 1 23

3.3.2 Topology 2 26

iii
 3.4 Proposed New Structure 28

3.4.1 Circuit Analysis 30

3.4.2 Simulation Results 31

IV. DESIGN OF FULLY DIFFERENTIAL OPERATIONAL

AMPLIFIER 38

4.1 Design considerations 39

4.2 Operational Amplifier Architecture 40

4.2.1 Comparisons of Single Stage and Two Stages

Implementation 40

4.2.2 Comparisons of Single Ended and Differential

Implementation 41

4.3 Circuit Description 42

4.3.1 Main Stage 42

4.3.2 Bias Circuit 48

4.3.3 Common Mode Feedback Circuit 49

4.4 Simulation Results 52

V. EXPERIMENTAL RESULTS 60

5.1 Description of Experimental Chip 60

5.2 Test Setup 61

5.3 Test Results 62

VI. CONCLUSION 69

REFERENCES 71

APPENDIX: MOSIS PROCESS PARAMETER 74

IV
 LIST OF TABLES

3.1 Dimensions of transistors in Super-MOST 33

4.1 Dimensions of transistors in the operational amplifier 58

4.2 Summary of fully differential operational amplifier performance 59

 LIST OF FIGURES

2.1 Differential amplifier 6

2.2 AC equivalent model of the differential amplifier 8

2.3 Two-stage operational amplifier configuration 9

2.4 Telescopic cascode amplifier 12

2.5 Folded cascode operational amplifier 13

2.6 Mirrored cascode operational amplifier 13

2.7 Cascode Circuits 14

3.1 Cascode (a) transistors circuit, (b) small-signal equivalent circuit 17

3.2 Regulated cascode transistors 19

3.3 Simple Super-MOST structure 21

3.4 Modified Super-MOST structure 23

3.5 Super-MOST configuration 1 24

3.6 Super-MOST configuration 2 27

3.7 Proposed Super-MOST configuration 28

3.8 Symbols for (a) N-type, (b) P-type Super-MOST 29

3.9 Current-voltage characteristics of (a) a single n-transistor, (b) the N-type

Super-MOST with KG-T ranging from-1.5 V to-1 V 34

3.10 Current-voltage characteristics of (a) a single p-transistor, (b) the P-type

Super-MOST with KGS ranging from 1 V to 1.5 V 35

3.11 Simulation result of the current mirror using N-type Super-MOST with
/, ranging from 40 (xA to 200 fxA 36

VI
3.12 Frequency response of the inverting amplifier 37

3.13 Output voltage swing of the inverting amplifier 37

4.1 Main stage of the fully differential operational amplifier 43

4.2 Equivalent circuit of the Super-MOST 44

4.3 Equivalent circuit for the input differential pair 45

4.4 Small signal equivalent half circuit of the main stage 47

4.5 Bias circuit 48

4.6 Simplified configuration of a fully differential switched capacitor network . . 50

4.7 Common mode feedback circuit 51

4.8 Frequency reponse of the fully differential operational amplifier

(a) magnitude plot, (b) phase plot 53

4.9 Step response of the fully differential operational amplifier with

(a)0.2V,(b) 1.5 V input 54

4.10 Output voltage swing of the fully differential amplifier 55

4.11 Transient response with 5 mV sinusoidal input 56

4.12 Output response of an integrator implemented with

the operational amplifier 57

4.13 Output response of a differentiator implemented with

the operational amplifier 57

5.1 Layout of the experimental chip 64

5.2 Die photo of the experimental chip 65

5.3 Measured current-voltage characteristics of N-type Super-MOST 66

5.4 Measured current-voltage characteristics of P-type Super-MOST 66

vu
5.5 Input and output waveforms of the operational amplifier for
(a)frequencyof 2 kHz, and (b)frequencyof 200 kHz 67

5.6 Input and output waveforms for frequency varied sinusoidal signal
in the range of (a) hundred-ldlo-Hz, and (b) mega-Hz 68

vm
 CHAPTER I

INTRODUCTION

1.1 Motivation

CMOS technologies have rapidly improved over the past few years. To date, the

size of transistor is shrunk to sub-micron and fabrication processes attain finesse, resulting

in dramatic increases in the speed and density of integrated circuit devices. The result of

this trend is the system on a chip, in which aU circuitry wiU be housed within a couple of

square centimeter of die area, in particular for a large digital system. Compared with their

analog counterparts, digital circuits are less susceptible to noise and more endurance to

the supply and process variations, and allow easier design and test automation. These

facts contribute to more digital circuits and less analog circuits being integrated within a

chip.

However, since naturally occurring signals are analog, in order to perform any

digital signal processing (DSP), data conversion system is needed to digitize the signal at

the input and reproduce the signal at the output. For example, applications such as high

definition television (HDTV), compact disc players, CD ROM, and modems, as well as

special systems such as medical imaging, speech processing, and radar employ data

conversion systems for interfacing. As the demand for these high performance

appUcations increases, the design of data conversion system becomes increasingly difficult.

This is because a high speed and high accuracy analog circuit is not easy to attain, and

tradeoff often has to be made. Furthermore, in the mixed signal system, analog portions

1
are susceptible to the coupling noise via power supply, substrate current and crosstalk of

adjacent line during digital switching. As a result, mixed signal system designs become a

challenging problem.

In most of the data conversion systems, such as switched capacitor circuits [1],

sigma-delta converters [2], pipeline A/D converters [3], [4], algorithmic A/D converters

[5], [6], and sample-and-hold amplifiers [7], [8], operational ampUfiers form the basic

building block. High gain and high unity gain frequency amplifiers are needed to meet the

requirements for high performance systems. Satisfying both of these requirements,

however, is difficult to achieve since high unity gain frequency calls for short channel

devices which has low intrinsic gain. Therefore, gain enhancement techniques are

necessary for designing a high gain and high unity gain frequency operational amplifier.

This thesis investigates the gain boosting technique proposed by K.Bult and G.

Geelen [9]. An improved cascode circuit that combines both high gain and high speed is

developed. Using this cascode circuit, a high performance fully differential operational

amplifier is designed. A prototype of the cascode circuit and operational ampUfier was

fabricated in a 2 |im n-well CMOS technology. Simulation results indicate that the

cascode circuit has at least 100 MQ output impedance, while the amplifier has an open

loop gain of 98 dB and a unity gain frequency of 17 MHz for 10 pF load capacitor.
1.2 Structure of Thesis

This thesis is outlined as follows. Chapter n analyzes a differential amplifier,

which is the building block for an operational amplifier. Various operational amplifier

topologies are also examined with emphasis on the speed and gain analysis. Some

previous works are studied and their performance limitations are discussed.

In chapter in, the problems associated with the conventional cascode circuits are

identified and an improved version of cascode circuit, which is called Super-MOST, is

introduced. Also presented is the principle and operation of the Super-MOST. Two

previous designs using this principle are then described along with their drawbacks. A

new topology is proposed that has superior performance over the two previous design.

Chapter IV describes the design of the fuUy differential operational amplifier. The

reasons of choosing the topology are explained. Also, a common mode feedback stage is

presented that is employed to control the output bias point.

Chapter V shows the experimental results from a prototype chip which includes

the Super-MOST and the operational amplifier. In chapter VI, the summary of this

research and the suggestions for future work are presented.

 CHAPTER II

OPERATIONAL AMPLIHER DESIGN REVIEW

This chapter presents an overview of some of previous CMOS operational

amplifier configurations, but stand alone designs are not addressed. Since this research is

focused on designing an operational amplifier that can be used as a building block for

analog signal processing system, the primary emphasis in this chapter is placed on the

factors affecting the gain and speed of an operational amplifier. Detailed discussions of

design techniques and performance tradeoff can be found in many literature [10], [11],

[12].

Section 2.1 describes some of the parameters that characterize an operational

amplifier, thus providing an assessment of an operational amplifier. Section 2.2 gives a

conceptual description of the building block for an operational amplifier - differential

amplifier. Some of the operational amplifier topologies are described and issues related to

the performances of each circuit are discussed in Section 2.3; however, this section is not

intended to be a comprehensive review; rather, it provides some background for the

design of operational amplifiers.

2.1 Performance Metrics

A full assessment of the performance of operational amplifiers requires an

evaluation of a large number of parameters [13], [14]. This section defines a number of

terms for performance metrics.

 DC gain is the low frequency gain of the amplifier and usually characterizes the

accuracy of the amplifier.

Unity gain bandwidth is the frequency at which the open loop gain of the

amplifier becomes unity or 0 dB.

Phase margin is defined as the phase shift of the amplifier at the unity gain

bandwidth.

Slew rate is the rate of output change for a large input step signal.

Settling time is the amount of time the amplifier required to settle within a

predetermined tolerance (typical value is 0.1 percent) of the final value of the

output step response.

Input common mode range is the range of input voltages over which the

operational amplifier can still operate properly, i.e., all transistors in the input

stage are operated in saturation region.

Ou^ut voltage swing is the voltage range over which all the transistors in the

output stage are still biased in saturation region.

Power supply rejection ratio is defined as the ratio of the differential gain to the

gain from the variation of power supply to the output with the differential input set

to zero.

Common mode rejection ratio is defined as the ratio of the differential gain to the

common mode gain.

2.2 Differential Amplifiers

In most operational amplifier topologies, the input stage is realized by a differential

pair. It is, without doubt, the most commonly used building block in analog processing

system. Therefore, we examine its small signal behavior, which serves as the background

material for the next section. Shown in Fig. 2.1 is the CMOS differential pair. It consists

of a curtent source with value Ibias and two equal or matched transistors Ml and M2. For

differential output, transistors M3 and M4 are implemented as current source/sink loads or

active loads; while for single ended, they are connected as a current mirror. Here, it is

assumed that M3 and M4 are current source loads for the analysis, but similar analysis can

also be applied to the current mirror load.

'DD

'outl
M3
5 M4 'bias

Vout2

Ml M2 - V.

bias

Vss

Fig. 2.1. Differential amplifier.

 Conceptually, the smaU signal analysis of the differential amplifier of Fig. 2.1 can

be best understood by using the ac equivalent model shown in Fig. 2.2. This model

assumes that the sources of the two input transistors is effectively shorted to ground as the

voltage across the ideal current source does not vary. Practically, there is finite impedance

across the current source, however, no significant change on the differential gain

derivation is resulted. The differential gain of this circuit can now be calculated.

^oull ~ ^outl ~ ~\^m\ ^zs\ V dsl l^dsa ) ~ Sm2 ^gs2 yds! lyds^ )) (.^' ^ )

If we assume that g^^ = g^^ and r^JIr^j = rj^2\\fds4 (i-e- M1=M2, M3=M4), Eq. (2.1) can

be further simplified and then the voltage gain can be expressed as

\=-8.i{r^ih3)- (2.2)

Typically values for gm and r^j are in the order of hundred-|iS and MQ., respectively, and

the voltage gain of the differential amplifier is only about 20-25 dB. Further increase in

the gain requires some modifications on the configiu^ation.

The frequency response of the differential amplifier is mainly associated with the

sum of parasitic capacitors at the output nodes. At node 1, the parasitic capacitors consist

of Chdi, Cbd3, Cgs3 and Cgdi; while at node 2, they are Ctdi, Cbd4, Cgs4 and Cgdi- Since

matched transistors are assumed, the equivalent capacitance at these two nodes is the

same. From this conclusion, the frequency response of the differential amplifier consists of

a single pole given by 1 / {rj^\r^^\C^^^ + C^^^ + C^^^ + C^^j).

 + +

grfVgi/r> r&i TcfeS Voul Vou2\r<b* raa /p>&V^

Fig. 2.2. AC equivalent model of the differential amplifier.

2.3 Operational Amplifier Topologies

The small voltage gain of the differential amplifier is found inapplicable for most

analog system design. For this reason, operational amplifier is introduced to circumvent

the limitation of differential amplifier. Most operational amplifier architectures employ the

differential amplifier as the building block and, in general, can be classified into two broad

categories, namely, single-stage or multi-stage operational amphfiers. Also they can be

implemented as either single-ended or fully differential types. The merits and drawbacks

of these two implementation will be discussed in Chapter IV.

2.3.1 Multi-Stage Amplifier

The most widely used circuit approach for the implementation of operational

amplifiers is the two-stage configuration [15] shown in Fig. 2.3. This configuration

consists of a differential amplifier as the first stage, a curtent source load inverting

amplifier as the second stage, and a Miller compensation capacitor Cc. Both of the dc

8
 Fig. 2.3. Two-stage operational amplifier configuration.

gain and the gain bandwidth product of the circuit are found to be related to the bias

cmxent and the sizes of input transistors. Although both of these parameters can be

increased by using larger device area, the tradeoff between the dc gain and gain bandwidth

product has to be made by varying the bias curtent. These relationships thus provide

flexibility in meeting the desired performance.

The principal drawback of this architecture is the degradation of the settling

behavior resulted from the nondominant pole formed by the output impedance and the

load capacitance. This implies that the capacitive loading is limited and relied on the

compensation capacitor Cc [10]. Furthermore, the effect of the right half-plane zero

resulted from feedforward through Cc often requires other circuit techniques to ensure

stabiUty [10], [16].

In precision applications involving large loop gain, this configuration may be

inadequate. More gain can be obtained by appending cascode transistors to the first stage,

second stage or both. The result is that the incremental gain of the circuit is equal to the

open circuit gain of the cascode transistor. For example, a triple cascode amplifier has

been implemented in [17] where the gain is proportional to (gmrof- One disadvantage of
this technique is a substantial reduction in voltage swing, which resulted in limited

allowable number of cascode devices. However, in applications where dynamic range is

the primary concern, two-stage topology has its own merit. The first stage can provide a

high gain, while the second stage is designed for rail-to-rail output swing [18].

The other approach, which is well known but not commonly employed, for

achieving high gain is cascading amplifier stages. Though, unlike the cascode topology,

this approach does not suffer the reduction in voltage swing, the frequency response is

degraded as each cascade stage introduces an additional pole. This problem is alleviated

by the nested Miller compensation structure [19] which utilizes Miller capacitors that are

connected from the output node of the amplifier to the inputs of the subsequent internal

amplifier stages, and thus, nondominate poles are splitted apart. In [20], an operational

amplifier employs similar compensation scheme, mulipath hybrid nested Miller structure.

This design was reported to obtain a high gain without degradation in speed.

Despite its advantage, the nested Miller compensation structure has a major

drawback that the bandwidth is reduced by pole splitting capacitors. This implies that

further increase in the number of cascading stages wiU eventually be limited by the

bandwidth of the circuit. Additionally, this structure has a slower slew rate than the two-

stage counterpart as there are increases in charging current for the compensation

capacitors.

In summary, multi-stage topologies can allocate gain and voltage swing in separate

stages, thereby providing viable choices for low voltage design and resistive load drivers.

Since Miller capacitors for frequency compensation must be used in these topologies, the

10
load driving capacitance is restricted. The high gain requirement for multi-stage is to use

long channel devices biased at low current levels, contradicting the requirement for a high

slew rate.

2.3.2 Single-Stage Amplifier

In switched capacitor designs that utilize operational amplifier, the single stage

topology is more commonly used [21], [22] than a multi-stage amplifier because of its

capability of driving large capacitive load. This is due to the fact that the load capacitor

acts as the compensation capacitor simultaneously, and the dominate pole is formed by the

total output resistance and the load capacitance.

In order to obtain high gain, a single-stage topology which employs cascode

devices can be used. Fig. 2.4 shows one of the version of the single-stage topology - the

telescopic cascode operational amplifier. Since the circuit employs five stacked devices,

its output voltage swing is limited. To achieve both high gain and large voltage swing, the

channel width of the devices in the circuit must be large so that their transconductances

are maximized and their saturation voltages are minimized. On the other hand, the bias

currents must be made large enough to obtain a high slew rate while the channel length of

the devices are made longer to maintain a high gain. The large size of the transistors

results in large parasitic capacitance, thereby degrading the settling behaviors.

The folded cascode architecture or the mirrored cascode architecture, as shown in

Fig. 2.4 and Fig. 2.5, respectively, is designed to increase the input and output voltage

swings. Here the circuit has three stacked devices in the input stage, and four in the

11
output stage, giving larger input and output swings than the telescopic cascode

counterpart. However, these two structures have different performances for various load

capacitance. The mirrored cascode architecture demonstrates faster settling time for large

capacitive loads due to its high slew rate, while the folded cascode architecture provides

better settling time for smaU capacitive loads due to its superior small signal response. In

order to overcome the corresponding problems associated with these two structures, a

complementary folded cascode architecture is introduced [23] for providing exceUent

frequency response for various load capacitors. However, one disadvantage of this

architecture is its very low dc gain which is not suitable for high precision appUcation.

In summary, single stage topologies are the feasible choice for high frequency

switched capacitor filters, but they usuaUy have limited dc gain.

Vr

Fig. 2.4 Telescopic cascode amplifier.

12
 VDD

' biasl

|-^V..
h
M 5 ^ | M 6 ^ >Vbias2

Vo,

M7
71M \L"'
1

M9
p H I U"o
Fig. 2.5. Folded cascode operational amplifier.

I VDD

M5 I fI M3 M4 I M6

M7 M8 - V bias

H I Ml M2~~|
H' 'V

M9 MIO

Mil
0 M12

"Vss

Fig. 2.6. Mirrored cascode operational ampUfier.

13
2.3.3 Gain Boosting Techniques

The Umited gain in single-stage topologies and the low bandwidth associated with

multi-stage architectures have resiilted in the need for the development of gain boosting

techniques [24], [25]. The principle of these techniques is to add a feedback ampUfier to

the cascode device, as shown in Fig. 2.7(b), yielding an output impedance approximately

A times larger than the simple cascode circuit of Fig. 2.7(a), where A is the open loop gain

of the feedback amplifier. This ampUfier tends to maintain the drain voltage of Ml by

adjusting the gate voltage of M2. In other words, if there are changes in the drain current

at the output, the amplifier varies the gate voltage of M2 such that the changes in the drain

voltage is minimized.

(roi + (l+gm2roi)ro2) (roi -I- (l+gm2Aroi)ro2)

M2 -V bias2

Ml
J - Vbiasl

- VSS
(a) simple (b) gain-enhanced

Fig. 2.7. Cascode circuit

14
 The operational ampUfier designs in [24] and [26] utUized the gain boosting

techniques to increase the dc gain without degradation in speed. In their designs, a fully

differential folded cascode topology is implemented and the gain enhancement is obtained

by replacing the regular cascode circuits with active cascode circuits. By using two fully

differential operational amplifiers instead of four single-ended ampUfiers for the gain

enhancement, an improvement in performance over [24] has been reported [26].

However, the disadvantage of these implementations is the complexity of the design and

its layout [9]. The requirement of long wire in layouts results in larger die area and higher

crosstalk interference.

In summary, the gain boosting techniques can be used in high gain and fast settUng

operational ampUfier designs, but care must be exercised with layout plans.

15
 CHAPTER n i

SUPER-MOST STRUCTURE

This chapter addresses the problems associated with the gain boosting technique,

as mentioned in the previous chapter. A building block Super-MOST is presented. In

section 3.1, a brief overview of some of the structures which are commonly used in

current mirrors is presented. Section 3.2 discusses the basic operating principles of the

Super-MOST. In section 3.3, some previous structures of Super-MOST are reviewed and

remarks are made. Then, in section 3.4, a new structure is presented along with its

simulation results.

3.1 Overview of Curtent Mirror Structures

A single MOS transistor, biased in the saturation region, has an approximate

output impedance 7/A/DS which is typicaUy in the range of 100 kilo-ohms. This magnitude

is not large enough to give a good accuracy in a current mirror or to provide a high gain in

an ampUfier.

Cascoding an additional device, as shown in Fig. 3.1(a), wiU increase the output

impedance by the intrinsic MOS transistor gain gmro. The output impedance can be easily

derived from the small signal equivalent circuit shown in Fig. 3.1(b) to be

rou,={8n.2fds2+^ydsl+fds2- (3-1)

16
 'DD

'ref
H
Vin - | P M I

1 'SS

(a)

rds2

gm2Va

Tdsl
4> gmlVi,

(b)

Fig. 3.1. Cascode (a) transistors circuit, (b) small signal equivalent circuit

17
Typical VOM of this structure is ten times larger than that of a single transistor. This

impedance boosting results in better accuracy in a current mirror or a larger gain in an

amplifier. However, the output voltage swing is reduced by Vosisat) of the additional

cascode device.

An improved version of the cascoded structure is the regulated cascode transistors

[25]. By means of an additional gain stage consisting theti-ansistorM3 and a current

source as shown in Fig. 3.2, the output impedance of the structure is further increased to

the order of hundred mega-ohms compared with the simple cascoded version of Fig.3.1.

Acting as a feedback amplifier, the transistor M3 and the current source maintain the drain

of the transistor Ml at a constant voltage. This eUminates the cortesponding variation in

drain current, resulting in a higher output impedance. The value of the output impedance

can be calculated as

rout = [gntl^dsl iSmSr^S + 0 + ^}dsi + ^<fc2 (3-2)

While the two cascode structures provide much higher output impedance, they

have two significant disadvantages. First, the output voltage swing is decreased by

yDS(sat)min of the cascode transistor. Secondly, if the input signal voltage VGSI is increased,

the fixed bias of the cascode device will tend to drive the lower device to the ohmic

region. This introduces nonUnearities in the output signal. The solution is to use an

adaptive Vbias or self-biasing that enables all the transistors to operate in the saturation

region so that the nonUnearities are eliminated. This self-biasing is the basic principle of a

Super-MOST which is discussed in the next section.

18
 VDD

)1

M2 (1

ir
IL M3

Vi Ml
' '

Vss

Fig. 3.2. Regulated cascode transistors

3.2 Principle of Super-MOST

The topology of Super-MOST is the modified version of regulated cascode

transistors. A feedback amplifier is used to boost the output impedance to the order

which is proportional to the gain of the ampUfier. As mentioned in the previous section,

the improvement of Super-MOST over the regulated cascode structure results from the

self biasing principle.

A simple configuration of Super-MOST is shown in Fig. 3.3. A voltage sensing

branch, transistors M4 and M5, is added to the regulated cascode structure. This branch

is a simple inverting amplifier. The input voltage to this amplifier is the same as that to the

lower device of the cascode transistors. Thus the curtent IDS4 through M4 is related to

VGSI and can be written as

19
 ^DSA~ jj VGSI ^TA) (3-3)

This current is then converted back to voltage by the active load transistor M5, which has

the gate connected to the drain. This will ensure M5 operated in saturation region. The

bias voltage VGSS can then be calculated by

yGSS=}^JoSA+yTS- (3.4)

This voltage in turn wiU become the biasing voltage for the current source, transistor M6,

of the feedback amplifier. An adaptive biasing network is thus estabUshed.

Care must be exercised to estabUsh proper bias for M2 such that VDS of Ml is not

driven to ohmic region or is at the edge of the saturation. If Ml is operated in the ohmic

region, it wiU introduce nonUnearities to the output signal; while if VDS is driven high

above the edge of saturation, it will increase the output voltage swing. These two

requirements often conflict with one another, so a compromise needs to be made. The

foUowing derivations give an indication of how to satisfy the requirements.

An attempt is made to formalize the relations of bias voltages for transistors of the

adaptive biasing network for the proper operation of main transistor Ml. For simpUcity,

kW-
the expression '- is replaced by P , , where / is the index of the respective transistor.
2L-

Eq. (3.3) shows that/os^ is related to VGSI, the bias voltage of Ml. Substituting (3.3) into

(3.4), a direct relationship between VGSS and VGSI is then written as

yoss = JE(^c5i-^r4) + V'. (3.5)

20
 - V DD

. i ) M6 M5

1 1 (1
M2 (1

M3
>
V m MI M4

1.
Fig. 3.3. Simple Super-MOST stiiicture.

Applying the curtent-voltage relationship, IDS6 is given by

V nr- \ "
'DS6 ~" P ( -V 76 (3.6)
vPs ;

Normally, VT of M6 and M5 have the same value because their source and substrate are

tied to the same node. Eq. (3.6) can be simplified to

^ DS6 ~ P 6 o VGSI ^T4 ) (3.7)

Ps

Since the current through fransistor M3 is identical to IDS6, VGSS can be expressed in terms

of VGSI by using Eq. (3.7).

Vas^=-^^(Vos.-yT4)+Vr^- (3.8)

It is assumed that all theti-ansistorsare operated in saturation region in the above

derivations.

21
 It can be observed from Fig. 3.3 that VGSS is equal to VDSI by the principle of KVL.

Combining the result that is obtained from Eq. (3.8), an expression of VDSI in terms of VGSI

is written as

Vosi = j^i'^os^ -yT4)+Vrs. (3.9)

P6p4
The term I is determined by the ratio between the respective sizes of the

transistors since the parameter k is process-dependent, and so this term is considered as a

constant once W/L of each transistor is fixed. The magnitudes of VT4 and VT3 are also

process-dependent These two results thus imply that VDSI is directiy proportional to VGSI'-

yosi = ^yos:+c, (3.10)

where P = 1 - ^ and C = 7 " I 4 ^ V V 4 . This indicates that V^,, V,,^,,,^^^ if

P > 1 andl/,, > Vr, - l M 7 ^ ^ , where V,,,,,^^^ = {V^^i " ^ n ) -

To reduce the voltage across drain-source of Ml, additional tiansistors are

included in the voltage loop as shown in Fig. 3.4. An expression is obtained by using

KVL:

'^DSl ~'GS3 ~*^GS2- ^--^.A^y

If (YGSS "^Gsa) - (YGSI -V'n), Ml wUl be biased near the edge of saturation. This

condition gives the design constraint which determines ratios of W/L of the transistors for

the circuit

22
 VGS2 + '*|

M2
Ml + V GS3

l DSl

Fig. 3.4. Modified Super-MOST structure.

3.3 Super-MOST Topologies

This section describes two previous designs and gives an intuitive analysis of their

performances. Both of these topologies employ the structure of the regulated cascode

transistors with an adaptive biasing network. The biasing networks, however, distinguish

the different biasing requirements and design techniques for these two topologies.

Discussion of the circuits wiU emphasis the biasing network only and not the main

transistor Ml and cascode transistor M2.

3.3.1 Topology 1

Fig. 3.5 shows one of the configurations for Super-MOST [9]. Transistors M3,

M4, M9, MIO, M i l and M12 form the biasing circuit The additional gain stage, which

consists of transistors M5, M6, M7 and M8, produces impedance boosting effect. These

tiansistors act to maintain the drain voltage of Ml such that V^^i = ^osuMOmin

This condition is achieved if Eq. (3.10) is satisfied. It can be proved by applying

KVL around the loop as indicated in Fig. 3.5. The foUowing equation is obtained:

23
 ^DSl ~ ycSlO '^yCSS ~^GS11 ~^GS9 (3.12)

In the previous section, it is assumed that aU the tiansistors are operated in the saturation

region, except one of the tiansistors Ml 1 or MIO in Fig. 3.5 which has to be biased in

ohmic region. Note that Von = Von = VGIO, and Vsjj = VDJO. If M i l and MIO are

assumed to be biased in the saturation region, the foUowing conditions have to be

satisfied:

(3.13)

ii) ^D5io = ^sii - ^510 ^ Von " ^510 " ^7 (3.14)

Drain

Folcas

Gate

Source

Fig. 3.5. Super-MOST configuration 1. [9]

24
Reartanging tiiese two equations and summing them together yields

VV,i-Ko<0. (3.15)

However, Eq. (3.15) can not be met since the source of Ml 1 is at higher potential than the

source of MIO. It foUows that either Ml 1 or MIO cannot be operated in saturation

region. In the ohmic region, the curtent-voltage relationship is given by

l0S=^{vGS-yT-^y0S- (3.16)

Since VDS in this equation is not a constant, a closed form representation of VGS intermsof

IDS cannot be obtained.

As mentioned in the previous section, in order to satisfy the condition,

Vpsi = V,)si(sat)mm' ^ach term on the right-hand side of (3.12) has to expressed as a

function of VGSI- However, from (3.16), it is very complicated to solve for VGSI in terms of

VGSI if the corresponding ttansistor i is biased in the ohmic region.

Though this Super-MOST topology was reported to have an intiinsic gain of more

than 90 dB, there is a significant disadvantage. As concluded from the above argument, it

is difficult to obtain a suitable bias, which is determined by the W/L ratios, for a transistor

operated in the ohmic region. The design often requires "trial-and-error" steps, which

means extensive amount of simulation time to acquire proper sizes of tiansistors.

25
3.3.2 Topology 2

Another version of Super-MOST was reported in [27]. Fig. 3.6 iUusttates the

topology of this design. It employs the surular structiare of the previous design.

Transistors Ml and M2 are the main transistor and the cascode tiansistor, respectively.

The additional gain stage is composed of cascaded amplifiers that include transistors M3,

M4, M8, M9, MIO and Ml 1. The first stage consists of M3, MIO , and Ml 1. Transistors

M4, M8, and M9 form the second stage. The input tiansistors for these two stages are

M3 and M4 respectively. Transistors M5, M6, and M7 form the voltage sensing circuit,

and provide the adaptive bias voltages for the cascode current sources for the two gain

stages.

To ensure that V^ji = ^DSKsat)mm' Eq. (3.10) must be satisfied. Again KVL is

appUed around the loop as shown in Fig. 3.6. The voltage across the drain and source of

Ml, VDSI in terms of the gate-source voltage of other tiansistors, VGSI, is:

^DSl ~ 'GS3 ~\'GS4\- \J-^')

Expressing VGSI on the right-hand side of this equation in terms of VGSI, the condition for

satisfying the bias requirement, V^^, = yosusaDr^ > can be related to the sizes of the

transistors, thereby establishing design consttaint for the circuit.

It is noted from Fig. 3.6 that the ttansistor M4 has its drain connected to the lower

power supply rail. This connection may cause problems in this configuration. TypicaUy,

the buUc of M4, a p-channel ttansistor, is taken to the most positive potential. Consider

the relation of the threshold voltage, VT, to the buUc-source voltage, VBS, of a p-channel

26
 VDD

M M9 M7
^

Ml 0 h I MsSj I HM6
Drain
M2^

PMS
Folcas r"^M4
Ml M5
Gate -

Source

Fig. 3.6. Super-MOST configuration 2. [27]

ttansistor, Vj = Vj-o - Y ( V ^ + ^BS ~ V^) > a large potential difference between buUc-to-

source causes a large |Vj-|. If ^j\ > ^GS\^ the ttansistor will not be turn on or will operate

in the subthreshold region. LUce the previous design, it may be difficult to find the proper

bias to satisfy the requirement (Y^si = ^DsusaDmm ) The solution is to place tiansistor M4

in a separated well such that it wUl operate in the saturation region.

Output impedance of this cUcuit was reported to be as large as a few hundreds of

mega-ohms. However, the main shortcoming of this circuit is that ttansistor M4 need to

be placed in a separated weU. If both N-type and P-type Super-MOST have to be

implemented in the same die, Twin-Well process is required and more expensive

technology is needed.

27
3.4 Proposed New Structure

To circumvent the shortcomings of the previous two designs, a new sttucture as

shown in Fig. 3.7 is proposed in this section. This circuit comprises an adaptive biasing

feedback network and uses the principle similar to that discussed in Section 3.2.

Transistors M5-M7 form the voltage sensing circuit which adjusts the bias voltages for the

gain stage tiansistors M3-M4 and M8-M11, with respect to the change of gate voltage

of M1. This gain stage is biased in the proper region such that the drain voltage

of Ml will be maintained just above the edge of saturation. Fig. 3.8 shows the symbols

VDD
>l A
Mil M9 M7

tt

MIO MS r~^M6
Drain 1
( 1

M2 h
J

M3 ' { )
|4
i M4
'
Folcas :

Gate Ml M5
I*

Source m Vss

Fig. 3.7. Proposed Super-MOST configuration.

28
 F " G G

(a) (b)

Fig. 3.8. Symbols for (a) N-type, (b) P-type Super-MOST.

for the Super-MOST, where G is the gate, D is the drain, S is the source, and F is the

folcas which is the low impedance point of the Super-MOST.

Unlike the design in Topology 1, all the tiansistors in this circuit operate in the

saturation region. As a result, it is more easy to obtain a relationship for the ratio of W/L

of tiansistors in the feedback network than that in Topology 1, and reducing the time

required on the design. Comparing to the circuit of Topology 2, ttansistor M4 in this

circuit is a n-channel device and has its gate and drain shorted; therefore, a separated well

is not required for this ttansistor to operate in the saturation region. Therefore, this circuit

can be reaUzed in N-weU or P-well technology such that manufacturing cost can be

reduced.

29
3.4.1 Circuit Analysis

The sizes of ttansistors can be obtained by using the same principle discussed in

Section 3.2. Writing a loop equation around ttansistors Ml, M3 and M4 yields

^DSl ~ ^GS3 ~^GS4- (3.18)

kW 2
Applying the curtent-voltage relation, /^^ =(VGS -V-J-) for a tiansistor in the

saturation region, the expressions for VGSS and VGS4 in terms of VGSI are given as

^GSi ~ J r, r. VGSI y^J'^yn^ (3.19)

a n d V G 5 4 = j | 2 ^ ( ^ G 5 1 - ^ r 5 ) + ^7-4- (3.20)

kW-
respectively, where p; = '-. Substituting the expressions (3.19) and (3.20) into (3.18)

yields

A
Ps Pn (3.21)
yosi - J n VGS\ ^75 )'^^T3 ^T4'
P7 VV
VP K3 P4y

If VDSI is assumed to be just above the edge of saturation, then Vp^^ = V^^j -Fj., H- C,

where C is normally taken as few hundred mV. Equating this relation with Eq. (3.21)

gives an expression:

V P5 Pn (3.22)
^ Gsi -V
y Tl +C
^ ^ 1/ R vGSl ^TSj'^^TS ^T4-
P7 P. V P4 y

Assuming V^si - V^i = V^si "~ yrs and comparing coefficients on both sides of (3.22), the

foUowing conditions are presumed:

30
 p.
1) J l ^ = l' (3.23)

^1, (3.24)
WPS 'VP4J
iii) VV3=VV4. (3.25)

These conditions impose the design criteria on sizes of the ttansistors for tiie feedback

network to minimize the voltage across the cascoded ttansistors Ml and M2.

3.4.2 Simulation Results

Both N-type and P-type Super-MOST were designed accordmg to the conditions

given by Eqs. (3.23), (3.24), and (3.25). For the P-type Super-MOST, the n-ttansistors in

Fig. 3.7 are replaced by p-ttansistors and vice-verse. Sizes of each ttansistor are given in

Table 1. Ciurent characteristics of these two Super-MOST sttuctures were simulated in

Pspice using parameter given in the Appendix. Fig. 3.9(a) shows the current IDS of a

single n-channel ttansistor when VGS is ranging from -1.5 V to -1 V and VDS is changing

from -2.5 V to 2.5 V. Same simulation is done on the N-type Super-MOST. The result is

shown in Fig. 3.9(b). An increase in the output impedance of approximately 1000 times

compared to the single ttansistor is measured. The value is approximately 300 MQ.. For

the P-type Super-MOST, a simulation was run when the VGS is ranging from 1 V to 1.5 V;

and the results for a single p-channel ttansistor and the P-type Super-MOST are shown in

Fig. 3.10. The output impedance given from the graph of Fig. 3.10(b) is approximately

100 MQ.. Note that the satiiration voltage of these two Super-MOST is only sUghtiy

31
above that of one single tiansistor. A simple curtent mirror structure using N-type Super-

MOST was simulated. The input current level is varied from 40 |iA to 200 [xA. Fig. 3.11

Ulusttates that this current mirror has a very high output impedance. An inverting

amplifier utUizing Super-MOST is designed and simulated with 10 pF load capacitor. The

frequency response of this ampUfier is depicted in Fig. 3.12, where 100 dB dc gain is

demonstiated. Fig. 3.13 shows that the output voltage swing isfrom- 2 V to 2 V.

32
 Table 3.1. Dimensions oftiansistorsin Super-MOST.

N -Type Super-MOST
Transistor W(^m) L(|im) Transistor W(^m) L(|lm)
Ml 24 2 M7 7 2
M2 24 2 M8 6 3
M3 3 7 M9 3 6
M4 7 2 MIO 7 2
M5 3 3 Mil 4 2
M6 12 2
P -Type Sut)er-MOST
Transistor W(^m) L(|im) Transistor W(|im) L(|im)
Ml 100 2 M7 3 3
M2 100 2 M8 3 3
M3 3 7 M9 3 12
M4 4 3 MlO 6 3
M5 6 2 Mil 3 6
M6 9 3

33
2O0un

looufl-!

-Oufl +
-3.0U -2.0U O.OU 1 . OU 2.OU 3.OU
n ID(M1)
UDS

(a)

-|

-3.BU -2.0U -1.eU 0.BU 1.0U 2.aU 3.0U

ID(H2)
UDS

(b)

Fig. 3.9. Curtent-voltage characteristics of (a) a single n-ttansistor, (b) the N-type
Super-MOST with VGS ranging from -1.5 V to -1 V.

34
 3B0un

2 00uA

lOOuO.'

-Oufl-I-
-3.0U -2.8U
D -ID(M1)

(a)

200uA

m
h 1--- T __, I 1
-3.0U -2.0U -1.0U 1.0U 2.0U 3.0U
OU
o -ID(I12)
UDS

(b)

Fig. 3.10. Curtent-voltage characteristics of (a) a single p-ttansistor, (b) the P-type
Super-MOST with VGS ranging from 1 V to 1.5 V.

35
Fig. 3.11. Simulation result of the cmrent mirtor using N-type Super-MOST
with /, ranging from 40 |J.A to 200 |iA.

36
1B0T^

(100,000u,98.012)

7417n -59.089ni)

-100-1- T 1 .___, 1
lOOuHz 1.0Hz lOKHz 100MHz I.OTHz
db(U(4})
Frequency

Fig. 3.12. Frequency response of the inverting ampUfier.

4.01I--

(-1.2001,1.9667)

OU-

(-1.1998,-1.9659)

-k.W + I 1
-1.25U -1.20U -1.15U
a U(l)
UIN

Fig. 3.13. Output voltage swing of the inverting ampUfier.

37
 CHAPTER IV

DESIGN OF FULLY DIFFERENTIAL OPERATIONAL AMPLIFIER

As pointed out in Chapter n, compromise between dc gain and speed often has to

be made in an operational ampUfier design. It is difficult to maximize one characteristic

without sacrificing the other. A solution to this problem by using gain boosting technique

to improve the dc gain without penalty in speed has been proposed [9]. When used in

operational ampUfier design, tiiis technique results a combination of tiie high-frequency

behavior of a single-stage operational amplifier with a dc-gain compatible to a multi-stage

ampUfier design.

This chapter presents the design of a fully differential amplifier that incorporates an

architecture similar to [9]. Process parameters are supported by one of the vendors of

MOSIS, Orbit. Most of the designs described in this chapter are computer-simulated

using the device parameters provided for the process. Analog Low Noise 2 |Lim

technology. The Usting of the parameters is given in the Appendix.

Section 4.1 examines the design considerations for an operational ampUfier which

is used in switohed capacitor circuits. Sections 4.2 to 4.3 describe the main circuit, the

bias circuit, and the common-mode feedback circuit. Computer simulation results are

presented in Section 4.4.

38
4.1 Design Considerations

Operational ampUfier is often found in switched capacitor filter and Analog-to-

Digital (A/D) or Digital-to-Analog (D/A) architectures, but the requirements for the

ampUfier in these two appUcations are different. An operational amplifier in a switched

capacitor filter usually has to deal only with small changes in the output during any

particular clock cycle because the sampling frequency is usually much greater than the

signal bandwidth. In conttast, an operational amplifier in an A/D or D/A must be able to

drive large output swing in one clock period. For smaU signals, the settiing time of an

operational amplifier is mainly dependent on the bandwidth of the amplifier. On the other

hand, for large signals, the slew rate of the amplifier becomes a major conttibutor to the

settiing time. Therefore, both high slew rate and wide bandwidth are important factors in

choosing the right architecture for the amplifier in an A/D or D/A converter. In the

switched capacitor designs, only bandwidth of an amplifier is the determining factor.

Besides the slew rate and the bandwidth, open loop gain is another important

factor in choosing the right architecture for an operational ampUfier. The switched

capacitor technique is based on the idea that a capacitor is periodically switched and can

be arranged to cause packets of charge to be tiansferted between two circuit nodes.

These operations assume that the operational ampUfier has infinite gain. In reaUty,

however, most MOS operational amplifiers have relatively low gain, typically in the range

of 1000. The effect of finite gain of an operational amplifier on a switched capacitor

integrator has been discussed in [28] and [29]. In an A/D or D/A converter, the linearity

of the conversion [30] determines the gain requkement of an operational amplifier which

39
incorporates switched capacitor technique to perform multiplying or sampUng function. It

is concluded that high loop gain of the operational amplifier conttibutes to better

performances.

One of the goals of this thesis is to design an operational ampUfier as a buUding

block which can be used in any switched capacitor designs. Thus the configuration of the

amplifier need to meet tiie gain and speed requirements to achieve optimal performance in

the switched capacitor circuits.

4.2 Operational Amplifier Architecture

In Chapter n, various architectures of operational amplifier and the corresponding

advantages and disadvantages were discussed. The selection of the architecture for the

operational ampUfier is briefly discussed.

4.2.1 Comparisons of Single Stage and Two Stages Implementation

The single stage configuration, which is a folded cascode structure, seems to be a

logical choice for designing a building block mainly because of two reasons. First, unlike

the two stages configuration which is frequency compensated by a pole spUtting capacitor,

the load capacitor acts simultaneous as the compensation capacitor in a single stage.

Thus, the folded cascode configuration simpUfies the compensation scheme especiaUy

when the load consists of a smaU capacitor, and it also imposes less constiaints on the

output load capacitance. Second, the slew rate of the operational ampUfier in a single

stage is determined by the load capacitor (CL); on the other hand, for a two-stages

40
configuration, it is Umited by the biasing curtent of the first stage and the compensation

capacitor (Cc). The slew rate (SR) of these two configurations are given as

Single Stage: SR= ,

Two Stages: SR = ,

where / is the bias curtent. GeneraUy, the slew rate is faster in the single stage than in the

two stages configuration.

4.2.2 Comparisons of Single Ended and Differential Implementation

Though a single ended implementation requires approximately half the hardware of

a fuUy differential approach, and is usuaUy significantiy less complex, for example, no

common-mode feedback circuitty is required, a fully differential architecture is employed

in the design of the operational amplifier because of certain advantages. First, in circuits

where supply voltage has to be reduced to consume less power, dynamic range becomes

critical. In this case, a differential implementation is preferred over a single ended because

the output signal swing is doubled, whUe the magnitude of the input-referred operational

amplifier noise remains the same, giving a 6 dB improvement in operational ampUfier noise

Umited dynamic range. Second, the first order charge injection effect from MOS ttansistor

switches is canceled due to the inherentiy differential nature of the circuit. Third, the

power supply rejection ratio is higher for a differential architecture than a single ended

structure.

41
4.3 Circuit Description

The operational amplifier consists of three parts, the main stage, the bias circuit,

and the common mode feedback circuit.

4.3.1 Main Stage

The main stage of the operational amplifier, shown in Fig 4.1, is a folded cascode

configuration. The load branch and the taU current source are different from the

conventional design. Blocks SM5 - SM8 act as the load of the amplifier. Block SM9 is

the tail ciurent of the differential amplifier which consists of ttansistors Ml to M4. Blocks

SM5 - SM9 are the Super-MOSTs. The reason of using Super-MOST instead of a single

ttansistor is because of its high output impedance. The dc gain (Av) and common mode

rejection ratio (CMRR) of the operational amplifier are benefited from the use of Super-

MOST because these two characteristics are related to the equivalent impedance seen by

the input tiansistor at the drain and the tail current source. They can be approximated as

A^=2g/,, (4.1)

CMRR = g^,r^ (4.2)

where

gmi : tiansconductance of the input n-channel ttansistor,

rds9: output impedance of ttansistor SM9,

Vout: equivalent impedance seen by the input ttansistors Ml or M2 at the drain.

Botii of these equations indicate that high output impedance is desired. As described in

Chapter ID, the Super-MOST has an output impedance at least hundred times larger than

42
 'DD

VcM
PM2_ I M4

SM5 SM7

H I MI M2 I H' I' Vo,

Vn -

SM6 SM9 SM8

- Vss

Fig. 4.1. Main stage of tiie fuUy differential operational amplifier.

a single ttansistor while increases the voltage across the drain and source by only one

VoSfmin)-

For the input differential pair, normal ttansistors are used instead of Super-MOST.

This is because there is no significant advantage of using Super-MOST over normal

ttansistors for the input pair Ml and M2 but more severe mismatch problems are resulted.

It can be proved that equivalent ttansconductance of the Super-MOST (gmeff) is close to g^

of a single ttansistor assuming that the main ttansistor Ml of the Super-MOST has the

same size and bias curtent. From the simplified configuration of the Super-MOST shown

in Fig. 4.2, the effective ttansconductance can be derived as

43
 'DD

Vss

Fig. 4.2. Equivalent circuit of the Super-MOST.

^ iSn.2rdsM + l) + r^Jr^2)
(4.3)
""' ^"fe2^..(A + l) + r,,/r,,-Hl)=^-'

where

A : gain of the feedback amplifier within the Super-MOST,

gmi : ttansconductance of ttansistor Ml in the Super-MOST,

gm2'-ttansconductanceof ttansistor M2 in the Super-MOST.

From (4.3), it can be concluded that the use of Super-MOST in the input pair does not

increase the dc gain of an operational amplifier.

Super-MOST inherentiy display somewhat higher input offset voltage than normal

tiansistors for the same level of geometric mismatch or process gradient. The reason for

this is perhaps best understood by means of the conceptual circuit shown in Fig. 4.3. Here

the input active devices are biased at a curtent / and display a ttansconductance gm- If the

44
load elements, in this case assumed to be resistors, are assumed to have a A percentage

mismatch, then in order for the output voltage of the differential ampUfier to be zero, the

absolute difference in the curtents in the two devices must be equal to A/. This in turn

requires that the dc input difference voltage applied to bring about this difference be

(4.4)
o m

Thus, the input offset in this case depends on the I/gm ratio of the active devices. As it can

be seen from (4.3), variation of gme^is normaUy smaller than gm of a single ttansistor

assuming the same level of geometric mismatch. A similar dependence is found for

mismatches in many of the parameters of the active devices themselves, such as channel

length and width mismatches, as well as the threshold mismatch.

-Vr

R: Ri

-I-,

gmVi gmV2l
Q o
-I-
V2 ^

0
Fig. 4.3. Equivalent circuit for the input differential paU.

45
 The inputttansistorsMl and M2 are NMOS rather than PMOS because less area

is required to obtain an equivalentttansconductancefor the same bias curtent as indicated

by

gnt = J ^ ^ > (4.5)

where k is the process gain factor \i/tox, and it is usually 2-3 times larger for a n-device

than for a p-device.

It is seen from (4.1) and (4.2), the dc gain and common mode rejection ratio of the

operational amplifier are increased by the magnitude of output impedance of the Super-

MOST, which is more than hundredtimesthan the conventional design. The dc gain of

the operational ampUfier can be derived from its differential half equivalent circuit as

shown in Fig. 4.4 as

A,=-2g,(g,,,(A + l)r,o,-HK, (4.6)

where

A : gain of the feedback amplifier within the Super-MOST,

gmi :tiansconductanceof the input pairtiansistorMl or M2,

gsM -tiansconductanceoftiansistorM2 in the Super-MOST M5,

KM : output impedance oftiansistorM2 in the Super-MOST M5,

r,: equivalent impedance at node 1.

The equivalent impedance is given by

nn=igdsl+8ds3+8s0lT^ ('^'7)

46
 Fig. 4.4. Small signal equivalent half circuit of the main stage.

where goi and gos are the output conductance of tiansistor Ml and M3 respectively, and

gs02 is the output conductance of ttansistor Ml in the Super-MOST M5.

The bias voltages Vp and Vn need to be optimized so as to (i) maximize the input

common mode range and output voltage swing of the operational amplifier, (ii) minimize

the size of ttansistors. These voltages need also to be greater than threshold voltage to

ensure that all ttansistors are biased in the saturation region. Since the supply voltage is

2.5 V, Vp and V are set at + 1.2 V and - 1.2 V, respectively, to fulfiU these consttaints.

The bias current for the input differential amplifier and the load is related to (i) slew rate,

(ii) dc gain, and (iu) power dissipation as discussed in Chapter II. In order to achieve a

balance among large slew rate, high dc gain, and low power dissipation, a current level of

130 |LiA is selected.

47
4.3.2 Bias Circuit

The bias circuit for the main stage is shown in Fig. 4.5. It consists of six

ttansistors to set up the two bias voltages Vp and K. AU the ttansistors in this circuit are

implemented as active resistors by connecting their gate to the drain. Transistors Ml, M2,

and M3 are biased to set Vp at -H 1.2 V and - 1.2 V is taken from the bias point Vn of

ttansistors M4, M5, and M6. This circuit utiUzes two branches of ttansistors ratiier than a

single branch even though the two bias voltages can be set up by a single branch. The

drawback is because a voltage of 2.4 V has to be dropped across the middle ttansistor of a

single branch and so that the length of tiiis ttansistor need to be very long. Therefore, a

single branch implementation does not reduce the utUized area. On the other hand, larger

variation in the bias points, which is due to process gradients, may arise from using a

single branch.

v.DD
? M3 M6
S
V

c M2
M5 1
Vn

jMl
.M4 D
'SS

Fig. 4.5. Bias cUcuit

48
4.3.3 Common Mode Feedback Circuit

There is an inherent problem of using fully differential configxttation. The output

common mode level is not weU-defined if the circuit is used in closed loop form. This can

be best understood conceptually by considering the circuit of Fig. 4.6. When reset

switches Si and S2 are on, the ampUfier becomes unity gain differential feedback. Since

Ibias must balance (IDS +104), Vx and Vy are not well defined. For example, if hias is sUghtiy

less than {IDS + ID4), the output nodes approach VDD, driving M3 and M4 into Unear

region. WhUe the feedback simply senses die difference between Vx and Vy and is

therefore unable to correct the common mode level. For this reason, differential

operational ampUfiers need to employ a common mode feedback networks to achieve a

stable common mode level.

The principal issue in the design of common mode feedback networks is that they

must maintain a constant common mode level even for large differential voltage swings.

Primarily, there are two approaches to realize these networks. The first approach, which

is usually incorporated in switched capacitor circuits, is to utUize capacitors network to

sense and correct the common mode level [31]. However, this approach requires

refreshing period to charge the capacitors to a proper voltage and so it implies that it

operates in discrete time domain. The second approach is to employ sensing amplifier to

tiack the output voltages to maintain the common mode level [32], [33]. Unlike the

previous approach, this does not require separate circuit to contiol the period of

refreshing, but the tiansient response is usuaUy slower.

49
 Since the second approach requires a simpler configuration, it is used in the design

of the common mode feedback circuit. Fig. 4.7 illustiates the circuit schematic which

consists of two differential pairs (Ml, M2 and M3, M4), two tail current sources (M7 and

M8), and a curtent mirror load (M5, M6). In this circuit, the two differential pairs sum

their differential curtents into the current mirror load with the output taken from M6. The

common mode voltage is held at a reference potential VCM which is usuaUy the analog

ground in order to maximize the output voltage swing.

- V DO

M3
5 MA
5
_S^^, X Y ,V^

P
MI M2

Vs

Fig. 4.6. SimpUfied configuration of a fully differential switched capacitor network.

50
 S^
M5
7"
I M6
'DD

'CM

s Ml M2 M3 M4

P^
V,

Vn - _M1. Qi,

-Vss

Fig. 4.7. Common mode feedback circuit

51
4.4 Simulation Results

The complete operational amplifier design was simulated in Pspice using the

process parameters Usted in the Appendix. The simulatedfrequencyresponse of the

amplifier witii load capacitance variedfrom0 to 20 pF is depicted in Fig. 4.8 where a dc

gain of 98 dB is shown in part (a) and it can be seen in part (b) that there is at least 45

degrees of phase margin with various load. Thetiansientresponse with a small signal (+

0.2 V) and a large signal ( 1.5 V) step input are shown in Fig. 4.9. The output voltage

swing is shown in Fig. 4.10. Thetiansientresponse with 5 mV sine wave input is shown

in Fig. 4.11. An integrator and a differentiator implemented by using the operational

amplifier were simulated and the results are depicted in Fig. 4.12 and Fig. 4.13,

respectively. The sizes of thettansistorsare given in Table 4.1. The summary of the fuUy

differential operational amplifier is shown in Table 4.2.

52
-80 I-
leOuHz LOHz 1QKHZ 1OOMHz
a o ^ JL o db(U(3) - U ( 6 ) )
Frequency

(a)

8dT

-2aodH

-40flcl-l-
lOOuHz 1.0Hz 10OtiHz 1.OTHz
D 0 V A o p(U(3)-U(6))
Frequency

(b)

Fig. 4.8. Frequency response of tiie fuUy differential operational ampUfier

(a) magnitude plot, (b) phase plot.

53
 257.78nU r-

8U-1 Probe Cursor

D1 = 10.077U, 204.826m
D2 = lO.OOOu, - 1 9 9 . 9 9 7 m
dif= 77.382n, 404.823m

- 2 3 7 . BiinU "- -i---

9.691us lO.OOOus 10.400US 10.6ii3us
i^jUO) -U(6) o U(oin-) -U(uin+)
Time

(a)

1.816U -

Probe Cursor
OUH
K1 = 9 0 . 1 2 7 U , 776.971n
K2 = 9 0 . 0 1 8 U , -1.4483
dif= 116.888n, 2.2253

-1.751U '
89.Q16US 9Q.008US 91.000US
rD"iU(3) -U(6)
Tine

(b)

Fig. 4.9 Step response of the fuUy differential operational ampUfier with
(a)0.2V,(b) 1.5 V input.

54
4.0UT

(100.000u,2.2672)

0U-I

(-77.157u,-2.2318)

-4.8U-I- r--- _ _ i I 1
-2e0nU -leenu 8U leonu 2e0mU
D U(3) -U(6)
uin

Fig. 4.10. Output voltage swing of the fully differential operational amplifier.

55
2.0U-

-2.0U-I- 1 n T- r-
Os lOus 20us 30us 40us SOUS
Q U(3) - U ( 6 ) 0 250(U(13) -U(12))
Tine

Fig. 4.11. Transient response with 5 mV sinusoidal input.

56
 20OIIIUT

TTn

0U \i = } M e g , t: = 0 1 uH

-200nU-"
R = 2 Meg, C = 0 0 1 uF;

-488nU-l- 1 1- 1--- I H
Os 0.2s 0.4s 0.6s 0.8s 1.0s
U(6)-U(3) V A 1B(U(win+)-U(uin-))
Tine

Fig. 4.12. Output response of an integrator implemented with the operational amplifier.

4.0U-

MSL

OU
"WuT

R = 2 neg, C = 0.01 uF

_ _ i
-4.0U+ r r r
Os 0.25 0.4s 0.6s e.8s 1.0s
U(6)-U(3) 0 100(U(uin+)-U(uin-))
Tine

Fig. 4.13. Output response of a differentiator implemented with tiie operational amplifier.

57
 Table 4.1. Dimensions of ttansistors in tiie operational ampUfier.

SM5, SM7 SM6, SM8 SM9

W(^im) L(|im) W(|im) L(|Lim) W(|im) L(|j,m)
Ml 38 2 Ml 160 2 Ml 75 2
M2 38 2 M2 160 2 M2 75 2
M3 3 6 M3 3 7 M3 3 7
M4 9 2 M4 4 3 M4 6 2
M5 3 3 M5 10 2 M5 3 3
M6 12 2 M6 9 3 M6 10 2
M7 7 2 M7 3 2 M7 6 2
M8 6 2 M8 3 3 M8 4 2
M9 3 7 M9 3 8 M9 3 7
MIO 7 2 MIO 6 3 MIO 7 2
Mil 4 2 Mil 3 5 Mil 4 2
CMFB Bias Stage Input Pairs
W(^im) L(|j,m) W(^m) L(|j,m) W(|im) L(|im)
Ml 60 2 Ml 34 4 Ml 300 2
M2 60 2 M2 11 9 M2 300 2
M3 60 2 M3 8 4 M3 160 2
M4 60 2 M4 34 4 M4 160 2
M5 24 2 M5 9 25
M6 24 2 M6 8 4
M7 6 2
M8 6 2

58
Table 4.2. Summary of fuUy differential operational amplifier performance.

Simulated ampUfier performance

Supply voltage 2.5V

Bias curtent 250 |iA

Power dissipation 3mW

Load capacitance 10 pF

Open loop gain 98 dB

Unity gain bandwidth 17 MHz

Slew rate 22 V/|is

0.2 V output settle within 0.1 % 80 ns

PSRR+(0) >200 dB

PSRR-(O) >200 dB

CMRR >200 dB

Input common mode range -1.5 V 1 . 9 V

Differential output voltage swing -2.23 V 2.27 V

59
 CHAPTER V

EXPERIMENTAL RESULTS

This chapter describes the implementation of the Super-MOST and the operational

amplifier. Botii of the sttuctures were integrated on a tiny chip that was fabricated by

Orbit 2 |j,m Low Noise Analog CMOS technology, supported by MOSIS. The description

of the layout for a prototype implementation is presented in the next section. The test

setup is described in Section 5.2. Experimental results are presented in Section 5.3.

5.1 Description of Experimental Chip

The layout of the chip is shown in Fig. 5.1. The chip is designed to be mounted on

a 40-pin tiny chip package. Four separated circuits are put in the prototype chip. The

complete fully differential operational ampUfier is seen on the top of the chip. Below this

circuit is the operational ampUfier design without the bias cUcuit. The bias voltages are

taken from external supply so that the operational amplifier design can be verified. The N

type Super-MOST is at bottom left; and the P type Super-MOST is at bottom right. The

die photo of the experimental chip is shown in Fig. 5.2.

The layout of the tiansistors in the chip uses the foUowing guideUnes to minimize

component mismatch and noise injection problems:

i. wide tiansistors are spUt into parallel connection of smaUer ttansistors,

u. matched ttansistors, such as the input differential pans, are artanged in common

centioid symmetty,

60
ui. WeUs and Guard Rings are placed at critical parts to shield noise injected from

the substtate and crosstaUc.

Two types of pads, which are supported by MOSIS, are used for the interface

between ckcuits and pins in the chip. Power pad, a sandwich of two metal layers, is used

for the connection of power supply, and bias voltages to the cUcuits. To buffer tiiose

varying signals (V,, V<,, of the operational ampUfier; VG , VD of the Super-MOST) from

damaging the circuitry inside tiie chip, analog I/O pad is used. This pad consists of diode

connected ttansistors and resistors for curtent limitation.

5.2 Test Setup

This chip is designed to be operated with + 2.5 V supply. Two 2.5 V voltage

sources are connected in series to give 2.5 V with the analog ground taken from the

middle point.

Transistor Curve Tracer is used to characterize the current-voltage relationship of

the Super-MOST. A step voltage generated from the Curve Tracer is applied to the gate

of the Super-MOST. This voltage is set to vary from 0 V to 2.6 V with 0.2 V increment

for each step. The current-voltage characteristic curve is displayed on the screen of the

Curve Tracer and is then recorded by an oscUloscope camera.

A 5 MHz function generator is used to apply a differential analog input signal,

which includes a sinewave and frequency varied sinewave, to the operational amplifier.

The differential output from tiie operational amplifier is measured by an 100 MHz

oscUloscope, and is recorded by a camera.

61
5.3 Test Results

The current-voltage characteristics of the N-type Super-MOST is illusttated in

Fig.5.3 where the scale of the horizontal (x) axis is 0.5 V/div and the scale of vertical (y)

axis is 50 [O-A/div. It can be seen tiiat IDS = OA if VGS ^ 0.8 V and VDS(SAT) is close to

VDS(SAT)min of a slugle tiauslstor; for example, the second curve from the x-axis

cortesponds to VDS(SAT) = 0.5 V and VGS = 1.4 V when V,h = 0.9 V given from the process

parameters. The slope shown on each curve is caused by the caUbration error of the

Curve Tracer; otherwise, the graph exhibits large output impedance. Fig. 5.4 shows the

results of the measurement of the P-type Super-MOST. The x-axis is 1 V/div scale and

the y-axis is 200 |J,A /div. SmaUer curtent and larger VDS(SAT) are exhibited in this graph

compared to Fig 5.3 for the same VGS- However, as indicated from this graph, the output

impedance is quite large for the P-type Super-MOST.

Shown in Fig. 5.5 and Fig. 5.6 are the oscillographs of the input and output

waveforms of the operational ampUfier. In Fig. 5.5(a), the larger amplitude sinusoidal

waveform is the input signal witii amplitude of 240 mV and frequency of 2 kHz while the

smaUer one is the output with approximated 2 V in ampUtude and same frequency but a

smaU phase shift. In Fig. 5.5(b), an amplitude of 240 mV and a frequency of 200 kHz

input signal (the larger ampUtude waveform) generates a phase shift output with amplitude

of approximated 1.8 V and witii the same frequency. These two figures indicate that the

phase shift of the output increases when tiie frequency of tiie input increases. The

oscUlographs in Fig. 5.6 show tiie frequency response of tiie operational ampUfier. Ui Fig.

5.6(a), the input frequency varies in the range of hundred-kilo-Hz and in Fig. 5.6(b) in the

62
range of mega-Hz. Botii graphs iUusttate that the output gain decreases as the input

frequency increases. From the results of Fig. 5.5 and Fig. 5.6, it can be concluded that the

operational ampUfier exhibits good performances in low frequencies.

63
Fig. 5.1. Layout of the experimental chip.

64
Fig. 5.2. Die photo of tiie experimental chip.

65
Fig. 5.3. Measured current-voltage characteristics of N-type Super-MOST.

rt(MtMMMMktMtfMHM*HMM^M^

Fig. 5.4. Measured curtent-voltage characteristics of P-type Super-MOST.

66
 (a)

(b)

Fig. 5.5. Input and output waveforms of the operational ampUfier for (a) frequency of
2 kHz, and (b)frequencyof 200 kHz.

67
 im ii/ mus
IliintnillMilfflHI;!
iliiiiiiiiiiijijiiiyr
nnk^mUmUmmml

ii iiuuilmmmim

(a)

i w iv a^

I f uhlilnnMlHlHuiHH

(b)

Fig. 5.6. Input and output waveforms for frequency varied sinusoidal signal in the range
of (a) hundred-kilo-Hz, and (b) mega-Hz.

68
 CHAPTER VI

CONCLUSION

In high precision appUcations, operational ampUfiers are required to attain high

gain and high speed. However, most of the operational amplifier topologies suffer

ttadeoff between these two requirements. Obtaining both requirements becomes a

difficult task that requires a compUcated circuit architecture and often results in

degradation in other characteristics.

An improved cascode circuit employing the gain boosting technique is inttoduced

in this work. With an active feedback amplifier maintaining the voltage at the drain of the

main ttansistor of the cascode circuit, the output impedance is enhanced by a factor of the

gain of the amplifier over a simple cascode circuit. Since an adaptive sensing network that

biases the ampUfier is able to ttack the input gate voltage such that the two cascode

ttansistors are operated in the saturation region, the cascode ckcuit can be function as a

single ttansistor. Simulation results have demonstiated that the cascode circuit obtains an

output impedance in the order of 100 MQ with a saturation voltage sUghtiy above a single

ttansistor; and has a superior performance when implemented in a current mirror or an

inverting ampUfier

A fuUy differential operational ampUfier which incorporates the cascode circuit in

the topology has been presented. For the purpose of acting as a building block in an

analog system, the operational amplifier must be able to drive various capacitive load

without degradation in performance. Close examination of different topologies concludes

69
tiiat the folded cascode structure is a feasible choice. However, a gain enhancement for

this folded cascode topology is required and is obtained through the high output

impedance of the cascode circuit. Also the common mode rejection ratio and the power

supply rejection ratio are improved by employing the cascode circuit as the tail current

source. In order to maintain the common mode output voltage of a fully differential

amplifier, a common mode feedback stage is required. This common mode feedback stage

is implemented by using two differential pairs.

An experimental chip was fabricated in a 2 [xm N-weU technology. This chip

consists of both N-type and P-type Super-MOST, and the fuUy differential operational

amplifier. Experimental results show that the Super-MOST circuits have an output

impedance in the order of 100 MQ, and the fuUy differential operational ampUfier has

good performance in low frequencies.

70
 REFERENCES

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[9] K. Bult and G.J.G.M. Geelen, "The gain boosting technique," Analog Integrated
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[10] P.R. Gray and R.G. Meyer, "MOS operational amplifier design-a tutorial
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[12] S.M. MaUya and J. H. Nevin, "Design procedures for a fuUy differential folded-
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[13] S. Franco. Design with Operational Amplifier and Analog Integrated Circuits.
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[15] J.E. Solomon, "The monoUthic op amp: A tutorial study," IEEE. J. Solid-State
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[ 16] B.K. Ahuja, "An improved frequency compensation techiuque for CMOS
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[17] H. Ohara et al., "A CMOS programmable seif-caUbrating 13-bit eight-channel data
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[18] J.N. Babanezhad, "A raU-to-rail CMOS op amp," IEEE. J. Solid-State Circuits, vol
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[19] Ruud G.H. Eschauzier, L.P.T. Kerklaan, and J.H. Huijsing, "A 100-Mhz 100-dB
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[20] Ruud G.H. Eschauzier, R. Hogervorst, and J.H. Huijsing, "A programmable 1.5 V
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73
 APPENDIX

MOSIS PROCESS PARAMETER

74
 MOSIS PROCESS PARAMETER

RUN: N57V VENDOR: ORBIT

TECHNOLOGY: SCNA20 FEATURE SIZE: 2.0 microns

N57V SPICE LEVEL2 PARAMETERS

.MODEL CMOSN NMOS LEVEL=2 PHI=0.700000 TOX=4.4900E-08 XJ=0.200000U

TPG=1
+ VTO=0.8836 DELTA=2.3180E-i-00 LD=2.2580E-07 KP=4.7767E-05
+ UO=621.1 UEXP=1.5300E-01 UCRIT=9.1900E-I-04RSH=2.52E+01
+ GAMMA=0.6621 NSUB=7.8110E-hl5 NFS=7.1500E+11 VMAX=6.5940E+04
+ LAMBDA=3.2490E-02 CGDO=6.12E-10 CGSO=6.12E-10
-H CGBO=3.4595E-10 CJ=1.12E-04 MJ=0.95 CJSW=4.30E-10
-fMJSW=0.455PB=0.61
* Weff = Wdrawn - Delta_W
* The suggested Delta_W is 2.6460E-09

.MODEL CMOSP PMOS LEVEL=2 PHI=0.700000 TOX=4.4900E-08 XJ=0.200000U

TPG=-1
+ VTO=-0.8459 D E L T A = 4 . 2 9 0 0 E - K 0 0 LD=2.3460E-07 KP=1.5574E-05
+ UO=202.5 UEXP=2.5600E-01 UCRIT=1.2610E-h05 RSH=5.94E+01
+ GAMMA=0.6851 NSUB=8.3620E+15 NFS=1.0830E+11 VMAX=9.9990E+05
+ LAMBDA=4.3760E-02 CGDO=6.12E-10 CGSO=6.12E-10
+ CGBO=3.8732E-10 CJ=3.24E-04 MJ=0.633 CJSW=1.89E-10
+ MJSW=0.929 PB=0.90
* Weff = Wdrawn - Delta_W
* The suggested Delta_W is -2.7000E-07

75
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