Section 5 - 5 Biasing in BJT Amplifier Circuits Lecture

4/6/2011 section 5_5 Biasing in BJT Amplifier Circuits 1/1
5.5 Biasing in BJT Amplifier Circuits
Reading Assignment: 436-442
Now lets examine how we DC bias BJTs amplifiers!
HO: A GRAPHICAL ANALYSIS OF BJT AMPLIFIERS
If we dont bias properly, distortion can result!
EXAMPLE: AMPLIFIER DISTORTION
There is a classic bias circuit for BJT amplifiers; lets see what it
is!
HO:DC BIASING USING A SINGLE POWER SUPPLY
We can also use a DC current source to bias the BJT.
HO:BJT BIASING USING A CURRENT SOURCE
Lets do an example DC bias design.
EXAMPLE: SINGLE-SUPPLY DC BIAS
Jim Stiles The Univ. of Kansas Dept. of EECS

4/6/2011 A Graphical Analysis of a BJT Amplifier lecture 1/18
Graphical Analysis of a BJT

Amplifier
VCC
Consider again this simple BJT amplifier:
RC
iC vO (t ) = VO + vo (t )
RB +
We note that for this vCE
amplifier, the output
voltage is equal to the
+ vi (t )
collector-to-emitter
voltage (vO (t ) = vCE (t ) ).
+
VBB


y = m x + b
If we apply KVL to the collector-emitter leg, we find:
VCC iC RC vCE = 0
We can rearrange this to get an expression for the collector current iC in

terms of voltage vCE (i.e., iC = f (vCE ) ):
1 VCC
iC = vCE +
RC RC
Note this is an equation of a line!
1 VCC
iC = vCE +
RC RC
y = m x + b

The load line

This equation is referred to as the amplifiers load line, which we can graphically
represent as:
y = iC
VCC
b=
RC
1
m=
RC
x = vCE
VCC
The load line provides the circuit relationship (via KVL) between iC and vCE .
The value of iC and vCE must lie somewhere along the load line!

iC vs vCE for a BJT

Exactly where on the load line depends on the device (BJT) relationship between
iC and vCE .
Recall that this relationship is:
iC
active
saturation
vCE
The value of iC and vCE must also lie somewhere along this device curve!

Sort of like the Grandview triangle
Q: How can the values for iC and vCE simultaneously be a point on the load line,
and a point on the device (BJT) curve?
A: Easy! the values for iC and vCE lie at the point where the two curves
intersect!
iC
VCC
iC ,vCE
RC
vCE
VCC

But it all depends on the input!

Of course, the values of iC and vCE depend on the input to the amplifier:
v I (t ) = VBB + vi (t )
As the voltage v I (t ) changes, so will the values iC and vCE .
Note, however, that the load line will not changethe slope 1 RC and y-
intercept VCC RC are independent of voltage v I (t ) .
What does change is the BJT relationship between iC and vCE .
For example, in active mode, the collector current iC is independent of vCE (were
ignoring the Early effect)!
However, the collector current iC of a BJT is dependent on the voltage base-to-

emitter v BE .
Thus, as v I (t ) changes, so does v BE , resulting in a new BJT relationship (curve)

between iC and vCE .

ic changes as the input changes

Graphically, we can represent this as:
iC
vI 3 = vI (t3 )
vI 2 = vI (t2 )
vI 1 = vI (t1 )
vCE
where VI 1 , VI 2 , VI 3 are three different input voltages such that VI 1 <VI 2 <VI 3 .
Thus, as the input voltage v I (t ) changes with time, the BJT iC versus vCE curve
will change, and its intersection with the amplifier load line will changeiC and
vCE will likewise be a function of time!

The operating point

Say that the small-signal input voltage is zero (vo (t ) = 0 ).
In this case, the input voltage is simply a constant bias voltage (v I (t ) = VBB ).
The collector current and voltage collector-to-emitter are likewise DC bias

values ( IC and VCE ).
The intersection of the two curves in this case define the operating point (bias
point, Q point) of the amplifier.
iC
VCC
Q po int
RC
IC vI =VBB
vCE
VCC
VCE

What happens if you make IB too large

Q: I see! We know that a large DC collector current results in a large
transconductance gma result that is typically required for large voltage gain.
It appears that we should make VBB (and thus IC ) as large as possible, right?
A: NO! There is a big problem with making the bias voltage VBB too largeBJT
saturation will result !
We can graphically show this unfortunate occurrence:
iC
VCC v I = VBB (large!)
RC
IC
saturation
vCE
VCE 0.2 V VCC

Theres still a problem

A BJT in saturation makes a poor amplifier!
Q: Oh I see! We need to set bias voltage VBB to be large, but not so large that
we push the BJT into saturation, right?
iC
VCC active
RC v I = VBB (large)
IC
vCE
VCE > 0.7 V VCC
A: NO!! There is a big problem with this strategy as well!
Remember, it is the total input voltage that will determine the BJT curve. If
we DC bias the amplifier so that it is nearly in saturation, then even a small
voltage vi can push the BJT into saturation mode.

A little more than bias;

then a little less than bias
For example, recall that the small signal input vi (t ) is an AC signal. In other
words its time averaged (i.e., DC ) value is zero, meaning that the value of vi (t )
will effectively be negative half of the time and positive the other half.
Say then that the magnitude of the small signal input is limited to a value vi :
vi (t ) vi
So that:
vi vi (t ) vi for all time t
and thus:
VBB vi v I (t ) VBB + vi for all time t
Lets now look at three scenarios for the small-signal input voltage vi :
1) vi = vi 2) vi = 0 3) vi = +vi

Were hitting the floor

The resulting output voltage will of course be different for each case:
iC
VCC vI =VBB + vi
RC
v I = VBB
vI =VBB vi
vCE
0.2 V VCC
VCE vCE = VCE vo
Look what happened here!
If the input small-signal is large and positive, the total input voltage ( and thus
total vBE) will be too large, and thus push the BJT into saturation.

Distortion!!!!!!!!
The output voltage in this case (when v I =VBB + vi ) will simply be equal to:
vO (t ) 0.2 (BJT saturated)
as opposed to the ideal value:
vO (t ) =VCE + vo (BJT active)
where vo = Avo vi . Note for this amplifier, the small-signal voltage gain Avo is
negative, so that the value vo is also negative:
vo = Avo vi < 0
Since the BJT is in saturation during some portion of vi (t ) , the amplifier output
signal will not look like the input signaldistortion will result!

I never said this was easy

Q: Now I get it! We need to make VBB small, so that the BJT does not enter
saturation, and the output signal is not distorted!
A: NO!! There is a problem with this too!
We can again graphically examine what happens if we make the bias voltage VBB
too small.
iC
VCC
RC
vI =VBB + vi
v I = VBB
vCE
vCE = VCE + vo VCE
v I = VBB vi vCE = VCC
Look what happened here!

Now were hitting the ceiling

If the input small-signal is large and negative, the total input voltage ( and
thus total vBE) will be too small, and thus push the BJT into cutoff.
Note the collector current will be zero (iC = 0 ) when the BJT is in cutoff!
The output voltage in this case (i.e., when v I = VCE vi ) will simply be equal to:
vO (t ) = VCC (BJT cutoff)
as opposed to the ideal value:
vO (t ) =VCE vo (BJT active)
where vo = Avo vi . Note for this amplifier, the small-signal voltage gain is
negative, so that the value vo is positive.
Since the BJT is in cutoff during some portion of vi (t ) , the amplifier output
signal will not look like the input signaldistortion will result!

What do we do?
Q: Yikes! Is there nothing we can do to avoid signal distortion?
A: To get allow for the largest possible (distortion-free) output signal vo (t ) , we

typically need to bias our BJT such that we are about half way between
biasing the BJT in saturation and biasing the BJT in cutoff.
Note if the BJT is in saturation:
VCC
iC
RC
(BJT saturation)
vCE 0.2 V

Bias in the middle

Whereas, if it is in cutoff:
iC = 0
(BJT cutoff)
vCE =VCC
It is evident that for this particular amplifier, biasing half-way between

saturation and cutoff means biasing such that:
VCC
VCE
2
or equivalently:
VCC
IC
2RC

iC
The output is maximized
Q po int
VCC
RC
vI =VBB + vi
VCC
2RC vI =VBB
vI =VBB vi
vCE
VCC VCC
vCE = VCE + vo VCE =
2 vCE = VCE v o
The bias solution above is optimal for this particular amplifier design. Other
amplifier designs will result in other optimal bias designsit is up to you
determine what they are.
Remember, the total voltage vCE (t ) must be larger than 0.7 V for all time;
otherwise saturation (and thus signal distortion will result).
Likewise, the total collector current iC (t ) must be greater than zero for all
time; other wise cutoff (and thus signal distortion) will result.

4/6/2011 Example Amplifier Distortion 1/9
Example: Amplifier
Distortion
Recall this circuit from a previous handout:
15.0 V
RC =5 K
vO (t ) = VO + vo (t )
RB =5 K
= 100
vi (t )
+
_
+ RE =5 K COUS
5.8 V

We found that the small-signal voltage gain is:
vo (t )
Avo = = 66.7
vi (t )
Say the input voltage to this amplifier is:
vi (t ) = Vs cost
Q: What is the largest value that Vs can take without producing

a distorted output?
A: Well, we know that the small-signal output is:
vo (t ) = Avo vi (t )
= 66.7Vs cost
BUT, this is not the output voltage!
The total output voltage is the sum of the small-signal output

voltage and the DC output voltage!
Note for this example, the DC output voltage is the DC

collector voltage, and we recall we determined in an earlier
handout that its value is:
VO = VC = 10 V
Thus, the total output voltage is :
vO (t ) = VO + vo (t )
= 10.0 66.7 Vs cost
It is very important that

you realize there is a limit
on both how high and how
low the total output
voltage vO (t ) can go!
Thats right! If the

total output voltage
vO (t ) tries to exceed
these limitseven for a
momentthe BJT will
leave the active mode.
And leaving the

active mode results
in signal distortion!
Lets break the problem down into two separate problems:
1) If total output voltage vO (t ) becomes too small,

the BJT will enter saturation.
2) If total output voltage vO (t ) becomes too large,

the BJT will enter cutoff.
Well first consider problem 1.
For the BJT to remain in active mode, vCE (t ) must remain

greater than 0.7 V for all time t (or equivalently vCB (t ) > 0.0 ).
From an earlier handout, we know that VE = 5.05 V . The large

capacitor on the emitter keeps this voltage constant with
respect to time.
Therefore, the voltage vCE (t ) will remain greater than 0.7 V

only if the collector voltage vC (t ) remains greater than
5.05 + 0.7 = 5.75 V . Note 5.75 is the base voltage VB.
Of course, the collector voltage is also the output voltage

(vO (t ) = vC (t ) ), so that we can conclude that the output voltage
must remain larger than VB =5.75 V to remain in active mode:
5.75 < vO (t ) = 10 66.7Vs cost
In other words, the lower limit on the total output voltage is:
L = 5.75V
Note that we can solve this equation to determine the maximum

value of small-signal input magnitude Vs :
5.75 < 10 66.7Vs cost

66.7Vs cost < 4.25
Vs cost < 0.064
Since cost can be as large as 1.0, we find that the magnitude

of the input voltage can be no larger than 64 mV, i.e.,
Vs < 0.064 V
If the input magnitude exceeds this value, the BJT will

(momentarily) leave the active region and enter the saturation
mode!
Now lets consider problem 2
For the BJT to remain in active mode, the collector current

must be greater than zero (i.e., iC > 0 ). Otherwise, the BJT will
enter cutoff mode.
Applying Ohms Law to the collector resistor, we find the

collector current is:
VCC vO 15 vO
iC = =
RC 5
it is evident that collector current is positive only if vO < 15 V .
In other words, the upper limit on the total output voltage is:
L+ = 15.0 V
Since:
vO (t ) = 10 66.7Vs cost
we can conclude that in order for the BJT to remain in active

mode:
10 66.7Vs cost > 15.0
Therefore, we find:
5.0
Vs cost > = 0.0075
66.7
Since cost 1 , the above equation means that the input

signal magnitude Vs can be no larger than:
Vs < 75 mV
If the input magnitude exceeds 75 mV, the BJT will

(momentarily) leave the active region and enter the cutoff
region!
In summary:
1) If Vs > 64 mV , the BJT will at times enter saturation,

and distortion will occur!
2) If Vs > 75 mV , the BJT will at times enter cutoff, and

even more distortion will occur!
To demonstrate this, lets consider three examples:
1. Vs < 64 mV
The output signal in this case remains between VCC=15.0 V and

VB=5.75 V for all time t. Therefore, the output signal is not
distorted.
vO (t )
L+ =VCC = 15
VO = 10
L =VB = 5.75
2. 64 mV < Vs < 75 mV
The output signal in this case remains less than VCC=15.0 V for
all time t. However, the small-signal output is now large enough
so that the total output voltage at times tries to drop below
VB = 5.75V (i.e., VCE drops below 0.7 V). For these times, the
BJT will enter saturation, and the output signal will be
distorted.
vO (t )
L+ =VCC = 15
VO = 10
L =VB = 5.75
3. Vs > 75 mV
In this case, the small-signal input signal is sufficiently large so

that the total output will attempt to exceed both limits (i.e.,
VCC = 15.0 V and VB = 5.75 V ). Therefore, there are periods of
time when the BJT will be in cutoff, and periods when the BJT
will be in saturation.
vO (t )
L+ =VCC = 15
VO = 10
L =VB = 5.75
For a given amplifier voltage gain, you must

determine the largest possible input vi (t ) that
will produce a distortion-free output signal.
To do this, you must determine the limits of the

total output voltage. There will be two limitsone
for saturation (L-) and one for cutoff (L+).
4/8/2011 DC Biasing using a Single Power Supply lecture 1/21
D.C Biasing using a

Single Power Supply
The general form of a single-supply BJT amplifier biasing circuit is:
VCC VCC VEE VEE
RC RE
IC
R1 R2
+ +
VCE VEC
- -
R2 R1 RC
RE IC

Just three goals

Generally, we have three goals in designing a biasing network:
1) Maximize Gain
Typically, we seek to set the operating point of the BJT amplifier such that
the resulting small signal voltage gain is maximized.
However, we sometimes seek to set the bias point such that the output
resistance is minimized, or the input resistance is maximized.
2) Maximize Voltage Swing
We seek to set the operating point of the BJT amplifier such that the
maximum small signal output can a large as possible.
If we make VCE too small, then the BJT will easily saturate, whereas if VCE is
too large, the BJT will easily cutoff.

This suddenly seems like a lot of goals

3) Minimize Sensitivity to changes in
Manufacturing and temperature variances will result in significant changes

in the value .
We seek to design the bias network such that the amplifier parameters will
be insensitive to these changes.
Q: Youre kidding me right?
Were supposed to achieve all these goals with

just four resistors?
A: Actually, the three design goals listed

above are often in conflict.
We typically have to settle for a compromise

DC bias design.

How we maximize gain

Lets take a closer look at each of the three design goals:
1) Maximize Gain
Typically, the small-signal voltage gain of a BJT amplifier will be proportional to

transconductance gm :
Avo gm
Thus, to maximize the amplifier voltage gain, we must maximize the BJT
transconductance.
Q: What does this have to do with D.C. biasing?
A: Recall that the transconductance depends on the DC collector current IC :
IC
gm =
VT

Maximize that darn bias current!

Therefore the amplifier voltage gain is typically proportional to the DC
collector current:
IC
Avo
VT
We of course cant decrease the thermal voltage VT , but we can design the bias
circuit such that IC is maximized.
To maximize Avo , maximize IC

We dont want distortion!

2) Maximize Voltage Swing
Recall that if the DC collector voltage VC is biased too close to VCC , then even a
small small-signal collector voltage vc (t ) can result in a total collector voltage
that is too large, i.e.:
vC (t ) = VC + vc (t ) VCC
In other words, the BJT enters cutoff, and the result is a distorted signal!
To avoid this (to allow vc (t ) to be as large as possible without BJT entering

cutoff), we need to bias our BJT such that the DC collector voltage VC is as
small as possible.

How to avoid cutoff

Note that the collector voltage is:
VC = VCC RC IC
Therefore VC is minimized by designing the bias circuit such that the DC

collector current IC is as large as possible.
Q: Hey hey! It looks like amplifier bias design is going

to be easy. We can both maximize transconductance
gm and minimize the DC collector voltage VC by
maximizing the DC collector current IC !
A: Just a second! We must also consider the signal distortion that occurs when
the BJT enters saturation.

But also avoid saturation

Saturation of course is avoided if the total voltage collector to emitter remains
greater than 0.7 V, i.e.:
vCE (t ) = VCE + vce (t ) > 0.7 V
Thus, to avoid BJT saturationand the resulting signal distortionwe need to

bias our BJT such that the DC voltage VCE is as large as possible.
To minimize signal distortion, maximize VCE

BJTs are pretty sensitive

3) Minimize Sensitivity to changes in
We find that BJTs are very sensitive to temperaturespecifically, the value of

is a function of temperature.
Likewise, the value of is not particularly constant with regard to the

manufacturing process.
We find that 100 otherwise identical BJTs will result have 100 different
values of !
Both of these facts lead to the requirement that our bias design be insensitive
to the value of .
Specifically, we want to design the bias network such that the DC bias currents
(e.g., IC ) do not change values when does.
Mathematically, we can express this requirement as minimizing the value:
d IC
d

How do we determine this derivative?

Lets determine this derivative value for our standard bias network:
VCC VCC
Q: Yuck! This looks like a disturbingly difficult
circuit to analyze.
RC IC
R1 A: One way to simplify the analysis it to use a
Thevenins equivalent circuit.
+
VCC
VCE
-
Specifically, replace this portion R1
R2 RE of the bias circuit with its
Thevenins equivalent:
R2

Good ol Thevenins!
We find that this equivalent circuit is:
RB = R1 R2
R2 +
VCC
R1 + R2 -
VCC
RC IC
The bias network can therefore be equivalently represented as:
+
RB = R1 R2
VCE
-
R2 +
VCC
R1 + R2 - RE

Youre always having fun

if youre doing calculus
If we ASSUME that the BJT is in active mode, then we ENFORCE the proper
equalities and ANALYZE this circuit to find collector current IC:
(VBB 0.7 )
IC =
( + 1 ) RE + RB
We find therefore that:
d IC (VBB 0.7 )
=
d RE
2
+ 1
R B
Note then that:
d IC
lim =0
RE
RB
d

Maximize that darn resistor!

In other words, if we wish to make the DC collector current insensitive to
changes in , we need to make:
RE RB
We of course could accomplish this by making the base resistance RB = R1 R2

small, but we will find out later that there are problems with doing this.
Instead, we can minimize the circuit sensitivity to changes in by maximizing

the emitter resistor RE .
To minimize d IC d , maximize RE

This seems so simple

So, lets recap what we have learned about designing our bias network:
1. Make IC as large as possible.
2. Make VCE as large as possible.
3. Make RE as large as possible.
Q: Seems easy enough! Lets get

started biasing BJT amplifiers!
A: Not so fast! We still have a serious problem.

NOT!
To see what this problem is, write the KVL equation for the Collector-Emitter
Leg of the Bias Network:
VCC IC RC VCE IE RE = 0
VCC VCC
or
RC IC IC RC +VCE + IE RE = VCC
R1
+
Maximize Avo by
maximizing this
VCE
term.
But the total of
- the three terms
Minimize distortion must equal this!
R2 RE by maximizing this
term.
Minimize sensitivity by
maximizing this term.

A logical compromise
Q: Yikes! Its like owing 3 really big guys $15

each, but having only $15 in your pocket.
What do we do?
VCC
IC RC =
3
A: Split the total voltage 3 ways (give each guy $5). VCC
VCE =
3
VCC
+ IE RE =
3
IC RC +VCE + IE RE = VCC

The result of this compromise

In other words, for an npn BJT, set:
2 1
VC = V and VE = V
3 CC 3 CC
VCC VCC
RC
R1 2
VC = V
3 CC
+
VCE
-
1
VE = V
3 CC
R2 RE

Dont forget pnp

Likewise, for a pnp BJT, set:
2 1
VE = VEE and VC = VEE
3 3
VEE VEE
RE
R2
2
VE = VEE
3
+
VEC
-
1
VC = VEE
3
R1 RC

What should IC be?

Q: We have determined that the product IC RC should be equal to VCC 3 .
We can of course accomplish this with a larger resistor RC and a smaller current
IC, or a larger current IC and a smaller resistor RC. What should the value of IC
be?
A: Generally speaking, the value of the DC collector current IC affects:
1) Voltage Gain ( gm as IC ).
2) Input Resistance ( r 0 as IC ).
3) BJT Output Resistance ( ro 0 as IC ).
4) Power Consumption ( P as IC ).
5) Amplifier Bandwidth ( BW " " as IC ).
The best value of collector current IC is a trade between these parameters.

There are two resistors left

Q: OK, we now have enough information to set IC ,VC , and VE , and thus
resistors RC and RE .
But we still have two bias resistors left R1 and R2 . How do we determine their
values?
A: Well, we have found that reducing RB = R1 R2 decreases the circuit

sensitivity to This is good!
But, we will find that reducing RB = R1 R2 will often decrease the amplifier input
resistance Ri This is bad!
Also, we find that reducing RB = R1 R2 will increase the power dissipation

This is also bad!

A rule of thumb
VCC
VCC I1 if I1 IB
R1 + R2
VCC2
P = VCC I1
I1 R1 R1 + R2
IB A general rule of thumb is to select the values of R1 and

R2 so that IC is:
0.1 IC < I1 < IC

R2
Remember, the resistors R1 and R2 also determine the base

voltage VB, which should approximately be:
VB = VBE +VE
VCC
= 0.7 +
3

4/11/2011 Example Single Supply DC Bias 1/5
Example: Single-
Supply DC Bias
Consider this small-signal amplifier:
15 V 15 V
RC
R1
vO (t )
= 100
COUS
+
vi (t )
- R2 RE
COUS
Say we decide that the DC collector current should be

IC = 5 mA .
Lets find the resistor values for R1 , R2 , RC and RE that properly

bias this amplifier!
Step 1: Write the DC Circuit Schematic
After all, we are designing the DC bias!
15 V 15 V
RC IC
R1
+
VCE
R2 RE IE
Step 2: Enforce the design goals for VE and VC
Recall that our DC bias rule-of thumb was to divide the VCC
voltage into thirds so that:
VE =VCC 3 = 5.0 V
and
VC = 2VCC 3 = 10.0 V
Since we want IC = 5 mA , we find that the collector resistor

must be:
VCC VC 15 10
RC = = = 1K
IC 5
Likewise, the emitter resistor is:
VE 5.0
RE = = VE = = 0.99K 1K
IE IC 5.05
Step 3: Choose I1 and find R1 and R2
Recall our rule-of-thumb for the current I1 is:
0.1 IC < I1 < IC
Lets pick a value in the middle, i.e.:
I1 = 0.5 IC = 2.5 mA
Since we know that that the base voltage is approximately:
VB 0.7 +VE = 5.7 V
and we know that the base current is:
IC 5.0
IB = = = 0.05 mA
100
we can thus determine resistor R1 :
15.0 VB
R1 =
I1
15 V 15.0 5.7
=
2.5
= 3.72 K
R1 I1 = 2.5 mA
Likewise, since we know that the
IB = 0.05 mA current I2 is:
VB = 5.7 V
I 2 = I1 I B
= 2.5 0.05
2.5 mA
R2 I2
we can find the second resistor R2 :
VB 5.7
R2 = = = 2.28 K
I2 2.5
Therefore, our completed amplifier design is:

15 V 15 V
1K 5.0 mA
3.7 K
vO (t )
COUS
= 100
+
vi (t )
- 2.3K 1K
COUS
4/13/2011 BJT Biasing using a Current Source lecture 1/5
BJT Biasing using

a Current Source
Another way to bias a BJT small signal amplifier is to use one voltage source and
one current source. This biasing scheme has a number of important advantages:
VCC VCC 1. The DC emitter current is independent of or

BJT temperature!
RC IC Therefore, the DC collector current IC = IE IE is

R1 nearly independent of these parameters as well.
+
2. This means that the emitter voltage can be set at
VCE an arbitrarily low value!
- Therefore, the output voltage swing can be much

larger than an equivalent single-supply amplifier!
R2
I
3. We can make resistors R1 and R2 large without
making design sensitive to temperature and .

The current source:

not as easy as it appears
Note that ideally, we would set the emitter votage to zero (VE = 0 ), and thus
the collector voltage to VC =VCC 2 to maximize the output swing (i.e., maximize
the largest possible undistorted output signal).
VCC VCC
Q: But, isnt it diddly darn

RC difficult to actually build
IC
R1 an ideal current source!?
+
VCE
- A: True! For reasons we shall study

later, most current sources require a
R2 minimum voltage across them in order
I
to operate properly.

Put collector voltage half way

between floor and ceiling
Thus, our bias rule should be:
Make the DC emitter voltage VE as small as possible (and still have the
current source work!).
Then set the current source to a value equal to the desired DC collector
current (i.e., IC IE ):
I = I E IC
To maximize the output voltage swing, we still want to place the DC collector
voltage VC half way between VCC and VE .
VCC +VE
VC =
2
The collector resistor therefore should be:
VCC VC VCC VC VCC VE

RC = = =
IC I 2I

R1 and R2: same as before
The remaining resistors R1 and R2 are determined in the same manner as with
the single-supply bias design, i.e.:
VCC VB
R1 =
I1
and
VB VB
R2 =
I 2 I1
where the base voltage is approximately:
VB = 0.7 +VE
and the current I1 is any value in the range:
0.1 IC < I1 < IC

Just the kind of subtle

topic I might put on an exam
For example, say we wish to design a biasing network where:
IC = 2 mA VE 2.0V VCC = 15.0 V I1 = 0.5 IC
The result would be:

It is obvious to me that this bias
15.0 15.0 design satisfies the parameters
described above.
RC = 3.25 K But, dont take my word for it

R1 = 12.3K verify for yourself that these
resistor values are correct.
R2 = 2.7 K
2.0 mA

Example: Single-
Supply DC Bias
Consider this small-signal amplifier:
15 V 15 V
RC
R1
vO (t )
= 100
COUS
+
vi (t )
- R2 RE
COUS
Say we decide that the DC collector current should be

IC = 5 mA .
Lets find the resistor values for R1 , R2 , RC and RE that properly

bias this amplifier!
Step 1: Write the DC Circuit Schematic
After all, we are designing the DC bias!
15 V 15 V
RC IC
R1
+
VCE
R2 RE IE
Step 2: Enforce the design goals for VE and VC
Recall that our DC bias rule-of thumb was to divide the VCC
voltage into thirds so that:
VE =VCC 3 = 5.0 V
and
VC = 2VCC 3 = 10.0 V
Since we want IC = 5 mA , we find that the collector resistor

must be:
VCC VC 15 10
RC = = = 1K
IC 5
Likewise, the emitter resistor is:
VE 5.0
RE = = VE = = 0.99K 1K
IE IC 5.05
Step 3: Choose I1 and find R1 and R2
Recall our rule-of-thumb for the current I1 is:
0.1 IC < I1 < IC
Lets pick a value in the middle, i.e.:
I1 = 0.5 IC = 2.5 mA
Since we know that that the base voltage is approximately:
VB 0.7 +VE = 5.7 V
and we know that the base current is:
IC 5.0
IB = = = 0.05 mA
100
we can thus determine resistor R1 :
15.0 VB
R1 =
I1
15 V 15.0 5.7
=
2.5
= 3.72 K
R1 I1 = 2.5 mA
Likewise, since we know that the
IB = 0.05 mA current I2 is:
VB = 5.7 V
I 2 = I1 I B
= 2.5 0.05
2.5 mA
R2 I2
we can find the second resistor R2 :
VB 5.7
R2 = = = 2.28 K
I2 2.5
Therefore, our completed amplifier design is:

15 V 15 V
1K 5.0 mA
3.7 K
vO (t )
COUS
= 100
+
vi (t )
- 2.3K 1K
COUS

Section 5 - 5 Biasing in BJT Amplifier Circuits Lecture

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Section 5 - 5 Biasing in BJT Amplifier Circuits Lecture

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4/6/2011 section 5_5 Biasing in BJT Amplifier Circuits 1/1

5.5 Biasing in BJT Amplifier Circuits

Reading Assignment: 436-442

Now lets examine how we DC bias BJTs amplifiers!

HO: A GRAPHICAL ANALYSIS OF BJT AMPLIFIERS

If we dont bias properly, distortion can result!

EXAMPLE: AMPLIFIER DISTORTION

HO:DC BIASING USING A SINGLE POWER SUPPLY

We can also use a DC current source to bias the BJT.

HO:BJT BIASING USING A CURRENT SOURCE

Lets do an example DC bias design.

EXAMPLE: SINGLE-SUPPLY DC BIAS

Jim Stiles The Univ. of Kansas Dept. of EECS

Graphical Analysis of a BJT

Jim Stiles The Univ. of Kansas Dept. of EECS

We can rearrange this to get an expression for the collector current iC in

Note this is an equation of a line!

Jim Stiles The Univ. of Kansas Dept. of EECS

The load line

Jim Stiles The Univ. of Kansas Dept. of EECS

iC vs vCE for a BJT

Recall that this relationship is:

Jim Stiles The Univ. of Kansas Dept. of EECS

Sort of like the Grandview triangle

Jim Stiles The Univ. of Kansas Dept. of EECS

But it all depends on the input!

As the voltage v I (t ) changes, so will the values iC and vCE .

What does change is the BJT relationship between iC and vCE .

However, the collector current iC of a BJT is dependent on the voltage base-to-

Thus, as v I (t ) changes, so does v BE , resulting in a new BJT relationship (curve)

Jim Stiles The Univ. of Kansas Dept. of EECS

ic changes as the input changes

Jim Stiles The Univ. of Kansas Dept. of EECS

The operating point

The collector current and voltage collector-to-emitter are likewise DC bias

Jim Stiles The Univ. of Kansas Dept. of EECS

What happens if you make IB too large

We can graphically show this unfortunate occurrence:

Jim Stiles The Univ. of Kansas Dept. of EECS

Theres still a problem

A: NO!! There is a big problem with this strategy as well!

Jim Stiles The Univ. of Kansas Dept. of EECS

A little more than bias;

vi vi (t ) vi for all time t

VBB vi v I (t ) VBB + vi for all time t

Jim Stiles The Univ. of Kansas Dept. of EECS

Were hitting the floor

Look what happened here!

Jim Stiles The Univ. of Kansas Dept. of EECS

vO (t ) 0.2 (BJT saturated)

as opposed to the ideal value:

vO (t ) =VCE + vo (BJT active)

Jim Stiles The Univ. of Kansas Dept. of EECS

I never said this was easy

A: NO!! There is a problem with this too!

Look what happened here!

Jim Stiles The Univ. of Kansas Dept. of EECS

Now were hitting the ceiling

vO (t ) = VCC (BJT cutoff)

as opposed to the ideal value:

vO (t ) =VCE vo (BJT active)

Jim Stiles The Univ. of Kansas Dept. of EECS

A: To get allow for the largest possible (distortion-free) output signal vo (t ) , we