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Digital signal
Digital system only two discrete levels or values, low (0) or high (1). In case of positive
logic high is from 3.5-5v and low is 0-1v. In case of negative logic high is 0-1v and low is
3.5-5v. As long as voltage remains in these levels the state is considered low or high
depending on logic used. Digital system are less susceptible to noise due to the range in
logic voltages. High is also called as on and low as off.

Digital Electronics
For TTL
Vin = 0-0.8 (low)
Vin = 2-5 (high)
Vout = 0-0.4 (low)
Prof. H. Arya
Vout = 2.4-5 (high)
DEPT. OF AEROSPACE ENGINEERING
IIT BOMBAY

(a) Positive logic and (b) negative logic

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Basic digital circuits Basic digital circuits

OR operation
AND operation

Y = A B C ...N
Y = A + B + C + ...N
Y = ABC...N Standard symbol for OR gate
Standard symbol for AND gate

A,B,C .. N are input variables (possible values only 0 &1 ) and Y is output. Y will be Output of OR gate is 1, if and only if one or more inputs are 1
high only when all the inputs are high (positive logic)

Truth table for a 2-input OR gate

Truth table for a 2-input AND gate

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Basic digital circuits Derived gates

NOT operation

Y=A Standard symbol for NOT gate

Basic gates in digital circuitry are AND, OR and NOT. Using these three
basic gates other type of gates are obtained. NAND, NOR, XOR

NOT gate also known as inverter. It is one input (A) and one output (Y) device. Output is
complement of input. Bubble in the circuit always denotes inversion in digital circuits.

Truth table for a NOT gate

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NAND operations NAND as universal gate

NOT-AND operation is known as NAND, it is a AND gate followed by a NOT gate.
Standard symbol is AND with bubble. Using NAND gate, basic digital circuits i.e. AND, OR, NOT can be obtained and
this property makes it a universal gate.

Y = A B C ...N; Y = ABC...N

Truth table for a NAND gate

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NOR operations Using NOR as universal gate

NOT-OR operation is known as NOR. It is OR gate followed by a NOT gate.
Standard symbol is OR gate with a bubble. Using NOR gate, basic digital circuits i.e. AND, OR, NOT can be obtained and
this property makes it a universal gate.

Y = A + B + C + ...N

Truth table for a two input NOR gate

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Exclusive-OR (EX-OR) operations Exclusive-NOR (EX-NOR) operations

It is not a basic gate, and the operation can be performed using the basic It is EX-OR gate followed by a NOT
gates - AND, OR and NOT.
Y = A B + AB
Standard notation
Y = AB Y = A B + AB Standard notation Y = A o B
Y = A B + AB

Truth table for a EX-OR gate

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Boolean algebraic theorems De Morgans theorem

Any boolean expression can be converted from AND to OR and vice versa using
De Morgans theorem

A + B = A.B
A.B = A + B
A.B.C = A + B + C
This can be extended to any number of variables.

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Combinational logic design

The aim is to design a circuit with minimum number of devices to reduce cost, power
Mainly two type of classification in digital circuits. Combinational logic circuits and
consumption, save space etc.
Sequential logic circuits. Combinational logic circuits only depends on the
combination of the gates where as sequential logic circuit depends on the
combination of gates and sequence of input, it is history dependent. Algebraic method
Karnaugh map technique

Any arbitrary logical function can be expressed in one of the following form
Sum-of-products form (SOP)
Product-of-sums form (POS)
These forms help in designing the circuits having standard components

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Combinational logic design Combinational logic design

Let the logical equation: Y = (A + BC)(B + CA ) Y = AB + A C + BC

Y = A ( B + CA ) + BC( B + CA )
Y = AB + A CA + BCB + BCCA
Y = AB + A C + BC ACA = AC;
BCB = BC;
BCCA = 0

Above equation is in SOP form, it can be realised by AND - OR gates

Realized in two levels, I level AND gates and II level OR gate

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Combinational logic design Combinational logic design

Y = AB + A C + BC Y = AB A C BC
Y = AB + A C + BC

By De Morgans theorem
Y = AB AC BC

Y = Y1 Y2 Y3 Y1 = AB; Y2 = AC; Y3 = BC

Only NAND gates can be used to realize the earlier equation

Both levels are performed by NAND gates

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Combinational logic design Combinational logic design

Y = (A + BC)(B + CA ) Y = ( A + C)(A + B)(B + C)

Y = ( A + C)(A + B)(B + C)(B + A)

Y = ( A + C)(A + B)(B + C)

This can be realized using OR-AND gates

This representation is called product of sums POS

First level using only OR gates and second level using AND gate

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Combinational logic design Combinational logic design

Y = ( A + C) + ( A + B) + (B + C)
Y = (A + C)(A + B)(B + C)
Y = ( A + C) + ( A + B) + (B + C)
Y = YA + YB + YC

YA = (A + C); YB = (A + B); YC = (B + C)

This can be realized only with NOR gates

Both the levels are realized using NOR gates

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Combinational logic design Standard form of logic equation

Y = (A + BC)(B + CA ) If each term in SOP or POS form contains all the literals then it is in standard
form.
Y = A C + BC Y = (A + BC)(B + CA )
Y = (A + C)(B + C) Y = ( A + C)(A + B)(B + C) Y = AB + A C + BC

Y = AB (C + C ) + AC ( B + B ) + ( A + A) BC Theorem 1.7

Y = ABC + ABC + ABC + A BC + ABC + ABC

Standard form in SOP

This is the simplified form of original equation and this uses the
least number of devices Y = ABC + ABC + A BC + ABC

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Standard form of logic equation Minterms/maxterms for three variables

Method to express logical
functions in shorthand
For Three variable
If each term in SOP or POS form contains all the literals then it is in standard
form. notations
Y = (A + BC)(B + CA ) A B C minterms maxterms
Y=m3+m4+m6+m7 0 0 0 AB C = m 0 A + B + C = M 0
Y = ( A + C)(A + B)(B + C) A B C = m1 A + B + C = M1
Y = AB + A C + BC Y=m(3,4,6,7) 0 0 1
0 1 0 AB C = m 2 A + B + C = M2
Y=m0+m1+m2+m5 ABC = m 3
0 1 1 A + B + C = M3
Y = ( A + BB + C)( A + B + CC)( A A + B + C) Theorem 1.1 & 1.8
Y=M0M1M2M5 1 0 0 AB C = m 4 A + B + C = M 4
Y=M(0,1,2,5) 1 0 1 AB C = m 5 A + B + C = M 5
Y = ( A + B + C )( A + B + C )( A + B + C ) Theorem 1.10 1 1 0 AB C = m 6 A + B + C = M 6
( A + B + C )( A + B + C )( A + B + C ) 1 1 1 ABC = m 7 A + B + C = M7

Standard form in POS

Y = ABC + ABC + A BC + ABC
Y = ( A + B + C )( A + B + C )( A + B + C )( A + B + C ) Y = ( A + B + C )( A + B + C )( A + B + C )( A + B + C )

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Karnaugh Map representation of logical functions

Karnaugh Map representation of logical functions
K-map for two (A,B) and three variables (A,B,C). Cells are filled depending on the
logical equation. Gray code is used to identify the cell.
A systematic graphical approach for simplification and manipulations of
logical expressions. Information available in truth table or POS or SOP
form is used in K-map. This technique can be extended for any number
of variable, beyond six variables it is too cumbersome. For Three variable
A B C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

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Karnaugh Map representation of logical functions Karnaugh Map representation of logical functions

Similarly for four variables

The number in top left hand corner

shows the minterm or maxterm.
Depending on the logical equations
cells are filled with 1 or 0

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Minimisation problem using K-Map Half adder

f (A, B, C, D) = m(0,1,2,3,5,7,8,9,11,14) A logic circuit adding two bits is called

as half adder. A and B are two inputs.
Groups of four are S is sum and C is carry as output.

(8,9,0,1), (1,5,7,3), (1,9,11,3)

& (0,1,3,2) Sum S= AB
(8,9,0,1) =
Carry C = AB
A BCD + A BCD + A BCD + A BCD
= BC
f (A, B, C, D) =
ABCD + BC + BD + AD + A B

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Full adder N-bit adder

In a full adder carry coming from low order bit is also considered. Input is An, Bn and
Cn-1 Output is Sn and Cn

Sn = A n Bn C n 1 + A n Bn C n 1 + A n Bn C n 1 + A n B n C n 1 An adder circuit for two n bit

number consist of n full adder
C n = A n B n + B n C n 1 + A n C n 1 circuits. It accepts two n-bit
number and produces output
of (n+1) bit binary number as
sum. Half adder may be used
to add least significant bit

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N-bit comparator

Comparator logic circuit is used to Digital Circuits

compare two digital numbers. It is two input
and three output device. Input is n-bit data.
Sequential Logic

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Sequential Logic Asynchronous & Synchronous

It is a combination of combinational digital circuits. The output depends on the input
sequence. The output depends on the past history and it is given in some form of
feed back to the input.
Asynchronous: A sequential circuits whose output depends upon the sequence of
input signals. Output will be affected whenever input changes.
Synchronous: A sequential circuits whose output can be defined from the
knowledge of timing signal. Output will be affected only during timing signal. In
general timing signal is called as clock signal.

Inputs Outputs
Combinational
circuit
Memory Inputs Outputs
elements Combinational
circuit
Memory
elements
Clock signal

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Clock signal
It is a periodic train of clock pulses, generated by system clock and used for
synchronization of the events. Or the outputs are affected only by application of
clock pulse. Output will change with 0, or 1 (level logic) or rising edge or falling
edge (edge logic).
Clocked S-R flip-flop with Preset and Clear
In S-R flip-flop when S=1 and R=0 then output Q=1 and when S=0 and R=1 then
output Q=0. When Pr = Cr = 1 it works as a clocked S-R flip flop. In the logic symbol
if bubble is used, it means active-low. The intended function is performed when Pr =
0 and Cr = 0, as shown in figure. Pr and Cr can be applied independent of clock.
Once the intended function is over these inputs are pulled high (low in case of
negative logic), to perform like a normal S-R flip flop.

Operation of S-R flip flop with preset & clear

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J-K flip-flop D-type flip-flop
The uncertainty state i.e. S = 1 and R = 1 in S-R flip flop can be eliminated by J-K
It uses only one input referred as D-input or data input. The output at the end of
flip flop. Inputs J & K are ANDed with output to obtain S & R input. This will work for
clock pulse equals the input Dn before the clock pulse. The output is available
all possible combination of J & K inputs. When J & K = 0, the output is maintained
after one clock cycle and it is also known as delay flip flop.
from the previous state. When J & K = 1, the output is inverted from the previous
state. In other states output follows input.

Truth table for J-K flip flop

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T-type flip-flop T-type flip-flop

If J=K in JK flip-flop, it behaves as a toggle type flip flop. If T = 1, the

T - type flip-flop using S-R flip flop. The output changes with every clock pulse.
output toggles with every clock pulse. For every clock pulse the output
changes.

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Registers Data representation

A register is a group of flip-flops to store a group of bits (word). For storing n-bit Serial data - one bit at a time or with every clock pulse. One signal line is sufficient.
word n flip-flops are required. Data is applied at D-inputs and output is available More clock pulses for a given data.
at Q with the rising edge of the pulse. Preset and clear is used to set or reset the Parallel data - many bits at a time and same number of lines as number of bits. In one
output. clock pulse a word can be represented.

a) Serial form b) 4-bit parallel form, Data 0 1 0 1

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Registers Shift register

Registers are classified depending upon the way input is given and output is Master-slave flip-flops are cascaded to form shift register. The circuit shown is a
retrieved. Four possible mode of operations : universal shift register. Generally, preset is set high to make output 0, before data
transfer. After this data is fed serial or parallel, depending on requirements.
1) Serial-in, serial-out (SISO)
2) Serial-in, parallel-out (SIPO)
3) Parallel-in, serial-out (PISO)
4) Parallel-in, parallel-out (PIPO)
A register which can work in all the above four modes is called as universal
register

5 bit universal register

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Shift register Counters
Data 10110 is at serial input and seen at parallel output after 5 clock pulses. It is
shown how the data shifts with clock pulse. Digital counters are used for counting the number of events. n-flip flop can count 2n
number. A 3-bit counter can count from 0 to 7. Flip-flop used are toggle type,
toggles the output at falling edge.

3-bit counter using flip-flops

Waveform of shift registers for serial input

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Counters Bounce elimination switch

The output of Q0 (LSB) changes at every falling edge of the input pulse. The output
of Q1 changes at every falling edge of Q0 and so on. The output at is 100 (i.e. 4). A
decoder circuit is required to get the decimal number.
Mechanical switches have bouncing characteristics- multiple contacts. It also
means multiple change in state. Switch position decided 1 as input in one of the
terminals. At t = 0, switch is thrown from A to B. At t=0+ at S will be Vcc and at
time t1 R will be 0. In this position output is immune to any change at R and
hence even at t2, t3 etc output is maintained.

Wave form of a counter

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What is ADC?
Most of the sensors output is analog. Computers, micro-controller etc understands digital. ADC is a
system which converts the analog voltage into equivalent digital number. Analog to digital converter
(ADC) is an interface between analog world (voltages) and digital world (computer). The digital data
can be stored, manipulated for further use. Less storage space compared to mechanical data
storage devices - strip charts. High speed data acquisition possible.

Digital to Analog Conversion - These are available as 8-bit, 12-bit, 24-bit etc. also called as resolution. Data available at discrete
time step.

DAC
8 bit - 256 (28)
12 bit - 4096 (212)
Analog to Digital Conversion - 16 bit - 65536 (216)
ADC Input range will be divided in above number of steps.

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ADC Conversion steps Specifications for ADC
Following steps are involved in ADC:
1. Range of input voltage - 0-5 V, 0-10 V, 2.5 V, 5 V etc
1) Sampling - Multiplexing
2. Input impedance - k to M
2) Holding - Hold the value till conversion is over
3. Accuracy - 1/2 LSB or 0.02 % FS
3) Quantizing - Converting the analog voltage to digital value
4. Conversion time - 50 s to 50 ns
4) Encoding - Digital output may not be straight binary number
5. Format of digital output - straight binary, twos complement etc

Accuracy and sampling interval

Accuracy is lost in sampling. Wave form

distorts. Wave form can be captured with high
resolution and sampling rate. For practical
purpose 8-10 data required in one cycle of
highest frequency to represent waveform
correctly.

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What is DAC?
Computer output (digital) to analog voltage. Many devices - motors, actuators require
analog voltage for control.
Voltage v/s RPM
Voltage v/s displacement
Output from DAC is used as a control signal in the circuitry

Specifications for DAC

1. Resolution
2. Linearity
3. Accuracy
4. Settling time
5. Temperature sensitivity

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Monostable mode
Internal Block Diagram - 555 Monostable means only one state stable - off state. When triggered it will go to other state
temporarily. This can generate a single pulse when triggered. This can be used to switch on the
circuit/device for a specified time, whenever triggered.

Astable multivibrator

In astable mode it will keep on

generating the pulse. Stream of
rectangular on-off signal.

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