BOBBY_DSB

JNTU ONLINE EXAMINATIONS [Mid 1 -MCA]

By BOBBY_DSB

1. A personal computer can be used for_________ applications [01D01]

a.One
b.Two
c. Three
d. Many
2. ROM in 8051 has_______ Kbytes [01M01]

a.0
b. 4
c. 8
d.16
3. RAM in 8052 has ________ bytes [01M02]

a.128
b.64
c. 32
d. 256
4. ROM in 8052 has____________Kbytes [01M03]

a.0
b.4
c.8
d.16
5. An embedded product using a microprocessor can do _____ task (s)
[01S01]

a. One
b.Two
c. Three
d.Many
6. Intels 8051 is a _______ bit microcontroller [01S02]

a.4
b. 8
c. 16
d.32
7. Number of timers in 8031 is __________ [01S03]

a. 2
b.3
c. 4
d.6
8. Number of I/O pins in 8051 is ________ [01S04]

a.4
b.8
c. 16
d. 32
9. Number of interrupt sources in 8051 is ___________ [01S05]

a.4
b. 6
c. 8

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d.16
10. Number of serial ports in 8052 is _________ [01S06]

a. 1
b.2
c. 3
d.4
11. In 8051, the microcontroller wakes up at memory address ----, when it is
powered. [02D01]

a. 0000
b.000A
c. 000C
d.0002
12. The _______ instructions in 8051 copies data from one location to
another [02M01]

a. MOV
b.ADD
c. ORG
d.SJMP
13. Size of flag register in the 8052 is________ bits wide [02M02]

a.4
b. 8
c. 16
d.32
14. When the 8051 is powered up, the SP register contains value [02M03]

a.4
b.5
c. 6
d. 7
15. ________ produces opcode [02M04]

a.ORG 0H
b. MOV A,#12
c. ORG 2000H
d.Either ORG 0H or ORG 2000H
16. The vast majority of registers in 8051 are _______ bits [02S01]

a.4
b. 8
c. 16
d.32
17. A program that consists of 0s and 1s is called _______ language [02S02]

a. Machine
b.Assembly
c. High level
d.Either Assembly or high level
18. In the 8051, the program counter is ______ bits wide [02S03]

a.4
b.8
c.16
d.32

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19. The 8051 microcontroller has _______ data type(s) [02S04]

a. 1
b.2
c. 3
d.4
20. The stack pointer in the 8051 is_______ bits wide [02S05]

a.4
b. 8
c. 16
d.32
21. An MCU must have [03D01]

a. Oscillator and reset circuits

b.Oscillator, reset and watch dog timer circuits
c. Oscillator circuit
d.External memory interfacing units
22. P0.0 /AD0 in 8048 microcontroller pertains to ________signal [03D02]

a.Input
b.Output
c.Input/Output
d.Ground
23. A _______ is a single VLSI circuit with a CPU and few other structural
sections. [03M01]

a. Microprocessor
b.Microcontroller
c. Microcomputer
d.Personal Computer
24. Computers and microcontrollers differ in following aspects [03M02]

a.A microcontroller has memory & timer devices

b. A computer has a large memory
c. A microcontroller is for control applications
d.A microcontroller is for specipic applications
25. ROM in 8048 microcontroller is ___ KB [03M03]

a. 1
b.2
c. 3
d.4
26. __________ in 8048 microcontroller is data/address multiplexer [03S01]

a.DAM
b.DUX
c.MUX
d.MPX
27. ________ bit out bus is from PCH to program memory in 8048 [03S02]

a. 2
b.3
c. 4
d.8
28. ________ bit out bus from PCH to program memory in 8049 [03S03]

a.2
b. 3

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c. 4
d.8
29. A_______ is a microcomputer with a few other application specific
devices on a single chip [03S04]

a.Microprocessor
b. Microcontroller
c. Programmable Logic Controller
d.Microprocessor or programmable logic controller
30. On chip ROM is available in [03S05]

a.Microprocessor
b. Microcontroller
c. I/O units
d.Oscillator
31. Eight bit port with latch for input & output or IO operations is port
______ in 8048 microcontroller [04D01]

a.P1
b.P0
c. P2
d. PB
32. Eight - bit input port with analog inputs capability is port _______ in
68HC11 [04D02]

a.C
b.D
c.E
d.C or D
33. On chip EEPROM of 68HC11 microcontroller can be used in _______
modes [04M01]

a.2
b. 3
c. 4
d.5
34. Figure shows an 8 bit _________port

[04M02]

a.Input
b.Output
c.Input or output
d.Neither input nor output
35. Internal Bus width of 8096 microcontroller is _______ bit [04S01]

a. 8
b.16
c. 32
d.24
36. External address Bus width is_______ in 8048/8051 microcontroller
[04S02]

a.8
b. 16
c. 32
d.24

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37. External data bus width is________ in 8048/8051 microcontroller

[04S03]

a. 8
b.16
c. 32
d.24
38. An MCU (Microcontroller) parallel port normally is of _______ bits
[04S04]

a. 8
b.16
c. 32
d.24
39. 'X' in figure is --------

[04S05]

a. Real Time clock interrupts

b.Timeout interrupts
c. Output toggle
d.Input capture interrupt
40. Figure pertains to port _________ in expanded mode

[05D01]

a. P0
b.P1
c. P2
d.P3
41. PSW in special function registers stands for process________ word
[05D02]

a. Status
b.Serial
c. Supply
d.Stack
42. A ________ decouples on the VDD supply and rails the effect of the
transients [05D03]

a.Manual switch
b. Decoupling Capacitor (Cd)
c. Reset circuit
d.Grounding connection
43. Name of the port of an 8 quasi bi directional IO port in single chip mode
operation is port ______ [05M01]

a.P0
b.P2
c.P1
d.P3
44. Minimum frequency fosc to be set for oscillator circuit in 8051 family
should be ________ MHz. [05M02]

a. 1
b.2
c. 4
d.16

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45. Signal P.1.1 is connected at Pin _______ in 8051 microcontroller [05S01]

a.1
b. 2
c. 3
d.4
46. Signal TXD / P3.1 is connected at Pin______in 8051 microcontroller
[05S02]

a. 11
b.12
c. 13
d.14

47. Signal is connected at pin ----- in 8051 microcontroller [05S03]

a.12
b.13
c. 14
d. 15
48. _____ of 8051 processes instructions. [05S04]

a. CPU
b.ROM
c. RAM
d.Oscillator
49. Pin number _______ is used in 8051 for p110 bit 2 [05S05]

a.1
b.2
c.3
d.4
50. An instruction is read in between the period of _______ =0 and between
the middle of S2 just before the start of next ALE at S4 in Intel 8051. [06D01]

a.ALE

b.
c. RD
d.WR

51. When --------- and are short circuited in Intel 8051, the program
memory and data memory areas overlap. [06D02]

a.ALE

b.
c. RD
d.WR
52. The signal _______ when 0, uses data memory for the X - data reading
operation in Intel 8051. [06M01]

a.ALE

b.

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c.RD
d.WR
53. The signal ________ when 0 uses data memory for the data write
operation in Intel 8051. [06M02]

a.ALE

b.
c. RD
d. WR
54. During the period between the middle of two clock state S1 and S2
period, first _______ signal separates the A0 A7 bus in Intel 8051. [06M03]

a. ALE

b.
c. RD
d.WR
55. Figure pertains to______ in classic 8051

[06S01]

a. Internal program memory

b.Internal RAM DATA
c. Internal DATA RAM
d.External program memory
56. Figure pertains to ________ in classic 8051

[06S02]

a.Internal program memory

b.Internal RAM DATA
c. Internal DATA RAM
d. External Code memory
57. __________ can be accessed through indirect addressing mode used in
an instruction in classic 8051. [06S03]

a.Code memory (External)

b. X data
c. Internal Program Memory
d.Internal RAM DATA
58. RESET pin is active ___________ [06S04]

a.When connected to 1
b. For a few cycles only
c. When connected to 0
d.Only on watchdog timer reset
59. ___________ signal when 0, uses the program memory code bank 2 to
31 for the code reading operation for interfacing of external memories in Intel
8051 [06S05]

a.ALE

b.

c.

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d.
60. Timer 1 runs and timer 0 stops when [07D01]

a. TCON.6 =1 and TCON.4 = 0

b.TCON.4 = 0 and TCON.5 = 1
c. TCON.7 = 1 and TCON.5 = 0
d.All bilts of TCON are 1 s
61. If IP register has only the default priorities, then [07D02]

a. has the highest priority

b. has the highest and serial interface has the lowest priority
c. Timer overflows have the highest priorities
d.Interrupt processes in the order of its occurrence.
62. SI in 8051 facilitates a full duplex asynchronous serial communication
called _______ mode [07M01]

a.0
b. 1
c. 4
d.5
63. Direct address pertaining to SFR symbol SBUF is [07M02]

a. 0 x 88a
b. 0 x 98a
c.0 x 99
d.0 x 89
64. ________ is a call event arising from a signal of another internal or
external process, device, circuit or action [07M03]

a.CONST
b.CODE
c.Interrupt
d.Reset circuit
65. Synchronous serial cum asynchronous serial communication in 8051 is
called_______ [07S01]

a. Serial Interface
b.Interrupt
c. Internal program memory
d.Internal Data Memory
66. SI in 8051 facilitates a half duplex synchronous mode of operation called
mode ________ [07S02]

a. 0
b.1
c. 2
d.3
67. _______ mode is also called multiprocessor communication mode in
8051. [07S03]

a. SI synchronous
b.Serial asynchronous
c. Reset
d.Grounding

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68. A_______, given the count inputs at regular intervals, also functions as a
timer. [07S04]

a. TF2a
b. Counter
c. E x F 2
d.RCLK
69. A(n) __________ is an interruption of current sequence of instructions
[07S05]

a. Interrupt
b.CODE
c. CONST
d.Reset circuit
70. For adding the 'A' register contents with the R5 register contents, the
code ADD A, R1 is in [08D01]

a.Machine code
b. Assembly language
c. High level language
d.Machine code or high level language
71. In ______ addressing mode in 8051, data bits for the instruction are part
of the instruction as the next byte to the opcode [08D02]

a.Register
b. Immediate
c. Direct
d.Indirect register
72. In _________ addressing mode in 8051, data bits are at a register(s)
[08M01]

a. Register
b.Immediate
c. Direct
d.Indirect register
73. In_________addressing mode in 8051, the address is directly specified
in the instruction [08M02]

a.Register
b.Immediate
c.Direct
d.Indirect register
74. In ________ addressing mode in 8051, the address is indirectly specified
in the instruction by the contents of a pointer [08M03]

a.Register
b.Immediate
c. Direct
d. Indirect register
75. The bytes for the instructions executable on a CPU are called _______
codes [08S01]

a. Machine
b.Assembly
c. OP
d.Assembly or OP

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76. 68H is in _____ [08S02]

a. Machine code
b.Assembly language
c. High level language
d.Assembly language or High level language
77. In the_________, the codes are in large numbers for a program [08S03]

a. Machine code
b.Assembly language
c. High level language
d.Assembly language or High level language
78. At the end address, an instruction can be ________ to the source
program or routine. [08S04]

a.Data transfer
b. Halt
c. Logic operation
d.Bit manipulation
79. Each program, or_________ has a starting address and an end address
[08S05]

a. Routine
b.Opcode
c. Data transfer
d.Operand
80. The advantage of the _______instruction is that the values in the
registers RAM or SFRs can be saved for the LIFO operations later. [09D01]

a.MOV
b.MOVC
c. MOVX
d. PUSH
81. The advantage of a separate _______ is that it can be used to copy the
bytes from or to using the external RAM for the data memory for X - DATA
between 0000H to FFFFH [09D02]

a.MOV
b.MOVC
c.MOVX
d.PUSH
82. An use of instruction_______ is for copying the codes from one set of
memory area to another during the development phase. [09M01]

a.MOV
b. MOVC
c. MOVX
d.PUSH
83. An________ instruction for exchanging the A - register with a source
using the register mode. [09M02]

a.PUSH
b.MOV
c.XCH
d.POP
84. Advantage of _______ instruction is that the accumulator can be
temporarily be saved at an address and the value used from that address
arithmetic or logical operations [09M03]

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a.PUSH
b.MOV
c.XCH
d.POP
85. A_____ instruction in 8051 means copy the bits from one source to a
destination [09S01]

a. MOV
b.MOVC
c. MOVX
d.PUSH
86. An _______ instruction in 8051 means copy the 8 bit code from one
source at the program memory to the register A destination [09S02]

a.MOV
b. MOVC
c. MOVX
d.PUSH
87. A _______ instruction in 8051 means copy the 8 bit data into A and from
A using the external data memory address using DPTR or Ri as pointer
[09S03]

a.MOV
b.MOVC
c.MOVX
d.PUSH
88. ___________instruction means copy the 8 bit data into the stack after
incrementing SP [09S04]

a.MOV
b.MOVC
c. MOVX
d. PUSH
89. There are _______ distinct MOV instructions to transfer into an SFR
[09S05]

a.3
b.4
c.5
d.6
90. Instruction _______ in 8051 rotates bits left with MSB rotating into LSB
[10D01]

a.RRA
b.RRCA
c.RLA
d.RLCA
91. Instruction ______ in 8051 rotates bits left with MSB rotating into C and
C into LSB [10D02]

a.RRA
b.RRCA
c. RLA
d. RLCA
92. Instruction _______ in 8051 rotates bits right with LSB rotating into MSB
and also to C [10M01]

a. RRA
b.RRA

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c. RLA
d.RLCA
93. Instruction _______ in 8051 rotates bits right with rotating into C and C
into MSB [10M02]

a.RRA
b. RRCA
c. RLA
d.RLCA
94. A ______ instruction in bit manipulation in 8051 makes all bits = 0s
[10S01]

a. CLR
b.SWAP
c. CPL
d.RL
95. A_________ instruction in bit manipulation operation in 8051
complements all 1s to 0s and vice versa [10S02]

a.CLR
b.SWAP
c.CPL
d.RL
96. Instruction ADD A, Rn in 8051 is for ________ addressing mode [10S03]

a. Register
b.Direct
c. Indirect
d.Immediate
97. Instruction ADD A, @Ri in 8051 is for ______ addressing mode [10S04]

a.Register
b.Direct
c.Indirect
d.Immediate
98. Instruction ADD A, #data in 8051 is for _______ addressing mode
[10S05]

a.Register
b.Direct
c. Indirect
d. Immediate
99. Instruction SBB A, Rn in 8051 is for _____ addressing mode [10S06]

a. Register
b.Direct
c. Indirect
d.Immediate
100. ANL A, @Ri instruction in 8051 is for _______ addressing mode [11M01]

a.Register
b.Direct
c.Indirect
d.Immediate
101. ORL A, direct instruction in 8051 is for ____________ addressing mode
[11M02]

a.Register
b. Direct

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c. Indirect
d.Immediate
102. XRL A, # data instruction in 8051 is for ______ addressing mode
[11M03]

a.Register
b.Direct
c. Indirect
d. Immediate
103. ANL direct, A instruction in 8051 is for______ addressing mode [11M04]

a.Register
b. Direct
c. Indirect
d.Immediate
104. In 8051, one cycle = ____ μs for AND instructions for register addressing
mode [11S01]

a. 1
b.2
c. 3
d.4
105. In 8051, one cycle = ________ μs for OR instructions for direct
addressing mode [11S02]

a. 1
b.2
c. 3
d.4
106. In 8051, one cycle = ______ μs for XOR instructions for indirect
addressing mode [11S03]

a. 1
b.2
c. 3
d.4
107. _________ pertains to logic instruction in 8051. [11S04]

a.MOV
b. XRL
c. CPL
d.RR
108. _________ pertains to logic instruction in 8051. [11S05]

a.MOV
b. ANL
c. CPL
d.RR
109. ________ pertains to logic instruction in 8051. [11S06]

a.MOV
b. ORL
c. CPL
d.RR
110. CJNE A # data, rel instruction in 8051, is an ______ instruction [12D01]

a.Delay - cycle
b.Long Jump
c. Conditional Short Relative group

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d. Absolute jump
111. DJNZ Rn, Rel instruction in 8051 is an _______ instruction [12D02]

a.Conditional Short Relative jumps

b. Decrement and conditional Jump on Zero
c. Long Jump
d.Short Jump
112. JBC bit, rel instruction in 8051 is an ______ instruction [12M01]

a.Delay - cycle
b.Long Jump
c.Conditional Short Relative group
d.Absolute jump
113. RET1 instruction in 8051 is for _______ addressing mode [12M02]

a. Stack address
b.Direct
c. Indirect
d.Immediate
114. NOP instruction in 8051, is a(n) ______ instruction [12S01]

a. Delay - cycle
b.Long Jump
c. Conditional Short Relative group
d.Absolute jump
115. JNZ rel instruction in 8051, is a(n) _____ instruction [12S02]

a.Delay - cycle
b.Long Jump
c.Conditional Short Relative group
d.Absolute jump
116. JC rel instruction in 8051 is an________ instruction [12S03]

a.Delay cycle
b.Long Jump
c.Conditional Short Relative group
d.Absolute jump
117. CJNE @Ri, data, rel instruction in 8051 takes __________ cycles [12S04]
a.1
b. 2
c. 3
d.4
118. NOP instruction in 8051 takes ___________cycles [12S05]

a. 1
b.2
c. 3
d.4
119. The _______ facilitates an MCU for multiple real time control of the tasks
[13D01]

a.External Data Memory

b.Interrupt Structure
c.External Program Memory
d.Oscillator Circuit
120. _____________ activates the interrupt service [13M01]

a.Enabling And Masking of the sources

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b.Priority assignment
c.Identification of interrupt service on interrupt
d.Finding Vector address
121. On a timeout, an_______ of the on going program occurs after
completing the instruction being executed. [13M02]

a. Interrupt
b.Long jump
c. Short jump
d.Absolute jump
122. A flag enables identification by the processor an event when an
__________activates [13M03]

a.Bit manipulation
b. Interrupt service
c. Arithmetic operation
d.Data transfer
123. __________ pertains to interrupt structure [13M04]

a.RAM
b.ROM
c.Priority assignment
d.A/D converter
124. When a timer overflows, the same _______ the CPU [13S01]

a. Interrupts
b.Long Jumps
c. Short Jumps
d.Calls
125. When a timer reaches a prefixed count, the timer __________ the CPU
[13S02]

a. Interrupts
b.Long Jumps
c. Short Jumps
d.Calls
126. Error(s) during the run _______ the CPU [13S03]

a. Interrupt
b.Long Jump
c. Short Jump
d.Call
127. An __________ is an unplanned diversion after executing an instruction
on an event. [13S04]

a. Interrupt
b.Long jump
c. Short jump
d.Absolute jump
128. An__________ is an event at a process, device or circuit that causes the
interrupt [13S05]

a. Interrupt source
b.Oscillator circuit
c. D/A converter
d.A/D converte
129. NMI pin 80 x 86 is an example of ________ interrupts [ [14D01]

a. External pin

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b.Hardware interval
c. Software related
d.Hardware interval or software - related
130. INTO in 80 x 86 is an example of ________ interrupts [14D02]

a.External pin
b.Hardware interval
c.Software related
d.Hardware interval or software - related
131. If 'Td' is interrupt deadline time interval and Tlat is latency interval of the
interrupt, then Td - Tlat is [14M01]

a.+ ve
b.- ve
c.Zero- ve
d.Either + ve or Zero
132. Type 3 in 80 x 86 is an example of_________ interrupts [14M02]

a.External pin
b.Hardware interval
c.Software related
d.Hardware interval or software - related
133. If a timer has overflowed at an instance t0 and its service routine
initiates at time 't1', the latency interval for it Tlat is _________ [14S01]

a. (t1 - t0)
b. (t0 - t1)
c.t1
d. t0
134. If a timer has overflowed at an instance 't0' and the overflow interrupt is
serviced latest by 't2', then dead line time interval Td is [14S02]

a. t2
b. t0
c.(t2 - t0)
d. (t0 - t2)
135. Serial UART interface 0 x 0023 is an ________ in 8051. [14S03]

a. Interrupt Source
b.RAM
c. ROM
d.A/D converter
136. Serial syn. Interface 0 x 0053 is an _______ in 8051 [14S04]

a. Interrupt Source
b.RAM
c. ROM
d.A/D converter
137. An MCU can _________ on i) start of A/D conversion and ii) at the end of
the conversion [14S05]

a.PUSH
b. Interrupt
c. POP
d.MOV
138. Interrupt pin INTR is an example of _______ interrupts [14S06]

a. External pin

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b.Hardware interval
c. Software related
d.Hardware interval or software - related
139. Each of the ______ demands a temporary transfer of control from the
presently executed program to an ISR [15D01]

a. Interrupt sources
b.SFUF
c. SCON
d.T2CON
140. Illegal opcode pertains to ________ interrupts in 80 x 86 [15D02]

a.Internal pin
b.External pin
c.Software related
d.Either
141. ________ is an external interrupt in 8051. [15M01]

a.ITO
b. INTO
c. ITI
d.IE7
142. Error like division by zero pertains to ______ interrupts in 80x86.
[15M02]

a.Internal pin
b.External pin
c.Software related
d.Either
143. NMI pin interrupt in 80 x 86 is an example of _______ interrupts [15S01]

a. Non - maskable
b.Maskable
c. External
d.Internal
144. Clock monitor failure is an example in 68 HC11/12 for ________
interrupts [15S02]

a. Non - maskable
b.Maskable
c. External
d.Internal
145. Unimplemented instruction trap is an example in 68HC11/12 for
_________ interrupts [15S03]

a. Non- maskable
b.Maskable
c. External
d.Internal
146. All _______ can be simultaneously disabled at the primary level at the
CPU [15S04]

a.Timers
b. Interrupts
c. Oscillator circuits
d.Counters
147. All interrupts are _______ in 8051 [15S05]

a. Maskable

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b.Non - maskable
c. External
d.Internal
148. Nested interrupts for the maskable sources are permissible in [15S06]

a. 8051 and 80 x 86
b.68HC11/12
c. 8051,80x86 and 68HC11/12
d.8051 and 68HC11/12
149. In 8051, ________ is set to 1 for starting timer 0 [16D01]

a.TL0
b.TH0
c.TR0
d.TH1
150. In 8051,________ is set to 0 to stop the timer 0 [16D02]

a.TL0
b.TH0
c.TR0
d.TH1
151. A timer can also be used as a _________ when instead of internal clock
pulses, the external inputs for counting are given [16M01]

a. Counter
b.External counter
c. External timer
d.Pulse generator
152. If interrupt from a timer is enabled, an _________ executes [16M02]

a.SETBITO
b. Interrupt routine service
c. MOV IE #85H
d. INC R1
153. A system invariably needs ______ that can schedule the tasks in real
time [16S01]

a. Timers
b.Oscillator circuits
c. RAM
d.ROM
154. _____________ can be programmed for the measurement of durations of
the events [16S02]

a. Timers
b.Oscillator circuits
c. RAM
d.ROM
155. _________ can be programmed to initiate actions at scheduled instants
or sequences [16S03]

a. Timers
b.Oscillator circuits
c. RAM
d.ROM
156. _________ can capture the instances of the events [16S04]

a. Timers
b.Oscillator circuits

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c. RAM
d.ROM
157. A timer is a counter that receives the________ at a prefixed regular
intervals and which time - outs on each overflow [16S05]

a.Analog signals
b. Count pulses
c. Digital signals
d.Sinusoidal signals
158. The pulses received in a timer at prefixed regular intervals are called the
___________ [16S06]

a.internal pulses
b.Input pulses
c.Count pulses
d.Clock pulses
159. An overflow event indicated by the overflow interrupt is usable to initiate
an________using an ISR [17D01]

a. External event
b.Reset
c. Alarm
d.Data transfer
160. Once _______ starts on power up of the MCU, keeps running endlessly
even after its overflow [17D02]

a.Programmable timer
b. Free running counter
c. Oscillator circuit
d.Either programmable
161. In__________, timer starting & stopping cannot be programmed
[17M01]

a.8051
b.8086
c.68HC11/12
d.8051 or 8086
162. ___________ of T0 in 8051 resets on its own at the start of the
execution of ISR for T0 [17M02]

a.TH1
b. TF0
c. TR0
d.TL0
163. A ______ keeps a record of actual time before its next cycle starts
[17M03]

a.Programmable timer
b. Free running counter
c. Oscillator circuit
d.Either programmable
164. In 8086, count input interval is _________ μs [17S01]

a.1
b. 2
c. 3
d.4
165. In _________, its timer is a free - running counter [17S02]

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 BOBBY_DSB

a.8051
b.8086
c.68HC11/12
d.8051 or 8086
166. On overflow to '0', there is an _________ in all MCUs [17S03]

a. Interrupt
b.Reset
c. Long jump
d. Short jump
167. ______________, when used as a timer provides the real - time control
[17S04]

a.Programmable timer
b. Free running counter
c. Oscillator circuit
d.Either programmable
168. A __________ is like a moving needle that shows the seconds in a watch
or a clock [17S05]

a.Programmable timer
b. Free running counter
c. Oscillator circuit
d.Either programmable
169. SWT interrupt and ___________ interrupts are similar [18D01]

a.IRTC
b. OC
c. Overflow
d.Either RTC or overflow
170. In figure, x is ___________

[18G01]

a.ADC converter
b.DAC converter
c.Real time clock interrupts
d.Oscillator
171. Polling is at the ____________ of each instruction in 8051 [18M01]

a.Beginning
b. End
c. During
d.Beginning or during
172. Polling is at the ____________ of each ISR in 68HC 11/12 [18M02]

a.Beginning
b. End
c. During
d.Beginning or during
173. A overflow in a 16 - bit counter occurs after _______ inputs [18S01]

a. 216
b. 28
c.24
d. 22
174. As soon as the real time, shown by the clock ______ the preset time
value, the alarm raises [18S02]

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 BOBBY_DSB

a.Is lower than

b. Equals
c. Exceeds
d.Is much lower than
175. In figure, x is ________

[18S03]

a. Free - running counter

b.Timer
c. Oscillator circuit
d.A/D converter
176. All CPUs have an interrupt handling structure to control the program flow
in __________ [18S04]

a. Real time
b.Overflow
c. Starting
d.Resetting
177. Each interrupt source is identified by a _____ [18S05]

a.Direct address
b. Vector address
c.Flag
d.Direct vector address
178. Worst case interrupt latency period = ______ + T1exec + Tend + T1initial
[19D01]

a. (t1 - t0)
b. (t - t0)
c.t1
d. t0
179. An RTC interrupt occurs repeatedly every 32.768 μs and RTC ISR
executes for 32.768 μs. What is the fraction of time spent by CPU in RTC
interrupt service? [19D02]

a.0.01%
b. 0.1%.
c. 1%
d.10%
180. Interrupt Latency = -------- + T inst + Tend + T initial [19M01]

a. (t - t1)
b. (t1 - t)
c.t1
d.t
181. Interrupt________ can be defined as the interval between the
occurrance of the interrupt event and the start of the interrupt service for that
event [19S01]

a. Latency
b.Enabling and disenabling
c. Enabling
d.Disabling
182. Interrupt latency can be defined as the interval between the occurance of
the ______ and the start of the interrupt service for that event [19S02]

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 BOBBY_DSB

a.A/D conversion
b. Interrupt event
c. D/A conversion
d.Short jump
183. Interrupt latency can be defined as the interval between the occurance of
the interrupts event and the start of ________ for that event [19S03]

a.Overflow
b.A/D conversion
c.Interrupt service
d.D/A conversion
184. A foreground program is executing an instruction of 20.5μs duration
when the interrupt event occurs. Initial actions take 6 μs, before the execution
of the task related instructions, starts. The latency period in this case is
_____μs [19S04]

a.20.5
b.6
c.26.5
d.14.5
185. A foreground program is executing an instruction of 16μs duration when
the interrupt event occurs. Initial actions take 5μs, before the execution of the
task related instructions, starts. The latency period in this case is
__________μs [19S05]

a. 21
b.16
c. 6
d.11
186. A foreground program is executing an instruction of 2μs duration when
the interrupt event occurs. Initial actions take 6μs, before the execution of the
task related instructions, starts. The latency period in this case is ______μs
[19S06]

a.2
b.6
c.8
d.4
187. Interrupt service period of an ith interrupt task Ti = T initial +T execution +
_______ [19S07]

a. Tend
b. T latent
c.T reset
d. TH
188. If interrupt density is toc μs /32 μs. (where toc is the time spent in the
oc event servicing), toc should be ______ 32μs. [20M01]

a. Less than
b.Equal to
c. Higher than
d.Equal or higher than
189. Programming is done keeping inview the _________ latency for an
interrupt [20M02]

a.Initial time
b. Worst - case
c. End time

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 BOBBY_DSB

d.Execution time
190. Interrupt density depends upon sum of ratios of all ISR execution times
and their _________ [20M03]

a. Intervals of occurances
b.End times
c. Initial times
d.End times or Initial times
191. Each interrupt has a_______ period, which depends on the inherent
latency and other pending interrupts [20M04]

a.End
b. Latency
c. Execution
d.Initial
192. Interrupt density should be __________ [20S01]

a.1
b. Less than 1
c. More than 1
d.Any value
193. ISRs should be made as _______ as possible to reduce Ti interrupt
service period [20S02]

a. Short
b.Long
c. High
d.Too long
194. ISR should be _______ in 80 x 96 to reduce the interrupt densities
[20S03]

a. Short
b.Long
c. High
d.Too long
195. Software timer interrupts are like_______ [20S04]

a. Real - time clock interrupts

b.Programmable timers
c. Counters
d.Vectors to ISR - ADDR
196. Real time actions are feasible with a [20S05]

a.Overflow interrupts
b. Free running timer
c. Timer that is started by another timer
d.68HC11 RTC1 feature only
197. If Ti is the interrupt service period, of an ith interrupt task, Tiintr is the
interrupt interval between the ith interrupt events, then interrupt density =
--------- [20S06]

a. Ti / Tiintv
b. Tiintv / Ti
c.∑ (Ti / Tiintv)
d. ∑ (Tiintv/ Ti) (Summation is for i = 1 to n)

23