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Introduction to VHDL
Hyotaek Shim, Computer Architecture Laboratory
Programmable Logic Device (PLD)
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CPLD FPGA
SPLD
Simple PLD (SPLD)
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Multiple PAL
PAL-like
like blocks on a single chip with
programmable interconnect between blocks
Field-Programmable Gate Array (FPGA)
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An array
y of programmable
p g basic logic
g cells
surrounded by programmable interconnect
On the surface
surface, not much
Both can be used for designing ASICs and
simulating systems
Both are IEEE standards and are supported by
all the major EDA vendors
VHDL requires longer to learn and is not so
amenable to quick
quick-and-dirty
and dirty coding
Many engineers will one day be bi-lingual in
both HDLs
Introduction to VHDL
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Circuit module
Entity declaration + architecture body
Circuit Module
Architecture (Body)
Sequential,
Combinational
Subprograms
An entity
y is a simple
p declaration of a modules
inputs and outputs.
An architecture is a detailed description of modules
internal structure or behavior.
Syntax of a VHDL entity declaration
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entity example1 is
portt ( x1,
1 x2,
2 x3
3 : in
i std_logic
td l i ; -- input
i t signals
i l
in1 : in integer ;
val1 : out std_logic ; -- output signals
Signal Name val2 : out std_logic_vector(3 down to 0) ;
end example1 ;
Mode Type
architecture sample1 of example1 is
begin
-- hello world ;
end sample1 ;
Entity-name
y
User-defined identifier to name the entity
Signal-names
g
User-defined identifiers to name external-interface signal
Syntax of a VHDL entity declaration
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Mode : specifying
p y g the signal
g direction
In : the signal is an input to the entity.
Out : the signal is an output of the entity.
Inout: the signal can be read as an input or an output of the
entity. This mode is typically used for three-state
input/output pins.
Buffer: the signal is an output of the entity, and its value
can also be read and written inside the entitys architecture.
Upper Module
In or Inout In Inout Inout
Lower Module
Signal types
library IEEE ;
use IEEE.std_logic_1164.all
IEEE.std logic 1164.all ;
Logic
g circuit description
p in architecture body
y
process
concurrent statement
sequential statement
sequential statement
concurrent statement
Whats
What s the difference?
architecture con of drv is architecture seq of drv is
begin begin
A <= B; P
Process(B,
(B C)
begin
A <= C; A <= B
end con;; A <= C
end process;
end con2;
M l i l driver
Multiple d i
Several signal assignment to a single signal driver
Signal driver
A source which determines a value of each signal
A signal
g is updated
p by
y the driver at every
y source update
p
Delta Delays (1/2)
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Behavioral Style
Describes a system in terms of what it does(or how it
behaves)]
IF, CASE, FOR, mainly within Process statement
Dataflow Style
Specifies the relationship between the input and output
signals
AND, OR, NOT, XOR, etc.
end DATAFLOW ;
Architecture Style (3/4)
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Structural Style
Describes a system as interconnection of predefined
components, hierarchical design
consists
i t off modules
d l and
d iinterconnections
t ti
Component, Port Map
architecture STRUCTURE of COMPARE is
signal I : BIT ;
Entity Latch is
Port(LE, Din : in std_logic;
Dout : out std_logic);
std logic);
End Latch;
D-flip
p flop
p triggered
gg by
y rising
g edge
g
library IEEE;
use IEEE.std_logic_1164.all;
entity d-ff is
port(clk, d: in std_logic;
q : out std_logic);
_ g );
end d-ff;
8-bit
8 bit register
architecture Reg_arch of Reg is
begin
Library IEEE; process(clk, rst)
use IEEE.std_logic_1164.all;
begin
entity Reg is if(rst = '1') then
port(clk
( lk : ini std_logic;
d l i q <=
< ((others
th =>
> '0')
'0');
rst : in std_logic; elsif(clk'event and clk ='1')
ld : in std_logic; then
d : iin std_logic_vector(7
td l i t (7 if(ld = '1') then
downto 0);
q <= d;
q : out std_logic_vector(7
downto 0)); end if;
end Reg; end if;
end process;
endd Reg_arch;
R h
Typical Design Flow
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Synthesis
y = Translation+Optimization+Mapping
p pp g
Mapping (1/2)
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Original
g Netlist Possible Covering
g LUT Mapping
pp g from Covering
g
Mapping (2/2)
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LUT0
LUT4
LUT1
FF1
LUT5
LUT2
FF2
LUT3
Typical Design Flow
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FPGA
P
Programmable
bl Connections
C i