A Novel Single-Phase Power Factor Correction Scheme

Yimin Jiang, Fred C. Lee, Guichao Hua, Wei Tang

Virginia Power Electronics Center
The Bradley Department of Electrical Engineering
Virginia Polytechnic Institute and State University
Blacksburg, VA 24061

-
A b m d A novel single-phase power factor correction When unity power fador is achieved, the input and out-
scheme is proposed based on the power flow analysis. It put p e r relationship is shown in Fig. 1.
is found that the conventional PFC circuit must be
designed to handle the rated power, although its purpose
is only for power factor correction. With the proposed Pni-
scheme, the PFC circuit is in parallel with the mqjor Po I
power flow path, thus reduces its size and weight com-
pared to a conventional two-cascade-stage scheme. A
prototype circuit has been built and tested to verify this
concept. ti a
I. INTRODUCTION Fig. 1 Power Relationship of Single-phase PFC

The power fador correction (PFC) technique has been

gaining increasing attention in power electronics field in If precise regulation and fast dynamics at the output are
recent years. Many equipment are designed with the intend required, the two stage configuration shown in Fig. 2 is
to meet regulations like IEC 555-2 in regard to the total used, where a PFC stage is added in between the line and a
harmonic distortion (THD) of the current drawn by the off- D W C stage.
line equipment. For the conventional single-phase capaci-
tive rectifier, a large electrolytic capacitor filter is used to
reduce dc voltage ripple. This capacitor draws pulsating
current only when the input ac voltage is greater than the
capacitor voltage, thus the THD is high and the power f a 0
tor is poor. To reduce THD and improve power fador,
M TEFDLmD
passive filtering methods and adive wave-shaping
Fig. 2 Conventional Two Cascade Stage PFC Scheme
techniques have been explored. The passive methods [l]
are bulky and fail to provide satisfactory results. The active
methods using high frequency switching technique to shape The output capacitor of the PFC stage must be large
the input current are much preferred. Commonly used enough to handle the second harmonic power unbalance
topologies are boost type [2][3][4], buck type [5] and buck- between the input and the output within a line cycle as
boost type [6] topologies, and the boost type has been indicated in Fig. 1, as well as provide hold-up time if
proven to be most desirable in many applications. required. It not only slows down the PFC output dynamics
but also contains second harmonic ripple voltage, which
could not be removed by the voltage feedback. Usually, the
This work wad supported by Alcatel Standard Electrica, S.A. and Virginia
Center for Innovative Technology

28 7
0-7803-0982-0/93$3.00 1993 IEEE
PFC output voltage loop is designed with a c~oss-ovecfre-
quency well below the line second harmonic frequency.
That is why another DC/DC stage is necessary for tight
output regulation.
With these two stages in cascade, the input power factor
correction and the output regulation can be achieved inde
pendently. However, in this scheme the PFC Circuit must
handle the rated power. Some efforts have been reported in Fig. 3 Parallel Power Factor Cormtion Weme
recent literatures to develop simplified single-phase PFC cir- This concept looks quite straightforward if one under-
cuits. Basically, their aim is to incorporate the two stages stands the basic power relationship. It can be easily calcu-
into one by allowing them to share the active switch(es). lated that the P, is about 68% of the average input power,
The dither PFC [7], the resonant PFC [8], the BIFRED PFC and Pz is about 32%. Since the power PI is processed
[9] and the BIBRED PFC [9]circuits are examples. How- through only stage 1 bypassing PFC circuit, this scheme is
ever, these circuits fail to produce higher efficiency than the inherently more eficient than a two-cascade-stage saeme.
corresponding two-cascade-stage circuits due to the switch
sharing. Since the same switch must perform output voltage
III. OPERATION OF PPFC CIRCUIT
regulation and input power factor correction, severe limita-
tions exist and most of them can only operate in DCM with The circuit shown in Fig. 4 implements the above paral-
variable frequency control. This paper proposes a new lel power factor correction concept. The main power stage
concept to implement the high efficiency single-phase PFC is an isolated full bridge (FB) boost converter. The
for relatively high power applications. The PFC circuit is in auxiliary stage here is a typical forward converter, which, in
parallel with the main power flow path and is only rated for fact, can be replaced by any other topology.
30 percent of the total power. Therefor, it is inherently
more efficient and smaller in size and light in weight.

11. PARALLELPFC CONCEPT

The input power and the output power of the single-
c-
phase PFC circuit under unity power factor were drawn in
Wn
Fig. 1. The Pin is a sine square function biased by the
constant output power (assuming constant output p e r in M
this analysis). For the point of view of power fador correc- -
Di
tion, the PFC circuit does not need to process the entail
power. During the period to - t, when the input power pinis Fig. 4 Full-Bridge Boost Parallel PFC Circuit
greater than the output power Po, it can be expected that the
The operation waveforms of this PPFC circuit are shown
amount of PI power will be transferred, without going
in Figs. 5 and 6 where the SPlcis the output of a boost PFC
through a PFC circuit, to the output directly. Only the
controller.
excess power @,.-Po) is stored in an energy storage element,
usually a bulk capacitor. From t, through 4 when Po, Case I : > Po, see Fig. 5
the difference (Po-pin)is provided by a PFC circuit with the (a) Mode 1,t( - t,):
bulk capacitor as its input source. This is the concept of At to, S, and S, are turned on, and all four switches
Parallel Power Factor Correction (PPFC), which is shown in are conducting. The boost indudor is charged by the
Fig. 3 where the "stage 1" handles P, power and the "stage input voltage. No current flows in transformer T,.
2" processes P2 power.
All diodes D, - D, are reverse-biased.

288
 Mode 2 (tl - t2):
At t,, S,, S, and S, are tumed off. Then the boost
inductor current flows into the bulk capacitor through
the diode D,. It functions to put the excess energy
into the bulk capacitor as explained befom
Mode 3 (t2 - t,):
At time b, S, is tumed on, and two diagonal switches
S, and S, are conducting. Since the refleded output
(c) Mode 3 (b t3):
voltage at the primary side of T, is designed to be a
little less than the bulk capacitor voltage, the diode
D, is reverse-biased by the voltage difference, and
the boost inductor current goes through the trans-
former T, to the output. The decreasing slope of the
boost inductor current is a little less than that in
Mode 2. However, the difference is fairly small. At
time t,, S , and S, are tumed on; the other half of the
switching cycle begins, which is symmetrical to the
first half. It is noted that the reverse bias voltage on
D, is much smaller compattd with the reverse bias
voltage across the boost diode in a single-ended PFC
boost converter.
@) Mode 2 (t, - t2):
For the main boost stage, it is in the same state as in
Mode 1. Since the input power is less than the out-
put power, the forward converter is activated to pro-
vide the neoessary power to keep the output power
constant. This is the tum-on period of the forward
switch, charging the forward inductor.
-
This mode is same as the Mode 3 in Case 1 for the
main boost converter. It is also part of the switch-off
period of the forward converter. At time t,, the other
half cycle begins which is symmetrical to the first
half.
Pln < Po :
. . .
I.

I
PSnzPo: SI I
I I 1 I I I
I . . .
! 1 1 I I I m ti n t3
I '

I L I
Fig. 6 Control Waveforms of the FB-Boost
s1 I
I
I
PPFC Circuit (Pin< Po)
52 I
I
1

1 I
1
-I
s3 I I
I
1
!
I The duty cycle of signal S,, controls the input current to
I
achieve unity power factor. The time length of the Mode 2
t
I
s4 I 1 I I
I I I I
I in both cases of pin> Po and pi. < Pois controlled by a fast
tb ti IZ 13 output voltage compensator which basically controls the
power flow to achieve tight and fast output voltage regu-
Fig. 5 Control Waveforms of the FB-Boost
lation.
PPFC Circuit (P > Po)
The major drawback of the above circuit is that it
involves two transformers which have to meet safty-
Case 2: pin < Po, see Fig. 6
isolation specifications. A one-transformer version has also
(a) Mode 1 ,t( - t,): been developed as shown in Fig. 7.
For the main boost converter, it is identical to the
Mode 1 in Case 1. It is also part of the switch-off
period of the forward converter.

289
 . through diode D2.At time t , one of S, and S, is turned on
again, which allow the indudor energy being transferred to
lin .'I." I D4 the load through the transformer and the output rectifier.
Actually, since S, is on and S4 is off all the time within this
r! half line cycle, what happened here is exactly the same as in
VaC
the previous circuit.
For the other half line cycle where Pi. Po, S1 and S,
start to switch so that the proper amount of power can be
Fig. 7 One-TransformerPPFC circuit deliver to the load form the bulk capacitor without affecting
the input power factor. There are also more than one possi-
Since there are four active switches, the circuit can run ble way to operate this circuit. Here is one example as
in boost mode or buck mode or buck-boost mode depending explained below. From ,,t through t,, Si,zs are on, charging
on the switching timing of those switches. One possible the inductor, which is the same as for Pin > Po. At time t,,
operation principle is shown in Fig. 8. one of the S, and S, is tumed off, and the inductor energy is
released to the load through the transformer. At tz, q,, are
on, thus bulk capacitor starts to charge the indudor. At
Pin > Po: time t,, S, and one of S, and S, are tumed off (S, should be
I L-lh -kp.cl
tumed off before this point) and the diode D1is forced to
conduct, thus the inductor energy is transferred to the load
through the transformer. The inductor current during the
first two intervals,,t( - b) is coming from the AC source, so
0 n U t3
t2 can be used to control the power factor. At the same
I I time, t, can be used to regulate the output.
I I

I I I I
This circuit is simpler than the circuit in Fig. 4, and also
m n (2 U provides some important features such as soft-start, short
T8
circuit protection due to the existence of switch S,. How-
ever, using S, inaeases the conduction loss, and this circuit
Pln < Po:
draws pulsating current from the line when Pi, Po which
requires larger input filter. This circuit is also useful for
applications where the input line voltage is too high to use
boost type PFC circuits.
m n 0 0 U

I I I I I
I I I ! I IV. HARDWARE IMPLEMENTATION
I A prototype circuit as shown in Fig. 4 has been built to
lo n ( 2 U U verify this new single-phase PFC concept. The basic speci-
fications are:
Fig. 8 Operation of the OneTransformer PPFC Circuit
Po = 250 W, V, = 36 VDC;
Vi, = 110 VAC; Switching Frequency = 100 KHz.
In case of Pi, > Po, the operation is simple. There are
In the control circuits, the PFC controller UC3854 is
three intervals within a switching cycle. From to through t,,
used to create the signal Spfc. All the other control signals
S1,23 are closed which is the boost charging process taking
in Fig. 5 and Fig. 6 are generated from Spfcby a simple
energy from the AC source. At time t,, S , are turned off,
logic circuit.
thus the inductor energy is transferred to the bulk capacitor

2'90
 Figure 9 shows the experimental waveforms of the pro-
posed circuit. The line current follows the line voltage very
well, indicating that the unity power fador has been
achieved. The forward inductor current waveform demon-
strates the proper parallel power flow.
Figure 10 gives the efficiency measurement. It should
be noted that the efficiency is quite high for llOVAC line
voltage. The four boost switches are "450 (MOSFET)
and the fonvard switch is IRFPGSO (MOSFET). The 88%
efficiency corresponds to almost 94% efficiency of each
stage in a twocascadestage system, which is not easy to
achieve at this line voltage. If better switches are used,
such as IRFP460, the results will be further impmed.
Fig. 9 Experimental Waveforms
100 r
E 85,
7 0 ; 2 3 4 5 6 7 A
OUTPUT CURRENT (A)
Fig. 10 Efficiency Measurement of the PPFC Circuit
This isolated boost topology also provides an opportu-
nity to use IGBTs as the main power switches since soft
tumaff of IGBTs can be achieved quite easily here [ll].
The use of IGBTs is very attradive for high power applica-
tions due to the lower conduction loss and lower cost com-
pared with MOSFETs. This choice could result in a great
advantage over conventional ckuits. When using IGBTs,
the half-bridge boost converter shown in Fig. 11 would be
more preferred because it takes advantage of the IGBT's
high voltage rating and saves two main switches.
Lia
Fig. 11 Half-Bridge Boost Converter
To see the advantage of this circuit, a comparison needs
to be made with the conventional two-cascade-stage system.
A single-ended boost PFC stage followed by a FB PWM
stage in Fig. 12 is chosen as an example for the purpose of
comparison.
1 '0
I
1
I1
-4 9"
1 1
Fig. 12 Conventional Two-Cascadestage PFC Circuit
It is not simple to make this comparison very thoroughly
because the topologies and the operation principles are all
different. The optimization design whicb should be the
grounds of this comparison has not been created yet at this
stage. However, some merits of this PPFC circuit still can
be seen clearly. First, the rev- recovery problem and the
291
conduction loss of the boost diode D, in the PPFC circuit
(Fig. 4) is much less severe than that of D, in Fig. 12. This
is because the boost diode D, in Fig. 4 does not conduct at
all when Pin < Po. During the period when Pin> Po, though
D, is running, it carries less current and less reverse voltage
than the boost diode D, in Fig. 12. Besides, the leakage of
the transformer in Fig. 4 will also help to kill the reverse
recovery current. Secondly, there is only one inductor, the
boost indudor, in the main power path of the PPFC circuit,
while two inductors are in the main power path in Fig. 12.
When IGBTs are used for high power applications, it will
reduce the cost and further improve the efficiency compared
with the two-cascade-stage configuration where boost
switches are usually several MOSFETs in paralleL
v. SUMMARY
In this paper, a novel single-phase power factor correc-
tion scheme, the parallel power factor correction, was pro-
posed based on the power flow analysis. Both unity power
factor and tight output regulation were achieved. Compared
with a conventional two-cascadestage scheme, it provides
higher efficiency due to the parallel power processing. A
prototype circuit has been built and tested to verify this
concept. Also lower cost can be expected if using IGBTs as
the main switches. This scheme is essentially suitable for
building high power, high efficiency, high density off-line
power converters with PFC requirement.
It needs to be mentioned that, in the proposed scheme
since the output here is the parallel of two different conver-
ters (boost and buck), the compensator design of the output
regulation and other control issues need to be studied.
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C u m t Waveshaping Technique for Solid State Input
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99-105.
5. R.J. King, "Analysis and Design of an Unusual Unity-
Power-Factor Rectifier", IEEE Trans. on Industrial
Electronics, Vol. 38,No. 2, April 1991, pp. 126-134.
6. R. E r i c b n , M. Madigan, S. Singer, "Design of a Sim-
ple High-Power-Factor Redifier Based on the Flyback
Converter", IEEE APEC 1990, pp. 792-801.
7. I. Takahashi, R.Y.Igarashi, "A Switching Power Sup-
ply of 99% Power Factor By The Dither Rectifier",
INTELEC 1991, pp. 714-719.
8. MJ. Mutter, R.L. Steigenvald, M.H. Kheraluwala,
"Characteristics of Load Resonant Converters Operated
in a High Power Factor Mode", IEEE APEC 1991, pp.
5-16.
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Quality Rectifier-Regulators", IEEE PESC 1992, pp.
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